WO2021139040A1

WO2021139040A1 - Gallium oxide field effect transistor and manufacturing method therefor

Info

Publication number: WO2021139040A1
Application number: PCT/CN2020/086192
Authority: WO
Inventors: 吕元杰; 王元刚; 周幸叶; 刘宏宇; 宋旭波; 梁士雄; 马春雷; 付兴昌; 冯志红
Original assignee: 中国电子科技集团公司第十三研究所
Priority date: 2020-01-07
Filing date: 2020-04-22
Publication date: 2021-07-15
Also published as: CN111180398A; CN111180398B

Abstract

The present application is applicable to the field of semiconductor technology, and provides a gallium oxide field effect transistor and a manufacturing method therefor. The gallium oxide field effect transistor comprises a substrate, a gallium oxide channel layer provided on the substrate, and a source electrode and a drain electrode provided on the gallium oxide channel layer, a gate dielectric layer provided between the source electrode and the drain electrode, a gate electrode provided on the gate dielectric layer, and a passivation dielectric layer covering a surface area between the source electrode and the drain electrode, a fluorine implantation area being provided in the passivation dielectric layer, and the fluorine implantation area being located in the area on a side of the gate electrode close to the drain electrode. The gallium oxide field effect transistor provided in the present application can effectively suppress a peak electric field which may occur in the area on a side of the gate electrode close to the drain electrode, so that the distribution of the electric field is more uniform, and the breakdown voltage of the gallium oxide field effect transistor is greatly improved, facilitating expanding of the application of a gallium oxide field effect transistor device in high-voltage scenarios.

Description

Gallium oxide field effect transistor and preparation method thereof

Technical field

This application belongs to the field of semiconductor technology, and in particular relates to a gallium oxide field effect transistor and a preparation method thereof.

Background technique

At present, ultra-wide bandgap power electronic devices represented by gallium oxide have gradually become an important development field of power semiconductor devices in recent years, and are expected to replace traditional silicon-based power devices in certain specific fields.

As a new semiconductor material, ultra-wide bandgap gallium oxide has outstanding advantages in breakdown field strength, Baliga's merit and cost. Internationally, Baliga's figure of merit is usually used to characterize the suitability of materials for power devices. For example, the Balijia figure of merit for β- _{Ga 2} O ₃ materials is 4 times that of GaN materials, 10 times that of SiC materials, and 3444 times that of Si materials. β -Ga ₂ O ₃ power devices have the same withstand voltage as GaN and SiC devices, with lower on-resistance and lower power consumption, which can greatly reduce the power loss during device operation.

Since the Japan Information and Communication Research Institute (NICT) developed the first gallium oxide metal oxide semiconductor field effect transistor (Ga ₂ O ₃ MOSFET) device in 2013, researchers have improved the quality of Ga ₂ O ₃ crystal materials and optimized the device manufacturing process , Including methods such as optimizing channel layer doping, ohmic contact and Schottky contact technology, and gate field plate structure to continuously improve the _{performance of Ga 2} O ₃ MOSFET devices.

In 2016, NICT used Al ₂ O ₃ as the sub-gate dielectric and combined with the gate field plate structure to produce a Ga ₂ O ₃ MOSFET with a breakdown voltage of 750 V.

In 2019, ETRI adopted a source field plate structure, and at the same time, the air breakdown of the device was isolated by a fluorinated liquid during the test, and the breakdown voltage of the device reached 2320 V.

_{However, the breakdown voltage and conduction characteristics of Ga 2} O ₃ field effect transistor (FET) devices that have been reported so far are still far below the expected values of materials.

technical problem

In view of this, the present application provides a gallium oxide field effect transistor and a preparation method thereof to further increase the breakdown voltage of the existing gallium oxide field effect transistor.

Technical solutions

The first aspect of the embodiments of the present application provides a gallium oxide field effect transistor, including a substrate, a gallium oxide channel layer provided on the substrate, a source electrode provided on the gallium oxide channel layer, and The drain electrode, the gate dielectric layer provided between the source electrode and the drain electrode, the gate electrode provided on the gate dielectric layer, and the surface area between the source electrode and the drain electrode A passivation dielectric layer, the passivation dielectric layer is provided with a fluorine injection area, and the fluorine injection area is located in an area where the gate electrode is biased toward the drain electrode.

Further, the lower edge of the fluorine injection region does not reach the lower surface of the passivation medium layer.

Further, if the side where the source electrode is located is the left side of the gate electrode, and the side where the drain electrode is located is the right side of the gate electrode, the left edge of the fluorine injection region does not exceed The left edge of the gate electrode, and the length of the right edge of the fluorine injection region that exceeds the right edge of the gate electrode is not more than 10 micrometers.

The second aspect of the embodiments of the present application provides a manufacturing method of a gallium oxide field effect transistor, the manufacturing method includes:

Epitaxially grow a gallium oxide channel layer on the substrate;

Prepare a source electrode and a drain electrode on the gallium oxide channel layer;

Growing a gate dielectric layer between the source electrode and the drain electrode;

Prepare a gate electrode on the gate dielectric layer;

Preparing a passivation dielectric layer on the surface area between the source electrode and the drain electrode;

Fluorine ion implantation is performed into the passivation dielectric layer to form a fluorine implantation region, wherein the fluorine implantation region is located in a region where the gate electrode is biased toward the drain electrode.

Further, the performing fluorine ion implantation into the passivation medium layer to form a fluorine implantation region includes:

Sputter or evaporate the metal mask layer on the upper surface of the passivation dielectric layer;

Forming a photoresist mask layer on the metal mask layer, and using the photoresist mask layer as a mask to perform fluorine ion implantation into the passivation medium layer to form the fluorine implantation area;

Removing the photoresist mask layer and the metal mask layer.

Further, the implantation depth of the fluorine ion implantation is smaller than the thickness of the passivation dielectric layer.

Further, the fluorine ion implantation meter of the fluorine implantation area decreases sequentially from left to right

Further, the metal mask layer is a nickel mask layer or a chromium mask layer.

Further, the thickness of the metal mask layer does not exceed 1000 nanometers.

Beneficial effect

The gallium oxide field-effect transistor provided in the present application includes a substrate, a gallium oxide channel layer provided on the substrate, a source electrode and a drain electrode provided on the gallium oxide channel layer, and a gap between the source electrode and the drain electrode. The gate dielectric layer, the gate electrode provided on the gate dielectric layer, and the passivation dielectric layer covering the surface area between the source electrode and the drain electrode, pass through the passivation dielectric layer in the area where the gate electrode is biased toward the drain electrode The fluorine injection area is provided. The fluorine injection area can reduce or even deplete the electrons in the gallium oxide channel layer, and can increase the breakdown field strength of the passivation dielectric layer, thereby effectively suppressing the possible occurrence of the gate electrode in the area on the side of the drain electrode. The peak electric field makes the distribution of the electric field more uniform, and the breakdown voltage of the gallium oxide field effect transistor is greatly increased, which is beneficial to expand the application of gallium oxide field effect transistor devices in high-voltage scenarios.

Description of the drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the prior art and the drawings needed in the embodiments. Obviously, the drawings in the following description are only some of the present application. Embodiments, for those of ordinary skill in the art, without creative work, other drawings can be obtained based on these drawings.

FIG. 1 is a schematic diagram of a cross-sectional structure of a gallium oxide field effect transistor provided by an embodiment of the present application;

2 is an implementation flow chart of a method for manufacturing a gallium oxide field effect transistor provided by an embodiment of the present application;

FIG. 3 is an implementation flowchart of step 106 in the embodiment shown in FIG. 2 provided by an embodiment of the present application;

FIG. 4 is a schematic diagram of fluorine ion implantation provided by an embodiment of the present application.

Implementation of this application

In the following description, for the purpose of illustration rather than limitation, specific details such as a specific system structure and technology are proposed for a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid unnecessary details from obstructing the description of this application.

In order to make the objectives, technical solutions, and advantages of the present application clearer, specific embodiments will be described below in conjunction with the accompanying drawings.

Referring to FIG. 1, it shows a schematic diagram of a cross-sectional structure of a gallium oxide field effect transistor provided by an embodiment of the present application, which is described in detail as follows:

As shown in FIG. 1, the gallium oxide field effect transistor provided by the embodiment of the present application includes a substrate 10, a gallium oxide channel layer 11 provided on the substrate 10, and a source electrode provided on the gallium oxide channel layer 11 12 and the drain electrode 14, the gate dielectric layer 15 provided between the source electrode 12 and the drain electrode 14, the gate electrode 16 provided on the gate dielectric layer 15, and the surface area between the source electrode 12 and the drain electrode 14 The passivation dielectric layer 17 is provided with a fluorine injection region 18 in the passivation dielectric layer 17, and the fluorine injection region 18 is located in a region where the gate electrode 16 is biased toward the drain electrode 14.

Breakdown voltage is a key parameter of metal oxide semiconductor field effect transistors. After a lot of research and experimentation, the applicant of this application found that the breakdown of gallium oxide field effect transistors often occurs under the gate electrode. The reason is that the traditional The gate electrode (such as a right-angle gate electrode) has a spike electric field near the drain, and this spike electric field will cause breakdown. In the gallium oxide field effect transistor provided by the present application, since a fluorine injection area is provided in the passivation dielectric layer on the side of the gate electrode biased to the drain electrode, the fluorine injection area can reduce or even deplete the electrons in the gallium oxide channel layer. And can increase the breakdown field strength of the passivation dielectric layer, which can effectively suppress the peak electric field that may appear in the area on the side of the gate electrode biased to the drain electrode, so that the electric field distribution is more uniform, and the breakdown voltage of the gallium oxide field effect transistor is also Has been greatly improved.

In one embodiment, in order to prevent the fluorine injection region 18 from affecting the performance of the gallium oxide field effect transistor, the lower edge of the fluorine injection region 18 should not exceed the lower surface of the passivation dielectric layer 17.

In one embodiment, for the purpose of better depletion of electrons in the corresponding region in the passivation dielectric layer, the lateral position of the fluorine injection region 18 can be set according to the following restrictions: if the side where the source electrode 12 is located is the gate The left side of the electrode 16 and the side where the drain electrode 14 is located is the right side of the gate electrode 16, the left edge of the fluorine injection region 18 does not exceed the left edge of the gate electrode 16, and the right edge of the fluorine injection region 18 exceeds the gate electrode The length of the right edge of 16 is not more than 10 microns.

It can be seen from the above that the gallium oxide field effect transistor provided by the present application includes a substrate, a gallium oxide channel layer provided on the substrate, a source electrode and a drain electrode provided on the gallium oxide channel layer, a source electrode and a drain electrode. The gate dielectric layer between the electrodes, the gate electrode provided on the gate dielectric layer, and the passivation dielectric layer covering the surface area between the source electrode and the drain electrode, are located in the passivation dielectric layer and the gate electrode is biased toward the drain electrode. A fluorine injection area is provided in the area on the side of the gate electrode. The fluorine injection area can reduce or even deplete the electrons in the passivation dielectric layer, and increase the breakdown field strength of the passivation dielectric layer, thereby effectively suppressing the possible occurrence of the gate electrode in the area on the side of the drain electrode. The peak electric field makes the distribution of the electric field more uniform, and the breakdown voltage of the gallium oxide field effect transistor is greatly increased, which is beneficial to expand the application of gallium oxide field effect transistor devices in high-voltage scenarios.

Refer to FIG. 2, which shows an implementation flow chart of a method for manufacturing a gallium oxide field effect transistor provided by an embodiment of the present application, which is described in detail as follows:

In step 101, a gallium oxide channel layer is epitaxially grown on a substrate;

In the embodiments of the present application, the substrate may be a high-resistance gallium oxide substrate, or a semi-insulating silicon carbide substrate, a magnesium oxide substrate, or a sapphire substrate.

The epitaxially grown gallium oxide channel layer may be an n-type gallium oxide channel layer. In one embodiment, the n-type gallium oxide channel layer is realized by doping elements such as Si or Sn, and the doping concentration may be 1.0× In the range of 1015 cm-3 to 1.0×1020 cm-3, in some application scenarios, the doping concentration may also vary in a gradient.

In some embodiments, the layer thickness of the gallium oxide channel layer may be 10 nm to 1000 nm.

In another embodiment, an undoped gallium oxide layer can also be grown between the gallium oxide channel layer and the substrate. That is, an undoped gallium oxide layer can be grown on the substrate, and then a gallium oxide channel layer can be epitaxially grown on the undoped gallium oxide layer.

In step 102, a source electrode and a drain electrode are prepared on the gallium oxide channel layer;

In the embodiment of the present application, the n+ region can be prepared by ion implantation on the gallium oxide channel layer, and the source electrode and the drain electrode can be deposited on the n+ region. Specifically, the electrode is deposited by electron beam evaporation, and the metal can be deposited It is Ti/Au or Ti/Al/Ni/Au.

In the embodiment of the present application, the source electrode and the drain electrode may be deposited on both ends of the upper part of the gallium oxide channel layer.

In step 103, a gate dielectric layer is grown between the source electrode and the drain electrode;

In the embodiment of the present application, an atomic layer deposition method may be used to grow a layer of aluminum oxide or hafnium oxide as the gate dielectric layer between the source electrode and the drain electrode, and the thickness of the gate dielectric layer may be 10-100 nm.

In step 104, a gate electrode is prepared on the gate dielectric layer;

In the embodiment of the present application, the gate electrode can be prepared on the gate dielectric layer by the electron beam evaporation method. The gate length of the prepared gate electrode can be 50 nanometers to 10 microns, and the deposition metal of the gate electrode can be Ni/Au or Pt/Au.

In step 105, a passivation dielectric layer is prepared on the surface area between the source electrode and the drain electrode;

In the embodiment of the present application, after the gate electrode is prepared, a passivation dielectric layer can be prepared on the surface area between the source electrode and the drain electrode, and the prepared passivation dielectric layer fully covers the gate electrode. In one embodiment, the passivation dielectric layer may be a silicon nitride passivation dielectric layer, specifically, PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma-enhanced chemical vapor deposition) method to grow silicon nitride passivation dielectric layer, the thickness of the silicon nitride passivation dielectric layer can be between 50 to 2000 nanometers.

In step 106, fluorine ion implantation is performed into the passivation dielectric layer to form a fluorine implantation region, wherein the fluorine implantation region is located in a region where the gate electrode is biased toward the drain electrode.

In the embodiment of the present application, the fluorine implantation area is formed by implanting fluorine ions into the passivation dielectric layer, and the fluorine implantation area is used to reduce or even deplete the electrons in the corresponding position in the gallium oxide channel layer, and can improve the passivation dielectric layer The breakdown field is strong, thereby effectively suppressing the peak electric field that may appear in the area on the side of the gate electrode biased to the drain electrode. Since the peak electric field often exists in the area on the side of the gate electrode biased to the drain electrode, the fluorine injection area is correspondingly located in the area of the gate electrode on the side of the drain electrode.

In an embodiment, the above step 106 may be specifically completed by the following steps:

In step 1061, a metal mask layer is sputtered or evaporated on the upper surface of the passivation medium layer;

Since the passivation dielectric layer may be etched during the fluorine ion implantation process, in the embodiment of the present application, a metal mask layer is sputtered or evaporated on the upper surface of the passivation dielectric layer, which can be used as a mask to prevent the passivation dielectric layer It is etched during the fluorine ion implantation process.

In one embodiment, the thickness of the metal mask layer may not be higher than 1000 nanometers to avoid affecting the fluoride ion implantation effect.

In one embodiment, the metal mask layer may be a nickel mask layer or a chromium mask layer, which can better protect the passivation dielectric layer from being etched and has a better fluoride ion implantation effect.

In step 1062, a photoresist mask layer is formed on the metal mask layer, and fluorine ion implantation is performed into the passivation medium layer using the photoresist mask layer as a mask to form the fluorine implantation area ；

In the embodiment of the present application, photoresist can be used as a mask to perform fluorine injection treatment on the gate electrode bias and drain electrode area. Specifically, as shown in FIG. 4, the gallium oxide field obtained through step 101 to step 105 The effect transistor includes the substrate 10, the gallium oxide channel layer 11, the source electrode 12, the drain electrode 14 and the gate dielectric layer 15, the gate electrode 16, covering the passivation of the surface area between the source electrode 12 and the drain electrode 14, from bottom to top. Medium layer 17. Next, a metal mask layer 19 can be grown on the upper surface of the passivation medium layer 17, a photoresist mask layer 20 is formed on the metal mask layer 19, and the photoresist mask layer 20 is used as a mask to pass the photoresist The ion implantation window on the mask layer 20 (the arrow position in FIG. 4) implants fluorine ions into the passivation dielectric layer 17.

In some embodiments, the implantation depth of the fluorine ion implantation is smaller than the thickness of the passivation dielectric layer. If the side where the source electrode is located is the left side of the gate electrode, and the side where the drain electrode is located is the right side of the gate electrode, the left edge of the fluorine injection region does not exceed the gate electrode. The left edge of the electrode, and the length of the right edge of the fluorine injection region that exceeds the right edge of the gate electrode is not more than 10 micrometers.

In one embodiment, the amount of fluorine ion implantation in the fluorine implantation area decreases sequentially from left to right. There is a strong peak electric field in the gallium oxide channel on the side of the gate electrode and the drain electrode of the gallium oxide field effect transistor, which will cause the device to easily break down. Due to the presence of fluorine ions in the fluorine injection region, the electrons in the gallium oxide channel can be depleted (or reduced). Therefore, the existence of the F injection region can effectively reduce the peak electric field intensity. However, if the amount of fluoride ion implantation is large, the channel electrons will be consumed too much, which will cause the on-resistance of the device to increase, which is detrimental to the device performance. Therefore, the amount of fluoride ion implantation can be sequentially reduced from the right edge of the gate electrode to the right, so as to achieve the purpose of not only increasing the breakdown voltage, but also maintaining a low on-resistance.

In step 1063, the photoresist mask layer and the metal mask layer are removed.

In the embodiment of the present application, after the fluorine ion implantation is completed, the photoresist and the nickel metal mask layer (or the chromium metal mask layer) can be removed to complete the fabrication of the device.

The method for preparing a gallium oxide field effect transistor provided by the embodiment of the present application can directly use the above steps 1061 to 1063 to implant fluorine ions on the existing gallium oxide field effect transistor to form fluoride ions in the region on the side of the gate electrode and the drain electrode. The injection area suppresses the peak electric field and improves the breakdown voltage of the gallium oxide field effect transistor device.

It can be seen from the above that the gallium oxide field effect transistor provided by the present application includes a substrate, a gallium oxide channel layer provided on the substrate, a source electrode and a drain electrode provided on the gallium oxide channel layer, a source electrode and a drain electrode. The gate dielectric layer between the electrodes, the gate electrode provided on the gate dielectric layer, and the passivation dielectric layer covering the surface area between the source electrode and the drain electrode, are located in the passivation dielectric layer and the gate electrode is biased toward the drain electrode. A fluorine injection area is provided in the area on the side of the fluorine injection area. The fluorine injection area can reduce or even deplete the electrons in the gallium oxide channel layer, and can increase the breakdown field strength of the passivation dielectric layer, thereby effectively suppressing the gate electrode from the area on the drain electrode side The peak electric field that may appear inside makes the distribution of the electric field more uniform, and the breakdown voltage of the gallium oxide field effect transistor is greatly increased, which is conducive to expanding the application of gallium oxide field effect transistor devices in high-voltage scenarios.

The above-mentioned embodiments are only used to illustrate the technical solutions of the present application, not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, a person of ordinary skill in the art should understand that it can still implement the foregoing The technical solutions recorded in the examples are modified, or some of the technical features are equivalently replaced; these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the application, and should be included in Within the scope of protection of this application.

Claims

A gallium oxide field effect transistor includes a substrate, a gallium oxide channel layer provided on the substrate, a source electrode and a drain electrode provided on the gallium oxide channel layer, and the source electrode and The gate dielectric layer between the drain electrodes, the gate electrode provided on the gate dielectric layer, and the passivation dielectric layer covering the surface area between the source electrode and the drain electrode are characterized in that:

The passivation dielectric layer is provided with a fluorine injection area, and the fluorine injection area is located in an area where the gate electrode is biased toward the drain electrode.
4. The gallium oxide field effect transistor according to claim 1, wherein the lower edge of the fluorine injection region does not reach the lower surface of the passivation dielectric layer.
The gallium oxide field effect transistor of claim 2, wherein if the side where the source electrode is located is the left side of the gate electrode, and the side where the drain electrode is located is the side of the gate electrode On the right side, the left edge of the fluorine injection area does not exceed the left edge of the gate electrode, and the length of the right edge of the fluorine injection area exceeding the right edge of the gate electrode is no more than 10 micrometers.
A preparation method of a gallium oxide field effect transistor, characterized in that the preparation method includes:

Epitaxially grow a gallium oxide channel layer on the substrate;

Prepare a source electrode and a drain electrode on the gallium oxide channel layer;

Growing a gate dielectric layer between the source electrode and the drain electrode;

Prepare a gate electrode on the gate dielectric layer;

Preparing a passivation dielectric layer on the surface area between the source electrode and the drain electrode;

Fluorine ion implantation is performed into the passivation dielectric layer to form a fluorine implantation region, wherein the fluorine implantation region is located in a region where the gate electrode is biased toward the drain electrode.
4. The method for manufacturing a gallium oxide field effect transistor according to claim 4, wherein said implanting fluorine ions into the passivation dielectric layer to form a fluorine implantation region comprises:

Sputtering or evaporating a metal mask layer on the upper surface of the passivation dielectric layer;

Forming a photoresist mask layer on the metal mask layer, and using the photoresist mask layer as a mask to perform fluorine ion implantation into the passivation medium layer to form the fluorine implantation area;

Removing the photoresist mask layer and the metal mask layer.
The method for manufacturing a gallium oxide field effect transistor according to claim 5, wherein the implantation depth of the fluorine ion implantation is smaller than the thickness of the passivation dielectric layer.
The method for manufacturing a gallium oxide field effect transistor according to claim 6, wherein if the side where the source electrode is located is the left side of the gate electrode, and the side where the drain electrode is located is the On the right side of the gate electrode, the left edge of the fluorine injection area does not exceed the left edge of the gate electrode, and the right edge of the fluorine injection area exceeds the right edge of the gate electrode by no more than 10 micrometers.
7. The method for manufacturing a gallium oxide field effect transistor according to claim 7, wherein the fluorine ion implantation amount of the fluorine implantation area is sequentially reduced from left to right.
The method for manufacturing a gallium oxide field effect transistor according to any one of claims 5 to 8, wherein the metal mask layer is a nickel mask layer or a chromium mask layer.
9. The method for manufacturing a gallium oxide field effect transistor according to claim 9, wherein the thickness of the metal mask layer does not exceed 1000 nanometers.