WO2021138985A1 - 显示面板的侧缘绑定结构及其制造方法 - Google Patents

显示面板的侧缘绑定结构及其制造方法 Download PDF

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Publication number
WO2021138985A1
WO2021138985A1 PCT/CN2020/077199 CN2020077199W WO2021138985A1 WO 2021138985 A1 WO2021138985 A1 WO 2021138985A1 CN 2020077199 W CN2020077199 W CN 2020077199W WO 2021138985 A1 WO2021138985 A1 WO 2021138985A1
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Prior art keywords
side edges
substrate
display panel
glue
chip
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PCT/CN2020/077199
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English (en)
French (fr)
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汤爱华
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深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US16/755,572 priority Critical patent/US11296130B2/en
Publication of WO2021138985A1 publication Critical patent/WO2021138985A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Definitions

  • the present application relates to the technical field of display panels, and in particular to a side edge binding structure of a display panel and a manufacturing method thereof.
  • the display panel also includes a display area and a non-display area; in order to meet the so-called full screen on the market and obtain a larger screen size in a limited device volume, the display area of the display panel must be maximized and the non-display area must be reduced. The area of the district.
  • the driving chip of the display panel is directly arranged on the substrate of the display panel (chip on glass, COG). Since the driving chip is provided on the periphery of the display panel, this area cannot be used as the display area. Therefore, the non-display area of the display panel adopting the COG process is larger, and the frame of the display panel is also thicker.
  • Chip on film improves the former technology. It arranges the driving circuit on the non-display area of the traditional display panel on the flexible circuit board connected to the display panel, which can appropriately reduce the area of the non-display area.
  • the use of the COF process can moderately reduce the non-display area of the display panel, but the non-display area still needs to leave an area for bonding the circuit pins of the flexible circuit board, which also limits the reduction limit of the non-display area. Therefore, a binding structure or technology of an improved COF process is needed to solve the current limitation of the reduction of the non-display area, obtain a smaller non-display area, and realize a display panel with an ultra-narrow frame.
  • the present application provides a display panel, which includes a first substrate, a plurality of bonding pads, an insulating glue, a sealant, a barrier layer, a second substrate, and a chip on film.
  • the first substrate includes a thin film transistor, a display area, and a non-display area located at the periphery of the display area.
  • the plurality of bonding pads are disposed on the non-display area on the first substrate, are electrically connected to the thin film transistor, and extend to the side edge of the first substrate.
  • the insulating glue is coated on the plurality of binding pads.
  • the sealant is coated on the first substrate along the boundary line between the display area and the non-display area.
  • the barrier layer is arranged on the insulating glue.
  • the second substrate is arranged on the sealant.
  • the side edges of the first substrate, the side edges of the plurality of binding pads, the side edges of the insulating glue, the side edges of the barrier layer, and the side edges of the second substrate are coplanar.
  • the chip on film is disposed on the side edges of the coplanar first substrate, the side edges of the plurality of bonding pads, the side edges of the insulating glue, and the The side edge of the barrier layer and the side edge of the second substrate.
  • the chip-on-chip film includes an anisotropic conductive film coated with conductive glue, and the side edges of the plurality of binding pads are bound to the chip-on-chip film by the conductive glue and the anisotropic conductive film And each of the bonding pads is electrically connected to a corresponding circuit on the chip on film.
  • the barrier layer prevents the conductive glue from overflowing, so that the circuits between each of the bonding pads are insulated from each other.
  • the side edges of the first substrate, the side edges of the plurality of binding pads, the side edges of the insulating glue, the side edges of the barrier layer, and the second The side edges of the two substrates include a flat surface.
  • the barrier layer in an embodiment is a polystyrene layer.
  • the barrier layer and the sealant are made of the same material, and the sealant covers the non-display area.
  • the insulating glue is Taffeta blue glue.
  • the conductive adhesive is silver paste.
  • the present application also provides a method for manufacturing a display panel, including the following steps:
  • Step S10 Provide a first substrate, including a thin film transistor, a display area, and a non-display area located at the periphery of the display area.
  • Step S20 A plurality of bonding pads are arranged on the non-display area on the first substrate, and the plurality of bonding pads are electrically connected to the thin film transistor and extend to the side edge of the first substrate.
  • Step S30 coating insulating glue on the plurality of binding pads.
  • Step S40 Apply sealant on the first substrate along the boundary line between the display area and the non-display area.
  • Step S50 forming a barrier layer on the insulating glue. as well as
  • Step S60 setting a second substrate on the sealant.
  • the side edges of the first substrate, the side edges of the plurality of binding pads, the side edges of the insulating glue, the side edges of the barrier layer, and the side edges of the second substrate are coplanar.
  • the method further includes the following steps:
  • Step S70 Coplanar side edges of the first substrate, side edges of the plurality of binding pads, side edges of the insulating glue, side edges of the barrier layer, and side edges of the second substrate Chip-on-chip film is attached to the side edge.
  • the chip-on-chip film includes an anisotropic conductive film coated with conductive glue, and the side edges of the plurality of binding pads are bound to the chip-on-chip film by the conductive glue and the anisotropic conductive film And each of the bonding pads is electrically connected to a corresponding circuit on the chip on film. And when the side edges of the plurality of bonding pads are bound to the chip-on-chip film, the barrier layer prevents the conductive glue from overflowing, so that the circuits between each of the bonding pads are insulated from each other.
  • the side edges of the first substrate, the side edges of the plurality of binding pads, the side edges of the insulating glue, the side edges of the barrier layer, and the The side edge of the second substrate is polished or cut to form a flat surface.
  • step S50 of an embodiment further includes the following steps:
  • Step S51 coating a polystyrene layer on the insulating glue to form the barrier layer.
  • step S50 of another embodiment further includes the following steps:
  • Step S51 coating the sealant of step S40 on the insulating glue to form the barrier layer, and cover the non-display area.
  • the insulating glue is Taffeta blue glue.
  • the conductive adhesive is silver paste.
  • the chip-on-chip film is bound by the side edges, which effectively reduces the area of the non-display area of the display panel in the prior art, and realizes an ultra-narrow bezel display with the non-display area width less than 1 mm panel.
  • the barrier layer it is possible to prevent the conductive adhesive from overflowing during the bonding process and shorting the circuit between each bonding pad.
  • FIG. 1 is a top view of a first substrate according to an embodiment of the application.
  • 2 to 8 are structural diagrams of the manufacturing process of the first embodiment of the application.
  • Fig. 9 is a cross-sectional view taken along line A-A in Fig. 8.
  • Fig. 10 is a structural diagram of a second embodiment of the application.
  • the first substrate 100 includes a display area 121 of the display panel and a non-display area 122 of the display panel located at the periphery of the display area 121.
  • the dotted line in FIG. 1 represents the boundary line 123 between the display area 121 and the non-display area 122.
  • FIG. 2 to FIG. 8 Please refer to FIG. 2 to FIG. 8 for the manufacturing process structure diagram of the first embodiment of the present application.
  • Step S10 Provide the first substrate 100 as described above.
  • the first substrate 100 may be an array substrate of the display panel, which is not limited in this application.
  • the first substrate 100 also includes a thin film transistor 110.
  • step S20 disposing a plurality of binding pads 200 on the non-display area 122 on the first substrate 100.
  • the plurality of bonding pads 200 are electrically connected to the thin film transistor 110 and extend to the side edge 101 of the first substrate.
  • the plurality of bonding pads 200 are the circuit pins of the thin film transistor 110.
  • step S30 coating insulating glue 300 on the plurality of binding pads 200.
  • the insulating glue 300 is used to protect and insulate the plurality of binding pads 200.
  • the insulating glue 300 described in this application is Tuffy blue glue (tuffy blue glue), and can also be other insulating coatings, UV curing glue, or silica gel, which is not limited in this application.
  • step S40 apply a sealant 400 on the first substrate 100 along the boundary line 123 between the display area 121 and the non-display area 122.
  • the sealant 400 is a frame sealant of the display panel, and is used to surround the display area 121 to facilitate liquid crystal filling in a subsequent process.
  • step S50 forming a barrier layer 500 on the insulating glue 300.
  • Step S50 further includes step S51: coating a polystyrene (PS) layer on the insulating glue 300 to form the barrier layer 500. Since each of the binding pads 200 has a certain thickness, the terrain between each of the binding pads 200 is relatively low.
  • the insulating glue 300 coated in the step S30 is only used to protect and insulate the plurality of binding pads 200, and the surface of the insulating glue 300 after coating is still uneven. Therefore, the main purpose of this step is to flatten the insulating glue 300.
  • step S60 setting a second substrate 600 on the sealant 400.
  • the second substrate 600 may be a color film substrate (color film substrate) of the display panel. substrate), this application does not impose restrictions on this.
  • step S70 Coplanar side edges 101 of the first substrate 100, side edges 201 of the plurality of binding pads 200, side edges 301 of the insulating glue 300, and the barrier layer
  • the side edge 501 of 500 and the side edge 601 of the second substrate 600 are attached with a chip on film 700.
  • the side edge 601 of 600 is the edge of the display panel, and the edge of the display panel can be formed into a flat surface by machining methods such as grinding or cutting.
  • the chip on film 700 includes an anisotropic conductive film 710 coated with a conductive adhesive 720, and the side edges 201 of the plurality of bonding pads 200 are bound by the conductive adhesive 720 and the anisotropic conductive film 710 (Bonding) the chip on film 700, and each of the bonding pads 200 is electrically connected to the corresponding circuit on the chip on film 600, and then electrically connected to the driving circuit of the display panel to complete the display The side binding structure of the panel.
  • the conductive adhesive 720 described in the present application is a silver paste, which can have conductive and adhesive effects after curing or drying.
  • the conductive adhesive 720 may also be other conductive paint, copper paste, or resin with conductive powder, which is not limited in this application.
  • the display panel completed through the above process includes: the first substrate 100 having the thin film transistor 110, the display area 121, and the non-display area 122; and the non-display area disposed on the first substrate 100
  • FIG. 9 is a cross-sectional view of A-A in FIG.
  • the barrier layer 500 prevents the conductive glue 720 from overflowing in the direction of the insulating glue 300 during the bonding and bonding process of the chip on film 700, which prevents the conductive glue 720 from shorting each
  • the circuit between the bonding pads 200 effectively improves the process yield.
  • the manufacturing process of the second embodiment of the present application is similar to the first embodiment, and has the same steps S10 to S50 as the first embodiment.
  • the step S50 further includes a step S51: coating the sealant 400 of the step S40 on the insulating glue 300 to form the barrier layer 500 and cover the non-display area 122. Then, the step S60 and the step S70 that are the same as the first embodiment are performed.
  • step S51 of the second embodiment of the present application the sealant 400 of the step S40 is used on the first substrate 100 from the boundary of the display area 121 and the non-display area 122
  • the wire 123 is continuously coated and covers the non-display area 122 onto the insulating glue 300.
  • the design of step S51 is to prevent the conductive glue 720 from overflowing in the direction of the insulating glue 300, and to prevent the conductive glue 720 from shorting the gap between each of the binding pads 200.
  • the circuit on the other hand, also simplifies the process of forming the barrier layer 500.
  • the display panel completed through the above process includes: the first substrate 100 having the thin film transistor 110, the display area 121, and the non-display area 122; and the non-display area disposed on the first substrate 100
  • the side edge 101 of the substrate 100, the side edge 201 of the plurality of binding pads 200, the side edge 301 of the insulating glue 300, the side edge 501 of the barrier layer 500, and the side edge of the second substrate 600 601's flip chip film 700.

Abstract

一种显示面板及其制造方法。显示面板包括第一基板（100）、多个绑定垫（200）、绝缘胶（300）、密封胶（400）、阻挡层（500）、第二基板（600）、覆晶薄膜（700）。显示面板将覆晶薄膜通过侧缘绑定的方式，有效缩小现有技术的显示面板非显示区的面积，实现非显示区宽度小于1mm的超窄边框显示面板。同时，通过阻挡层的设计，能够避免绑定过程中导电胶溢胶而短接每一绑定垫之间的电路。

Description

显示面板的侧缘绑定结构及其制造方法 技术领域
本申请涉及显示面板技术领域，特别是涉及一种显示面板的侧缘绑定结构及其制造方法。
 背景技术
随着科技日益进步，智能手机、平版电脑、穿戴型装置等电子产品也渐渐普及，而这些装置无一不需要显示面板。而显示面板还包括显示区及非显示区；为了满足市场上所称之全面屏、在有限的装置体积中取得更大的屏幕尺寸，就必须将显示面板的显示区最大化、并且缩小非显示区的面积。
在传统的显示面板中，显示面板的驱动芯片是直接设置在显示面板的基板上（chip on glass，COG）。由于显示面板周缘设置了驱动芯片，这块区域便无法作为显示区，所以采用COG工艺的显示面板的非显示区较大、显示面板的边框也较粗。
覆晶薄膜（chip on film，COF）改良了前者技术，其将传统显示面板非显示区上的驱动电路设置在连接显示面板的柔性电路板上，便能适度的缩小非显示区的面积。
 技术问题
采用COF工艺能适度缩小显示面板的非显示区，但非显示区仍需要留有绑定（bonding）柔性电路板电路接脚的区域，而这也限制了非显示区的缩小极限。因此需要一种改良COF工艺的绑定结构或技术，来解决目前非显示区缩小的极限，取得更小的非显示区、实现超窄边框的显示面板。
 技术解决方案
为解决上述问题，本申请提供一种显示面板，包括第一基板、多个绑定垫、绝缘胶、密封胶、阻挡层、第二基板、覆晶薄膜。所述第一基板包括薄膜晶体管、显示区、以及位于所述显示区外围的非显示区。所述多个绑定垫设置于所述第一基板上的所述非显示区，电性连接所述薄膜晶体管，并且延伸至所述第一基板的侧缘。所述绝缘胶涂布于所述多个绑定垫上。所述密封胶沿所述显示区与所述非显示区的交界线涂布于所述第一基板上。所述阻挡层设置在所述绝缘胶上。以及所述第二基板设置在所述密封胶上。其中，所述第一基板的侧缘、所述多个绑定垫的侧缘、所述绝缘胶的侧缘、所述阻挡层的侧缘、以及所述第二基板的侧缘共平面。
在本申请所述的显示面板中，所述覆晶薄膜设置于共平面的所述第一基板的侧缘、所述多个绑定垫的侧缘、所述绝缘胶的侧缘、所述阻挡层的侧缘、以及所述第二基板的侧缘。其中，所述覆晶薄膜包括涂布有导电胶的异方性导电薄膜，所述多个绑定垫的侧缘通过所述导电胶及所述异方性导电薄膜绑定所述覆晶薄膜，并且每一所述绑定垫电性连接所述覆晶薄膜上对应的电路。以及当所述多个绑定垫的侧缘绑定所述覆晶薄膜时，所述阻挡层阻止所述导电胶溢胶，使得每一所述绑定垫之间的电路彼此绝缘。
在本申请所述的显示面板中，所述第一基板的侧缘、所述多个绑定垫的侧缘、所述绝缘胶的侧缘、所述阻挡层的侧缘、以及所述第二基板的侧缘包括平整的表面。
在本申请所述的显示面板中，一实施例的所述阻挡层为聚苯乙烯层。
在本申请所述的显示面板中，另一实施例的所述阻挡层与所述密封胶为相同材料，并且所述密封胶覆盖所述非显示区。
在本申请所述的显示面板中，所述绝缘胶为塔菲蓝胶。
在本申请所述的显示面板中，所述导电胶为银浆。
本申请还提供一种显示面板制造方法，包括以下步骤：
步骤S10：提供第一基板，包括薄膜晶体管、显示区、以及位于所述显示区外围的非显示区。
步骤S20：在所述第一基板上的所述非显示区设置多个绑定垫，所述多个绑定垫电性连接所述薄膜晶体管并延伸至所述第一基板的侧缘。
步骤S30：在所述多个绑定垫上涂布绝缘胶。
步骤S40：在所述第一基板上沿所述显示区与所述非显示区的交界线涂布密封胶。
步骤S50：在所述绝缘胶上形成阻挡层。以及
步骤S60：在所述密封胶上设置第二基板。
其中，所述第一基板的侧缘、所述多个绑定垫的侧缘、所述绝缘胶的侧缘、所述阻挡层的侧缘、以及所述第二基板的侧缘共平面。
在本申请所述的显示面板制造方法中，还包括以下步骤：
步骤S70：在共平面的所述第一基板的侧缘、所述多个绑定垫的侧缘、所述绝缘胶的侧缘、所述阻挡层的侧缘、以及所述第二基板的侧缘贴附覆晶薄膜。
其中，所述覆晶薄膜包括涂布有导电胶的异方性导电薄膜，所述多个绑定垫的侧缘通过所述导电胶及所述异方性导电薄膜绑定所述覆晶薄膜，并且每一所述绑定垫电性连接所述覆晶薄膜上对应的电路。以及当所述多个绑定垫的侧缘绑定所述覆晶薄膜时，所述阻挡层阻止所述导电胶溢胶，使得每一所述绑定垫之间的电路彼此绝缘。
在本申请所述的显示面板制造方法中，所述第一基板的侧缘、所述多个绑定垫的侧缘、所述绝缘胶的侧缘、所述阻挡层的侧缘、以及所述第二基板的侧缘通过打磨或是切割形成一个平整的表面。
在本申请所述的显示面板制造方法中，一实施例的所述步骤S50还包括以下步骤：
步骤S51：在所述绝缘胶上涂布聚苯乙烯层形成所述阻挡层。
在本申请所述的显示面板制造方法中，另一实施例的所述步骤S50还包括以下步骤：
步骤S51：在所述绝缘胶上涂布所述步骤S40的所述密封胶形成所述阻挡层，并且覆盖所述非显示区。
在本申请所述的显示面板制造方法中，所述绝缘胶为塔菲蓝胶。
在本申请所述的显示面板制造方法中，所述导电胶为银浆。
 有益效果
本申请的所述显示面板将所述覆晶薄膜通过侧缘绑定的方式，有效缩小现有技术的显示面板非显示区的面积，实现所述非显示区宽度小于1 mm的超窄边框显示面板。同时，通过阻挡层的设计，能够避免绑定过程中所述导电胶溢胶而短接每一所述绑定垫之间的电路。
 附图说明
图1为本申请实施例的第一基板上视图。
图2～图8为本申请第一实施例的制造流程结构图。
图9为图8中的A-A剖面图。
图10为本申请第二实施例的结构图。
本申请的实施方式
藉由以下具体实施例之详述，更加清楚描述本申请之特征与精神，而并非以所揭露的具体实施例来对本申请之范畴加以限制。相反地，其目的是希望能涵盖各种改变及具相等性的安排于本申请所欲申请之权利要求的范畴内。
请参照图1，在本申请实施例的显示面板中，第一基板100包括所述显示面板的显示区121及位于所述显示区121外围的所述显示面板的非显示区122。图1中的虚线表示所述显示区121与非显示区122的交界线123。
第一实施例：
本申请第一实施例的制造流程结构图请参照图2～图8。
首先请参照图2，步骤S10：提供如前所述的第一基板100。所述第一基板100可以是所述显示面板的阵列基板（array substrate），本申请对此不做限制。所述第一基板100除了包括所述显示区121、所述非显示区122、以及所述交界线123之外，还包括薄膜晶体管110。
请参照图3，步骤S20：在所述第一基板100上的所述非显示区122设置多个绑定垫200。所述多个绑定垫200电性连接所述薄膜晶体管110，并且延伸至所述第一基板的侧缘101。所述多个绑定垫200即是所述薄膜晶体管110的电路接脚。
请参照图4，步骤S30：在所述多个绑定垫200上涂布绝缘胶300。所述绝缘胶300用以保护、绝缘所述多个绑定垫200。本申请所述绝缘胶300为塔菲蓝胶（tuffy blue glue），也可以是其他绝缘涂料、UV固化胶、或是硅胶，本申请对此不做限制。
请参照图5，步骤S40：在所述第一基板100上沿所述显示区121与所述非显示区122的所述交界线123涂布密封胶400。所述密封胶400为所述显示面板的框胶（frame sealant），用于包围所述显示区121，以利后续的制程的液晶填充。
请参照图6，步骤S50：在所述绝缘胶300上形成阻挡层500。在步骤S50中还包括步骤S51：在所述绝缘胶300上涂布聚苯乙烯（polystyrene，PS）层形成所述阻挡层500。由于每个所述绑定垫200具有一定厚度，所以在每个所述绑定垫200之间的地势较低。在所述步骤S30涂布的所述绝缘胶300仅用以保护、绝缘所述多个绑定垫200，而涂布后的所述绝缘胶300表面仍为凹凸不平整。因此，本步骤主要目的在于将所述绝缘胶300平整化。
请参照图7，步骤S60：在所述密封胶400上设置第二基板600。所述第二基板600可以是所述显示面板的彩膜基板（color film substrate），本申请对此不做限制。
请参照图8，步骤S70：在共平面的所述第一基板100的侧缘101、所述多个绑定垫200的侧缘201、所述绝缘胶300的侧缘301、所述阻挡层500的侧缘501、以及所述第二基板600的侧缘601贴附覆晶薄膜700。所述第一基板100的侧缘101、所述多个绑定垫200的侧缘201、所述绝缘胶300的侧缘301、所述阻挡层500的侧缘501、以及所述第二基板600的侧缘601是为所述显示面板的边缘，可以利用打磨（grinding）或是切割（cutting）等机械加工方式将所述显示面板的边缘形成一个平整的表面。
所述覆晶薄膜700包括涂布有导电胶720的异方性导电薄膜710，所述多个绑定垫200的侧缘201通过所述导电胶720及所述异方性导电薄膜710绑定（bonding）所述覆晶薄膜700，并且每一所述绑定垫200电性连接所述覆晶薄膜600上对应的电路，进而电性连接起所述显示面板的驱动电路，完成所述显示面板的侧面绑定结构。本申请所述导电胶720为银（silver）浆，在固化或干燥后能具有导电及黏着效果。所述导电胶720也可以是其他导电涂料、铜（copper）浆、或是参有导电粉末的树脂，本申请对此不做限制。
通过以上制程完成的所述显示面板包括：具有所述薄膜晶体管110、所述显示区121、以及非显示区122的所述第一基板100；设置于所述第一基板100上的所述非显示区122的所述多个绑定垫200；涂布于所述多个绑定垫200上的所述绝缘胶300；涂布于所述第一基板100上的所述密封胶400；设置在所述绝缘胶300上的所述阻挡层500；设置在所述密封胶400上的所述第二基板600；以及设置于共平面的所述第一基板100的侧缘101、所述多个绑定垫200的侧缘201、所述绝缘胶300的侧缘301、所述阻挡层500的侧缘501、以及所述第二基板600的侧缘601的覆晶薄膜700。
请参照图9，图9为图8中的A-A剖面图，从上视的角度剖视所述显示面板。所述阻挡层500在所述覆晶薄膜700绑定压合的过程中，阻止所述导电胶720朝向所述绝缘胶300的方向溢胶，也就防止所述导电胶720短接每一所述绑定垫200之间的电路，有效提升制程良率。
第二实施例：
本申请第二实施例的制造流程与所述第一实施例近似，具有与第一实施例相同的所述步骤S10～所述步骤S50。
请参照图10，所述步骤S50还包括步骤S51：在所述绝缘胶300上涂布所述步骤S40的所述密封胶400形成所述阻挡层500，并且覆盖所述非显示区122。接著进行与第一实施例相同的所述步骤S60及所述步骤S70。
在本申请第二实施例的所述步骤S51中，即是利用所述步骤S40的所述密封胶400在所述第一基板100上自所述显示区121与所述非显示区122的交界线123连续涂布、覆盖所述非显示区122至所述绝缘胶300上。第二实施例对所述步骤S51的设计，一方面阻止所述导电胶720朝向所述绝缘胶300的方向溢胶、防止所述导电胶720短接每一所述绑定垫200之间的电路，另一方面也简化所述阻挡层500形成的过程。
通过以上制程完成的所述显示面板包括：具有所述薄膜晶体管110、所述显示区121、以及非显示区122的所述第一基板100；设置于所述第一基板100上的所述非显示区122的所述多个绑定垫200；涂布于所述多个绑定垫200上的所述绝缘胶300；涂布于所述第一基板100上的所述密封胶400；设置在所述绝缘胶300上并且与所述密封胶400连成一体的所述阻挡层500；设置在所述密封胶400上的所述第二基板600；以及设置于共平面的所述第一基板100的侧缘101、所述多个绑定垫200的侧缘201、所述绝缘胶300的侧缘301、所述阻挡层500的侧缘501、以及所述第二基板600的侧缘601的覆晶薄膜700。
虽然本申请已用优选实施例揭露如上，然其并非用以限定本申请，本申请所属技术领域中具有通常知识者，在不脱离本申请之精神和范围内，当可作各种之更动与润饰，因此本申请之保护范围当视权利要求书所界定范围为准。

Claims (18)

  1. 一种显示面板，包括：
    第一基板，包括薄膜晶体管、显示区、以及位于所述显示区外围的非显示区；
    多个绑定垫，设置于所述第一基板上的所述非显示区，所述多个绑定垫电性连接所述薄膜晶体管，并且延伸至所述第一基板的侧缘；
    绝缘胶，涂布于所述多个绑定垫上；
    密封胶，沿所述显示区与所述非显示区的交界线涂布于所述第一基板上；
    阻挡层，设置在所述绝缘胶上；以及
    第二基板，设置在所述密封胶上；
    其中，所述第一基板的侧缘、所述多个绑定垫的侧缘、所述绝缘胶的侧缘、所述阻挡层的侧缘、以及所述第二基板的侧缘共平面。
  2. 如权利要求1所述的显示面板，还包括：
    覆晶薄膜，设置于共平面的所述第一基板的侧缘、所述多个绑定垫的侧缘、所述绝缘胶的侧缘、所述阻挡层的侧缘、以及所述第二基板的侧缘；
    其中，所述覆晶薄膜包括涂布有导电胶的异方性导电薄膜，所述多个绑定垫的侧缘通过所述导电胶及所述异方性导电薄膜绑定所述覆晶薄膜，并且每一所述绑定垫电性连接所述覆晶薄膜上对应的电路；以及
    当所述多个绑定垫的侧缘绑定所述覆晶薄膜时，所述阻挡层阻止所述导电胶溢胶，使得每一所述绑定垫之间的电路彼此绝缘。
  3. 如权利要求1所述的显示面板，其中，所述第一基板的侧缘、所述多个绑定垫的侧缘、所述绝缘胶的侧缘、所述阻挡层的侧缘、以及所述第二基板的侧缘包括平整的表面。
  4. 如权利要求1所述的显示面板，其中，所述阻挡层为聚苯乙烯层。
  5. 如权利要求4所述的显示面板，其中，所述绝缘胶为塔菲蓝胶。
  6. 如权利要求4所述的显示面板，其中，所述导电胶为银浆。
  7. 如权利要求1所述的显示面板，其中，所述阻挡层与所述密封胶为相同材料，并且所述密封胶覆盖所述非显示区。
  8. 如权利要求7所述的显示面板，其中，所述绝缘胶为塔菲蓝胶。
  9. 如权利要求7所述的显示面板，其中，所述导电胶为银浆。
  10. 一种显示面板制造方法，包括以下步骤：
    步骤S10：提供第一基板，包括薄膜晶体管、显示区、以及位于所述显示区外围的非显示区；
    步骤S20：在所述第一基板上的所述非显示区设置多个绑定垫，所述多个绑定垫电性连接所述薄膜晶体管，并且延伸至所述第一基板的侧缘；
    步骤S30：在所述多个绑定垫上涂布绝缘胶；
    步骤S40：在所述第一基板上沿所述显示区与所述非显示区的交界线涂布密封胶；
    步骤S50：在所述绝缘胶上形成阻挡层；以及
    步骤S60：在所述密封胶上设置第二基板；
    其中，所述第一基板的侧缘、所述多个绑定垫的侧缘、所述绝缘胶的侧缘、所述阻挡层的侧缘、以及所述第二基板的侧缘共平面。
  11. 如权利要求10所述的显示面板制造方法，还包括以下步骤：
    步骤S70：在共平面的所述第一基板的侧缘、所述多个绑定垫的侧缘、所述绝缘胶的侧缘、所述阻挡层的侧缘、以及所述第二基板的侧缘贴附覆晶薄；
    其中，所述覆晶薄膜包括涂布有导电胶的异方性导电薄膜，所述多个绑定垫的侧缘通过所述导电胶及所述异方性导电薄膜绑定所述覆晶薄膜，并且每一所述绑定垫电性连接所述覆晶薄膜上对应的电路；以及
    当所述多个绑定垫的侧缘绑定所述覆晶薄膜时，所述阻挡层阻止所述导电胶溢胶，使得每一所述绑定垫之间的电路彼此绝缘。
  12. 如权利要求10所述的显示面板制造方法，其中，所述第一基板的侧缘、所述多个绑定垫的侧缘、所述绝缘胶的侧缘、所述阻挡层的侧缘、以及所述第二基板的侧缘通过打磨或是切割形成一个平整的表面。
  13. 如权利要求10所述的显示面板制造方法，其中，所述步骤S50还包括以下步骤：
    步骤S51：在所述绝缘胶上涂布聚苯乙烯层形成所述阻挡层。
  14. 如权利要求13所述的显示面板制造方法，其中，所述绝缘胶为塔菲蓝胶。
  15. 如权利要求13所述的显示面板制造方法，其中，所述导电胶为银浆。
  16. 如权利要求10所述的显示面板制造方法，其中，所述步骤S50还包括以下步骤：
    步骤S51：在所述绝缘胶上涂布所述步骤S40的所述密封胶形成所述阻挡层，并且覆盖所述非显示区。
  17. 如权利要求16所述的显示面板制造方法，其中，所述绝缘胶为塔菲蓝胶。
  18. 如权利要求16所述的显示面板制造方法，其中，所述导电胶为银浆。
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TWI737520B (zh) * 2020-08-14 2021-08-21 友達光電股份有限公司 顯示面板
CN113568224B (zh) * 2020-08-14 2022-10-21 友达光电股份有限公司 显示装置
CN112526792A (zh) * 2020-11-24 2021-03-19 北海惠科光电技术有限公司 一种显示面板、显示装置及其制作方法
CN113066363B (zh) * 2021-03-09 2023-10-17 Tcl华星光电技术有限公司 显示面板及其制作方法
CN112946962A (zh) * 2021-03-09 2021-06-11 Tcl华星光电技术有限公司 显示面板及其制作方法
CN113299852B (zh) * 2021-05-11 2022-12-06 深圳市华星光电半导体显示技术有限公司 显示面板
CN115407539A (zh) * 2021-05-28 2022-11-29 福州京东方光电科技有限公司 显示面板及显示装置
CN113421489B (zh) * 2021-06-08 2022-07-12 Tcl华星光电技术有限公司 显示面板及其制作方法、显示装置
CN114019706B (zh) * 2021-10-21 2023-03-28 武汉华星光电技术有限公司 显示面板及显示面板制作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108153070A (zh) * 2017-12-29 2018-06-12 惠州市华星光电技术有限公司 一种液晶面板及其制作方法、显示装置
CN109426018A (zh) * 2017-08-22 2019-03-05 京东方科技集团股份有限公司 基板及其制造方法、显示面板、拼接屏
CN110007534A (zh) * 2019-04-09 2019-07-12 深圳市华星光电技术有限公司 一种液晶显示面板及其制备方法
CN110277018A (zh) * 2019-06-24 2019-09-24 武汉华星光电技术有限公司 显示面板及其制备方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109426018A (zh) * 2017-08-22 2019-03-05 京东方科技集团股份有限公司 基板及其制造方法、显示面板、拼接屏
CN108153070A (zh) * 2017-12-29 2018-06-12 惠州市华星光电技术有限公司 一种液晶面板及其制作方法、显示装置
CN110007534A (zh) * 2019-04-09 2019-07-12 深圳市华星光电技术有限公司 一种液晶显示面板及其制备方法
CN110277018A (zh) * 2019-06-24 2019-09-24 武汉华星光电技术有限公司 显示面板及其制备方法

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