WO2021135180A1 - 一种存储器阵列结构 - Google Patents

一种存储器阵列结构 Download PDF

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WO2021135180A1
WO2021135180A1 PCT/CN2020/103763 CN2020103763W WO2021135180A1 WO 2021135180 A1 WO2021135180 A1 WO 2021135180A1 CN 2020103763 W CN2020103763 W CN 2020103763W WO 2021135180 A1 WO2021135180 A1 WO 2021135180A1
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column
row
lead
switch
memory
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PCT/CN2020/103763
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English (en)
French (fr)
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沈灵
蒋宇
严慧婕
李志芳
董林妹
段杰斌
温建新
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上海集成电路研发中心有限公司
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Priority to US17/784,652 priority Critical patent/US20230005990A1/en
Publication of WO2021135180A1 publication Critical patent/WO2021135180A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors

Definitions

  • the present invention relates to the technical field of integrated circuit design, in particular to a memory array structure applied to in-memory operations.
  • AI artificial intelligence
  • MAC multiplication and addition
  • the traditional computing processing system is a general-purpose system, and there is no special optimization for the computing requirements of artificial intelligence.
  • the traditional arithmetic processing system adopts the Von Neumann structure, its arithmetic and storage areas are separated, so there will be a bottleneck problem in data transmission.
  • a commonly proposed solution is to combine storage and operation, and run some operations directly on the storage side.
  • This method mainly utilizes the resistance characteristic of the memory to realize the simulated in-memory (in-memory) operation.
  • FIG. 1 is a schematic diagram of an existing storage structure, which shows a basic topology structure of a storage-calculation neural network without a control end.
  • the storage structure uses a crossbar architecture.
  • the memory array is composed of several rows and columns, each row and column has a separate lead line, and a memory device 10 is correspondingly provided at the intersection of each row lead line r and column lead line c.
  • the positive electrode of each storage device 10 is individually connected to the row lead-out line r of its row, and the negative electrode is connected to the column lead-out line c of its column.
  • the disadvantage of this structure is that it cannot effectively solve the problem of the sneak path, which will cause a great waste of power consumption.
  • a switch 11 is added at each cross point of the cross matrix of Fig. 1 at the same time, so that the positive pole of each storage device 10 is individually connected to the row lead r of the row where it is located, and the negative pole passes through the switch 11. It is connected to the column lead line c of the column, although the leakage problem can be solved, but it will increase the area of the entire matrix.
  • both of the above two structures have the problem that the entire matrix or the storage operation units in the same row are required to be turned on during operation, which not only causes the loss of power consumption, but also limits the application scenarios of the entire operation storage matrix.
  • the purpose of the present invention is to overcome the above-mentioned defects in the prior art and provide a memory array structure.
  • the present invention provides a memory array structure, which is composed of a plurality of memory devices in rows and columns.
  • Each row of the array is provided with a row lead-out line
  • each column is provided with a column lead-out line
  • the storage device corresponds to It is located at the intersection of each row lead-out line and the column lead-out line; wherein, the first end of each storage device is individually connected to the row lead-out line of the row where each storage device is located.
  • the second end is connected to the first end of a switch in the same column, and the second end of the switch is connected to the column lead wire of the column in which it is located; wherein each column is provided with one or more switches, and each switch The first end of is connected to the second ends of one to all of the storage devices in the same column.
  • the switch is provided with a control terminal
  • each row of the array is provided with a control lead-out line
  • the control terminals of the switches located in different columns in the same row are connected to the control lead-out line in the same row.
  • the control terminals of the switches in the same column are respectively connected to the control lead wires of different rows.
  • control lead-out line is arranged in parallel with the row lead-out line.
  • the on-resistance of the switch is smaller than the parallel resistance when all the storage devices in the same column connected to it are in a low resistance state, and the off-resistance of the switch is higher than that of any one of the storage devices in the same column connected to it.
  • the resistance value in the high resistance state is smaller than the parallel resistance when all the storage devices in the same column connected to it are in a low resistance state, and the off-resistance of the switch is higher than that of any one of the storage devices in the same column connected to it.
  • the storage device is a non-volatile storage device.
  • the storage device is a resistive random access memory
  • a first terminal of the memory device is a positive electrode of the resistive random access memory
  • a second terminal of the memory device is a negative electrode of the resistive random access memory
  • the positive electrode of the resistive random access memory is the top electrode of the resistive random access memory
  • the negative electrode of the resistive random access memory is the bottom electrode of the resistive random access memory
  • the switch is an NMOS device
  • the first terminal or the second terminal of the switch is the source terminal or the drain terminal of the NMOS device
  • the control terminal of the switch is the gate of the NMOS device.
  • each of the row lead wires is not opened at the same time.
  • control lead wires of each row are not opened at the same time.
  • the advantage of the present invention is that the present invention can obtain the corresponding analog current output of the signal input of different rows specified according to the multiplication and addition operation requirements of each column in the same time, realize the multiplication and addition operations of different scales and different input signals, greatly Improve the operation speed and the efficiency of array usage.
  • Fig. 1 is a schematic diagram of a basic topology structure of an existing storage-calculation neural network without a control end.
  • Figure 2 is a schematic diagram of the basic topology of an existing storage-computing neural network with a control terminal
  • FIG. 3 is a schematic diagram of the topological structure of a memory-computing neural network of a memory array structure according to a preferred embodiment 1 of the present invention.
  • FIG. 4 is a schematic diagram of a topological structure of a memory-computing neural network of a memory array structure according to a preferred embodiment 2 of the present invention.
  • FIG. 3 is a schematic diagram of the topological structure of a memory-computing neural network of a memory array structure according to a preferred embodiment 1 of the present invention.
  • the present invention provides a new type of memory array structure applied to in-memory operations.
  • the memory array structure is composed of a plurality of storage devices 20 arranged in rows and columns, such as a 6 ⁇ 6 array shown in the figure.
  • the memory array structure of the present invention is a matrix structure.
  • the core feature that is different from the normal matrix structure of FIG. 2, for example, is that there are multiple memory devices 20 in different rows in the same column, which can be connected to the same switch 21.
  • the control leads of the switches 21 are independent of each other, and can share the control leads with the switches 21 of other columns.
  • the electrical devices inside the memory array structure are mainly composed of memory cells (memory devices 20) and switches 21.
  • Each row in the array is provided with a row lead-out line R, and each column is provided with a column lead-out line C.
  • the memory device 20 is correspondingly located at the intersection of each row lead-out line R and column lead-out line C; at the same time, there are one or more switches 21 in each column.
  • each storage device 20 is individually connected to the row lead R of the row where the storage device 20 is located, and the second end of each storage device 20 is connected to the first end of a certain switch 21 in the same column.
  • the second end of 21 is connected to the column lead line C of the column where it is located.
  • switches 21 there can be one or more switches 21 in each column of the array, and the first end of each switch 21 can be connected to the second end of one or more storage devices 20 in the same column, or even all the storage devices 20 in the same column. The second end.
  • the switch 21 can be provided with at least one control terminal; each row of the array can be provided with a control lead S.
  • the control terminals of the switches 21 in different columns in the same row are connected to the control lead wires S in the same row; the control terminals of the switches 21 in the same column are respectively connected to the control lead wires S in different rows. That is, on each control lead wire S, one or more control terminals of the switch 21 can be connected, but at most one switch 21 in the same column is connected.
  • control lead-out line S can be arranged in parallel with the row lead-out line R.
  • the storage unit (storage device 20) may be a two-terminal or multi-terminal non-volatile storage device, and its main feature is that it exhibits two or more resistance characteristics under the same external electrical signal conditions.
  • the row and column two lead-out lines are related to the memory cell.
  • the first end (defined as the positive electrode) of the storage device 20 is directly connected to the row lead-out line R, and the first end of the storage device 20 is directly connected to the row lead-out line R.
  • the two ends (defined as the negative electrode) are connected to the column lead line C through the switch 21.
  • each floating gate device has a gate, a source, and a drain, that is, there are three terminals.
  • the two ends of the source and the drain can be used as two ends with resistance characteristics, and there is a common voltage control signal for the gates of each row.
  • the voltage control signal needs to be loaded with an appropriate level so that the floating gate device can be in a normal readout state.
  • the control signal must exist, it has no direct relationship with the arithmetic logic of the architecture, so it is not reflected in the array structure.
  • the switch 21 has at least one open/close control terminal, and two ends (first end and second end) that can be opened or closed.
  • the opening and closing control terminal is used to input external control signals, and the function is to make the switch 21 open or close.
  • the on-resistance of the switch 21 is much smaller than the parallel resistance value when all the storage devices 20 in the same column connected to it are in the low resistance state, and the off resistance of the switch 21 is higher than the resistance value of any storage device 20 in the same column connected to it in the high-resistance state. . That is, the requirement for the resistance characteristic of the switch 21 is that the resistance when it is turned on is much smaller than the parallel value of the lowest possible resistance of several storage devices 20, and the resistance when it is turned off is much higher than the highest possible resistance of the storage device 20.
  • each row lead wire R adds an analog or digital voltage signal
  • each column lead wire C adds a fixed analog or digital voltage signal
  • each control lead wire S adds a digital The voltage signal is used to determine whether the switch 21 is on or off.
  • the lead lines R of each row may not be opened at the same time.
  • the control lead wire S of each row may not be opened at the same time.
  • the analog output current value of each column is the voltage difference between the row voltage of the memory cell connected to the switch 21 of the column and the column voltage divided by the sum of all currents of the cell resistance.
  • the advantage of the above structure of the present invention is that the corresponding analog current output of the signal input of different rows specified according to the multiplication and addition operation requirements of each column can be obtained in the same time.
  • the present invention also has some differences in peripheral control, and can be configured according to special applications.
  • FIG. 4 is a schematic diagram of a topological structure of a memory-computing neural network of a memory array structure according to a preferred embodiment 2 of the present invention. As shown in FIG. 4, it exemplarily introduces a 6 ⁇ 6 array architecture based on resistive random access memory cells (resistive random access memory) (RRAM).
  • RRAM resistive random access memory
  • the row lead-out line R and the column lead-out line C are used as the basis for dividing the array size, the array is composed of 6 rows (row lead-out lines R 1 -R 6 ) and 6 columns (column lead-out lines C 1 ⁇ C 6 ), which exist at the same time 6 switches control the lead wires S 1 to S 6 .
  • the storage device 20 is selected as an RRAM device
  • the switch 21 is selected as an NMOS device in the CMOS process (PMOS can also be used in theory, but compared to NMOS, the area cost will be high).
  • the RRAM device 20 is a two-terminal device with a top electrode (anode) and a bottom electrode (anode), and it has two resistance states: a high-resistance state and a low-resistance state.
  • the NMOS device 21 is connected to one of the switches to control the voltage level of the gate of the lead wire S to control the on and off of both ends of the source and drain.
  • the on-resistance of the NMOS device switch 21 is much smaller than the low-resistance of the RRAM device 20, and its off-resistance is much higher than the high-resistance of the RRAM device 20.
  • RRAM cells 20 there are 6 RRAM cells 20 in each row and each column. There are one to several switches 21 in each column.
  • the top electrode of the RRAM device 20 of each row is connected to the row lead-out line R of the row
  • the drain terminal of each switch 21 is connected to the bottom electrode of one or more RRAM devices 20 of the column
  • the source terminal is connected to the column lead-out line C of the column.
  • the gate is connected to a certain control lead wire S.
  • the RRAM cells 20 connected to the same switch 21 in a column are defined as an RRAM cluster together with the switch 21, which is represented by the letter A.
  • RRAM clusters A 1 to A 15 there are a total of 15 RRAM clusters A 1 to A 15 .
  • a 1 has 3 RRAM cells 20, and the switch control lead wire is S 1 ;
  • a 2 has 3 RRAM cells 20, and the switch control lead wire is S 4 .
  • a 3 has three RRAM cells 20 and the switch control lead line is S 3 ;
  • a 4 has three RRAM cells 20 and the switch control lead line is S 5 .
  • RRAM clusters A 5 and A 6 there are two RRAM clusters A 5 and A 6 , A 5 has 5 RRAM cells 20, and the switch control lead wire is S 3 ; A 6 has 1 RRAM cell 20 and the switch control lead wire is S 6 .
  • RRAM clusters A 7 and A 8 there are two RRAM clusters A 7 and A 8 , A 7 has two RRAM cells 20, and the switch control lead wire is S 2 ; A 8 has 4 RRAM cells 20 and the switch control lead wire is S 6 .
  • the row lead wires R 1 to R 6 are used as input signal terminals, and the column lead wires C 1 to C 6 are used as output signal terminals. It can be divided into analog or digital signal transmission methods. The multiplication and addition calculations of the two methods are similar.
  • lead row R 1 ⁇ R 6 are each loading end of an analog voltage, in column C 1 ⁇ C 6 lead to load each one and the same analog voltage, then the lead column C 1 ⁇ C 6 The current at the end is the sum of the currents flowing through the RRAM cells 20 of the strobed RRAM cluster A, which is equivalent to performing two operations of multiplication and addition at the same time.
  • the corresponding control lead wire does not only control one RRAM cell in each column, but can select different rows in each column of the switch according to needs. And different numbers of RRAM cells.
  • the advantage of this is that when doing multiplication and addition operations, the items that can be multiplied in each column can be different. In this way, through reasonable signal input and reasonable control terminal input, multiplication and addition operations of different scales and different input signals can be made at the same time, which greatly improves the calculation speed and the efficiency of the array.

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Abstract

本发明公开了一种存储器阵列结构，由多个存储器件按行列组成阵列，阵列的每行设有行引出线，每列设有列引出线，存储器件对应位于每个行引出线与列引出线的交叉点处；其中，每个存储器件的第一端单独与其所在行的行引出线连接，每个存储器件的第二端与处于同列的一个开关的第一端连接，开关的第二端与其所在列的列引出线连接；其中，每列设有一至多个开关，每个开关的第一端连接处于同列的一至全部存储器件的第二端。本发明能够在同一个时间内获得根据每一列的乘加运算需求指定的不同行的信号输入的相应的模拟电流输出，实现不同规模不同输入信号的乘加运算，极大提高了运算速度和阵列使用效率。

Description

一种存储器阵列结构
交叉引用
本申请要求2019年12月30日提交的申请号为CN201911388598.5的中国专利申请的优先权。上述申请的内容以引用方式被包含于此。
技术领域
本发明涉及集成电路设计技术领域，特别是涉及一种应用于存内运算的存储器阵列结构。
技术背景
人工智能(AI)的发展对传统的运算处理系统提出了新的需求，主要的问题在于人工智能网络的运算量大，数据多，而且运算的需求比较集中，多数的运算主要在于乘加上(MAC)上。
传统的运算处理系统是通用的系统，对人工智能的运算需求没有专门的优化。此外，由于传统的运算处理系统采用的是冯诺依曼结构，其运算和存储区域是分开的，所以会存在数据传输的瓶颈问题。
现在普遍提出的一种解决方法是将存储和运算结合起来，直接在存储端运行部分的运算。该方法主要是利用存储器的电阻特性，实现模拟的存内(存储器内部)运算。
请参考图1，图1是现有的一种存储结构示意图，其显示一种无控制端的存算神经网络的基本拓扑架构。如图1所示，该存储结构采用了交叉矩阵(crossbar)架构。其存储器阵列由若干行列组成，每个行和列均存在单独 的引出线，并且在每个行引出线r与列引出线c的交叉点处都对应设有一个存储器件10。其中，每一个存储器件10的正极单独与其所在行的行引出线r连接，负极与其所在列的列引出线c连接。这种结构的缺点在于无法有效解决漏电通路(sneak path)的问题，会造成极大的功耗浪费。
如果如图2所示，在上述图1的交叉矩阵的每一个交叉点上同时再增加一个开关11，使每一个存储器件10的正极单独与其所在行的行引出线r连接，负极通过开关11与其所在列的列引出线c连接，虽然可以解决漏电问题，但是会增大整个矩阵的面积。
此外，以上两种结构都存在运算时需要整个矩阵或者处于相同行的存储运算单元都打开的问题，不仅会造成功耗的损失，同时也限制了整个运算存储矩阵的应用场景。
因此，需要提出一种不仅能够节省面积和功耗，同时具备灵活开关控制的存储器矩阵架构。
发明概要
本发明的目的在于克服现有技术存在的上述缺陷，提供一种存储器阵列结构。
为达成上述目的，本发明提供了一种存储器阵列结构，由多个存储器件按行列组成阵列，所述阵列的每行设有行引出线，每列设有列引出线，所述存储器件对应位于每个所述行引出线与所述列引出线的交叉点处；其中，每个所述存储器件的第一端单独与其所在行的所述行引出线连接，每个所述存储器件的第二端与处于同列的一个开关的第一端连接，所述开关的第二端与其所在列的所述列引出线连接；其中，每列设有一至多个所述开关，每个所述开关的第一端连接处于同列的一至全部所述存储器件的第二端。
进一步地，所述开关设有控制端，所述阵列的每行设有控制引出线，位于同一行中不同列的所述开关的所述控制端共同连接在所在行的所述控制引出线上，处于同列的各所述开关的所述控制端分别连接在不同行的所述控制引出线上。
进一步地，所述控制引出线与所述行引出线平行设置。
进一步地，所述开关的导通电阻小于其连接的同列全部所述存储器件处于低阻态时的并联电阻值，所述开关的关断电阻高于其连接的同列任意一个所述存储器件处于高阻态时的电阻值。
进一步地，所述存储器件为非易失存储器件。
进一步地，所述存储器件为阻变式存储器，所述存储器件的第一端为所述阻变式存储器的正极，所述存储器件的第二端为所述阻变式存储器的负极。
进一步地，所述阻变式存储器的正极为所述阻变式存储器的顶电极，所述阻变式存储器的负极为所述阻变式存储器的底电极。
进一步地，所述开关为NMOS器件，所述开关的第一端或第二端为所述NMOS器件的源端或漏端，所述开关的控制端为所述NMOS器件的栅极。
进一步地，各所述行引出线不同时打开。
进一步地，各行的所述控制引出线不同时打开。
本发明的优点在于，本发明能够在同一个时间内获得根据每一列的乘加运算需求指定的不同行的信号输入的相应的模拟电流输出，实现不同规模不同输入信号的乘加运算，极大地提高了运算速度和阵列使用效率。
附图说明
图1是现有的一种无控制端的存算神经网络的基本拓扑架构示意图。
图2是现有的一种带控制端的存算神经网络的基本拓扑架构示意图
图3是本发明一较佳实施例一的一种存储器阵列结构的存算神经网络的拓扑架构示意图。
图4是本发明一较佳实施例二的一种存储器阵列结构的存算神经网络的拓扑架构示意图。
发明内容
以下将结合说明书附图对本发明的内容作进一步的详细描述。应理解的是本发明能够在不同的示例上具有各种的变化，其皆不脱离本发明的范围，且其中的说明及图示在本质上当作说明之用，而非用以限制本发明。需说明的是，附图均采用非常简化的形式且均使用非精准的比率，仅用以方便、明晰地辅助说明本发明实施例的目的。
在以下本发明的具体实施方式中，请参考图3，图3是本发明一较佳实施例一的一种存储器阵列结构的存算神经网络的拓扑架构示意图。如图3所示，本发明提供一种新型的应用于存内运算的存储器阵列结构，存储器阵列结构由多个存储器件20按行列组成阵列，例如图示的一种6×6阵列。
本发明的存储器阵列结构是一个矩阵结构，其区别于例如图2的通常矩阵结构的核心特征在于，存在同一列中多个不同行的存储器件20可以与同一个开关21连接，处于同一列的开关21的控制引出互相独立，可以与其他列的开关21共享控制引出。
请参考图3。存储器阵列结构内部的电学器件主要由存储单元(存储器件20)与开关21组成。阵列中的每行设有行引出线R，每列设有列引出线C。存储器件20对应位于每个行引出线R与列引出线C的交叉点处；同时， 每一列存在一至多个开关21。
其中，每个存储器件20的第一端单独与该存储器件20所在行的行引出线R连接，每个存储器件20的第二端与处于同列的某一个开关21的第一端连接，开关21的第二端与其所在列的列引出线C连接。
在阵列的每列中可设有一至多个开关21，且每个开关21的第一端可连接处于同列的一个或多个存储器件20的第二端，甚至可连接处于同列的全部存储器件20的第二端。
请参考图3。开关21可设有至少一个控制端；阵列的每行可设有控制引出线S。位于同一行中不同列的开关21的控制端共同连接在所在行的控制引出线S上；处于同列的各开关21的控制端分别连接在不同行的控制引出线S上。即在每一条控制引出线S上，可以接一个或者多个开关21的控制端，但是至多连接一个处于同一列的开关21。
进一步地，控制引出线S可与行引出线R平行设置。
存储单元(存储器件20)可以是两端或者多端的非易失存储器件，其主要特征在于，在外部电信号条件相同的情况下，体现出两种或者两种以上的阻值特性。
如果存储单元是两端器件，那么在架构中与存储单元相关的是行和列两组引出线，存储器件20的第一端(定义为正极)直接连接行引出线R，存储器件20的第二端(定义为负极)通过开关21连接列引出线C。
如果存储单元是两端以上的多端器件，那么除了其中体现电阻特性的两端与两端器件的连接相同外，其余端需要有额外的引出控制来执行写操作。这些控制与器件本身的电阻变化有关，而与整个架构的运算逻辑和连接关系 无关。例如，按照EEPROM结构排布的浮栅器件阵列，每一个浮栅器件都存在栅极、源级和漏极，即存在三个端。其中，源、漏两端可以作为具有电阻特性的两端，每一行的栅极则存在一个公共的电压控制信号。在工作时，对该电压控制信号需要加载一个合适的电平，以便能够使浮栅器件处于正常的读出状态。不过，虽然该控制信号必须存在，但是与架构的运算逻辑没有直接关系，所以在阵列结构中未加体现。
开关21至少存在一个开闭控制端，以及可以打开或者关闭的两端(第一端和第二端)。开闭控制端用于输入外部控制信号，作用是使开关21打开或者关闭。
开关21导通电阻远小于其连接的同列全部存储器件20处于低阻态时的并联电阻值，开关21的关断电阻高于其连接的同列任意一个存储器件20处于高阻态时的电阻值。即对于开关21的电阻特性的要求是，其开启时的电阻远小于若干个存储器件20可能的最低阻值的并联值，关闭时的电阻远高于存储器件20可能的最高阻值。
本发明的存储器阵列结构中，存储单元的阻值已经通过合理的电信号控制写入。在存内运算工作时，每一个行引出线R加上一个模拟或者数字的电压信号，每一个列引出线C加上一个固定的模拟或者数字电压信号，每一个控制引出线S加上一个数字电压信号，用来决定开关21的通断。其中，各行引出线R可不同时打开。各行的控制引出线S可不同时打开。
在这种工作模式下，每一列的模拟输出电流值就是该列导通的开关21连接的存储单元所在行的电压与列电压的电压差值除以该单元电阻的所有电流的和。通过合理控制开关21控制端的电信号，可以使每一列输出接收 特定行输入信号的乘加电流值，而不是像通常的阵列那样，每一列都只能接收选定打开的相同行的输入信号的乘加结果。
本发明上述结构的优势在于，在同一个时间内就可以获得根据每一列的乘加运算需求指定的不同行的信号输入的相应的模拟电流输出。
本发明相对于现有的一些存算网络，在外围控制上也存在一些不同，可以根据特殊的应用场合来配置。
请参考图4，图4是本发明一较佳实施例二的一种存储器阵列结构的存算神经网络的拓扑架构示意图。如图4所示，其示例性介绍一种基于阻变存储单元(阻变式存储器)(RRAM)的一个6×6规模的阵列架构。
如以行引出线R和列引出线C作为阵列规模的划分依据，该阵列由6行(行引出线R 1-R 6)和6列(列引出线C 1～C 6)组成，同时存在6条开关控制引出线S 1～S 6。
该阵列中，存储器件20的选择为RRAM器件，开关21的选择为CMOS工艺中的NMOS器件(PMOS理论上也是可以采用的，但其相比于NMOS，面积代价将很高)。其中，RRAM器件20为存在顶电极(正极)和底电极(负极)的两端器件，其存在高阻态和低阻态两种电阻状态。NMOS器件21由连接其中一条开关控制引出线S的栅极的电压高低来控制源漏两端的通断。NMOS器件开关21的导通电阻远小于RRAM器件20的低阻态电阻，其关断电阻远高于RRAM器件20的高阻态电阻。
每行和每列均存在6个RRAM单元20。每一列存在一至若干个开关21。每一行的RRAM器件20的顶电极连接该行的行引出线R，每一个开关21的漏端连接该列的一个或者多个RRAM器件20的底电极，源端连接该列的列引出 线C，栅极连接某一条控制引出线S。
为了具体说明图4中阵列的架构，把一列中连接到同一个开关21的RRAM单元20与该开关21一起定义成一个RRAM簇，用字母A表示。
如图4所示，一共存在15个RRAM簇A 1～A 15。其中，第一列存在两个RRAM簇A 1和A 2，A 1存在3个RRAM单元20，开关控制引出线为S 1；A 2存在3个RRAM单元20，开关控制引出线为S 4。第二列存在两个RRAM簇A 3和A 4，A 3存在3个RRAM单元20，开关控制引出线为S 3；A 4存在3个RRAM单元20，开关控制引出线为S 5。第三列存在两个RRAM簇A 5和A 6，A 5存在5个RRAM单元20，开关控制引出线为S 3；A 6存在1个RRAM单元20，开关控制引出线为S 6。第四列存在两个RRAM簇A 7和A 8，A 7存在2个RRAM单元20，开关控制引出线为S 2；A 8存在4个RRAM单元20，开关控制引出线为S 6。第五列存在一个RRAM簇A 9，有6个RRAM单元20，开关控制引出线为S 2。第六列存在6个均只有1个RRAM单元20的RRAM簇A 10～A 15，开关控制引出线为S 1～S 6。
在应用时，以行引出线R 1～R 6为输入信号端，列引出线C 1～C 6为输出信号端。可以分为模拟或数字的信号传输方式，两种方式的乘加计算类似。以使用模拟信号为例，在行引出线R 1～R 6端各自加载一个模拟电压，在列引出线C 1～C 6各自加载一个相同的模拟电压，那么在列引出线C 1～C 6端的电流就是选通的RRAM簇A的RRAM单元20流经的电流之和，即相当于同时做了乘法和加法两个操作。
例如，当只有行引出线R 1打开时，RRAM簇A 1和A 10的所有RRAM器件20存在电流，而其他簇的RRAM器件20均关闭。
与传统的RRAM阵列比较，本发明的RRAM阵列中，对应的控制引出线并 不是只能控制每一列中的一个RRAM单元，而是可以根据需要，选通该行存在开关的每一列中不同行以及不同数量的RRAM单元。这样体现出的优势在于做乘加运算时，每一列能够做乘法的项可以不同。这样通过合理的信号输入，以及合理的控制端输入，可以在同一个时间做出不同规模不同输入信号的乘加运算，极大地提高了运算速度和阵列使用效率。
例如，如果只打开控制引出线S 2和S 6，那么第一列和第二列没有乘加运算，第三列对行引出线R 6的信号做乘加，第四列和第五列对所有行的信号做乘加，第六列对行引出线R 2和R 6做乘加。尽管在同一个时间内同时存在六个输入，但是某些列只对其中部分输入信号做了运算，这是例如图1和图2所示的两种架构所办不到的。
以上所述的仅为本发明的实施例，所述实施例并非用以限制本发明专利保护范围，因此凡是运用本发明的说明书及附图内容所作的等同结构变化，同理均应包含在本发明的保护范围内。

Claims (10)

  1. 一种存储器阵列结构，其特征在于，由多个存储器件按行列组成阵列，所述阵列的每行设有行引出线，每列设有列引出线，所述存储器件对应位于每个所述行引出线与所述列引出线的交叉点处；其中，每个所述存储器件的第一端单独与其所在行的所述行引出线连接，每个所述存储器件的第二端与处于同列的一个开关的第一端连接，所述开关的第二端与其所在列的所述列引出线连接；其中，每列设有一至多个所述开关，每个所述开关的第一端连接处于同列的一至全部所述存储器件的第二端。
  2. 根据权利要求1所述的存储器阵列结构，其特征在于，所述开关设有控制端，所述阵列的每行设有控制引出线，位于同一行中不同列的所述开关的所述控制端共同连接在所在行的所述控制引出线上，处于同列的各所述开关的所述控制端分别连接在不同行的所述控制引出线上。
  3. 根据权利要求2所述的存储器阵列结构，其特征在于，所述控制引出线与所述行引出线平行设置。
  4. 根据权利要求1或2所述的存储器阵列结构，其特征在于，所述开关的导通电阻小于其连接的同列全部所述存储器件处于低阻态时的并联电阻值，所述开关的关断电阻高于其连接的同列任意一个所述存储器件处于高阻态时的电阻值。
  5. 根据权利要求1所述的存储器阵列结构，其特征在于，所述存储器件为非易失存储器件。
  6. 根据权利要求1所述的存储器阵列结构，其特征在于，所述存储器件为阻变式存储器，所述存储器件的第一端为所述阻变式存储器的正极，所述存储器件的第二端为所述阻变式存储器的负极。
  7. 根据权利要求6所述的存储器阵列结构，其特征在于，所述阻变式存储器的正极为所述阻变式存储器的顶电极，所述阻变式存储器的负极为所 述阻变式存储器的底电极。
  8. 根据权利要求2所述的存储器阵列结构，其特征在于，所述开关为NMOS器件，所述开关的第一端或第二端为所述NMOS器件的源端或漏端，所述开关的控制端为所述NMOS器件的栅极。
  9. 根据权利要求2所述的存储器阵列结构，其特征在于，各所述行引出线不同时打开。
  10. 根据权利要求2或9所述的存储器阵列结构，其特征在于，各行的所述控制引出线不同时打开。
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