WO2021117511A1 - 撮像装置および電子機器 - Google Patents

撮像装置および電子機器 Download PDF

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Publication number
WO2021117511A1
WO2021117511A1 PCT/JP2020/044298 JP2020044298W WO2021117511A1 WO 2021117511 A1 WO2021117511 A1 WO 2021117511A1 JP 2020044298 W JP2020044298 W JP 2020044298W WO 2021117511 A1 WO2021117511 A1 WO 2021117511A1
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Prior art keywords
pixel
unit
charge
sensor
wiring
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English (en)
French (fr)
Japanese (ja)
Inventor
貴志 町田
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Sony Semiconductor Solutions Corp
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Sony Semiconductor Solutions Corp
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Priority to CN202080081365.5A priority Critical patent/CN114731380B/zh
Priority to JP2021563853A priority patent/JPWO2021117511A1/ja
Priority to EP20899725.4A priority patent/EP4075793A4/en
Priority to US17/756,591 priority patent/US12155950B2/en
Publication of WO2021117511A1 publication Critical patent/WO2021117511A1/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/807—Pixel isolation structures
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/702—SSIS architectures characterised by non-identical, non-equidistant or non-planar pixel layout
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/703—SSIS architectures incorporating pixels for producing signals other than image signals
    • H04N25/704—Pixels specially adapted for focusing, e.g. phase difference pixel sets
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/771—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/79—Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/199—Back-illuminated image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/803—Pixels having integrated switching, control, storage or amplification elements
    • H10F39/8037—Pixels having integrated switching, control, storage or amplification elements the integrated elements comprising a transistor
    • H10F39/80373—Pixels having integrated switching, control, storage or amplification elements the integrated elements comprising a transistor characterised by the gate of the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/809—Constructional details of image sensors of hybrid image sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/10—Circuitry of solid-state image sensors [SSIS]; Control thereof for transforming different wavelengths into image signals
    • H04N25/11—Arrangement of colour filter arrays [CFA]; Filter mosaics
    • H04N25/13—Arrangement of colour filter arrays [CFA]; Filter mosaics characterised by the spectral characteristics of the filter elements
    • H04N25/131—Arrangement of colour filter arrays [CFA]; Filter mosaics characterised by the spectral characteristics of the filter elements including elements passing infrared wavelengths
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
    • H10F39/182—Colour image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
    • H10F39/184—Infrared image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/811—Interconnections

Definitions

  • the present disclosure relates to an imaging device that performs imaging by performing photoelectric conversion, and an electronic device provided with the imaging device.
  • the image pickup apparatus as one embodiment of the present disclosure includes a first pixel and a second pixel.
  • the first pixel has m (m is an integer of 2 or more) first wirings and m first gate electrodes connected to m first wirings, respectively.
  • the second pixel has n (n is a natural number smaller than m) second wiring and n second gate electrodes connected to each of the n second wirings.
  • the electronic device as one embodiment of the present disclosure includes the above-mentioned imaging device.
  • FIG. 1 is a first cross-sectional view schematically showing a cross section of one normal pixel and one phase difference detection pixel in the solid-state image sensor shown in FIG. 1 along the stacking direction. It is a 2nd sectional view schematically showing the cross section along the stacking direction of one normal pixel and one phase difference detection pixel in the solid-state image pickup apparatus shown in FIG. FIG.
  • FIG. 1 is a first cross-sectional view schematically showing a cross section orthogonal to the stacking direction of one normal pixel and one phase difference detection pixel in the solid-state image sensor shown in FIG. 1.
  • FIG. 2 is a second cross-sectional view schematically showing a cross section orthogonal to the stacking direction of one normal pixel and one phase difference detection pixel in the solid-state image sensor shown in FIG. 1.
  • FIG. 3 is a third cross-sectional view schematically showing a cross section orthogonal to the stacking direction of one normal pixel and one phase difference detection pixel in the solid-state image sensor shown in FIG. 1.
  • FIG. 5 is a fifth cross-sectional view schematically showing a cross section orthogonal to the stacking direction of one normal pixel and one phase difference detection pixel in the solid-state image sensor shown in FIG. 1.
  • 6 is a sixth cross-sectional view schematically showing a cross section orthogonal to the stacking direction of one normal pixel and one phase difference detection pixel in the solid-state image sensor shown in FIG. 1.
  • FIG. 7 is a seventh cross-sectional view schematically showing a cross section orthogonal to the stacking direction of one normal pixel and one phase difference detection pixel in the solid-state image sensor shown in FIG. 1.
  • FIG. 8 is an eighth cross-sectional view schematically showing a cross section orthogonal to the stacking direction of one normal pixel and one phase difference detection pixel in the solid-state image sensor shown in FIG. 1.
  • It is a schematic diagram which shows an example of the layout of a sensor pixel in a pixel array part.
  • It is a circuit diagram which shows the circuit structure of one normal pixel and one phase difference detection pixel in the solid-state image pickup apparatus as the first modification of this disclosure.
  • FIG. 5 is a first cross-sectional view schematically showing a cross section of one normal pixel and one phase difference detection pixel in the solid-state image sensor shown in FIG. 5 along the stacking direction.
  • FIG. 5 is a second cross-sectional view schematically showing a cross section of one normal pixel and one phase difference detection pixel in the solid-state image sensor shown in FIG. 5 along the stacking direction.
  • It is sectional drawing which shows typically the cross section orthogonal to the stacking direction of one normal pixel and one phase difference detection pixel in the solid-state image sensor shown in FIG.
  • FIG. 5 is a first cross-sectional view schematically showing a cross section of one normal pixel and one phase difference detection pixel in the solid-state image sensor shown in FIG. 5 along the stacking direction.
  • FIG. 5 is a second cross-sectional view schematically showing a
  • FIG. 5 is a first cross-sectional view schematically showing a cross section of one normal pixel and one phase difference detection pixel in the solid-state image sensor shown in FIG. 8 along the stacking direction. It is a 2nd sectional view schematically showing the cross section along the stacking direction of one normal pixel and one phase difference detection pixel in the solid-state image pickup apparatus shown in FIG. It is sectional drawing which shows typically the cross section orthogonal to the stacking direction of one normal pixel and one phase difference detection pixel in the solid-state image sensor shown in FIG. It is a circuit diagram which shows the circuit structure of one normal pixel and one phase difference detection pixel in the solid-state image pickup apparatus as the third modification of this disclosure.
  • FIG. 11 is a first cross-sectional view schematically showing a cross section of one normal pixel and one phase difference detection pixel in the solid-state image sensor shown in FIG. 11 along the stacking direction.
  • FIG. 2 is a second cross-sectional view schematically showing a cross section of one normal pixel and one phase difference detection pixel in the solid-state image sensor shown in FIG. 11 along the stacking direction.
  • It is sectional drawing which shows typically the cross section orthogonal to the stacking direction of one normal pixel and one phase difference detection pixel in the solid-state image sensor shown in FIG.
  • FIG. 1 is a first cross-sectional view schematically showing a cross section of one normal pixel and one phase difference detection pixel in the solid-state image sensor shown in FIG. 11 along the stacking direction.
  • FIG. 2 is a second cross-sectional view schematically showing
  • FIG. 6 is a first cross-sectional view schematically showing a cross section of one normal pixel and one phase difference detection pixel in the solid-state image sensor shown in FIG. 14 along the stacking direction.
  • FIG. 2 is a second cross-sectional view schematically showing a cross section of one normal pixel and one phase difference detection pixel in the solid-state image sensor shown in FIG. 14 along the stacking direction.
  • It is sectional drawing which shows typically the cross section orthogonal to the stacking direction of one normal pixel and one phase difference detection pixel in the solid-state image sensor shown in FIG.
  • It is a circuit diagram which shows the circuit structure of one normal pixel and one phase difference detection pixel in the solid-state image pickup apparatus as the fifth modification of this disclosure.
  • FIG. 6 is a first cross-sectional view schematically showing a cross section of one normal pixel and one phase difference detection pixel in the solid-state image sensor shown in FIG. 17 along the stacking direction.
  • FIG. 2 is a second cross-sectional view schematically showing a cross section of one normal pixel and one phase difference detection pixel in the solid-state image sensor shown in FIG. 17 along the stacking direction.
  • It is sectional drawing which shows typically the cross section orthogonal to the stacking direction of one normal pixel and one phase difference detection pixel in the solid-state image sensor shown in FIG.
  • FIG. 5 is a first cross-sectional view schematically showing a cross section of one normal pixel and one phase difference detection pixel in the solid-state image sensor shown in FIG. 20 along the stacking direction.
  • FIG. 2 is a second cross-sectional view schematically showing a cross section of one normal pixel and one phase difference detection pixel in the solid-state image sensor shown in FIG. 20 along the stacking direction.
  • It is sectional drawing which shows typically the cross section orthogonal to the stacking direction of one normal pixel and one phase difference detection pixel in the solid-state image sensor shown in FIG.
  • It is a circuit diagram which shows the circuit structure of one normal pixel and one phase difference detection pixel in the solid-state image pickup apparatus which concerns on 2nd Embodiment of this disclosure.
  • FIG. 3 is a cross-sectional view schematically showing a cross section of one normal pixel and one phase difference detection pixel in the solid-state image sensor shown in FIG. 23 along the stacking direction.
  • FIG. 3 is a plan view schematically showing a planar configuration of a surface of a semiconductor substrate in the solid-state image sensor shown in FIG. 23. It is a circuit diagram which shows the circuit structure of one normal pixel and one phase difference detection pixel in the solid-state image pickup apparatus as the 7th modification of this disclosure.
  • FIG. 6 is a cross-sectional view schematically showing a cross section of one normal pixel and one phase difference detection pixel in the solid-state image sensor shown in FIG. 26 along the stacking direction.
  • FIG. 3 is a cross-sectional view schematically showing a cross section of one normal pixel and one phase difference detection pixel in the solid-state image sensor shown in FIG. 23 along the stacking direction.
  • FIG. 6 is a plan view schematically showing a planar configuration of a surface of a semiconductor substrate in the solid-state image sensor shown in FIG. 26. It is a circuit diagram which shows the circuit structure of one normal pixel and one phase difference detection pixel in the solid-state image pickup apparatus as the eighth modification of this disclosure.
  • FIG. 5 is a cross-sectional view schematically showing a cross section of one normal pixel and one phase difference detection pixel in the solid-state image sensor shown in FIG. 29 along the stacking direction. It is a top view which shows typically the plane structure of the surface of the semiconductor substrate in the solid-state image sensor shown in FIG.
  • FIG. 3 is a plan view schematically showing a planar configuration of a surface of a semiconductor substrate in the solid-state image sensor shown in FIG. 32. It is the schematic which shows the overall configuration example of an electronic device. It is a block diagram which shows an example of the schematic structure of a vehicle control system. It is explanatory drawing which shows an example of the installation position of the vehicle exterior information detection unit and the image pickup unit.
  • FIG. 3 is a plan view schematically showing a planar configuration of a surface of a semiconductor substrate in the solid-state image sensor shown in FIG. 38. It is a block diagram which shows the structural example of the solid-state image sensor as the 9th modification of this disclosure. It is a block diagram which shows the structural example of the solid-state image sensor as the tenth modification of this disclosure. It is a schematic diagram which shows an example of the layout of the sensor pixel in the pixel array part as the eleventh modification of this disclosure.
  • a global shutter type imaging pixel (hereinafter, simply referred to as a global shutter pixel) as described in Patent Document 1 above requires a transistor for performing charge transfer, an imaging pixel other than the global shutter type (hereinafter, simply referred to as a global shutter pixel).
  • a global shutter pixel an imaging pixel other than the global shutter type (hereinafter, simply referred to as a global shutter pixel).
  • more transistors are required as compared with those simply referred to as non-global shutter pixels). Therefore, in order to independently drive each of the plurality of global shutter pixels, more signal lines are required than in the case of independently driving each of the plurality of non-global shutter pixels.
  • the present disclosure has been made in view of these problems, and provides an image pickup apparatus capable of in-plane miniaturization without impairing operating performance, and an electronic device provided with such an image pickup apparatus. I am aiming.
  • Second Embodiment An example of a solid-state image sensor in which a normal pixel and an image plane phase difference pixel are provided, and a photoelectric conversion unit and a memory are arranged in the same layer. 4.
  • Modification example of the second embodiment 4-1 A seventh modification of a solid-state image sensor in which the number of wirings of image plane phase difference pixels is 3 less than the number of wirings of normal pixels. 4-2.
  • An eighth modification of a solid-state image sensor in which the number of wirings of image plane phase difference pixels is one less than the number of wirings of normal pixels. 4-4.
  • Other Modifications An example of a solid-state image pickup device including a normal pixel which is an FD holding type global shutter pixel and an image plane phase difference pixel.
  • FIG. 1 is a block diagram showing a configuration example of a function of the solid-state image sensor 101 according to the first embodiment of the present technology.
  • the solid-state image sensor 101 is a so-called global shutter type back-illuminated image sensor such as a CMOS (ComplementaryMetalOxideSemiconductor) image sensor.
  • CMOS ComplementaryMetalOxideSemiconductor
  • the solid-state image sensor 101 captures an image by receiving light from a subject, performing photoelectric conversion, and generating an image signal.
  • the global shutter method is basically a method of performing global exposure that starts exposure for all pixels at the same time and ends exposure for all pixels at the same time.
  • all the pixels mean all the pixels of the portion appearing in the image, and dummy pixels and the like are excluded.
  • the global shutter method also includes a method of performing global exposure not only on all the pixels of the portion appearing in the image but also on the pixels in a predetermined region.
  • a photoelectric conversion unit such as a photodiode that receives light from a subject and converts it into an electric signal has a light receiving surface on which light from the subject is incident and wiring such as a transistor that drives each pixel.
  • wiring such as a transistor that drives each pixel.
  • the solid-state image sensor 101 includes, for example, a pixel array unit 111, a vertical drive unit 112, a column signal processing unit 113, a data storage unit 119, a horizontal drive unit 114, a system control unit 115, and a signal processing unit 118.
  • the pixel array unit 111 is formed on the semiconductor substrate 11 (described later). Peripheral circuits such as the vertical drive unit 112, the column signal processing unit 113, the data storage unit 119, the horizontal drive unit 114, the system control unit 115, and the signal processing unit 118 are placed on the same semiconductor substrate 11 as the pixel array unit 111, for example. It is formed.
  • the pixel array unit 111 has a plurality of sensor pixels PX including a photoelectric conversion unit PD (described later) that generates and stores electric charges according to the amount of light incident from the subject. As shown in FIG. 1, the sensor pixels PX are arranged in the horizontal direction (row direction) and the vertical direction (column direction), respectively.
  • pixel drive lines 116 are wired along the row direction for each pixel row composed of sensor pixels PX arranged in a row in the row direction, and are composed of sensor pixels PX arranged in a row in the column direction.
  • a vertical signal line VSL is wired along the row direction for each pixel row.
  • the vertical drive unit 112 includes a shift register, an address decoder, and the like.
  • the vertical drive unit 112 simultaneously drives all of the plurality of sensor pixels PX in the pixel array unit 111 by supplying signals or the like to the plurality of sensor pixels PX via the plurality of pixel drive lines 116, or pixels. Drive in line units.
  • the signal output from each unit pixel of the pixel row selectively scanned by the vertical drive unit 112 is supplied to the column signal processing unit 113 through each of the vertical signal lines VSL.
  • the column signal processing unit 113 performs predetermined signal processing on the signal output from each unit pixel of the selected row through the vertical signal line VSL for each pixel column of the pixel array unit 111, and the pixel signal after the signal processing. Is temporarily retained.
  • the column signal processing unit 113 includes, for example, a shift register and an address decoder, and includes noise removal processing, correlated double sampling processing, and A / D (Analog / Digital) conversion A / D conversion processing of analog pixel signals. Etc. to generate a digital pixel signal.
  • the column signal processing unit 113 supplies the generated pixel signal to the signal processing unit 118.
  • the horizontal drive unit 114 is composed of a shift register, an address decoder, and the like, and the unit circuits corresponding to the pixel strings of the column signal processing unit 113 are sequentially selected. By the selective scanning by the horizontal drive unit 114, the pixel signals processed by the column signal processing unit 113 for each unit circuit are sequentially output to the signal processing unit 118.
  • the system control unit 115 includes a timing generator or the like that generates various timing signals.
  • the system control unit 115 controls the drive of the vertical drive unit 112, the column signal processing unit 113, and the horizontal drive unit 114 based on the timing signal generated by the timing generator.
  • the signal processing unit 118 temporarily stores data in the data storage unit 119 as necessary, and performs signal processing such as arithmetic processing on the pixel signal supplied from the column signal processing unit 113, and each pixel signal. It outputs an image signal consisting of.
  • the data storage unit 119 temporarily stores the data required for the signal processing when the signal processing unit 118 performs the signal processing.
  • FIG. 2 shows a circuit configuration example of two sensor pixels PX1 and PX2 among a plurality of sensor pixels PX constituting the pixel array unit 111.
  • the sensor pixels PX (PX1, PX2) in the pixel array unit 111 realize a memory-holding type global shutter.
  • the sensor pixel PX1 is a normal pixel for image detection that acquires visible light information, and includes a photoelectric conversion unit PD1, first to third transfer transistors TG1A to TG1C, a charge holding unit MEM1, an emission transistor OFG1, an emission unit OFD1 and the like. It has a buffer BUF1.
  • the first transfer transistor TG1A includes a transfer gate TRZ1
  • the second transfer transistor TG1B includes a transfer gate TRY1 and a transfer gate TRX1
  • the third transfer transistor TG1C includes a transfer gate TRG1.
  • the gate electrode of the discharge transistor OFG1 is connected to the signal line SL1
  • the transfer gate TRZ1 is connected to the signal line SL2
  • the transfer gate TRY1 is connected to the signal line SL3
  • the transfer gate TRX1 is connected to the signal line SL4.
  • the transfer gate TRG1 is connected to the signal line SL5.
  • the sensor pixel PX1 further includes a power supply VDD, a charge-voltage conversion unit FD1, a reset transistor RST1, an amplification transistor AMP1, a selection transistor SEL1 and the like.
  • the gate electrode of the reset transistor RST1 is connected to the signal line SL6, and the gate electrode of the selection transistor SEL1 is connected to the signal line SL7.
  • the sensor pixel PX1 may share the charge-voltage conversion unit FD1, the reset transistor RST1, the amplification transistor AMP1, the selection transistor SEL1, and the like with the sensor pixel PX4 (described later) adjacent to the sensor pixel PX1.
  • the sensor pixel PX4 is a normal pixel for image detection that acquires visible light information.
  • the sensor pixel PX2 is a pixel that acquires information other than visible light information, and specifically, for example, an image plane phase difference detection pixel (hereinafter, referred to as a ZAF pixel) for obtaining a phase difference signal for autofocus. is there.
  • the sensor pixel PX2 includes a photoelectric conversion unit PD2, first to third transfer transistors TG2A to TG2C, a charge holding unit MEM2, and a buffer BUF2.
  • the sensor pixel PX2 of the present embodiment does not have an emission transistor and an emission unit.
  • the first transfer transistor TG2A includes a transfer gate TRZ2
  • the second transfer transistor TG2B includes a transfer gate TRY2 and a transfer gate TRX2
  • the third transfer transistor TG2C includes a transfer gate TRG2.
  • the transfer gate TRZ2 is connected to the signal line SL9
  • the transfer gate TRY2 is connected to the signal line SL10
  • the transfer gate TRX2 is connected to the signal line SL11
  • the transfer gate TRG2 is connected to the signal line SL12.
  • the sensor pixel PX2 further includes a power supply VDD, a charge-voltage conversion unit FD2, a reset transistor RST2, an amplification transistor AMP2, a selection transistor SEL2, and the like.
  • the gate electrode of the reset transistor RST2 is connected to the signal line SL6 like the gate electrode of the reset transistor RST1, and the gate electrode of the selection transistor SEL2 is connected to the signal line SL7 like the gate electrode of the selection transistor SEL2.
  • the sensor pixel PX2 may share the charge-voltage conversion unit FD2, the reset transistor RST2, the amplification transistor AMP2, the selection transistor SEL2, and the like with the sensor pixel PX3 (described later) adjacent to the sensor pixel PX2.
  • the sensor pixel PX3 is a normal pixel for image detection that acquires visible light information.
  • the first to third transfer transistors TG1A to TG1C, TG2A to TG2C, the reset transistors RST1 and RST2, the amplification transistors AMP1 and AMP2, and the selection transistors SEL1 and SEL2 are all N-type MOS transistors.
  • Drive control of the system control unit 115 is performed on each gate electrode of the first to third transfer transistors TG1A to TG1C, TG2A to TG2C, reset transistors RST1, RST2, amplification transistors AMP1 and AMP2, and selection transistors SEL1 and SEL2, respectively.
  • the vertical drive unit 112 and the horizontal drive unit 114 supply drive signals via the signal lines SL1 to SL7 and SL9 to SL12.
  • These drive signals are pulse signals in which a high level state becomes an active state (on state) and a low level state becomes an inactive state (off state).
  • setting the drive signal to the active state is also referred to as turning on the drive signal
  • making the drive signal inactive is also referred to as turning off the drive signal.
  • the photoelectric conversion units PD1 and PD2 are photoelectric conversion elements composed of, for example, PN junction photodiodes, and are configured to receive light from a subject and generate and store electric charges according to the amount of the received light by photoelectric conversion. Has been done.
  • the charge holding units MEM1 and MEM2 are provided between the photoelectric conversion units PD1 and PD2 and the charge-voltage conversion units FD1 and FD2, respectively, and are generated in the photoelectric conversion units PD1 and PD2 in order to realize the global shutter function. This is a region for temporarily holding the accumulated charge until it is transferred to the charge / voltage conversion units FD1 and FD2, respectively.
  • the first transfer transistor TG1A and the second transfer transistor TG1B are sequentially arranged between the photoelectric conversion unit PD1 and the charge holding unit MEM1, and the third transfer transistor TG1C is the charge holding unit MEM1. It is arranged between the charge / voltage conversion unit FD1 and the charge / voltage conversion unit FD1.
  • the first transfer transistor TG1A and the second transfer transistor TG1B charge the electric charges stored in the photoelectric conversion unit PD1 according to the drive signals applied to the transfer gate TRZ2, the transfer gate TRY2, and the transfer gate TRX2, respectively. It is configured to transfer to the charge holding unit MEM1.
  • the first transfer transistor TG2A and the second transfer transistor TG2B are sequentially arranged between the photoelectric conversion unit PD2 and the charge holding unit MEM2, and the third transfer transistor TG2C is charged. It is arranged between the holding unit MEM2 and the charge-voltage conversion unit FD2.
  • the first transfer transistor TG2A and the second transfer transistor TG2B charge the electric charges stored in the photoelectric conversion unit PD2 according to the drive signals applied to the transfer gate TRZ2 and the transfer gate TRY2 and the transfer gate TRX2, respectively. It is configured to transfer to the charge holding unit MEM2.
  • the third transfer transistor TG1C and the third transfer transistor TG2C are temporarily held by the charge holding unit MEM1 and the charge holding unit MEM2, respectively, according to the drive signals applied to the transfer gates TRG1 and TRG2, respectively. It is configured to transfer charges to the charge-voltage conversion units FD1 and FD2, respectively.
  • the charges held in the charge holding units MEM1 and MEM2 are the third. It is transferred to the charge-voltage conversion units FD1 and FD2 via the transfer transistors TG1C and TG2C.
  • the buffer BUF1 in the sensor pixel PX1 is a charge storage region formed between the first transfer transistor TG1A and the second transfer transistor TG1B.
  • the buffer BUF2 in the sensor pixel PX2 is a charge storage region formed between the first transfer transistor TG2A and the second transfer transistor TG2B.
  • the reset transistor RST1 in the sensor pixel PX1 has a drain connected to the power supply VDD and a source connected to the charge-voltage conversion unit FD1.
  • the reset transistor RST1 initializes, that is, resets the charge-voltage conversion unit FD1 according to the drive signal applied to the gate electrode. For example, when the reset transistor RST1 is turned on by the drive signal, the potential of the charge-voltage conversion unit FD1 is reset to the voltage level of the power supply VDD. That is, the charge-voltage conversion unit FD1 is initialized.
  • the reset transistor RST2 in the sensor pixel PX2 has a drain connected to the power supply VDD and a source connected to the charge-voltage conversion unit FD2.
  • the reset transistor RST2 initializes, that is, resets, the charge-voltage conversion unit FD2 according to the drive signal applied to the gate electrode. For example, when the reset transistor RST2 is turned on by the drive signal, the potential of the charge-voltage conversion unit FD2 is reset to the voltage level of the power supply VDD.
  • the charge-voltage conversion unit FD1 in the sensor pixel PX1 converts the charge transferred from the photoelectric conversion unit PD1 into an electric signal (for example, a voltage signal) via the first to third transfer transistors TG1A to TG1C and the charge holding unit MEM1. It is a floating diffusion region that is converted and output.
  • a reset transistor RST1 is connected to the charge-voltage conversion unit FD1, and a vertical signal line VSL is connected via an amplification transistor AMP1 and a selection transistor SEL1.
  • the charge-voltage conversion unit FD2 in the sensor pixel PX2 converts the charge transferred from the photoelectric conversion unit PD2 via the first to third transfer transistors TG2A to TG2C and the charge holding unit MEM2 into an electric signal (for example, a voltage signal). It is a floating diffusion region that is output.
  • a reset transistor RST2 is connected to the charge-voltage conversion unit FD2, and a vertical signal line VSL is connected via an amplification transistor AMP2 and a selection transistor SEL2.
  • the amplification transistor AMP1 outputs an electric signal according to the potential of the charge-voltage conversion unit FD1. Further, the amplification transistor AMP2 outputs an electric signal corresponding to the potential of the charge-voltage conversion unit FD2.
  • the amplification transistors AMP1 and AMP2 constitute, for example, a constant current source and a source follower circuit provided in the column signal processing unit 113.
  • the selection transistors SEL1 and SEL2 are turned on when the sensor pixels PX1 and PX2 are selected, respectively, and an electric signal from the load-voltage conversion units FD1 and FD2 via the amplification transistors AMP1 and AMP2 is transmitted through the vertical signal line VSL to the column. It is designed to be output to the signal processing unit 113.
  • the sensor pixel PX1 further includes a discharge unit OFD1 in addition to the charge-voltage conversion unit FD1 as a charge transfer destination of the photoelectric conversion unit PD1.
  • the discharge transistor OFG1 is arranged between the buffer BUF1 and the discharge unit OFD1.
  • the discharge transistor OFG1 has a drain connected to the discharge unit OFD1 and a source connected to the buffer BUF1.
  • the discharge transistor OFG1 initializes, that is, resets the photoelectric conversion unit PD1 in response to the drive signal applied to the gate electrode. Resetting the photoelectric conversion unit PD1 means depleting the photoelectric conversion unit PD1.
  • the discharge transistor OFG1 forms an overflow path, and the electric charge overflowing from the photoelectric conversion unit PD1 is discharged to the discharge unit OFD1.
  • the emission transistor OFG1 can directly reset the photoelectric conversion unit PD51.
  • FIG. 3A and 3B show cross-sectional configuration examples of four sensor pixels PX1 to PX4 among the plurality of sensor pixels PX constituting the pixel array unit 111, respectively.
  • FIG. 3A represents a cross section in the arrow-viewing direction along the IIIA-IIIA cutting line in the X-axis direction, passing through the sensor pixels PX1 and the sensor pixels PX2 shown in FIGS. 4A to 4H, respectively.
  • FIG. 3B shows a cross section in the arrow-viewing direction along the IIIB-IIIB cutting line in the Y-axis direction.
  • FIGS. 4A to 4H show a plan configuration example of four sensor pixels PX1 to PX4 arranged in a grid pattern of 2 rows and 2 columns, respectively. Specifically, FIGS. 4A to 4H represent the planar configurations at the height positions Lv1 to Lv8 shown in FIGS. 3A and 3B, respectively.
  • FIG. 4I is a schematic diagram showing an example of the layout pattern of the sensor pixels PX1 to PX4 in the pixel array unit 111.
  • Lv9 means the height position Lv9 shown in FIGS. 3A and 3B, and is the height position corresponding to the light-shielding film forming layer including the ZAF light-shielding film 16 described later.
  • the sensor pixels PX1 to PX4 shown in FIGS. 4A to 4H are repeatedly arranged along the X-axis direction and the Y-axis direction as the minimum unit. ing.
  • the sensor pixels PX2 in the pixel array unit 111 need to be ZAF pixels, and some sensor pixels PX2 arbitrarily selected in the pixel array unit 111 may be ZAF pixels. Just do it.
  • the sensor pixel PX2 on which the ZAF light-shielding film 16 is formed is a ZAF pixel.
  • the sensor pixel PX3 and the sensor pixel PX4 are normal pixels having substantially the same configuration as the sensor pixel PX1. Therefore, the sensor pixel PX3 and the sensor pixel PX4 are the photoelectric conversion unit PD3, PD4, the first to third transfer transistors TG3A to TG3C, TG4A to TG4C, the charge holding unit MEM3, MEM4, the discharge transistor OFG3, OFG4, and the discharge unit OFD3. , OFD4, buffer BUF3, BUF4, power supply VDD, etc. Further, the sensor pixel PX3 shares the vertical signal line VSL2, the charge / voltage conversion unit FD2, the reset transistor RST2, the amplification transistor AMP2, and the selection transistor SEL2 with the sensor pixel PX2. The sensor pixel PX4 shares the vertical signal line VSL1, the charge / voltage conversion unit FD1, the reset transistor RST1, the amplification transistor AMP1, and the selection transistor SEL1 with the sensor pixel PX1.
  • the pixel array unit 111 joins the first substrate S1 including the first layer LY1 and the second layer LY2 and the second substrate S2 including the third layer LY3. It has a structure bonded at the interface K. At the joining interface K, the wiring layers are joined together. As the bonding between the wiring layers, so-called Cu-Cu bonding in which the surfaces of metal layers such as Cu (copper) are activated by plasma irradiation and bonded to each other is preferable.
  • Photoelectric conversion units PD (PD1 to PD4) and the like are formed on the first layer LY1 of the pixel array unit 111.
  • the sensor pixels PX1 to PX4 have a semiconductor substrate 11 formed of a semiconductor material such as Si (silicon) and photoelectric conversion units PD (PD1 to PD4) embedded in the semiconductor substrate 11 in the first layer LY1. doing. Further, the semiconductor substrate 11 includes a front surface 11S1 and a back surface 11S2 opposite to the front surface 11S1.
  • the back surface 11S2 is a surface on which light from the outside is incident, and is provided with a color filter forming layer including color filter CFs (CF1 to CF4) (see FIGS. 3A, 3B, and 4B).
  • On-chip lenses LS are further provided on the side opposite to the back surface 11S2 of the color filters CF (CF1 to CF4) (see FIGS. 3A, 3B and 4A). Further, the tips of the two vertical trench gates 51 and 52 extending in the depth direction (+ Z direction) from the lower part of the transfer gates TRZ (TRZ1 to TRZ4) provided on the surface 11S1 are the photoelectric conversion units PD ( It is in contact with PD1 to PD4) (see FIGS. 3A, 3B and 4E).
  • the sensor pixel PX2 is a ZAF pixel
  • the sensor pixel PX2 further has a light-shielding film forming layer including the ZAF light-shielding film 16 between the back surface 11S2 and the color filter forming layer including the color filter CF2. ..
  • the first layer LY1 of the semiconductor substrate 11 is further provided with an element separation unit 12 so as to surround the photoelectric conversion units PD (PD1 to PD4), respectively (FIGS. 3A, 3B and 4C).
  • the element separation unit 12 is a wall-shaped member that extends in the Z-axis direction so as to penetrate the semiconductor substrate 11 at the boundary position between the sensor pixels PX adjacent to each other and surrounds each photoelectric conversion unit PD.
  • the sensor pixels PX adjacent to each other are electrically separated from each other by the element separation unit 12. Further, the element separation unit 12 prevents the leakage light from the adjacent sensor pixels PX from being incident on the photoelectric conversion units PD (PD1 to PD4) to generate noise such as color mixing.
  • the element separation unit 12 is made of an insulating material such as silicon oxide.
  • the first to third transfer transistors TG1A to TG1C, TG2A to TG2C, TG3A to TG3C, TG4A to TG4C, charge holding units MEM1 to MEM4, and discharge transistors OFG1, OFG3, OFG4, discharge units OFD1, OFD3, OFD4, buffers BUF1 to BUF4, power supply VDD, charge-voltage conversion units FD1 to FD4, and the like are formed (see FIGS. 3A, 3B, and 4G).
  • the charge holding units MEM1 to MEM4 are located below, for example, transfer gates TRY1 to TRY4, TRX1 to TRX4, and TRG1 to TRG4.
  • Two vertical trench gates 51 and 52 arranged in the X-axis direction are provided in the second layer LY2 of the sensor pixels PX1 to PX4, respectively (see FIGS. 3A, 3B, 4E and 4F). ..
  • the vertical trench gates 51 and 52 form a part of the charge transfer unit, connect the photoelectric conversion units PD1 to PD4 and the transfer gates TRZ1 to TRZ4, respectively, and connect the buffers BUF1 to BUF4 from the photoelectric conversion units PD1 to PD4. It is a path for transferring charges to the charge holding units MEM1 to MEM4, which are transfer destinations. Only one vertical trench gate may be arranged, or three or more vertical trench gates may be arranged.
  • a horizontal light-shielding film 13 extending along the XY surface so as to overlap the vertical trench gates 51 and 52 in the Z-axis direction is provided (FIGS. 3A, 3A, See FIGS. 3B and 4D).
  • the horizontal light-shielding film 13 is connected to, for example, the end portion of the element separation portion 12 opposite to the back surface 11S2.
  • a part of the horizontal light-shielding film 13 is provided with openings 13K1 to 13K4 so as to partially partition the photoelectric conversion units PD1 to PD4 in the Z-axis direction.
  • the electric charges generated in the photoelectric conversion units PD1 to PD4 move to the vertical trench gates 51 and 52 through the openings 13K1 to 13K4, respectively.
  • the positions of the openings 13K1 to 13K4 on the XY plane are different from the positions of the openings 14K1 to 14K4 on the XY plane in the horizontal light-shielding film 14 described later.
  • a horizontal light-shielding film 14 extending along the XY plane is further provided between the photoelectric conversion units PD1 to PD4 and the charge holding units MEM1 to MEM4 (FIGS. 3A, 3B and 4F).
  • the horizontal light-shielding film 14 is a member that prevents light from entering the charge-holding units MEM1 to MEM4, and the light transmitted through the photoelectric conversion units PD1 to PD4 is incident on the charge-holding parts MEM1 to MEM4. And suppresses the generation of noise.
  • the light incident from the back surface 11B and transmitted through the photoelectric conversion units PD1 to PD4 without being absorbed by the photoelectric conversion units PD1 to PD4 is reflected by the horizontal shading film 14 and is again incident on the photoelectric conversion units PD1 to PD4.
  • the horizontal light-shielding film 14 is also a reflector, and the light transmitted through the photoelectric conversion units PD1 to PD4 is incident on the photoelectric conversion units PD1 to PD4 again to improve the photoelectric conversion efficiency.
  • the horizontal light-shielding film 14 is provided with an opening 14K (14K1 to 14K4) through which the electric charge generated by the photoelectric conversion units PD1 to PD4 can pass.
  • the vertical trench gates 51 and 52 are provided so as to penetrate the openings 14K1 to 14K4, respectively. It is preferable that the horizontal light-shielding film 14 is provided over the entire XY surface of the pixel array portion 111 except for the openings 14K1 to 14K4.
  • the horizontal light-shielding films 13 and 14 each have a two-layer structure of, for example, an inner layer portion and an outer layer portion surrounding the inner layer portion.
  • the inner layer portion is made of, for example, a material containing at least one of a light-shielding elemental metal, a metal alloy, a metal nitride, and a metal silicide.
  • Al (aluminum) is the most optically preferable constituent material.
  • the inner layer portion may be made of graphite or an organic material.
  • the outer layer portion is made of an insulating material such as SiOx (silicon oxide). The outer layer portion ensures electrical insulation between the inner layer portion and the semiconductor substrate 11.
  • the semiconductor substrate 11 is partially removed by, for example, a wet etching process to form a space inside the semiconductor substrate 11, and then the above-mentioned material is applied to the space. It can be formed by embedding.
  • a wet etching process for example, when the semiconductor substrate 11 is composed of Si ⁇ 111 ⁇ , a predetermined alkaline aqueous solution is used, and the etching rate differs depending on the plane orientation of Si ⁇ 111 ⁇ . Perform sex etching. More specifically, in the Si ⁇ 111 ⁇ substrate, the property that the etching rate in the ⁇ 110> direction is sufficiently higher than the etching rate in the ⁇ 111> direction is utilized.
  • the ⁇ 111> direction is a direction having three Si back bonds.
  • the ⁇ 110> direction is a direction having one or two Si back bonds, and in the present embodiment, the X-axis direction corresponds to this.
  • KOH, NaOH, CsOH or the like can be applied if it is an inorganic solution, and EDP (ethylenediamine pyrocatechol aqueous solution), N2H4 (hydrazine), NH 4 OH (ammonium hydroxide) if it is an organic solution. ), TMAH (tetramethylammonium hydroxide), etc. are applicable.
  • the semiconductor substrate 11 is, for example, a P-type (first conductive type), and the photoelectric conversion unit PD and the charge holding units MEM1 to MEM4 are N-type (second conductive type).
  • VSL1 and VSL2 charge-voltage conversion units FD1 and FD2, reset transistors RST1 and RST2, amplification transistors AMP1 and AMP2, selection transistors SEL1 and SEL2, and the like are formed on the third layer LY3 (FIG. 3A). , See FIGS. 3B and 4H).
  • the operation of the sensor pixel PX will be described with reference to FIGS. 2 to 4H and the like.
  • the sensor pixel PX which is a normal pixel excluding the sensor pixel PX2, which is a ZAF pixel
  • a high level drive signal is sent to the emission transistor OFG and the transfer gate TRZ before exposure.
  • the discharge transistor OFG and the transfer gate TRZ are turned on.
  • the electric charge accumulated in the photoelectric conversion unit PD is discharged to the discharge unit OFD, and the photoelectric conversion unit PD is reset.
  • the discharge transistor OFG and the transfer gate TRZ are turned off by supplying a low level drive signal to the discharge transistor OFG and the transfer gate TRZ, respectively, based on the drive control of the system control unit 115.
  • exposure is started in all the sensor pixels PX in the pixel array unit 111, and electric charges are generated and accumulated in each photoelectric conversion unit PD that receives the light from the subject.
  • the drive signals to the transfer gate TRZ and the transfer gate TRY are turned on in all the sensor pixels PX of the pixel array unit 111 based on the drive control of the system control unit 115.
  • the charge accumulated in the photoelectric conversion unit PD is transferred from the photoelectric conversion unit PD to the charge holding unit MEM via the transfer gate TRZ and the transfer gate TRY, and is temporarily transferred to the charge holding unit MEM. Is held in.
  • the drive signals to the transfer gate TRZ and the transfer gate TRY are turned off, and then the charges held in the charge holding unit MEM of each sensor pixel PX are sequentially read out.
  • the operation is performed.
  • the charge reading operation is performed, for example, in units of rows of the pixel array unit 111.
  • the transfer gate TRX and the transfer gate TRG are turned on by a drive signal for each row to be read.
  • the charges held in the charge holding unit MEM of each sensor pixel PX are transferred to the charge-voltage conversion unit FD line by line.
  • an electric signal indicating the level corresponding to the charge held in the charge-voltage conversion unit FD is vertically passed through the amplification transistor AMP and the selection transistor SEL in sequence. It is output to the column signal processing unit 113 through the signal line VSL.
  • the solid-state image sensor 101 of the present embodiment includes a sensor pixel PX1 which is a normal pixel as a first pixel and a sensor pixel PX2 which is a ZAF pixel as a second pixel.
  • the sensor pixel PX1 has seven signal lines SL1 to SL7 and seven gate electrodes connected to the signal lines SL1 to SL7, that is, the gate electrode of the discharge transistor OFG1 and the first to third transfer transistors TG1A.
  • the sensor pixel PX2 which is a ZAF pixel as the second pixel, has six gate electrodes connected to the six signal lines SL6 to SL7 and SL9 to SL12 and the signal lines SL6 to SL7 and SL9 to SL12, respectively.
  • the above-mentioned problem is avoided and miniaturization is realized by reducing the number of signal lines SL connected to the sensor pixel PX2.
  • the signal charge overflowing from the sensor pixel PX2 is a shared charge voltage when the normal pixel is read out. There is a concern that it will flow into the conversion unit and be superimposed as noise on the signal of the normal pixel.
  • an emission transistor OFG is also provided in the sensor pixel PX2, the emission transistor is turned on, and the signal charge overflowing from the sensor pixel PX2 is shared charge voltage conversion from the sensor pixel PX2. It is desirable to prevent it from flowing into the section.
  • the sensor pixel PX2 in the solid-state imaging device 101 of the present embodiment by adjusting the design margin of the potential even without the emission transistor, the reading of other normal pixels sharing the charge-voltage conversion unit can be performed. At that time, it is possible to prevent the signal charge from flowing into the shared charge-voltage conversion unit.
  • the sensor pixel PX2 has the same configuration as other normal pixels except that it does not have an emission transistor (OFG). Therefore, other characteristics of the sensor pixel PX2, such as the saturation capacitance of the charge holding unit MEM2, can be substantially equal to those of other normal pixels.
  • FIG. 5 is a circuit diagram showing the circuit configuration of the sensor pixel PX in the pixel array unit 111A as the first modification, and corresponds to FIG. 2 of the first embodiment.
  • FIGS. 6A and 6B show cross-sectional configuration examples of four sensor pixels PX1 to PX4 among the plurality of sensor pixels PX constituting the pixel array unit 111A, respectively.
  • FIG. 7 shows the planar configuration at the height position Lv7 shown in FIGS.
  • FIG. 6A and 6B in the four sensor pixels PX1 to PX4 arranged in a grid pattern of 2 rows and 2 columns.
  • FIG. 7 corresponds to FIG. 4G of the first embodiment. Note that FIG. 6A shows a cross section in the arrow-viewing direction along the VIA-VIA cutting line in the X-axis direction shown in FIG. 7, and FIG. 6B shows the VIB-VIB cutting line in the Y-axis direction shown in FIG. It represents a cross section in the direction of the arrow along the line.
  • the pixel array unit 111A is configured so that the number of wirings of ZAF pixels is one less than the number of wirings of normal pixels.
  • the emission transistor (OFG2) in the sensor pixel PX2, which is a ZAF pixel, and the signal line (SL8) connected to the gate electrode of the emission transistor (OFG2) are omitted. I made it.
  • the sensor pixel PX2 which is a ZAF pixel, has an emission transistor OFG2 and a signal line SL8 connected to the gate electrode of the emission transistor OFG2, while the transfer gate TRX2 and the transfer gate TRX2. , It does not have a signal line SL11 connected to the transfer gate TRX2. Except for this point, the pixel array unit 111A has substantially the same configuration as the pixel array unit 111.
  • the number of signal lines connected to the sensor pixel PX2 is smaller than the number of signal lines connected to the sensor pixel PX1 as in the pixel array unit 111. Therefore, it is advantageous to realize the miniaturization of the entire configuration.
  • the sensor pixel PX2 which is a ZAF pixel, has an emission transistor OFG2. Therefore, even when the sensor pixel PX2 shares the charge-voltage conversion unit (FD) with other normal pixels, the sensor can be sensored by turning on the emission transistor OFG2 when reading out the normal pixel. It is possible to prevent the signal charge overflowing from the pixel PX2 from flowing into the shared charge-voltage conversion unit.
  • FD charge-voltage conversion unit
  • the upper limit of the saturation capacity of the charge holding unit MEM2 is the upper limit of the saturation capacity of the charge holding unit MEM2 in the sensor pixel PX2 of the pixel array unit 111. Will be lower than.
  • FIG. 8 is a circuit diagram showing a circuit configuration of the sensor pixel PX in the pixel array unit 111B as a second modification, and corresponds to FIG. 2 of the first embodiment.
  • FIGS. 9A and 9B show cross-sectional configuration examples of four sensor pixels PX1 to PX4 among the plurality of sensor pixels PX constituting the pixel array unit 111B, respectively.
  • FIG. 10 shows the planar configuration at the height position Lv7 shown in FIGS.
  • FIG. 10 corresponds to FIG. 4G of the first embodiment.
  • 9A shows a cross section in the arrow-viewing direction along the IXA-IXA cutting line in the X-axis direction shown in FIG. 10
  • FIG. 9B shows the IXB-IXB cutting line in the Y-axis direction shown in FIG. It represents a cross section in the direction of the arrow along the line.
  • the pixel array unit 111B is configured so that the number of wirings of ZAF pixels is one less than the number of wirings of normal pixels.
  • the pixel array unit 111B as a second modification includes the transfer gate TRY2 while the sensor pixel PX2, which is a ZAF pixel, has the emission transistor OFG2 and the signal line SL8 connected to the gate electrode of the emission transistor OFG2. It does not have the two transfer transistors TG2B and the signal line SL10 connected to the transfer gate TRY2. Except for this point, the pixel array unit 111B has substantially the same configuration as the pixel array unit 111.
  • the number of signal lines connected to the sensor pixel PX2 is smaller than the number of signal lines connected to the sensor pixel PX1 as in the pixel array unit 111. Therefore, it is advantageous to realize the miniaturization of the entire configuration.
  • the sensor pixel PX2 which is a ZAF pixel, has an emission transistor OFG2. Therefore, even when the sensor pixel PX2 shares the charge-voltage conversion unit (FD) with other normal pixels, the sensor can be sensored by turning on the emission transistor OFG2 when reading out the normal pixel. It is possible to prevent the signal charge overflowing from the pixel PX2 from flowing into the shared charge-voltage conversion unit.
  • FD charge-voltage conversion unit
  • the upper limit of the saturation capacity of the charge holding unit MEM2 is the upper limit of the saturation capacity of the charge holding unit MEM2 in the sensor pixel PX2 of the pixel array unit 111. Will be lower than.
  • the upper limit of the saturation capacity of the photoelectric conversion unit PD2 in the pixel array unit 111B is lower than the upper limit of the saturation capacity of the photoelectric conversion unit PD2 in the sensor pixel PX2 of the pixel array unit 111.
  • FIG. 11 is a circuit diagram showing a circuit configuration of the sensor pixel PX in the pixel array unit 111C as a third modification, and corresponds to FIG. 2 of the first embodiment.
  • FIGS. 12A and 12B show cross-sectional configuration examples of four sensor pixels PX1 to PX4 among the plurality of sensor pixels PX constituting the pixel array unit 111C, respectively.
  • FIG. 13 shows the planar configuration at the height position Lv7 shown in FIGS.
  • FIG. 12A and 12B in the four sensor pixels PX1 to PX4 arranged in a grid pattern of 2 rows and 2 columns.
  • FIG. 13 corresponds to FIG. 4G of the first embodiment.
  • FIG. 12A shows a cross section in the arrow-viewing direction along the XIIA-XIIA cutting line in the X-axis direction shown in FIG. 13
  • FIG. 12B shows the XIIB-XIIB cutting line in the Y-axis direction shown in FIG. It represents a cross section in the direction of the arrow along the line.
  • the pixel array unit 111C is configured so that the number of wirings of ZAF pixels is one less than the number of wirings of normal pixels.
  • the pixel array unit 111C as a third modification includes the transfer gate TRZ2 while the sensor pixel PX2, which is a ZAF pixel, has the emission transistor OFG2 and the signal line SL8 connected to the gate electrode of the emission transistor OFG2. It does not have one transfer transistor TG2A and a signal line SL9 connected to the transfer gate TRZ2. Except for this point, the pixel array unit 111C has substantially the same configuration as the pixel array unit 111.
  • the number of signal lines connected to the sensor pixel PX2 is smaller than the number of signal lines connected to the sensor pixel PX1 as in the pixel array unit 111. Therefore, it is advantageous to realize the miniaturization of the entire configuration.
  • the sensor pixel PX2 which is a ZAF pixel, has an emission transistor OFG2. Therefore, even when the sensor pixel PX2 shares the charge-voltage conversion unit (FD) with other normal pixels, the sensor can be sensored by turning on the emission transistor OFG2 when reading out the normal pixel. It is possible to prevent the signal charge overflowing from the pixel PX2 from flowing into the shared charge-voltage conversion unit.
  • FD charge-voltage conversion unit
  • the upper limit of the saturation capacity of the charge holding unit MEM2 is the upper limit of the saturation capacity of the charge holding unit MEM2 in the sensor pixel PX2 of the pixel array unit 111. Will be lower than.
  • the upper limit of the saturation capacity of the photoelectric conversion unit PD2 in the pixel array unit 111C is lower than the upper limit of the saturation capacity of the photoelectric conversion unit PD2 in the sensor pixel PX2 of the pixel array unit 111.
  • FIG. 14 is a circuit diagram showing the circuit configuration of the sensor pixel PX in the pixel array unit 111D as the fourth modification, and corresponds to FIG. 2 of the first embodiment.
  • FIGS. 15A and 15B show cross-sectional configuration examples of four sensor pixels PX1 to PX4 among the plurality of sensor pixels PX constituting the pixel array unit 111D, respectively.
  • FIGS. 3A and 3B of the form corresponds to FIGS. 3A and 3B of the form.
  • FIG. 16 shows the planar configuration at the height position Lv7 shown in FIGS. 15A and 15B in the four sensor pixels PX1 to PX4 arranged in a grid pattern of 2 rows and 2 columns.
  • FIG. 16 corresponds to FIG. 4G of the first embodiment.
  • 15A shows a cross section in the arrow-viewing direction along the XVA-XVA cutting line in the X-axis direction shown in FIG. 16
  • FIG. 15B shows the XVB-XVB cutting line in the Y-axis direction shown in FIG. It represents a cross section in the direction of the arrow along the line.
  • the pixel array unit 111D is configured so that the number of wirings of ZAF pixels is 2 less than the number of wirings of normal pixels.
  • the sensor pixel PX2 which is a ZAF pixel, has an emission transistor OFG2 and a signal line SL8 connected to the gate electrode of the emission transistor OFG2, while the transfer gate TRY2 and the transfer gate TRX2 are provided. It does not have a second transfer transistor TG2B including, a signal line SL10 connected to the transfer gate TRY2, and a signal line SL11 connected to the transfer gate TRX2. Except for these points, the pixel array unit 111D has substantially the same configuration as the pixel array unit 111.
  • the number of signal lines connected to the sensor pixel PX2 is 2 less than the number of signal lines connected to the sensor pixel PX1. Therefore, it is advantageous to realize the miniaturization of the entire configuration.
  • the sensor pixel PX2 which is a ZAF pixel, has an emission transistor OFG2. Therefore, even when the sensor pixel PX2 shares the charge-voltage conversion unit (FD) with other normal pixels, the sensor can be sensored by turning on the emission transistor OFG2 when reading out the normal pixel. It is possible to prevent the signal charge overflowing from the pixel PX2 from flowing into the shared charge-voltage conversion unit.
  • the sensor pixel PX2 since the sensor pixel PX2 does not have the transfer gate TRY2 and the transfer gate TRX2, the upper limit of the saturation capacity of the charge holding unit MEM2 is the charge holding unit MEM2 in the sensor pixel PX2 of the pixel array unit 111.
  • the upper limit of the saturation capacity of the photoelectric conversion unit PD2 in the pixel array unit 111B is lower than the upper limit of the saturation capacity of the photoelectric conversion unit PD2 in the sensor pixel PX2 of the pixel array unit 111.
  • FIG. 17 is a circuit diagram showing a circuit configuration of the sensor pixel PX in the pixel array unit 111E as a fifth modification, and corresponds to FIG. 2 of the first embodiment.
  • FIGS. 18A and 18B show cross-sectional configuration examples of four sensor pixels PX1 to PX4 among the plurality of sensor pixels PX constituting the pixel array unit 111E, respectively.
  • FIG. 19 shows the planar configuration at the height position Lv7 shown in FIGS.
  • FIG. 18A and 18B in the four sensor pixels PX1 to PX4 arranged in a grid pattern of 2 rows and 2 columns.
  • FIG. 19 corresponds to FIG. 4G of the first embodiment.
  • FIG. 18A shows a cross section in the arrow-viewing direction along the XVIIIA-XVIIIA cutting line in the X-axis direction shown in FIG. 19, and
  • FIG. 18B shows the XVIIIB-XVIIIB cutting line in the Y-axis direction shown in FIG. It represents a cross section in the direction of the arrow along the line.
  • the pixel array unit 111E is configured so that the number of wirings of ZAF pixels is 3 less than the number of wirings of normal pixels.
  • the sensor pixel PX2 which is a ZAF pixel, has an emission transistor OFG2 and a signal line SL8 connected to the gate electrode of the emission transistor OFG2, while the first transfer including the transfer gate TRZ2.
  • the sensor pixel PX2 which is a ZAF pixel, is a non-global shutter pixel and does not have a MEM2. Therefore, in the sensor pixel PX2, exposure and charge transfer are performed by rolling.
  • the pixel array unit 111E is designed so that the signal charge generated by the photoelectric conversion in the photoelectric conversion unit PD2 is transferred to the surface 11S1 of the semiconductor substrate 11 by diffusion. That is, the photoelectric conversion unit PD2 is extended to the vicinity of the transfer gate TRG2. Except for these points, the pixel array unit 111E has substantially the same configuration as the pixel array unit 111.
  • the number of signal lines SL connected to the sensor pixel PX2 is 3 less than the number of signal lines SL connected to the sensor pixel PX1. Therefore, it is advantageous to realize the miniaturization of the entire configuration.
  • the sensor pixel PX2 which is a ZAF pixel, has an emission transistor OFG2. Therefore, even when the sensor pixel PX2 shares the charge-voltage conversion unit (FD) with other normal pixels, the sensor can be sensored by turning on the emission transistor OFG2 when reading out the normal pixel. It is possible to prevent the signal charge overflowing from the pixel PX2 from flowing into the shared charge-voltage conversion unit.
  • FD charge-voltage conversion unit
  • FIG. 20 is a circuit diagram showing a circuit configuration of the sensor pixel PX in the pixel array unit 111F as a sixth modification, and corresponds to FIG. 2 of the first embodiment.
  • FIGS. 21A and 21B show cross-sectional configuration examples of four sensor pixels PX1 to PX4 among the plurality of sensor pixels PX constituting the pixel array unit 111F, respectively.
  • FIG. 22 shows the planar configuration at the height position Lv7 shown in FIGS.
  • FIG. 22 corresponds to FIG. 4G of the first embodiment.
  • 21A shows a cross section in the arrow-viewing direction along the XXIA-XXIA cutting line in the X-axis direction shown in FIG. 22, and
  • FIG. 21B shows the XXIB-XXIB cutting line in the Y-axis direction shown in FIG. It represents a cross section in the direction of the arrow along the line.
  • the pixel array unit 111F is configured so that the number of wirings of ZAF pixels is 4 less than the number of wirings of normal pixels.
  • the sensor pixel PX2 which is a ZAF pixel, includes the emission transistor OFG2, the signal line SL8 connected to the gate electrode of the emission transistor OFG2, and the first transfer transistor TG2A including the transfer gate TRZ2.
  • the second transfer transistor TG2B including the transfer gate TRY2 and the transfer gate TRX2, the signal line SL9 connected to the transfer gate TRZ2, the signal line SL10 connected to the transfer gate TRY2, and the signal line SL11 connected to the transfer gate TRX2 are not provided.
  • the sensor pixel PX2 which is a ZAF pixel, is a non-global shutter pixel and does not have a MEM2. Therefore, in the sensor pixel PX2, exposure and charge transfer are performed by rolling.
  • the pixel array unit 111F is designed so that the signal charge generated by the photoelectric conversion in the photoelectric conversion unit PD2 is transferred to the surface 11S1 of the semiconductor substrate 11 by diffusion. That is, the photoelectric conversion unit PD2 is extended to the vicinity of the transfer gate TRG2.
  • the number of signal lines SL connected to the sensor pixel PX2 is 4 less than the number of signal lines SL connected to the sensor pixel PX1. Therefore, it is more advantageous to realize the miniaturization of the entire configuration.
  • FIG. 23 shows a circuit configuration example of two sensor pixels PX1 and PX2 among a plurality of sensor pixels provided in the pixel array portion of the solid-state image sensor 201 according to the second embodiment of the present technology. Corresponds to FIG. 2 of the first embodiment.
  • a stacked solid-state image sensor 101 in which a photoelectric conversion unit and a memory are laminated has been described.
  • the planar solid-state image sensor 201 in which the photoelectric conversion unit and the memory are provided in the same layer will be described.
  • the solid-state image sensor 201 is significantly different from the solid-state image sensor 101 in that it does not have the transfer gate TRZ of the stacked solid-state image sensor 101 in terms of circuit configuration.
  • FIG. 24 shows a cross-sectional configuration example of two sensor pixels PX1 and PX2 out of a plurality of sensor pixels PX constituting the pixel array portion of the solid-state image sensor 201
  • FIG. 3A of the first embodiment shows a cross-sectional configuration example. It corresponds.
  • FIG. 25 shows a planar configuration along the surface 11S1 of the four sensor pixels PX1 to PX4 arranged in a grid pattern of 2 rows and 2 columns.
  • FIG. 25 corresponds to FIG. 4G of the first embodiment.
  • FIG. 24 shows a cross section in the arrow-viewing direction along the XXIV-XXIV cutting line in the X-axis direction shown in FIG. 25.
  • a light-shielding film 17 for shielding light from entering the charge-holding portions MEM1 and MEM2 is arranged so as to spread along the XY surface in the vicinity of the back surface 11S2.
  • element separation units 12 extending in the thickness direction (Z-axis direction) are provided. However, the element separation unit 12 is partially removed from the charge transfer path from the photoelectric conversion units PD1 and PD2 to the charge holding units MEM1 and MEM2.
  • the sensor pixel PX2 is a ZAF pixel in the solid-state image sensor 201 of the present embodiment as well as the solid-state image sensor 101 of the first embodiment.
  • the sensor pixels PX2 are not provided with the discharge transistor OFG2, the transfer gate TRY2, the transfer gate TRX2, and the signal lines SL8 to SL10 connected to them.
  • the number of signal lines SL connected to the sensor pixel PX2 is smaller than the number of signal lines SL connected to the sensor pixel PX1. Therefore, it is advantageous to realize the miniaturization of the entire configuration.
  • FIG. 26 is a circuit diagram showing a circuit configuration of sensor pixels PX in the pixel array portion of the solid-state image sensor 201A as a seventh modification, and corresponds to FIG. 2 of the first embodiment.
  • FIG. 27 shows a cross-sectional configuration example of two sensor pixels PX1 and PX2 among the plurality of sensor pixels PX constituting the pixel array portion of the solid-state image sensor 201A.
  • FIG. 28 shows a planar configuration along the surface 11S1 of the four sensor pixels PX1 to PX4 arranged in a grid pattern of 2 rows and 2 columns.
  • FIG. 28 corresponds to FIG. 4G of the first embodiment.
  • FIG. 27 shows a cross section in the arrow-viewing direction along the XXVII-XXVII cutting line in the X-axis direction shown in FIG. 28.
  • the solid-state image sensor 201A has the same configuration as the solid-state image sensor 201 of the second embodiment, except that the discharge transistor OFG2 and the signal line SL8 connected to the discharge transistor OFG2 are further provided.
  • FIG. 29 is a circuit diagram showing a circuit configuration of the sensor pixel PX in the pixel array portion of the solid-state image sensor 201B as an eighth modification, and corresponds to FIG. 2 of the first embodiment.
  • FIG. 30 shows a cross-sectional configuration example of two sensor pixels PX1 and PX2 among a plurality of sensor pixel PXs constituting the pixel array portion of the solid-state image sensor 201B.
  • FIG. 31 shows a planar configuration along the surface 11S1 of the four sensor pixels PX1 to PX4 arranged in a grid pattern of 2 rows and 2 columns.
  • FIG. 31 corresponds to FIG. 4G of the first embodiment.
  • FIG. 30 shows a cross section in the direction of the arrow along the XXX-XXX cutting line in the X-axis direction shown in FIG. 31.
  • the solid-state image sensor 201B is the second embodiment described above, except that the discharge transistor OFG2, the signal line SL8 connected to the discharge transistor, the transfer gate TRY2, and the signal line SL9 connected to the transfer gate TRY2 are further provided. It has the same configuration as the solid-state image sensor 201 of the above embodiment.
  • FIG. 32 is a circuit diagram showing a circuit configuration of the sensor pixel PX in the pixel array portion of the solid-state image sensor 201C as a ninth modification, and corresponds to FIG. 2 of the first embodiment.
  • FIG. 33 shows a cross-sectional configuration example of two sensor pixels PX1 and PX2 among the plurality of sensor pixels PX constituting the pixel array portion of the solid-state image sensor 201C.
  • FIG. 34 shows a planar configuration along the surface 11S1 of the four sensor pixels PX1 to PX4 arranged in a grid pattern of 2 rows and 2 columns.
  • FIG. 34 corresponds to FIG. 4G of the first embodiment.
  • FIG. 33 shows a cross section in the arrow-viewing direction along the XXXIII-XXXIII cutting line in the X-axis direction shown in FIG. 34.
  • the solid-state image sensor 201C has the same configuration as the solid-state image sensor 201 of the second embodiment, except that the transfer transistor TRY2 and the signal line SL9 connected to the transfer transistor TRY2 are further provided.
  • FIG. 35 is a block diagram showing a configuration example of the camera 2000 as an electronic device to which the present technology is applied.
  • the camera 2000 is an optical unit 2001 including a lens group or the like, an image pickup device (imaging device) 2002 to which the above-mentioned solid-state image pickup device 101 or the like (hereinafter referred to as a solid-state image pickup device 101 or the like) is applied, and a camera signal processing circuit.
  • a DSP (Digital Signal Processor) circuit 2003 is provided.
  • the camera 2000 also includes a frame memory 2004, a display unit 2005, a recording unit 2006, an operation unit 2007, and a power supply unit 2008.
  • the DSP circuit 2003, the frame memory 2004, the display unit 2005, the recording unit 2006, the operation unit 2007, and the power supply unit 2008 are connected to each other via the bus line 2009.
  • the optical unit 2001 captures incident light (image light) from the subject and forms an image on the image pickup surface of the image pickup apparatus 2002.
  • the image pickup apparatus 2002 converts the amount of incident light imaged on the image pickup surface by the optical unit 2001 into an electric signal in pixel units and outputs it as a pixel signal.
  • the display unit 2005 is composed of a panel-type display device such as a liquid crystal panel or an organic EL panel, and displays a moving image or a still image captured by the image pickup device 2002.
  • the recording unit 2006 records a moving image or a still image captured by the imaging device 2002 on a recording medium such as a hard disk or a semiconductor memory.
  • the operation unit 2007 issues operation commands for various functions of the camera 2000 under the operation of the user.
  • the power supply unit 2008 appropriately supplies various power sources serving as operating power sources for the DSP circuit 2003, the frame memory 2004, the display unit 2005, the recording unit 2006, and the operation unit 2007 to these supply targets.
  • the technology according to the present disclosure can be applied to various products.
  • the technology according to the present disclosure is realized as a device mounted on a moving body of any kind such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, and a robot. You may.
  • FIG. 36 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technique according to the present disclosure can be applied.
  • the vehicle control system 12000 includes a plurality of electronic control units connected via the communication network 12001.
  • the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an in-vehicle information detection unit 12040, and an integrated control unit 12050.
  • a microcomputer 12051, an audio image output unit 12052, and an in-vehicle network I / F (Interface) 12053 are shown as a functional configuration of the integrated control unit 12050.
  • the drive system control unit 12010 controls the operation of the device related to the drive system of the vehicle according to various programs.
  • the drive system control unit 12010 provides a driving force generator for generating the driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism for adjusting and a braking device for generating a braking force of a vehicle.
  • the body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs.
  • the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as headlamps, back lamps, brake lamps, blinkers or fog lamps.
  • the body system control unit 12020 may be input with radio waves transmitted from a portable device that substitutes for the key or signals of various switches.
  • the body system control unit 12020 receives inputs of these radio waves or signals and controls a vehicle door lock device, a power window device, a lamp, and the like.
  • the vehicle outside information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000.
  • the image pickup unit 12031 is connected to the vehicle exterior information detection unit 12030.
  • the vehicle outside information detection unit 12030 causes the image pickup unit 12031 to capture an image of the outside of the vehicle and receives the captured image.
  • the vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing such as a person, a vehicle, an obstacle, a sign, or a character on the road surface based on the received image.
  • the imaging unit 12031 is an optical sensor that receives light and outputs an electric signal according to the amount of the light received.
  • the image pickup unit 12031 can output an electric signal as an image or can output it as distance measurement information. Further, the light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.
  • the in-vehicle information detection unit 12040 detects the in-vehicle information.
  • a driver state detection unit 12041 that detects the driver's state is connected to the in-vehicle information detection unit 12040.
  • the driver state detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 determines the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated, or it may be determined whether the driver is dozing.
  • the microcomputer 12051 calculates the control target value of the driving force generator, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and the drive system control unit.
  • a control command can be output to 12010.
  • the microcomputer 12051 aims to realize the functions of ADAS (AdvancedDriverAssistanceSystem) including collision avoidance or impact mitigation of a vehicle, follow-up running based on an inter-vehicle distance, vehicle speed maintenance running, vehicle collision warning, vehicle lane deviation warning, and the like. Cooperative control can be performed.
  • ADAS AdvancedDriverAssistanceSystem
  • the microcomputer 12051 controls the driving force generator, the steering mechanism, the braking device, and the like based on the information around the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, so that the driver can control the driver. It is possible to perform coordinated control for the purpose of automatic driving, etc., which runs autonomously without depending on the operation.
  • the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the vehicle exterior information detection unit 12030.
  • the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or the oncoming vehicle detected by the external information detection unit 12030, and performs coordinated control for the purpose of anti-glare such as switching the high beam to the low beam. It can be carried out.
  • the audio image output unit 12052 transmits an output signal of at least one of audio and an image to an output device capable of visually or audibly notifying information to the passenger or the outside of the vehicle.
  • an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices.
  • the display unit 12062 may include, for example, at least one of an onboard display and a heads-up display.
  • FIG. 37 is a diagram showing an example of the installation position of the imaging unit 12031.
  • the imaging unit 12031 As the imaging unit 12031, the imaging units 12101, 12102, 12103, It has 12104 and 12105.
  • the imaging units 12101, 12102, 12103, 12104, 12105 are provided at positions such as, for example, the front nose, side mirrors, rear bumpers, back doors, and the upper part of the windshield in the vehicle interior of the vehicle 12100.
  • the imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the upper part of the windshield in the vehicle interior mainly acquire an image in front of the vehicle 12100.
  • the imaging units 12102 and 12103 provided in the side mirrors mainly acquire images of the side of the vehicle 12100.
  • the imaging unit 12104 provided on the rear bumper or the back door mainly acquires an image of the rear of the vehicle 12100.
  • the imaging unit 12105 provided on the upper part of the windshield in the vehicle interior is mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.
  • FIG. 37 shows an example of the photographing range of the imaging units 12101 to 12104.
  • the imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose
  • the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively
  • the imaging range 12114 indicates the imaging range of the imaging units 12102 and 12103.
  • the imaging range of the imaging unit 12104 provided on the rear bumper or the back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 as viewed from above can be obtained.
  • At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information.
  • at least one of the image pickup units 12101 to 12104 may be a stereo camera composed of a plurality of image pickup elements, or may be an image pickup element having pixels for phase difference detection.
  • the microcomputer 12051 has a distance to each three-dimensional object within the imaging range 12111 to 12114 based on the distance information obtained from the imaging units 12101 to 12104, and a temporal change of this distance (relative velocity with respect to the vehicle 12100).
  • a predetermined speed for example, 0 km / h or more.
  • the microcomputer 12051 can set an inter-vehicle distance to be secured in front of the preceding vehicle in advance, and can perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. In this way, it is possible to perform cooperative control for the purpose of automatic driving or the like in which the vehicle travels autonomously without depending on the operation of the driver.
  • the microcomputer 12051 converts three-dimensional object data related to a three-dimensional object into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that can be seen by the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, the microcomputer 12051 via the audio speaker 12061 or the display unit 12062. By outputting an alarm to the driver and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be provided.
  • At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays.
  • the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured image of the imaging units 12101 to 12104.
  • pedestrian recognition includes, for example, a procedure for extracting feature points in an image captured by an imaging unit 12101 to 12104 as an infrared camera, and pattern matching processing for a series of feature points indicating the outline of an object to determine whether or not the pedestrian is a pedestrian. It is done by the procedure to determine.
  • the audio image output unit 12052 When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio image output unit 12052 outputs a square contour line for emphasizing the recognized pedestrian.
  • the display unit 12062 is controlled so as to superimpose and display. Further, the audio image output unit 12052 may control the display unit 12062 so as to display an icon or the like indicating a pedestrian at a desired position.
  • the above is an example of a vehicle control system to which the technology according to the present disclosure can be applied.
  • the technique according to the present disclosure can be applied to the imaging unit 12031 among the configurations described above.
  • the solid-state image sensor 101 or the like shown in FIG. 1A or the like can be applied to the image pickup unit 12031.
  • excellent operation of the vehicle control system can be expected.
  • the imaging device of the present disclosure is not limited to the imaging device that detects the light amount distribution of visible light and acquires it as an image, and acquires the distribution of the incident amount of infrared rays, X-rays, particles, or the like as an image. It may be an image pickup device.
  • the imaging device of the present disclosure may be in the form of a module in which an imaging unit and a signal processing unit or an optical system are packaged together.
  • the memory holding type global shutter type back-illuminated image sensor has been described, but the present disclosure is not limited to this.
  • a back-illuminated image sensor of the FD holding type global shutter type may be used.
  • the charge is held by the charge-voltage conversion unit FD instead of the charge-holding unit MEM.
  • the solid-state image sensor 301 also includes a sensor pixel PX1 as a normal pixel and a sensor pixel PX2 as an image plane phase difference pixel.
  • FIG. 38 is a circuit diagram showing a circuit configuration in the solid-state image sensor 301 as the eighth modification of the present disclosure, and FIG.
  • the solid-state image sensor of the technique of the present disclosure may have a configuration such as the solid-state image sensor 101A shown in FIG. 40A or the solid-state image sensor 101B shown in FIG. 40B.
  • FIG. 40A is a block diagram showing a configuration example of the solid-state image sensor 101A as a ninth modification of the present disclosure.
  • FIG. 40B is a block diagram showing a configuration example of the solid-state image sensor 101B as the tenth modification of the present disclosure.
  • a data storage unit 119 is arranged between the column signal processing unit 113 and the horizontal drive unit 114, and the pixel signal output from the column signal processing unit 113 causes the data storage unit 119. It is supplied to the signal processing unit 118 via the signal processing unit 118.
  • the data storage unit 119 and the signal processing unit 118 are arranged in parallel between the column signal processing unit 113 and the horizontal drive unit 114.
  • the column signal processing unit 113 performs A / D conversion for converting an analog pixel signal into a digital pixel signal for each row of the pixel array unit 111 or for each of a plurality of rows of the pixel array unit 111. There is.
  • the second pixel may be, for example, a polarized pixel including an infrared light information acquisition pixel or a polarizer.
  • 41 and 42 are schematic views showing layout patterns of sensor pixels PX1 to PX4 in the pixel array unit 111 as the eleventh modification and the twelfth modification of the present disclosure, respectively. In FIG.
  • NIR pixels having a near-infrared filter NIR that selectively transmits near-infrared light instead of the color filter CF2 are arranged at the position of the sensor pixel PX2 which is the second pixel.
  • the polarized pixel in which the polarizer PL is arranged is arranged at the position of the sensor pixel PX2 which is the second pixel.
  • the sensor pixel PX2 which is the second pixel, may have all the gate electrodes corresponding to all the gate electrodes in the sensor pixel PX1 as the first pixel.
  • a signal line connected to a part of a plurality of gate electrodes in the second pixel is not provided. You can do it like this.
  • the transfer gates TRZ2, TRY2, and TRX2 are arranged respectively, and (a part of) the wiring connected to each of them is not provided.
  • the number of the second wirings in the second pixel is smaller than the number of the first wirings in the first pixel. Therefore, it is possible to reduce the size of the entire configuration while ensuring the operating performance required for the second pixel as much as possible.
  • the Si ⁇ 111 ⁇ substrate in the present disclosure is a substrate or wafer made of a silicon single crystal and having a crystal plane represented by ⁇ 111 ⁇ in the notation of the Miller index.
  • the Si ⁇ 111 ⁇ substrate in the present disclosure also includes a substrate or wafer whose crystal orientation is deviated by several degrees, for example, a substrate or wafer deviated by several degrees from the ⁇ 111 ⁇ plane in the closest [110] direction. Further, it also includes a silicon single crystal grown on a part or the entire surface of these substrates or wafers by an epitaxial method or the like.
  • the ⁇ 111 ⁇ planes are crystal planes equivalent to each other in terms of symmetry, which are (111) plane, (-111) plane, (1-11) plane, (11-1) plane, and (-) plane. It is a general term for the 1-11) plane, the (-11-1) plane, the (1-1-1) plane, and the (1-1-1) plane. Therefore, the description of the Si ⁇ 111 ⁇ substrate in the specification and the like of the present disclosure may be read as, for example, a Si (1-11) substrate.
  • the bar sign for expressing the negative index of the Miller index is replaced with a minus sign.
  • the ⁇ 110> direction in the description of the present invention is the [110] direction, the [101] direction, the [011] direction, the [-110] direction, and [1-10], which are crystal plane directions equivalent to each other in terms of symmetry.
  • Direction, [-101] direction, [10-1] direction, [0-11] direction, [01-1] direction, [-1-10] direction, [-10-1] direction and [0-1- 1] It is a general term for directions, and may be read as either.
  • etching is performed in a direction orthogonal to the element forming surface and a direction further orthogonal to the direction orthogonal to the element forming surface (that is, a direction parallel to the element forming surface).
  • Table 1 shows a specific combination of a plane and an orientation in which etching in the ⁇ 110> direction is established on the ⁇ 111 ⁇ plane, which is the crystal plane of the Si ⁇ 111 ⁇ substrate in the present invention. ..
  • the ⁇ 110> direction of the present disclosure is limited to a direction orthogonal to the ⁇ 111 ⁇ plane which is an element forming surface and a direction parallel to the element forming surface. That is, the combination of the element forming surface of the Si ⁇ 111 ⁇ substrate of the present disclosure and the orientation for etching the Si ⁇ 111 ⁇ substrate is selected from any of the combinations indicated by ⁇ in Table 1.
  • the Si ⁇ 111 ⁇ substrate includes, for example, a substrate in which the surface of the substrate is processed so as to have an off angle with respect to the ⁇ 112> direction, as shown in FIG. 44.
  • the off angle is 19.47 ° or less, even in the case of a substrate having an off angle, the etching rate in the ⁇ 111> direction, that is, the direction having three Si back bonds, is in the ⁇ 110> direction, that is, Si back.
  • the relationship in which the etching rate in the direction of having one bond is sufficiently high is maintained.
  • the off angle increases, the number of steps increases and the density of microsteps increases, so 5 ° or less is preferable.
  • the off angle may be in the ⁇ 110> direction, and the off angle direction does not matter.
  • the Si plane orientation can be analyzed by using an X-ray diffraction method, an electron beam diffraction method, an electron backscatter diffraction method, or the like. Since the number of Si backbonds is determined by the crystal structure of Si, the number of backbonds can also be analyzed by analyzing the Si plane orientation.
  • the first pixel has a first transistor including the first gate electrode.
  • the first wiring of a part of the m first wiring and the second wiring of a part of the n second wiring are common common wirings (1) or The imaging device according to (2).
  • the common wiring includes a first common wiring and a second common wiring.
  • the first pixel comprises a first reset transistor including the first gate electrode connected to the first common wiring and a first selection transistor including the first gate electrode connected to the second common wiring.
  • the second pixel includes a second reset transistor including the second gate electrode connected to the first common wiring and a second selection transistor including the second gate electrode connected to the second common wiring.
  • the first pixel is an imaging pixel that acquires visible light information.
  • the imaging device according to any one of (1) to (4) above, wherein the second pixel acquires information other than the visible light information.
  • the second pixel is an image plane phase difference detection pixel, an infrared light information acquisition pixel, or a polarizer.
  • the imaging apparatus according to any one of (1) to (6) above, wherein the shape of the forming region of the first pixel and the shape of the forming region of the second pixel are substantially the same.
  • the first pixel further includes a first photoelectric conversion unit capable of generating a first charge according to the amount of received light by photoelectric conversion, and a first charge-voltage conversion unit that converts the first charge into a voltage signal.
  • the second pixel further includes a second photoelectric conversion unit capable of generating a second charge according to the amount of received light by photoelectric conversion, and a second charge-voltage conversion unit that converts the second charge into a voltage signal.
  • p p is a natural number smaller than m
  • first transistors are provided between the first photoelectric conversion unit and the first charge-voltage conversion unit.
  • q q is an integer of 0 or more smaller than p) of second transistors are provided between the second photoelectric conversion unit and the second charge-voltage conversion unit (1).
  • the first pixel is a global shutter pixel further including a charge holding unit capable of holding the first charge between the first photoelectric conversion unit and the first charge-voltage conversion unit (8).
  • Imaging device An electronic device equipped with an imaging device The image pickup device A first pixel having m (m is an integer of 2 or more) first wiring and m first gate electrodes connected to the m first wiring, respectively. An electronic device including n (n is a natural number smaller than m) second wiring and a second pixel having n second gate electrodes connected to each of the n second wirings.

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PCT/JP2020/044298 2019-12-10 2020-11-27 撮像装置および電子機器 Ceased WO2021117511A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN202080081365.5A CN114731380B (zh) 2019-12-10 2020-11-27 成像装置和电子设备
JP2021563853A JPWO2021117511A1 (https=) 2019-12-10 2020-11-27
EP20899725.4A EP4075793A4 (en) 2019-12-10 2020-11-27 Imaging device and electronic apparatus
US17/756,591 US12155950B2 (en) 2019-12-10 2020-11-27 Imaging device that allows miniaturization and electronic apparatus

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116801121A (zh) * 2022-03-09 2023-09-22 思特威(上海)电子科技股份有限公司 像素结构、图像传感器、电子设备及控制方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113437101B (zh) * 2015-02-27 2025-03-21 索尼公司 固态图像感测装置及电子装置
TWI869504B (zh) * 2019-12-13 2025-01-11 日商索尼半導體解決方案公司 攝像裝置及電子機器

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013157883A (ja) * 2012-01-31 2013-08-15 Sony Corp 固体撮像素子およびカメラシステム
JP2015142254A (ja) * 2014-01-29 2015-08-03 キヤノン株式会社 固体撮像装置及びその駆動方法並びにそれを用いた撮像システム
WO2016039152A1 (ja) * 2014-09-10 2016-03-17 ソニー株式会社 固体撮像装置およびその駆動方法、並びに電子機器
WO2016136486A1 (ja) 2015-02-27 2016-09-01 ソニー株式会社 固体撮像装置及び電子機器
JP2019036770A (ja) * 2017-08-10 2019-03-07 キヤノン株式会社 撮像装置及び撮像システム
JP2019193169A (ja) * 2018-04-26 2019-10-31 キヤノン株式会社 撮像装置、撮像システム、および、移動体

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100697793B1 (ko) * 2005-12-28 2007-03-21 후지쯔 가부시끼가이샤 반도체 촬상 장치
JP2009038263A (ja) * 2007-08-02 2009-02-19 Sharp Corp 固体撮像素子および電子情報機器
JP5693082B2 (ja) * 2010-08-09 2015-04-01 キヤノン株式会社 撮像装置
GB2492387B (en) 2011-06-30 2017-07-19 Cmosis Nv Pixel array with individual exposure control for a pixel or pixel region
JP5556823B2 (ja) * 2012-01-13 2014-07-23 株式会社ニコン 固体撮像装置および電子カメラ
JP2015037102A (ja) * 2013-08-12 2015-02-23 株式会社東芝 固体撮像装置
JP6176062B2 (ja) * 2013-11-06 2017-08-09 ソニー株式会社 固体撮像装置およびその駆動方法、並びに電子機器
JP6233188B2 (ja) * 2013-12-12 2017-11-22 ソニー株式会社 固体撮像素子およびその製造方法、並びに電子機器
JP2015164284A (ja) * 2014-01-28 2015-09-10 キヤノン株式会社 固体撮像素子、動き情報取得装置、および撮像装置
US9699393B2 (en) * 2014-06-26 2017-07-04 Semiconductor Components Industries, Llc Imaging systems for infrared and visible imaging with patterned infrared cutoff filters
JP6595839B2 (ja) * 2015-08-05 2019-10-23 キヤノン株式会社 撮像素子およびその制御方法、ならびに撮像装置
TWI717450B (zh) * 2016-02-18 2021-02-01 日商新力股份有限公司 固體攝像裝置、固體攝像裝置之驅動方法、及電子機器
JP6953263B2 (ja) * 2017-10-05 2021-10-27 キヤノン株式会社 固体撮像装置および撮像システム

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013157883A (ja) * 2012-01-31 2013-08-15 Sony Corp 固体撮像素子およびカメラシステム
JP2015142254A (ja) * 2014-01-29 2015-08-03 キヤノン株式会社 固体撮像装置及びその駆動方法並びにそれを用いた撮像システム
WO2016039152A1 (ja) * 2014-09-10 2016-03-17 ソニー株式会社 固体撮像装置およびその駆動方法、並びに電子機器
WO2016136486A1 (ja) 2015-02-27 2016-09-01 ソニー株式会社 固体撮像装置及び電子機器
JP2019036770A (ja) * 2017-08-10 2019-03-07 キヤノン株式会社 撮像装置及び撮像システム
JP2019193169A (ja) * 2018-04-26 2019-10-31 キヤノン株式会社 撮像装置、撮像システム、および、移動体

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4075793A4

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116801121A (zh) * 2022-03-09 2023-09-22 思特威(上海)电子科技股份有限公司 像素结构、图像传感器、电子设备及控制方法

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