WO2021115292A1 - 芯片模组及其制作方法和电子设备 - Google Patents
芯片模组及其制作方法和电子设备 Download PDFInfo
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- WO2021115292A1 WO2021115292A1 PCT/CN2020/134741 CN2020134741W WO2021115292A1 WO 2021115292 A1 WO2021115292 A1 WO 2021115292A1 CN 2020134741 W CN2020134741 W CN 2020134741W WO 2021115292 A1 WO2021115292 A1 WO 2021115292A1
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- shielding
- chip
- antenna structure
- chip module
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6661—High-frequency adaptations for passive devices
- H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
Definitions
- This application relates to the field of wireless communication technology, and in particular to a chip module, a manufacturing method thereof, and electronic equipment.
- the development of wireless communication technology requires that the chip modules used for communication become smaller and smaller, and their functions are becoming more and more powerful.
- the traditional method installs the chip-level antenna together with the radio frequency transceiver on the circuit board, so that the antenna and the circuit board occupy a certain space and hinder the miniaturization of the chip module.
- the electromagnetic radiation generated by the antenna is relatively large, and it is easy to cause electromagnetic interference to the electrical performance of peripheral devices, especially the bare chip structure of the chip.
- the device and even the system fail, which affects the quality of the product and the entire cycle of the research and development project. Therefore, how to solve the isolation problem between the chip and the antenna needs to be a key consideration for designers.
- the main purpose of the present application is to provide a chip module and its manufacturing method and electronic equipment, aiming to reduce the installation space of the chip module, reduce the electromagnetic interference of the antenna to the chip, and improve the stability of the chip operation.
- the present application provides a chip module, the chip module includes:
- a shielding structure, the shielding structure is provided in the substrate and is formed with an installation space;
- a chip, the chip is accommodated in the installation space and communicated with an external circuit;
- the antenna structure at least part of the antenna structure is exposed on the substrate, and the antenna structure is electrically connected to the chip.
- the cylindrical shielding body includes a top shielding layer and a side shielding layer connected to the top shielding layer, the side shielding layer is disposed along the outer edge of the top shielding layer, and the The top shielding layer and the side shielding layer jointly enclose an installation space, and the shielding plate is connected to a side of the side shielding layer away from the top shielding layer.
- the number of the side shielding layers is multiple, the plurality of side shielding layers are arranged at intervals along the outer edge of the top shielding layer, and the top shielding layer and the plurality of side shielding layers are spaced apart from each other.
- the side shielding layers jointly enclose an installation space, and the shielding plate is connected to the side of each side shielding layer away from the top shielding layer.
- the chip includes a first pin and a second pin
- a material of the shielding plate includes a conductive material
- the shielding plate includes a main body and a connecting part, and the main body is covered with At the opening, electrically connecting the cylindrical shielding body and the first pin;
- the substrate includes an encapsulation layer
- the encapsulation layer includes an inner encapsulation portion and an outer encapsulation portion
- the inner encapsulation portion is disposed in the mounting space and abuts against the chip and the encapsulation layer.
- the outer packaging part is arranged around the shielding structure.
- the substrate further includes a first insulating layer, the first insulating layer is provided on the surface of the packaging layer, and the first insulating layer is further formed with a through hole;
- the antenna structure is a redistribution layer, the redistribution layer is disposed in the first insulating layer, and at least a part of the redistribution layer penetrates the through hole.
- the chip module further includes a signal line, the signal line passes through the outer packaging part, and one end of the signal line is electrically connected to the redistribution layer and extends into the place. The other end of the part of the through hole is used to electrically connect with the chip.
- solder balls the number of the solder balls is at least three, one of the solder balls is arranged in one of the exposed openings, one of the solder balls is electrically connected to the signal line, and one of the solder balls is connected to the shield
- the main body of the board is electrically connected, and a solder ball is electrically connected to the connecting portion of the shielding board.
- This application also proposes a method for manufacturing a chip module, which includes the following steps:
- An antenna structure is provided, the antenna structure is arranged on a carrier board, the antenna structure is covered with a first insulating layer, and a through hole is formed in the portion of the first insulating layer corresponding to the antenna structure to connect the antenna structure to the signal line;
- a cylindrical shield body with an installation space is arranged on a surface of the first insulating layer facing away from the carrier board, wherein the installation space has an opening, and the chip is disposed in the installation space through the opening;
- the antenna structure is provided, the antenna structure is arranged on a carrier, the antenna structure is covered with a first insulating layer, and a through hole is formed in the portion of the first insulating layer corresponding to the antenna structure to
- the steps of connecting the antenna structure with the signal line include:
- the first insulating layer is provided with a cylindrical shielding body having an installation space, wherein the step of having an opening in the installation space includes:
- top shielding layer Forming a top shielding layer on the surface of the first insulating layer away from the antenna structure, wherein the outer contour of the top shielding layer does not coincide with the outer contour of the redistribution layer projected on the back of the first insulating layer;
- a side shielding layer is formed along the outer edge of the top shielding layer, so that the top shielding layer and the side shielding layer form a cylindrical shielding body with installation space, wherein the side of the side shielding layer away from the top shielding layer encloses and forms an opening.
- the step of arranging the chip through the opening in the installation space includes:
- the polished chip is attached to the inner wall surface of the installation space.
- the step of setting the packaging layer of the packaging chip and the cylindrical shielding body includes:
- first signal connection section Forming a first signal connection section on the surface of the first insulating layer away from the antenna structure, and the first signal connection section is electrically connected to the antenna structure;
- An encapsulation layer covering the first signal connection section, the second signal connection section, the chip and the cylindrical shielding body is arranged on the side of the first insulating layer away from the antenna structure.
- the step of exposing the pins of the chip, the upper end of the cylindrical shielding body, and the signal line of the antenna structure to the packaging layer includes:
- the thinning is stopped.
- the pins of the chip, the side cavity wall of the mounting space, and the upper end of the second signal connection section of the signal line are all exposed on the thinned and exposed surface After the steps to stop thinning, it also includes:
- a third signal connection section is laid on the surface of the encapsulation layer to form a signal line connecting the antenna structure, wherein one side of the third signal connection section is connected to the second signal connection section of the signal line.
- the step of providing a shielding plate covering the opening to form a shielding structure includes:
- a metal layer connecting the cylindrical shield body and the chip pins is formed on the packaging layer
- the metal layer is etched to form a main body portion connecting the cylindrical shield body and the first pin of the chip, and a connecting portion connecting the second pin of the chip is formed, forming a shielding plate to form a shielding structure.
- the metal layer is etched to form a main body portion connecting the cylindrical shield body and the first pin of the chip, and a connecting portion connecting the second pin of the chip is formed to form a shield
- the second insulating layer forms at least three exposure openings that expose the signal line, the main body portion of the shielding plate, and the connection portion of the shielding plate;
- a solder ball is formed at the exposed opening so that one of the solder balls is electrically connected to the third signal connection section, one of the solder balls is electrically connected to the main body of the shielding plate, and one of the solder balls is electrically connected to the shielding plate.
- the connection part of the board is electrically connected.
- This application also proposes an electronic device, including a chip module, and the chip module includes a substrate;
- a shielding structure, the shielding structure is provided in the substrate and is formed with an installation space;
- a chip, the chip is accommodated in the installation space and communicated with an external circuit;
- the antenna structure at least part of the antenna structure is exposed on the substrate, and the antenna structure is electrically connected to the chip.
- An antenna structure is provided, the antenna structure is arranged on a carrier board, the antenna structure is covered with a first insulating layer, and a through hole is formed in the portion of the first insulating layer corresponding to the antenna structure to connect the antenna structure to the signal line;
- a cylindrical shield body with an installation space is arranged on a surface of the first insulating layer facing away from the carrier board, wherein the installation space has an opening, and the chip is disposed in the installation space through the opening;
- a shielding structure is provided in the substrate, and a mounting space is provided in the shielding structure, and then the chip is placed in the mounting space.
- the pins of the chip are connected to the external circuit, and the antenna structure is further fixed through the substrate.
- the chip is arranged in the installation space of the shielding structure.
- the shielding structure can shield the electromagnetic radiation, which reduces the electromagnetic interference of the antenna to the chip and improves the stability of the chip operation.
- the shielding structure and the antenna structure are all packaged in the substrate, when circuit connection is required, a circuit layer is provided inside the substrate to realize electrical connection of various components, thereby saving the installation space of the chip module. In this way, the technical solution of the present application can reduce the installation space of the chip module, reduce the electromagnetic interference of the antenna to the chip, and improve the stability of the chip operation.
- FIG. 1 is a schematic structural diagram of an embodiment of a chip module according to the application where a first insulating layer and an antenna structure are provided on a carrier board;
- FIG. 2 is a schematic structural diagram of an embodiment in which a first insulating layer, an antenna structure, a cylindrical shielding body, and a chip are provided on the carrier board of the chip module of the present application;
- FIG. 3 is a schematic structural diagram of an embodiment of the chip module of the application having a first insulating layer, an antenna structure, a cylindrical shielding body, a chip, and an encapsulation layer on a carrier board;
- FIG. 5 is a schematic structural diagram of an embodiment of a chip module of the application.
- Fig. 6 is a partial schematic diagram of Fig. 5A;
- FIG. 8 is a schematic structural diagram of an embodiment of the chip module according to the application after the carrier board is removed;
- FIG. 9 is a flowchart of an embodiment of a method for manufacturing a chip module according to the present application.
- FIG. 10 is a flow chart of an embodiment of a method for manufacturing a chip module according to the present application.
- FIG. 11 is a flowchart of an embodiment of a method for manufacturing a chip module according to the present application.
- FIG. 13 is a flow chart of an embodiment of a method for manufacturing a chip module according to the present application.
- FIG. 14 is a flow chart of an embodiment of a method for manufacturing a chip module according to the present application.
- the present application proposes a chip module 100, which aims to reduce the installation space of the chip module 100, reduce the electromagnetic interference of the antenna to the chip 30, and improve the stability of the operation of the chip 30.
- the chip module 100 can be applied to electronic equipment. It is understandable that the electronic equipment can be, but not limited to, mobile phones, tablet computers, personal digital assistants (PDAs), e-book readers, MP3 (dynamic Video experts compress standard audio layer 3, Moving Picture Experts Group Audio Layer III) players, MP4 (Moving Picture Experts compress standard audio layer 4, Moving Picture Experts Group Audio Layer IV) players, laptops, car computers, set-top boxes, smart Televisions, wearable devices, navigators, handheld game consoles, etc.
- PDAs personal digital assistants
- MP3 dynamic Video experts compress standard audio layer 3, Moving Picture Experts Group Audio Layer III
- MP4 Motion Picture Experts compress standard audio layer 4, Moving Picture Experts Group Audio Layer IV
- the chip module 100 includes:
- a shielding structure 20, the shielding structure 20 is provided in the substrate 10, and an installation space 211 is formed;
- a chip 30, the chip 30 is accommodated in the installation space 211, and communicates with an external circuit;
- the antenna structure 40 at least part of the antenna structure 40 is exposed on the substrate 10, and the antenna structure 40 is electrically connected to the chip 30.
- the inside of the substrate 10 may include a separation layer made of multiple insulating materials. This arrangement can facilitate the packaging of the chip 30, the shielding structure 20 and the antenna structure 40, and the thickness of the substrate 10 can be set as required to ensure the stability and packaging effect. Miniaturization of the chip module 100 volume.
- the outer contour of the substrate 10 can also be set according to actual needs. Specifically, the outer contour of the substrate 10 can be set to be polygonal or circular, as long as it is convenient to package the chip 30, the shielding structure 20, and the antenna structure 40.
- the chip 30 is a structure with a silicon-containing semiconductor.
- the silicon-containing semiconductor is a wafer or other functional electronic components.
- the wafer refers to a silicon wafer used in the production of a silicon semiconductor integrated circuit. Because of its circular shape, it is called a wafer; it can be processed into a variety of circuit element structures on a silicon wafer to become an integrated circuit product with specific electrical functions.
- the antenna structure 40 may be a conventional antenna array, as long as it is convenient for wireless communication.
- a shielding structure 20 is provided in the substrate 10, and a mounting space 211 is provided in the shielding structure 20, and then the chip 30 is placed in the mounting space 211, wherein the pins of the chip 30 are connected to the external circuit, and further through The substrate 10 fixes the antenna structure 40. Since the chip 30 is placed in the installation space 211 of the shielding structure 20, when the antenna structure 40 generates electromagnetic radiation when the antenna structure 40 is working, the shielding structure 20 can shield the electromagnetic radiation, reducing the electromagnetic radiation of the antenna to the chip 30. Interference improves the stability of the operation of the chip 30.
- the shielding structure 20 and the antenna structure 40 are all packaged in the substrate 10, when circuit connection is required, a circuit layer is provided inside the substrate 10 to realize the electrical connection of various components, thereby saving the cost of the chip module 100. Installation space. In this way, the technical solution of the present application can reduce the installation space of the chip module 100, reduce the electromagnetic interference of the antenna to the chip 30, and improve the stability of the operation of the chip 30.
- the opening 2111 is provided to facilitate the placement of the chip 30 in the mounting space 211.
- the chip module 100 further includes a glue 60 that connects a surface of the chip 30 with the mounting space 211.
- the cavity wall is glued and fixed to ensure the initial fixation of the chip 30 and facilitate subsequent processing steps.
- the 60 pieces of glue can be conductive glue.
- the back of the chip 30 is fixed to the cylindrical shield body 21 by conductive glue. Considering that when the shielding structure 20 is shielded, electromagnetic signals will be transmitted in the shielding structure 20, and conductive The glue prevents the resistance of the shielding structure 20 from changing, and ensures the transmission of electromagnetic signals and the shielding effect.
- the cylindrical shield body 21 includes a top shield layer 212 and a side shield layer 213 connected to the top shield layer 212, and the side shield layer 213 extends along The outer edge of the top shielding layer 212 is provided, the top shielding layer 212 and the side shielding layer 213 are jointly enclosed to form an installation space 211, and the shielding plate 22 is connected to the side shielding layer 213 and facing away from the top shielding.
- the side shielding layer 213 can be a structure surrounding the outer edge of the top shielding layer 212, so that the cylindrical shielding body 21 is roughly a cylindrical structure with an opening 2111 at one end and a sealed end at the other end. This arrangement can greatly increase the shielding area.
- the number of the side shielding layers 213 is multiple, and the plurality of side shielding layers 213 are arranged at intervals along the outer edge of the top shielding layer 212, and the top shielding layers 212 and A plurality of the side shielding layers 213 are jointly enclosed to form an installation space 211, and the shielding plate 22 is connected to a side of each of the side shielding layers 213 away from the top shielding layer 212.
- a plurality of side shielding layers 213 are provided to provide support for the placement of the shielding plate 22, which greatly increases the shielding area of the cylindrical shielding body 21 and better guarantees the stability of the chip 30 in operation.
- the pins of the chip 30 may also be connected to an external circuit through the side shielding layer 213, which improves the adaptability of the chip 30 setting and improves the stability of the chip module 100.
- the substrate 10 includes an encapsulation layer 11, the encapsulation layer 11 includes an inner encapsulation portion 111 and an outer encapsulation portion 112, and the inner encapsulation portion 111 is disposed at all.
- the outer packaging portion 112 is arranged around the shielding structure 20. The chip 30 and the shielding structure 20 are fixed by providing the inner packaging portion 111 of the packaging layer 11 to ensure the stability of the operation of the chip 30.
- the material for the inner encapsulation part 111 is injected into the mounting space 211, and the material for the inner encapsulation part 111 injected is moderate.
- a shielding plate 22 covering the inner packaging part 111 is set.
- the outer packaging portion 112 is provided to fix the shielding structure 20 and the antenna structure 40 to ensure the stability of the chip 30 operation.
- the material for the outer packaging portion 112 may be coated on the outside of the packaging structure (outside the installation space 211), so as to fix the shielding structure 20.
- the material of the encapsulation layer 11 may specifically be an insulating material, as long as it is convenient to manufacture the encapsulation layer 11.
- the substrate 10 further includes a first insulating layer 12, the first insulating layer 12 is provided on the surface of the packaging layer 11, the first insulating layer Layer 12 is also formed with through holes;
- electronic components or other functional devices are arranged on the redistribution layer, so that the redistribution layer has corresponding functions and ensures the normal operation of the antenna structure 40 , And then ensure the stability of the chip module 100 work.
- the through holes are provided to facilitate the electrical connection between the redistribution layer and the external circuit (or the chip module 100).
- the chip module 100 further includes a signal line 50, the signal line 50 passes through the outer package portion 112, and one end of the signal line 50 It is electrically connected to the part of the redistribution layer extending into the through hole, and the other end is used to electrically connect to the chip 30.
- the arrangement of the signal line 50 facilitates the selection of the location of the antenna structure 40, thereby facilitating the normal operation of the chip module 100.
- the signal line 50 may include a first signal connection section 51 disposed between the encapsulation layer 11 and the first insulating layer 12.
- One side of the first signal connection section 51 is connected to the antenna structure 40, and the signal line 50 is also It includes a second signal connection section 52 penetrating through the encapsulation layer 11, the second signal connection section 52 is connected to a side of the first signal connection section 51 away from the antenna structure 40, and the signal line 50 also includes a third signal connection section 53.
- the third signal connection section 53 is provided on the side of the packaging layer 11 away from the first signal connection section 51, and is electrically connected to the second signal connection section 52.
- the substrate 10 further includes a supporting connection layer 13, the supporting connection layer 13 is provided on the surface of the packaging layer 11 away from the first insulating layer 12 ,
- the supporting and connecting layer 13 includes:
- the second insulating layer 131 covers the signal line 50 and the shielding plate 22 of the shielding structure 20, and the second insulating layer 131 further includes at least three exposed openings 1311, at least three The exposing opening 1311 is respectively used for exposing at least part of the signal line 50, the main body 221 of the shielding plate 22, and the connecting part 222 of the shielding plate 22; and
- solder balls 132 the number of solder balls 132 is at least three, one solder ball 132 is disposed in one of the exposed openings 1311, one solder ball 132 is electrically connected to the signal line 50, and one solder ball 132 is electrically connected to the signal line 50.
- the solder ball 132 is electrically connected to the main body portion 221 of the shielding plate 22, and a solder ball 132 is electrically connected to the connecting portion 222 of the shielding plate 22.
- the chip 30 and the antenna structure 40 are better electrically connected to the external circuit.
- the second insulating layer 131 is used to isolate the internal circuit of the chip module 100 from the external circuit when electrically connected to avoid short circuits, and on the other hand, it can facilitate the formation of the solder balls 132, thereby improving the chip module 100.
- the connection effect with the external circuit By setting bumping (bumps, solder balls 132) to connect with conductive pads on the circuit board, the chip module 100 can be driven well when power is on.
- the solder balls 132 can be made of copper and tin materials to ensure the conductive effect. Alternatively, a metal material (such as gold) with better conductivity can be provided to improve the electrical signal transmission of the chip module 100.
- the number of the solder balls 132 is at least three, and at least three of the solder balls 132 are evenly arranged in the exposure opening 1311.
- the manufacturing method of the chip module 100 includes the following steps:
- a release film is set on the carrier 70.
- the release film is an auxiliary thermal transfer film.
- the substrate is generally PET, and the conventional thickness is 12um-100um.
- a cold and hot tear-off film can be used, and the release film can be attached to the surface of the carrier 70 when needed.
- the surface where the release film and the chip module 100 are attached is processed to remove adhesion; usually, the chip module 100 and the carrier 70 will interact with each other after processing. It’s not easy to separate.
- the release film usually has a slight stickiness.
- a vacuum suction device (specifically, a vacuum suction nozzle, or a suction nozzle of a Die Bonder placement machine) can be controlled to suck the chip module 100 and then transport it to a suitable place.
- Step S20 a cylindrical shield body 21 with an installation space 211 is provided on a surface of the first insulating layer 12 facing away from the carrier 70, wherein the installation space 211 has an opening 2111, and the chip 30 is disposed in the installation space through the opening 2111 211; in one implementation, photolithography is used to make the first insulating layer 12, the coated first insulating layer 12 can be exposed, and then the first insulating layer 12 can be etched to form a cylindrical shield body 21
- the mounting groove is formed in the mounting groove to form a cylindrical shield body 21.
- a deposition process and an etching process are used to form the mounting groove of the first insulating layer 12, which is then used to install the cylindrical shield body 21.
- the cylindrical shield body 21 may also be a cylindrical shield fabricated externally. The main body 21 is directly installed in the installation groove when needed.
- Step S30 Set the package layer 11 of the packaged chip 30 and the cylindrical shield body 21, and expose the pins of the chip 30, the upper end of the cylindrical shield body 21 and the signal line 50 on the package layer 11; in this embodiment, The chip 30 and the cylindrical shield body 21 are fixed by providing the encapsulation layer 11, thereby ensuring the structural stability of the chip module 100.
- a coater can be used to coat the material for the encapsulation layer 11.
- a sensor for alignment can be provided on the coater, and when the sensor for alignment detects the alignment mark At this time, the detection result is fed back to the control system, so that the control system can obtain the distance of the spray head relative to the chip 30 based on the detection result, thereby facilitating the control of the spray head of the coating machine.
- the spray head may include a plurality of nozzles, so as to facilitate the improvement of the efficiency of coating the encapsulation layer 11.
- the electromagnetic waves that may cause interference will flow to the earth through the ground wire, and the signal in the shielded equipment or wire can be normal Transmission, thereby avoiding electromagnetic interference.
- a shielding structure 20 is provided in the chip module 100, and a mounting space 211 is provided in the shielding structure 20, and then the chip 30 is placed in the mounting space 211, wherein the pins of the chip 30 are connected to the external circuit,
- the antenna structure 40 is further fixed. Since the chip 30 is placed in the installation space 211 of the shielding structure 20, when the antenna structure 40 generates electromagnetic radiation during operation, the shielding structure 20 can shield the electromagnetic radiation, reducing the electromagnetic interference of the antenna to the chip 30 , Improve the stability of chip 30 operation.
- the chip 30, the shielding structure 20 and the antenna structure 40 are all packaged, when circuit connection is required, a circuit layer is provided inside the substrate 10 to realize electrical connection of various components, thereby saving the installation space of the chip module 100.
- the technical solution of the present application can reduce the installation space of the chip module 100, reduce the electromagnetic interference of the antenna to the chip 30, and improve the stability of the operation of the chip 30.
- a support layer is provided on the circuit layer group; the first insulating layer 12 is provided to provide support for subsequent circuits and prevent subsequent circuits from spreading to the circuit layer group during production, ensuring the electrical connection stability of the chip module 100.
- the manufacturing method of the support layer may include coating a PI layer (polyimide, polyimide film) on the circuit layer group by a spin coating method.
- the thermosetting polyimide has excellent thermal stability and chemical resistance. And mechanical properties, can provide a good support for the subsequent setting of the circuit.
- the PI layer is cured by exposure and development, so as to form a support layer with insulating function.
- a seed layer is formed by sputtering on the support layer; the seed layer is the electrical connection layer, and the electrical connection layer is provided to facilitate the subsequent electroplating process.
- the material of the electrical connection layer can be a metal material, and specifically it can be copper.
- Argon gas is passed through the target material for sputtering to form an electrical connection layer.
- a pulsed laser deposition method may also be used to deposit the electrical connection layer.
- the traditional electroplating layer can be aluminum. As the size of the semiconductor chip 30 decreases, the high resistance of aluminum gradually manifests itself, which makes the conductivity of the device worse.
- the electrical connection layer if silver is used as the electrical connection layer, the low resistivity advantage of silver can make the device have excellent electrical conductivity.
- the disadvantage is that the cost is too high.
- the advantage of using copper as the electrical connection layer is that the cost is lower than that of silver, the resistivity is much lower than that of aluminum and slightly higher than that of silver, and the conductivity is good.
- Step S13 setting a photoresist covering the seed layer, using photolithography technology to expose and develop the photoresist to form a photoresist layer pattern; using photolithography technology to expose and develop the photoresist to form Photoresist layer pattern; photoresist is an organic compound whose solubility in a specific developer changes greatly before and after exposure.
- the photoresist includes positive photoresist and negative photoresist.
- it is preferable to form a negative photoresist layer that is, the unexposed part of the negative photoresist is soluble in the developing solution, the exposed part is cured, and is insoluble in the developing solution.
- the pattern and mask remaining on the negative photoresist layer after development are The template shading pattern is opposite. A photoresist pattern is formed, so that the pattern of the subsequent wiring metal layer can be facilitated.
- Step S14 the seed layer is electroplated to form a wiring metal layer; in this embodiment, the wiring metal layer is electroplated by a telephone electroplating method, and the electroplating metal is copper.
- electroplating is used to form the rewiring layer circuit, that is, the rewiring layer.
- the specific process is: applying power between the electrical connection layer and the substrate, and the electrical The connecting layer serves as the anode and the substrate serves as the cathode. After voltage is applied, the copper in the electrical connection layer as the anode reacts and converts into copper ions and electrons. At the same time, the substrate as the cathode also reacts. The copper ions on the surface of the electrical connection layer near the substrate Combined with electrons to form copper plated on the surface of the electrical connection layer, finally, the electroplating of the wiring layer is completed.
- Step S15 the photoresist is removed to form a redistribution layer, where the redistribution layer is the antenna structure 40; in this embodiment, the photoresist can be removed by etching technology, specifically a wet etching method is used, and the to-be-etched Partial contact with the chemical solution achieves the effect of dissolving corrosion, forming the effect of concave-convex or hollowing out, thereby forming the wiring layer.
- Step S16 depositing and forming the first insulating layer 12 covering the rewiring layer by a deposition process; in this embodiment, the first insulating layer 12 is formed by a deposition process, so that the packaging structure can be fabricated after the first insulating layer 12.
- the deposition process is simple, with less consumables, uniform film texture, and strong bonding force with the substrate, which can provide good support for subsequent process steps.
- step S17 an etching process or a laser drilling process is used to form a through hole exposing the redistribution layer in the first insulating layer 12, and the through hole exposes a part of the redistribution layer. Both the etching process and the laser drilling process can better form the through hole, which facilitates the subsequent connection of the signal line 50 to the antenna structure 40 and facilitates the power-on of the antenna structure 40.
- RDL redistribution layer can have a grounding effect when carrying high currents, and the side carrying low currents can also play a grounding function at the same time, which improves the protection against noise interference and improves the performance of the device, so as to install electrons on the redistribution layer
- components or other functional devices wireless signal transceiving devices
- the normal operation of these devices is ensured to ensure the performance of the chip module 100.
- the first insulating layer 12 is provided with a cylindrical shielding body 21 having an installation space 211, wherein the installation space 211 has an opening 2111.
- Step S21 forming a top shielding layer 212 on the surface of the first insulating layer 12 away from the antenna structure 40, wherein the outer contour of the top shielding layer 212 does not coincide with the outer contour of the redistribution layer projected on the back of the first insulating layer 12;
- processes such as exposure and etching may be performed on the first insulating layer 12, so that the first insulating layer 12 forms a accommodating sink for accommodating the top shielding layer 212, and then a metal material is used as the manufacturing material on the sink.
- the deposition process or the sputtering process allows the top shielding layer 212 to be better deposited in the sink or the top shielding layer 212 is deposited by pulsed laser deposition.
- the target material can be used to pass argon gas into the metal.
- the top shielding layer 212 is formed by sputtering. Or, on the side of the flat first insulating layer 12, the metal layer is etched after depositing the metal layer, and a suitable top shielding layer 212 can also be formed. While this step S21 is being performed, the first signal connection section 51 may also be set, and the step of setting the first signal connection section 51 is similar to the setting of the top shielding layer 212.
- Step S22 forming a side shielding layer 213 along the outer edge of the top shielding layer 212, so that the top shielding layer 212 and the side shielding layer 213 form a cylindrical shielding body 21 with an installation space 211, wherein the side shielding layer 213 is away from the top shielding layer One side of 212 is enclosed to form an opening 2111.
- the side shielding layer 213 can be made by an electroplating process or a ball planting process.
- the material of the electroplating metal can be the same as that of the top shielding layer 212, and copper is specifically used as the electroplating metal.
- the formed top shielding layer 212 and the first insulating layer 12 electroplating is used to form the side shielding layer 213, that is, the side shielding layer 213.
- the specific process is: applying power between the top shielding layer 212 and the substrate,
- the top shielding layer 212 serves as an anode and the substrate serves as a cathode.
- the copper in the top shielding layer 212 as the anode reacts and converts into copper ions and electrons.
- the substrate serving as the cathode also reacts.
- the top shielding layer 212 near the substrate
- the copper ions on the surface combine with electrons to form copper plated on the surface of the top shielding layer 212, and finally, the electroplating of the side shielding layer 213 is completed.
- the ball planting process specifically brush the conductive ball particles on the surface of the top shielding layer 212 (the conductive ball particles are the same as the material of the top shielding layer 212); and then set the ball planting net on the top shielding layer 212 Pour the conductive ball particles into the ball planting net and spread it flat; when the conductive ball particles stick to the surface of the top shielding layer 212 from the through hole 2211 of the ball planting net, remove the ball planting net; heat until the conductive ball particles melt , Form a side shielding layer 213.
- the side shielding layer 213 may be arranged around the edge of the top shielding layer 212, or a plurality of side shielding layers 213 may be arranged at intervals along the edge of the top shielding layer 212, or only connected to the top shielding layer 212 to form the installation space 211, As long as it can better shield electromagnetic interference.
- the completed cylindrical shielding main body 21 has a cylindrical structure with an opening 2111 at one end and a sealed end at the other end. This arrangement can greatly increase the shielding area and ensure the working stability of the chip 30.
- the back of the chip 30 is attached to the top shielding layer 212, and the pins of the chip 30 extend away from the top shielding layer 212, thereby facilitating electrical connection with external circuits and ensuring the chip 30 Stability of work.
- the step of disposing the chip 30 in the installation space 211 through the opening 2111 includes:
- step S23 the height of the chip 30 is reduced through the grinding process, so that the height of the chip 30 is smaller than the height of the installation space 211;
- the principle of grinding precision processing grinding is to grind away the surface of the workpiece with a grind tool and abrasive on the basis of finishing processing.
- An abrasive precision machining method for extremely thin metals. Grinding is divided into manual grinding and mechanical grinding. Grinding uses abrasive particles coated or press-embedded on a grind tool to finish processing (such as cutting) on the machined surface through the relative movement of the grind tool and the workpiece under a certain pressure.
- the workpiece can be cut from 0.01 to 0.1 ⁇ m; and the workpiece and the grind are in random contact, the high points are trimmed each other, the error is gradually reduced, and the accuracy is improved at the same time.
- a chip 30 with a thinner thickness can be obtained.
- the height of the chip 30 to be lower than the height of the installation space 211, on the one hand, facilitates the complete placement of the chip 30 in the installation space 211, and on the other hand, it can ensure that the shielding plate 22 is covered on the cylindrical shield in the subsequent processing steps.
- the main body 21 ensures the installation effect of the chip 30.
- the chip 30 is well fixed and the stability of the chip 30 is ensured.
- a first signal connection section 51 is formed on the surface of the first insulating layer 12 away from the antenna structure 40, and the first signal connection section 51 is electrically connected to the antenna structure 40; in this embodiment, the first signal connection section 51 is The conductive layer laid on the surface of the first insulating layer 12 can increase the contact area between the antenna structure 40 and the signal line 50 and improve the stability of the antenna structure 40.
- the first signal connection section 51 is a metal layer
- deposition and etching processes may be used to make the metal layer into a suitable shape.
- the first signal connection section 51 is a redistribution layer, the specific manufacturing method and effect have been described above, and will not be repeated here.
- a second signal connection section 52 is formed along the height direction on the surface of the first signal connection section 51; in this embodiment, the first signal connection section 51 is a conductive layer laid on the surface of the first insulating layer 12.
- the extension distance of the signal line 50 is increased, and the selection of the location of the antenna structure 40 is improved, thereby ensuring the rationality and stability of the chip module 100 configuration.
- the second signal connection section 52 when the second signal connection section 52 is a metal layer, it may be made by a deposition and etching process, an electroplating process, or a value ball process. It should be noted that the height direction is the stacking direction of each layer of the chip module 100.
- an encapsulation layer 11 covering the first signal connection section 51, the second signal connection section 52, the chip 30 and the cylindrical shield body 21 is provided on the side of the first insulating layer 12 away from the antenna structure 40.
- the encapsulation layer 11 is mainly made of materials with insulating function, and its setting method can be deposited by coating machine coating or deposition process, and the entire structure is plastic-encapsulated to ensure that the entire structure can be completely plastic-encapsulated.
- the encapsulation layer 11 The thickness is controlled according to certain requirements.
- This solution uses a wafer-level plastic packaging solution to further ensure that the packaging layer 11 better covers the first signal connection section 51, the second signal connection section 52, the chip 30 and the cylindrical shield body 21. .
- the pins of the chip 30, the upper end of the cylindrical shielding body 21, and the signal line 50 of the antenna structure 40 are exposed on the encapsulation layer 11
- the steps include:
- Step S34 using a thinning process to reduce the thickness of the encapsulation layer 11; in this embodiment, the surface of the encapsulation layer 11 away from the first insulating layer 12 may be polished by a polishing process, thereby reducing the thickness of the encapsulation layer 11, or The laser thinning and grinding method is adopted to reduce the thickness of the packaging layer 11.
- Step S35 detecting the thinned and exposed surface of the encapsulation layer 11; it is understandable that when the thickness of the encapsulation layer 11 is reduced, the material of the encapsulation layer 11 inside will be exposed, and the surface of the encapsulation layer 11 material is The exposed surface is thinned.
- the packaging layer 11 is thinned to a certain extent, the pins of the chip 30 originally packaged in the packaging layer 11 and the ends of the shielding layer 213 on the side of the cylindrical mounting space 211 are exposed on the packaging layer 11, which is thinned and exposed. s surface.
- the surface of the encapsulation layer 11 can be detected by an image sensor, or the surface of the encapsulation layer 11 can be detected by a metal detection device, so that the pins of the chip 30 and the end of the side shield layer 213 of the cylindrical shield body 21 can be exposed. Undergo verification.
- Step S36 when it is detected that the pins of the chip 30, the side cavity wall of the mounting space 211, and the upper end portion of the second signal connection section 52 of the signal line 50 away from the second signal connection section 52 are all exposed on the thinned and exposed surface, stop the reduction. thin.
- the image sensor is used, the displayed effect is judged by the acquired image.
- the detection result of the metal detection device is used for judgment, so as to control the thinning process well and ensure the follow-up The processing effect of the processing step.
- a third signal connection section 53 is laid on the surface of the encapsulation layer 11 to form a signal line 50 connecting the antenna structure 40, wherein one side of the third signal connection section 53 is connected to the second signal connection section 52 of the signal line 50.
- the third signal connection section 53 is a conductive layer laid on the surface of the encapsulation layer 11, and this arrangement can increase the contact area between the external circuit and the signal line 50, and improve the stability of the antenna structure 40.
- the third signal connection section 53 is a metal layer
- deposition and etching processes may be used to make the metal layer into a suitable shape.
- the third signal connection section 53 is a redistribution layer, the specific manufacturing method and effect have been described above, and will not be repeated here.
- the step of disposing the shielding plate 22 covering the opening 2111 to form the shielding structure 20 includes:
- a metal layer connecting the cylindrical shield body 21 and the pins of the chip 30 is formed on the packaging layer 11.
- a metal layer covering the surface of the packaging layer 11 can be formed by a deposition process. It should be noted that the metal The layer is electrically connected to the pins of the chip 30 and the end of the cylindrical shielding body 21, so that the shielding area of the shielding structure 20 is larger and the shielding effect is improved.
- step S50 the second insulating layer 131 covering the shielding structure 20 and the third signal connection section 53 is formed by a deposition process or a coating process; the second insulating layer 131 is provided to stabilize the connection effect of the chip module 100 with the external circuit, and avoid The connection is short-circuited, and it is convenient to support the chip module 100, which improves the stability of the chip module 100.
- Step S60 through an etching process or a laser drilling process, so that the second insulating layer 131 forms at least three exposure openings 1311 that expose the signal line 50, the main body portion 221 of the shielding plate 22, and the connecting portion 222 of the shielding plate 22; Both the etching process and the laser drilling process can better form the exposed opening 1311, thereby facilitating the subsequent processing steps.
- a solder ball 132 is formed on the exposure opening 1311, so that one of the solder balls 132 is electrically connected to the third signal connection section 53, and a solder ball 132 is electrically connected to the main body portion 221 of the shielding plate 22 , A solder ball 132 is electrically connected to the connecting portion 222 of the shielding plate 22.
- the solder ball 132 may be formed by a value ball process or an electroplating process or a deposition process, as long as the signal transmission can be better ensured.
- bumping bumping
- solder balls 132 By setting bumping (bumps, solder balls 132) to connect with conductive pads on the circuit board, the chip module 100 can be driven well when power is on.
- the solder balls 132 can be made of copper and tin materials to ensure the conductive effect. Alternatively, a metal material (such as gold) with better conductivity can be provided to improve the electrical signal transmission of the chip module 100.
- the present application also proposes an electronic device (not shown), the electronic device includes any one of the above-mentioned chip modules 100, or includes any one of the above-mentioned chip modules 100 manufactured by the method of manufacturing the chip module 100 Since this electronic device adopts all the technical solutions of all the above-mentioned embodiments, it has at least all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be repeated here.
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Abstract
一种芯片模组(100)及其制作方法和电子设备，所述芯片模组(100)包括：基板(10)；屏蔽结构(20)，所述屏蔽结构(20)设于所述基板(10)内，并形成有安装空间(211)；芯片(30)，所述芯片(30)容置于所述安装空间(211)内，并与外部电路连通；以及天线结构(40)，至少部分所述天线结构(40)显露于所述基板(10)，所述天线结构(40)与所述芯片(30)电性连接。
Description
优先权信息
本申请要求于2019年12月13日申请的、申请号为201911287020.0的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
本申请涉及无线通信技术领域，特别涉及一种芯片模组及其制作方法和电子设备。
无线通信技术的发展要求用于通信的芯片模组体积越来越小，功能越来越强大。传统方法将芯片级天线与射频收发机一起安装在电路板上，这样天线和电路板占据了一定的空间阻碍了芯片模组的小型化。并且，对于传统的天线结构，天线产生的电磁辐射是比较大的，很容易对周边器件的电器性能造成电磁干扰，特别是芯片的裸片结构。从而造成器件乃至系统的失效，影响产品的质量和研发项目的整个周期。因此，如何解决芯片与天线之间的隔离问题，需要设计人员进行重点考虑的问题。
以上仅用于辅助理解本申请的技术方案，并不代表承认为现有技术。
发明内容
本申请的主要目的是提供一种芯片模组及其制作方法和电子设备，旨在减小芯片模组的安装空间，并且降低天线对芯片的电磁干扰，提高芯片运行的稳定性。
为实现上述目的，本申请提供一种的芯片模组，所述芯片模组包括：
基板；
屏蔽结构，所述屏蔽结构设于所述基板内，并形成有安装空间；
芯片，所述芯片容置于所述安装空间内，并与外部电路连通；以及
天线结构，至少部分所述天线结构显露于所述基板，所述天线结构与所述芯片电性连接。
在本申请的一些实施例中，所述屏蔽结构包括筒状屏蔽主体和屏蔽板，所述筒状屏蔽主体具有安装空间，所述筒状屏蔽主体形成有连通所述安装空间的开口，所述屏蔽板盖合于所述开口，并与所述筒状屏蔽主体固定连接，所述屏蔽板还形成有通孔。
在本申请的一些实施例中，所述筒状屏蔽主体包括顶屏蔽层和与所述顶屏蔽层连接的侧屏蔽层，所述侧屏蔽层沿所述顶屏蔽层的外边缘设置，所述顶屏蔽层和所述侧屏蔽层共同围合形成安装空间，所述屏蔽板连接于所述侧屏蔽层背离所述顶屏蔽层的一侧。
在本申请的一些实施例中，所述侧屏蔽层的数量为多个，多个所述侧屏蔽层沿所述顶屏蔽层的外边缘间隔排布，所述顶屏蔽层和多个所述侧屏蔽层共同围合形成安装空间，所述屏蔽板连接于每一所述侧屏蔽层背离所述顶屏蔽层的一侧。
在本申请的一些实施例中，所述芯片包括第一引脚和第二引脚，所述屏蔽板的材质包括导电材料，所述屏蔽板包括主体部和连接部，所述主体部盖合于所述开口，并将所述筒状屏蔽主体和所述第一引脚电性连接；
所述通孔形成于所述主体部，所述连接部设置于所述通孔围合的区域内，并与所述第二引脚电性连接。
在本申请的一些实施例中，所述基板包括封装层，所述封装层包括内封装部和外封装部，所述内封装部设置于所述安装空间内，并抵接所述芯片和所述安装空间的腔壁，所述 外封装部环绕所述屏蔽结构设置。
在本申请的一些实施例中，所述基板还包括第一绝缘层，所述第一绝缘层设于所述封装层的表面，所述第一绝缘层还形成有贯穿孔；
所述天线结构为重布线层，所述重布线层设置于所述第一绝缘层内，至少部分所述重布线层穿设于所述贯穿孔。
在本申请的一些实施例中，所述芯片模组还包括信号线，所述信号线穿设于所述外封装部，所述信号线的一端电性连接于所述重布线层伸入所述贯穿孔的部分，另一端用于与所述芯片电性连接。
在本申请的一些实施例中，所述基板还包括支撑连接层，所述支撑连接层设于所述封装层背离所述第一绝缘层的表面，所述支撑连接层包括：
第二绝缘层，所述第二绝缘层覆盖于所述信号线和所述屏蔽结构的屏蔽板，所述第二绝缘层还包括至少三个显露口，至少三个所述显露口分别用于显露至少部分所述信号线、所述屏蔽板的主体部和所述屏蔽板的连接部；和
焊球，所述焊球的数量为至少三个，一所述焊球设置于一所述显露口内，一所述焊球与所述信号线电性连接，一所述焊球与所述屏蔽板的主体部电性连接，一所述焊球与所述屏蔽板的连接部电性连接。
本申请还提出一种芯片模组的制作方法，该芯片模组的制作方法包括以下步骤：
提供天线结构，该天线结构安置于载板，在所述天线结构覆盖第一绝缘层，并在第一绝缘层对应天线结构的部分形成贯穿孔，以使天线结构与信号线连接；
在第一绝缘层背离载板的一表面设置具有安装空间的筒状屏蔽主体，其中，该安装空间具有开口，将芯片通过开口设置于所述安装空间内；
设置封装芯片和筒状屏蔽主体的封装层，并将芯片的引脚、筒状屏蔽主体的上端和信号线显露于所述封装层；
设置盖合于所述开口并与筒状屏蔽主体连接的屏蔽板，以形成屏蔽结构。
在本申请的一些实施例中，所述提供天线结构，该天线结构安置于载板，在所述天线结构覆盖第一绝缘层，并在第一绝缘层对应天线结构的部分形成贯穿孔，以使天线结构与信号线连接的步骤中，包括：
在线路层组设置支撑层；
在支撑层溅镀形成种子层；
设置覆盖种子层的光刻胶，采用光刻技术，对光刻胶进行曝光和显影，以形成光刻胶层图形；
电镀种子层以形成布线金属层；
去除光刻胶，形成重布线层，其中，该重布线层为天线结构；
通过沉积工艺沉积形成覆盖重布线层第一绝缘层；
通过刻蚀工艺或激光打孔工艺，以使第一绝缘层形成显露重布线层的贯穿孔，所述贯穿孔显露部分重布线层。
在本申请的一些实施例中，所述在第一绝缘层设置具有安装空间的筒状屏蔽主体，其中，该安装空间具有开口的步骤包括：
在第一绝缘层背离天线结构的表面形成顶屏蔽层，其中，该顶屏蔽层的外轮廓与重布线层投影于第一绝缘层背面的外轮廓不重合；
沿顶屏蔽层的外边缘形成侧屏蔽层，以使顶屏蔽层和侧屏蔽层形成具有安装空间的筒状屏蔽主体，其中，侧屏蔽层背离顶屏蔽层的一侧围合形成开口。
在本申请的一些实施例中，所述将芯片通过开口设置于所述安装空间内的步骤包括：
通过研磨工艺减小芯片的高度，以使芯片的高度小于安装空间的高度；
将研磨后的芯片贴合设置在安装空间的内壁面。
在本申请的一些实施例中，所述设置封装芯片和筒状屏蔽主体的封装层的步骤包括：
在第一绝缘层背离天线结构的表面形成第一信号连接段，该第一信号连接段电性连接于天线结构；
在第一信号连接段的表面沿高度方向形成第二信号连接段；
在第一绝缘层背离所述天线结构的一侧设置覆盖第一信号连接段、第二信号连接段、芯片和筒状屏蔽主体的封装层。
在本申请的一些实施例中，所述将芯片的引脚、筒状屏蔽主体的上端和天线结构的信号线显露于所述封装层的步骤包括：
采用减薄工艺减薄所述封装层的厚度；
检测封装层的被减薄而显露的表面；
当检测到芯片的引脚、安装空间的侧腔壁和信号线的第二信号连接段背离的上端部均显露于所述被减薄而显露的表面时，停止减薄。
在本申请的一些实施例中，所述当检测到芯片的引脚、安装空间的侧腔壁和信号线的第二信号连接段的上端部均显露于所述被减薄而显露的表面时，停止减薄的步骤之后还包括：
在封装层表面铺设第三信号连接段，形成连接天线结构的信号线，其中，该第三信号连接段的一侧连接于信号线的第二信号连接段。
在本申请的一些实施例中，所述设置盖合于所述开口的屏蔽板，形成屏蔽结构的步骤包括：
在封装层形成连接筒状屏蔽主体和芯片引脚的金属层；
对金属层进行刻蚀，形成连接筒状屏蔽主体和芯片第一引脚的主体部，以及形成连接芯片第二引脚的连接部，形成屏蔽板，以形成屏蔽结构。
在本申请的一些实施例中，所述对金属层进行刻蚀，形成连接筒状屏蔽主体和芯片的第一引脚的主体部，以及形成连接芯片的第二引脚的连接部，形成屏蔽板，以形成屏蔽结构的步骤之后包括：
通过沉积工艺或涂布工艺形成覆盖屏蔽结构和第三信号连接段的第二绝缘层；
通过刻蚀工艺或激光打孔工艺，以使第二绝缘层形成显露信号线、屏蔽板的主体部和屏蔽板的连接部的至少三个显露口；
在显露口形成焊球，以使一所述焊球与所述第三信号连接段电性连接，一所述焊球与屏蔽板的主体部电性连接，一所述焊球与所述屏蔽板的连接部电性连接。
本申请还包提出一种电子设备，包括芯片模组，所述芯片模组包括基板；
屏蔽结构，所述屏蔽结构设于所述基板内，并形成有安装空间；
芯片，所述芯片容置于所述安装空间内，并与外部电路连通；以及
天线结构，至少部分所述天线结构显露于所述基板，所述天线结构与所述芯片电性连接。
或者，包括芯片模组的制作方法制作的芯片模组，该芯片模组的制作方法包括以下步骤：
提供天线结构，该天线结构安置于载板，在所述天线结构覆盖第一绝缘层，并在第一绝缘层对应天线结构的部分形成贯穿孔，以使天线结构与信号线连接；
在第一绝缘层背离载板的一表面设置具有安装空间的筒状屏蔽主体，其中，该安装空间具有开口，将芯片通过开口设置于所述安装空间内；
设置封装芯片和筒状屏蔽主体的封装层，并将芯片的引脚、筒状屏蔽主体的上端和信号线显露于所述封装层；
设置盖合于所述开口并与筒状屏蔽主体连接的屏蔽板，以形成屏蔽结构。
本申请的技术方案通过在基板内设置屏蔽结构，并在屏蔽结构设置安装空间，再将芯 片放置在安装空间内，其中，芯片的引脚与外部电路连通，进一步通过基板固定天线结构，由于将芯片安置在屏蔽结构的安装空间内，在天线结构工作产生电磁辐射时，屏蔽结构可以对电磁辐射进行屏蔽，减少了天线对芯片的电磁干扰，提高了芯片运行的稳定性。并且由于将芯片、屏蔽结构和天线结构均封装在基板内，需要电路连接时，在基板内部设置线路层，以实现各部件的电性连接，从而节省了芯片模组的安装空间。如此，本申请的技术方案可以减小芯片模组的安装空间，并且降低天线对芯片的电磁干扰，提高芯片运行的稳定性。
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1为本申请芯片模组在载板设置第一绝缘层和天线结构一实施例的结构示意图；
图2为本申请芯片模组在载板设置第一绝缘层、天线结构、筒状屏蔽主体和芯片一实施例的结构示意图；
图3为本申请芯片模组在载板设置第一绝缘层、天线结构、筒状屏蔽主体、芯片和封装层一实施例的结构示意图；
图4为本申请芯片模组的封装层被减薄后一实施例的结构示意图；
图5为本申请芯片模组一实施例的结构示意图；
图6为图5A处的局部示意图；
图7为图5B处的局部示意图；
图8为本申请芯片模组去除载板后一实施例的结构示意图；
图9为本申请芯片模组的制作方法一实施例的流程步骤图；
图10为本申请芯片模组的制作方法一实施例的流程步骤图；
图11为本申请芯片模组的制作方法一实施例的流程步骤图；
图12为本申请芯片模组的制作方法一实施例的流程步骤图；
图13为本申请芯片模组的制作方法一实施例的流程步骤图；
图14为本申请芯片模组的制作方法一实施例的流程步骤图。
附图标号说明：
| 标号 | 名称 | 标号 | 名称 |
| 100 | 芯片模组 | 213 | 侧屏蔽层 |
| 10 | 基板 | 22 | 屏蔽板 |
| 11 | 封装层 | 221 | 主体部 |
| 111 | 内封装部 | 2211 | 通孔 |
| 112 | 外封装部 | 222 | 连接部 |
| 12 | 第一绝缘层 | 30 | 芯片 |
| 13 | 支撑连接层 | 31 | 第一引脚 |
| 131 | 第二绝缘层 | 32 | 第二引脚 |
| 1311 | 显露口 | 40 | 天线结构 |
| 132 | 焊球 | 50 | 信号线 |
| 20 | 屏蔽结构 | 51 | 第一信号连接段 |
| 21 | 筒状屏蔽主体 | 52 | 第二信号连接段 |
| 211 | 安装空间 | 53 | 第三信号连接段 |
| 2111 | 开口 | 60 | 胶合件 |
| 212 | 顶屏蔽层 | 70 | 载板 |
本申请目的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明，本申请实施例中所有方向性指示(诸如上、下、左、右、前、后……)仅用于解释在某一特定姿态(如附图所示)下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
另外，在本申请中涉及“第一”、“第二”等的描述仅用于描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
本申请提出一种芯片模组100，旨在减小芯片模组100的安装空间，并且降低天线对芯片30的电磁干扰，提高芯片30运行的稳定性。该芯片模组100可应用在电子设备之中，可以理解地，该电子设备可以是但并不限于手机、平板电脑、个人数字助理(Personal Digital Assistant，PDA)、电子书阅读器、MP3(动态影像专家压缩标准音频层面3，Moving Picture Experts Group Audio Layer III)播放器、MP4(动态影像专家压缩标准音频层面4，Moving Picture Experts Group Audio Layer IV)播放器、笔记本电脑、车载电脑、机顶盒、智能电视机、可穿戴设备、导航仪、掌上游戏机等。
下面将对本申请芯片模组100的具体结构进行介绍：
参照图1至图8，本申请芯片模组100一些实施例中，所述芯片模组100包括：
基板10；
屏蔽结构20，所述屏蔽结构20设于所述基板10内，并形成有安装空间211；
芯片30，所述芯片30容置于所述安装空间211内，并与外部电路连通；以及
天线结构40，至少部分所述天线结构40显露于所述基板10，所述天线结构40与所述芯片30电性连接。
可以理解的是，该屏蔽结构20的材质可以采用导电介质，从而便于为其他与之电性连接的部件供电。在一些实施例中，该屏蔽结构20可以通过半导体材料、金属材料、非金属导电材料或者前述几种材料的结合制作，只要使得屏蔽结构20具有良好的导电性进而便于实现屏蔽功能即可。在一实施例中，屏蔽结构20包括金属材料。电磁干扰主要以电磁波的方式传播造成干扰，电磁波在传播过程中，若遇到金属材料不仅不会穿过，而且会被迫改变方向沿着金属材料行进。若将金属材料包敷在所要屏蔽的设备或导线外面进行 屏蔽，并通过接地线与大地相连接，可能造成干扰的电磁波将通过接地线流向大地，被屏蔽的设备或导线中的信号就能够正常传送，从而避免了电磁干扰。该基板10的内部可以包括多层绝缘材料制作的分隔层，如此设置可以便于对芯片30、屏蔽结构20和天线结构40的封装，并且可以根据需要设置基板10的厚度，保证封装效果的稳定和芯片模组100体积的小型化。该基板10的外轮廓也可以根据实际需要进行设定，具体的，可以将基板10的外轮廓设置为多边形或者圆形，只要便于对芯片30、屏蔽结构20和天线结构40的封装即可。
在本申请的一实施例中，芯片30即为具有含硅半导体的结构，该含硅半导体为晶圆或者其他具有功能性的电子元器件，晶圆是指硅半导体集成电路制作所用的硅晶片，由于其形状为圆形，故称为晶圆；在硅晶片上可加工制作成各种电路元件结构，而成为有特定电性功能的集成电路产品。天线结构40可以为常规的天线阵列，只要便于进行无线通信即可。
本申请的技术方案通过在基板10内设置屏蔽结构20，并在屏蔽结构20设置安装空间211，再将芯片30放置在安装空间211内，其中，芯片30的引脚与外部电路连通，进一步通过基板10固定天线结构40，由于将芯片30安置在屏蔽结构20的安装空间211内，在天线结构40工作产生电磁辐射时，屏蔽结构20可以对电磁辐射进行屏蔽，减少了天线对芯片30的电磁干扰，提高了芯片30运行的稳定性。并且由于将芯片30、屏蔽结构20和天线结构40均封装在基板10内，需要电路连接时，在基板10内部设置线路层，以实现各部件的电性连接，从而节省了芯片模组100的安装空间。如此，本申请的技术方案可以减小芯片模组100的安装空间，并且降低天线对芯片30的电磁干扰，提高芯片30运行的稳定性。
参照图2，在本申请的一些实施例中，所述屏蔽结构20包括筒状屏蔽主体21和屏蔽板22，所述筒状屏蔽主体21具有安装空间211，所述安装空间211形成有开口2111，所述屏蔽板22盖合于所述开口2111，并与所述筒状屏蔽主体21固定连接，所述屏蔽板22还形成有通孔2211。通过设置筒状屏蔽主体21使得大部分的外部电磁干扰被筒状屏蔽主体21屏蔽，进而设置屏蔽板22，使得芯片30的各个方向均可以由屏蔽腔屏蔽电磁干扰，进一步提高屏蔽效果。可以理解的是，通过在屏蔽板22设置通孔2211，可以使芯片30的引脚在通孔2211处与外部电路连接，具体可以为芯片30引脚伸出通孔2211或者外部电路伸入通孔2211，只要便于保证芯片30正常工作即可。当然也可以在筒状屏蔽主体21设置通孔2211，只要便于芯片30与外部电路连接，保证芯片30正常工作即可。
并且，通过设置开口2111，便于芯片30安置于安装空间211内，在一实施例中，所述芯片模组100还包括胶合件60，所述胶合件60将芯片30的一表面和安装空间211的腔壁胶合固定，从而保证对芯片30的初步固定，便于后续的加工步骤。具体的，该胶合件60件可以为导电胶水，通过导电胶水将芯片30的背面与筒状屏蔽主体21固定，考虑到屏蔽结构20进行屏蔽时，电磁信号会在屏蔽结构20内传递，设置导电胶水防止屏蔽结构20的电阻变化，保证电磁信号的传递和屏蔽的效果。
参照图5至图8，在本申请的一些实施例中，所述筒状屏蔽主体21包括顶屏蔽层212和与所述顶屏蔽层212连接的侧屏蔽层213，所述侧屏蔽层213沿所述顶屏蔽层212的外边缘设置，所述顶屏蔽层212和所述侧屏蔽层213共同围合形成安装空间211，所述屏蔽板22连接于所述侧屏蔽层213背离所述顶屏蔽层212的一侧。该侧屏蔽层213可以为环绕顶屏蔽层212外边缘的结构，从而使得该筒状屏蔽主体21大致呈具有一端开口2111的、另一端密封的筒状结构，如此设置可以大大提高屏蔽的面积，保证芯片30的工作稳定性。或者，该侧屏蔽层213可以为连接顶屏蔽层212的结构，从而形成安装空间，以安装芯片30，并保证具有一定的屏蔽效果。该芯片30安置于安装空间211时，芯片30的背面贴合设置于顶屏蔽层212，芯片30的引脚朝向背离顶屏蔽层212的方向延伸，从而便于与外部 电路电性连接，保证芯片30工作的稳定性。
在本申请的一些实施例中，所述侧屏蔽层213的数量为多个，多个所述侧屏蔽层213沿所述顶屏蔽层212的外边缘间隔排布，所述顶屏蔽层212和多个所述侧屏蔽层213共同围合形成安装空间211，所述屏蔽板22连接于每一所述侧屏蔽层213背离所述顶屏蔽层212的一侧。本实施例中通过设置多个侧屏蔽层213对屏蔽板22的安置提供支撑，较大地提高筒状屏蔽主体21的屏蔽面积，较好地保证芯片30工作的稳定性。在一实施例中，芯片30的引脚也可以通过侧屏蔽层213与外部电路连接，提高了芯片30设置的适配性，提高芯片模组100的稳定性。
参照图4至图6，在本申请的一些实施例中，所述基板10包括封装层11，所述封装层11包括内封装部111和外封装部112，所述内封装部111设置于所述安装空间211内，并抵接所述芯片30和所述安装空间211的腔壁，所述外封装部112环绕所述屏蔽结构20设置。通过设置封装层11的内封装部111对芯片30和屏蔽结构20进行固定，保证芯片30工作的稳定性。具体的，可以在形成安装空间211，并且在安装空间211内贴合固定所述芯片30之后，在安装空间211注入内封装部111的制作材料，在注入的内封装部111的制作材料适中后并处理完成后，设置盖合内封装部111的屏蔽板22。以及，设置外封装部112可以对屏蔽结构20和天线结构40进行固定保证芯片30工作的稳定性。具体的，可以在完成封装结构的制作后，在封装结构的外侧(安装空间211外)涂布外封装部112的制作材料，从而对屏蔽结构20进行固定。所述封装层11的材质具体可以采用绝缘材料，只要便于制作封装层11即可。
参照图1至图3，在本申请的一些实施例中，所述基板10还包括第一绝缘层12，所述第一绝缘层12设于所述封装层11的表面，所述第一绝缘层12还形成有贯穿孔；
所述天线结构40为重布线层，所述重布线层设置于所述第一绝缘层12内，至少部分所述重布线层穿设于所述贯穿孔。通过设置第一绝缘层12可以对天线结构40进行良好固定，保证天线结构40正常工作，继而保证芯片模组100工作的稳定性。重布线层即为RDL层(Redistribution layer，再分布层、再分配层)，设置RDL层可以在承载高电流时兼具接地作用，而承载低电流的一侧亦同时发挥接地作用，提高对杂讯干扰的防护，改善器件的性能，一实施例中在重布线层上设置电子元器件或者其他功能装置(例如无线信号收发装置)，使得重布线层具有相应的功能，保证天线结构40正常工作，继而保证芯片模组100工作的稳定性。以及，设置贯穿孔便于重布线层与外部电路(或者芯片模组100)电性连接。
参照图4至图8，在本申请的一些实施例中，所述芯片模组100还包括信号线50，所述信号线50穿设于所述外封装部112，所述信号线50的一端电性连接于所述重布线层伸入所述贯穿孔的部分，另一端用于与所述芯片30电性连接。设置信号线50便于提高天线结构40设置位置选择情况，从而便于保证芯片模组100的正常工作。本实施例中，信号线50可以包括设置于封装层11和第一绝缘层12之间的第一信号连接段51，该第一信号连接段51的一侧连接天线结构40，信号线50还包括穿设于封装层11的第二信号连接段52，该第二信号连接段52连接于第一信号连接段51背离所述天线结构40的一侧，信号线50还包括第三信号连接段53，该第三信号连接段53设于封装层11背离第一信号连接段51的一侧，并与第二信号连接段52电性连接。通过设置多段信号连接段，提高了天线结构40信号的传输稳定性，并且提高天线结构40设置位置选择情况。在一实施例中，第一信号连接段51和第三信号连接段53还可以设置为重布线层，重布线层即为RDL层(Redistribution layer，再分布层、再分配层)，设置RDL层可以在承载高电流时兼具接地作用，而承载低电流的一侧亦同时发挥接地作用，提高对杂讯干扰的防护，改善器件的性能，提高天线结构40的性能。
参照图5至图8，在本申请的一些实施例中，所述基板10还包括支撑连接层13，所 述支撑连接层13设于所述封装层11背离所述第一绝缘层12的表面，所述支撑连接层13包括：
第二绝缘层131，所述第二绝缘层131覆盖于所述信号线50和所述屏蔽结构20的屏蔽板22，所述第二绝缘层131还包括至少三个显露口1311，至少三个所述显露口1311分别用于显露至少部分所述信号线50、所述屏蔽板22的主体部221和所述屏蔽板22的连接部222；和
焊球132，所述焊球132的数量为至少三个，一所述焊球132设置于一所述显露口1311内，一所述焊球132与所述信号线50电性连接，一所述焊球132与所述屏蔽板22的主体部221电性连接，一所述焊球132与所述屏蔽板22的连接部222电性连接。本实施例中，通过设置支撑连接层13使得芯片30与天线结构40更好的与外部电路电性连接。具体的，第二绝缘层131一方面用于使得芯片模组100的内部电路与外部电路进行电连接时相互隔离，避免短路，另一方面可以便于焊球132的形成，从而提高芯片模组100与外部电路的连接效果。通过设置Bumping(凸点，焊球132)，使得与电路板上的导电焊盘连接，从而在上电时可以良好的驱动芯片模组100。该焊球132可以与均采用铜、锡材料，从而保证导电效果。或者可以通过设置导电性能较好的金属材质(例如金)，从而提高芯片模组100的电信号传递。
在本申请的一些实施例中，所述焊球132的数量为至少三个，至少三个所述焊球132均匀排布于所述显露口1311内。通过设置多个焊球132，进一步提高芯片模组100与焊盘的接触效果，提高了芯片模组100与电路板连接时的焊接效果，保证芯片模组100工作的稳定性。
参照图9，本申请还提出一种芯片模组100的制作方法，该芯片模组100的制作方法包括以下步骤：
步骤S10，提供天线结构40，该天线结构40安置于载板70，在所述天线结构40覆盖第一绝缘层12，并在第一绝缘层12对应天线结构40的部分形成贯穿孔，以使天线结构40与信号线50连接；在本申请的一实施例中，该载板70形状可以根据实际产生情况确定，载板70的材质的材料可以包括例如玻璃材料、金属材料或塑料材料(如聚对苯二甲酸乙二醇醋(PET)、聚萘二甲酸乙二醇醋(PEN)、聚酰亚胺(PI))的各种材料中的一种或多种形成的基底，只要能为制作芯片模组100的各部件进行支撑，并且方便透光和/或传热即可。在将天线结构40安置于载板70前，在载板70设置离型膜，离型膜是一种热转印的辅助膜材，底材一般采用PET，常规厚度为12um-100um，在一实施例中，可以采用冷热撕离型膜，需要使用时将离型膜贴合于载板70的表面即可。在将芯片模组100制作完成后，对所述离型膜和所述芯片模组100相贴合的表面进行去除黏性的处理；通常芯片模组100与载板70之间加工后会相互黏，不易分开，通过在载板70和芯片模组100之间设置离型膜，可以在需要对加工完成的芯片模组100和载板70进行分离，离型膜通常具有轻微的粘性，在对其加热或者通过光线的照射(UV光或者特定波长的激光)会使得离型膜失去粘性，从而可以将芯片模组100、离型膜和载板70相互分离。需要说明的是，在形成芯片模组100的加工过程中，载板70、离型膜和芯片模组100在上下方向，从下至上依次堆叠设置，从而便于对芯片模组100的沉积和成型。在对离型膜和芯片模组100之间进行去除黏性的过程中，会将整个待加工件翻转180°，从而形成芯片模组100、离型膜和载板70在上下方向，从下至上依次堆叠设置，从而便于在去除黏性，可以理解的是，去除黏性后的离型膜的表面均不具有黏性了，如此可以将载板70通过运送装置运走，进而将防尘装置保留在产线继续运输。本实施例中，可以控制真空吸装置(具体可以为真空吸嘴，或者Die Bonder贴片机的吸嘴)对芯片模组100进行吸附，进而转运至合适的地方。
步骤S20，在第一绝缘层12背离载板70的一表面设置具有安装空间211的筒状屏蔽主体21，其中，该安装空间211具有开口2111，将芯片30通过开口2111设置于所述安装 空间211内；在一实施中采用光刻法制作第一绝缘层12，可以对涂布后的第一绝缘层12进行曝光，进而对第一绝缘层12进行蚀刻，从而形成安置筒状屏蔽主体21的安装槽，从而在安装槽沉积形成筒状屏蔽主体21。在一实施例中，采用沉积工艺和刻蚀工艺形成第一绝缘层12的安装槽，进而用于安装筒状屏蔽主体21，该筒状屏蔽主体21也可以是在外部制作完成的筒状屏蔽主体21，在需要时直接安装于安装槽内。
步骤S30，设置封装芯片30和筒状屏蔽主体21的封装层11，并将芯片30的引脚、筒状屏蔽主体21的上端和信号线50显露于所述封装层11；本实施例中，通过设置封装层11对芯片30和筒状屏蔽主体21进行固定，从而保证芯片模组100的结构稳定。具体的可以采用涂布机对封装层11的制作材料进行涂布，具体的本实施例中，可以在涂布机上设置用于对位的传感器，当用于对位的传感器检测到对位标记时，向控制系统反馈检测结果，从而控制系统能够得到基于检测结果的喷头相对芯片30的距离，从而便于对涂布机的喷头进行控制。在一实施例中，喷头可以包括多个喷嘴，从而便于提高涂布封装层11的效率。
步骤S40，设置盖合于所述开口2111并与筒状屏蔽主体21连接的屏蔽板22，以形成屏蔽结构20。可以理解的是，该屏蔽板22的材质与筒状屏蔽主体21的一致，从而保证电磁干扰屏蔽的一致性，在一实施例中，筒状屏蔽主体21和屏蔽板22的材质都采用金属，由于电磁干扰主要以电磁波的方式传播造成干扰，电磁波在传播过程中，若遇到金属材料不仅不会穿过，而且会被迫改变方向沿着金属材料行进。若将金属材料包敷在所要屏蔽的设备或导线外面进行屏蔽，并通过接地线与大地相连接，可能造成干扰的电磁波将通过接地线流向大地，被屏蔽的设备或导线中的信号就能够正常传送，从而避免了电磁干扰。
本申请的技术方案通过在芯片模组100内设置屏蔽结构20，并在屏蔽结构20设置安装空间211，再将芯片30放置在安装空间211内，其中，芯片30的引脚与外部电路连通，进一步固定天线结构40，由于将芯片30安置在屏蔽结构20的安装空间211内，在天线结构40工作产生电磁辐射时，屏蔽结构20可以对电磁辐射进行屏蔽，减少了天线对芯片30的电磁干扰，提高了芯片30运行的稳定性。并且由于将芯片30、屏蔽结构20和天线结构40均封装，需要电路连接时，在基板10内部设置线路层，以实现各部件的电性连接，从而节省了芯片模组100的安装空间。如此，本申请的技术方案可以减小芯片模组100的安装空间，并且降低天线对芯片30的电磁干扰，提高芯片30运行的稳定性。
参照图10，在本申请的一些实施例中，所述提供天线结构40，该天线结构40安置于载板70，在所述天线结构40覆盖第一绝缘层12，并在第一绝缘层12对应天线结构40的部分形成贯穿孔，以使天线结构40与信号线50连接的步骤中，包括：
步骤S11，在线路层组设置支撑层；设置第一绝缘层12为后续设置的电路提供支撑并且防止后续电路在制作时向线路层组扩散，保证芯片模组100的电连接稳定性。具体的，该支撑层的制作方法可以包括通过旋涂法在线路层组上涂覆PI层(polyimide，聚酰亚胺薄膜)，热固性聚酰亚胺具有优异的热稳定性、耐化学腐蚀性和机械性能，可以很好地为后续设置的电路提供支撑。再通过曝光和显影的方式使得PI层固化，从而形成具有绝缘功能的支撑层。
步骤S12，在支撑层溅镀形成种子层；该种子层即为电连接层，设置电连接层从而便于后续的电镀工艺，该电连接层的材质可以采用金属材质，具体的可以为铜，可以在靶材通入氩气进行溅射而形成电连接层，在一实施例中还可以采用脉冲激光沉积法沉积形成电连接层。一方面，在集成电路(Integrated Circuit，IC)行业中，传统的电镀层可以为铝，随着半导体芯片30工艺尺寸的减小，铝的高电阻缺点逐渐体现出来，使器件的导电性能变差；另一方面，若采用银作为电连接层，银的低电阻率优势可以使器件具有优异的导电性能，然而，缺陷在于成本过高。综上所述，在此采用铜作为电连接层，其优势在于，成本低于银、电阻率远远低于铝且略微高于银、导电性能良好。
步骤S13，设置覆盖种子层的光刻胶，采用光刻技术，对光刻胶进行曝光和显影，以 形成光刻胶层图形；采用光刻技术，对光刻胶进行曝光和显影，以形成光刻胶层图形；光刻胶是一种感光前后，在特定的显影液中的溶解度会发生很大变化的有机化合物。光刻胶包括正性光刻胶和负性光刻胶。在此优选的是形成负性光刻胶层，即负性光刻胶的未曝光部分溶于显影液，曝光部分固化，不溶于显影液，显影后负性光刻胶层保留的图案与掩模板遮光图案相反。形成光刻胶图形，从而可以便于后续布线金属层的图形。
步骤S14，电镀种子层以形成布线金属层；本实施例中，通过电话学电镀法进行电镀布线金属层，该电镀金属采用铜。根据形成的电连接层和修饰后的光刻胶图形，采用电化学电镀法电镀形成重布线层线路，也就是重布线层，具体过程是：将电源加在电连接层和基底之间，电连接层作为阳极，基底作为阴极，施加电压后，作为阳极的电连接层中的铜发生反应转化成铜离子和电子，同时作为阴极的基底也发生反应，基底附近的电连接层表面的铜离子与电子结合形成镀在电连接层表面的铜，最终，完成布线层的电镀。
步骤S15，去除光刻胶，形成重布线层，其中，该重布线层为天线结构40；本实施例中可以通过蚀刻技术去除光刻胶，具体的采用湿蚀刻法，在蚀刻时将待蚀刻部分接触化学溶液，达到溶解腐蚀的作用，形成凹凸或者镂空成型的效果，从而形成布线层。
步骤S16，通过沉积工艺沉积形成覆盖重布线层第一绝缘层12；本实施例中，通过沉积工艺形成第一绝缘层12，从而可以在第一绝缘层12后续进行封装结构的制作。沉积工艺的过程简单，耗材少，成膜质地均匀，并且与基体的结合力强，可以为后续的工艺步骤提供良好的支撑。
步骤S17，通过刻蚀工艺或激光打孔工艺，以使第一绝缘层12形成显露重布线层的贯穿孔，所述贯穿孔显露部分重布线层。通过刻蚀工艺和激光打孔工艺均可较好地形成贯穿孔，从而便于后续对天线结构40进行信号线50连接，便于为天线结构40进行上电。
设置RDL重布线层可以在承载高电流时兼具接地作用，而承载低电流的一侧亦同时发挥接地作用，提高对杂讯干扰的防护，改善器件的性能，从而在重布线层上设置电子元器件或者其他功能装置(无线信号收发装置)时，保证这些装置正常工作，保证芯片模组100性能。
参照图1、图2、图11，在本申请的一些实施例中，所述在第一绝缘层12设置具有安装空间211的筒状屏蔽主体21，其中，该安装空间211具有开口2111的步骤包括：
步骤S21，在第一绝缘层12背离天线结构40的表面形成顶屏蔽层212，其中，该顶屏蔽层212的外轮廓与重布线层投影于第一绝缘层12背面的外轮廓不重合；本实施例中，可以在第一绝缘层12进行曝光、刻蚀等工艺，以使第一绝缘层12形成容置顶屏蔽层212的容置沉台，进而在该沉台采用金属材料作为制作材料进行沉积工艺或者溅射(Sputter)工艺，使得沉台内较好地沉积形成顶屏蔽层212或者采用脉冲激光沉积法沉积形成顶屏蔽层212，具体而言，可以选用靶材通入氩气进行金属的溅射而形成顶屏蔽层212。或者在平整的第一绝缘层12一侧，沉积金属层后对金属层进行刻蚀，同样可以形成合适的顶屏蔽层212。在本步骤S21进行的同时，也可以对第一信号连接段51进行设置，设置第一信号连接段51的步骤与顶屏蔽层212的设置相近。
步骤S22，沿顶屏蔽层212的外边缘形成侧屏蔽层213，以使顶屏蔽层212和侧屏蔽层213形成具有安装空间211的筒状屏蔽主体21，其中，侧屏蔽层213背离顶屏蔽层212的一侧围合形成开口2111。本实施例中，可以通过电镀工艺或者植球工艺制作侧屏蔽层213，具体的，电镀金属的材质可以与顶屏蔽层212一致，具体采用铜作为电镀金属。根据形成的顶屏蔽层212和第一绝缘层12，采用电化学电镀法电镀形成侧屏蔽层213，也就是侧屏蔽层213，具体过程是：将电源加在顶屏蔽层212和基底之间，顶屏蔽层212作为阳极，基底作为阴极，施加电压后，作为阳极的顶屏蔽层212中的铜发生反应转化成铜离子和电子，同时作为阴极的基底也发生反应，基底附近的顶屏蔽层212表面的铜离子与电子结合形成镀在顶屏蔽层212表面的铜，最终，完成侧屏蔽层213的电镀。或者，通过植 球工艺，具体的在顶屏蔽层212的表面上刷匀助导电球颗粒(该导电球颗粒与顶屏蔽层212的材料一致)；再将植球网罩设在顶屏蔽层212的表面上；将导电球颗粒倒入植球网上并平铺；待导电球颗粒从植球网上的通孔2211粘到顶屏蔽层212的表面时，移除植球网；加热至导电球颗粒融化，形成侧屏蔽层213。该侧屏蔽层213可以为环绕顶屏蔽层212边缘设置的，或者是多个侧屏蔽层213沿顶屏蔽层212边缘间隔排布的，或者是仅连接于顶屏蔽层212形成安装空间211的，只要能较好地屏蔽电磁干扰即可。
设置完成的筒状屏蔽主体21大致呈具有一端开口2111的、另一端密封的筒状结构，如此设置可以大大提高屏蔽的面积，保证芯片30的工作稳定性。该芯片30安置于安装空间211时，芯片30的背面贴合设置于顶屏蔽层212，芯片30的引脚朝向背离顶屏蔽层212的方向延伸，从而便于与外部电路电性连接，保证芯片30工作的稳定性。
参照图1、图2、图11，在本申请的一些实施例中，所述将芯片30通过开口2111设置于所述安装空间211内的步骤包括：
步骤S23，通过研磨工艺减小芯片30的高度，以使芯片30的高度小于安装空间211的高度；研磨精密加工的原理：研磨是在精加工基础上用研具和磨料从工件表面磨去一层极薄金属的一种磨料精密加工方法。研磨分为手工研磨和机械研磨。研磨利用涂敷或压嵌在研具上的磨料颗粒，通过研具与工件在一定压力下的相对运动对加工表面进行的精整加工(如切削加工)。可对工件进行0.01～0.1μm切削；并且工件与研具随机接触，高点相互修整，误差逐步减小，精度同时得到提高。从而可以获得厚度较薄的芯片30。通过设置顶屏蔽层212和侧屏蔽层213之后，从而形成了可安置芯片30的安装空间211，该安装空间211的高度，即为侧屏蔽层213与顶屏蔽层212连接的一端，至侧屏蔽层213背离顶屏蔽层212的一端。将芯片30的高度设置为低于安装空间211的高度，一方面便于将芯片30完全安置于安装空间211内，另一方面可以保证在后续的加工步骤中将屏蔽板22盖合于筒状屏蔽主体21，保证芯片30的安装效果。
步骤S24，将研磨后的芯片30贴合设置在安装空间211的内壁面。在一实施例中，所述芯片模组100还包括胶合件60，所述胶合件60将芯片30的一表面和安装空间211的腔壁胶合固定，从而保证对芯片30的初步固定，便于后续的加工步骤。具体的，该胶合件60件可以为导电胶水，通过导电胶水将芯片30的背面与筒状屏蔽主体21固定，考虑到屏蔽结构20进行屏蔽时，电磁信号会在屏蔽结构20内传递，设置导电胶水防止屏蔽结构20的电阻变化，保证电磁信号的传递和屏蔽的效果。
通过将芯片30研磨后安装于安装空间211内，使得芯片30良好固定，保证了芯片30工作的稳定性。
参照图1至图4，以及图12，在本申请的一些实施例中，所述设置封装芯片30和筒状屏蔽主体21的封装层11的步骤包括：
步骤S31，在第一绝缘层12背离天线结构40的表面形成第一信号连接段51，该第一信号连接段51电性连接于天线结构40；本实施例中，第一信号连接段51为铺设于第一绝缘层12表面的导电层，如此设置可以增加天线结构40与信号线50的接触面积，提高天线结构40稳定性。在一实施例中，第一信号连接段51为金属层时，可以采用沉积和刻蚀工艺使得金属层形成合适的形状。在一实施例中，第一信号连接段51为重布线层时，具体的制作方式和效果前文已经描述，在此不做赘述。
步骤S32，在第一信号连接段51的表面沿高度方向形成第二信号连接段52；本实施例中，第一信号连接段51为铺设于第一绝缘层12表面的导电层，如此设置可以增加信号线50的延伸距离，提高天线结构40设置位置的选择，进而保证芯片模组100设置的合理性和稳定性。在一实施例中，第二信号连接段52为金属层时，可以采用沉积和刻蚀工艺或者电镀工艺或者值球工艺制作。需要说明的是，该高度方向即为芯片模组100各层的堆叠方向。
步骤S33，在第一绝缘层12背离所述天线结构40的一侧设置覆盖第一信号连接段51、第二信号连接段52、芯片30和筒状屏蔽主体21的封装层11。本实施例中，封装层11主要采用具有绝缘功能的材料制作，其设置方式可以采用涂布机涂布或者沉积工艺进行沉积，将整个结构进行塑封，确保整个结构可以完全塑封包围，封装层11的厚度按照一定要求进行控制，本方案采用晶圆级塑封方案，进一步保证封装层11较好地覆盖第一信号连接段51、第二信号连接段52、芯片30和筒状屏蔽主体21即可。
通过设置封装层11，保证芯片模组100结构的稳定性，从而保证其工作的稳定性。
参照图3、图4、图12，在本申请的一些实施例中，所述将芯片30的引脚、筒状屏蔽主体21的上端和天线结构40的信号线50显露于所述封装层11的步骤包括：
步骤S34，采用减薄工艺减薄所述封装层11的厚度；本实施例中，可以采用研磨工艺对封装层11背离第一绝缘层12的表面进行研磨，从而减少封装层11的厚度，或者采用激光减薄研磨的方式，减少封装层11的厚度。
步骤S35，检测封装层11的被减薄而显露的表面；可以理解的是，在封装层11的厚度降低时，会显露出其内部的封装层11材料，该封装层11材料的表面即为被减薄而显露的表面。在封装层11被减薄到一定程度时，原本封装于封装层11内的芯片30的引脚和筒状安装空间211侧屏蔽层213的端部均被显露于封装层11被减薄而显露的表面。具体的，可以通过图像传感器检测封装层11的表面，或者通过金属探测装置检测封装层11的表面，从而对芯片30的引脚和筒状屏蔽主体21的侧屏蔽层213的端部的显露状态进行确认。
步骤S36，当检测到芯片30的引脚、安装空间211的侧腔壁和信号线50的第二信号连接段52背离的上端部均显露于所述被减薄而显露的表面时，停止减薄。当采用图像传感器的方式时，通过获取到的图像对显露的效果进行判断，当通过金属探测装置时，以金属探测装置的检测结果进行判断，从而对减薄的进程进行良好的控制，保证后续加工步骤的加工效果。
参照图5至图8，在本申请的一些实施例中，所述当检测到芯片30的引脚、安装空间211的侧腔壁和信号线50的第二信号连接段52的上端部均显露于所述被减薄而显露的表面时，停止减薄的步骤之后还包括：
在封装层11表面铺设第三信号连接段53，形成连接天线结构40的信号线50，其中，该第三信号连接段53的一侧连接于信号线50的第二信号连接段52。本实施例中，第三信号连接段53为铺设于封装层11表面的导电层，如此设置可以增加外部电路与信号线50的接触面积，提高天线结构40稳定性。在一实施例中，第三信号连接段53为金属层时，可以采用沉积和刻蚀工艺使得金属层形成合适的形状。在一实施例中，第三信号连接段53为重布线层时，具体的制作方式和效果前文已经描述，在此不做赘述。
参照图5至图7，以及图13，在本申请的一些实施例中，所述设置盖合于所述开口2111的屏蔽板22，形成屏蔽结构20的步骤包括：
步骤S41，在封装层11形成连接筒状屏蔽主体21和芯片30引脚的金属层；本实施例中，可以通过沉积工艺形成覆盖在封装层11表面的金属层，需要说明的是，该金属层与芯片30的引脚和筒状屏蔽主体21的端部电性连接，从而使得屏蔽结构20的屏蔽面积更大，提高屏蔽效果。
步骤S42，对金属层进行刻蚀，形成连接筒状屏蔽主体21和芯片30第一引脚31的主体部221，以及形成连接芯片30第二引脚32的连接部222，形成屏蔽板22，以形成屏蔽结构20。本实施例中，通过刻蚀工艺将多余的金属刻蚀，从而使得屏蔽板22的形成两个相互不连接的部分，即主体部221和连接部222，使得芯片30具有良好的上电效果，保证芯片模组100正常工作。
参照图5至图7，以及图14，在本申请的一些实施例中，所述对金属层进行刻蚀，形成连接筒状屏蔽主体21和芯片30的第一引脚31的主体部221，以及形成连接芯片30的 第二引脚32的连接部222，形成屏蔽板22，以形成屏蔽结构20的步骤之后包括：
步骤S50，通过沉积工艺或涂布工艺形成覆盖屏蔽结构20和第三信号连接段53的第二绝缘层131；通过设置第二绝缘层131使得芯片模组100与外部电路连接的效果稳定，避免连接短路，并且便于对芯片模组100进行支撑，提高芯片模组100的稳定性。
步骤S60，通过刻蚀工艺或激光打孔工艺，以使第二绝缘层131形成显露信号线50、屏蔽板22的主体部221和屏蔽板22的连接部222的至少三个显露口1311；刻蚀工艺和激光打孔工艺均可较好的形成显露口1311，从而便于后续的加工步骤。
步骤S70，在显露口1311形成焊球132，以使一所述焊球132与所述第三信号连接段53电性连接，一所述焊球132与屏蔽板22的主体部221电性连接，一所述焊球132与所述屏蔽板22的连接部222电性连接。具体的，可以采用值球工艺或者电镀形成或者沉积工艺形成焊球132，只要能较好保证信号的传输即可。通过设置Bumping(凸点，焊球132)，使得与电路板上的导电焊盘连接，从而在上电时可以良好的驱动芯片模组100。该焊球132可以与均采用铜、锡材料，从而保证导电效果。或者可以通过设置导电性能较好的金属材质(例如金)，从而提高芯片模组100的电信号传递。
本申请还提出一种电子设备(未图示)，所述电子设备包括上述任一项所述的芯片模组100，或者包括上述任一项芯片模组100的制作方法制作的芯片模组100，由于本电子设备采用了上述所有实施例的全部技术方案，因此至少具有上述实施例的技术方案所带来的所有有益效果，在此不再一一赘述。
以上所述仅为本申请的优选实施例，并非因此限制本申请的专利范围，凡是在本申请的发明构思下，利用本申请说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本申请的专利保护范围内。
Claims (19)
- 一种芯片模组，其中，所述芯片模组包括：基板；屏蔽结构，所述屏蔽结构设于所述基板内，并形成有安装空间；芯片，所述芯片容置于所述安装空间内，并与外部电路连通；以及天线结构，至少部分所述天线结构显露于所述基板，所述天线结构与所述芯片电性连接。
- 如权利要求1所述的芯片模组，其中，所述屏蔽结构包括筒状屏蔽主体和屏蔽板，所述筒状屏蔽主体具有安装空间，所述筒状屏蔽主体形成有连通所述安装空间的开口，所述屏蔽板盖合于所述开口，并与所述筒状屏蔽主体固定连接，所述屏蔽板还形成有通孔。
- 如权利要求2所述的芯片模组，其中，所述筒状屏蔽主体包括顶屏蔽层和与所述顶屏蔽层连接的侧屏蔽层，所述顶屏蔽层和所述侧屏蔽层共同围合形成安装空间，所述屏蔽板连接于所述侧屏蔽层背离所述顶屏蔽层的一侧。
- 如权利要求3所述的芯片模组，其中，所述侧屏蔽层的数量为多个，多个所述侧屏蔽层沿所述顶屏蔽层的外边缘间隔排布，所述顶屏蔽层和多个所述侧屏蔽层共同围合形成安装空间，所述屏蔽板连接于每一所述侧屏蔽层背离所述顶屏蔽层的一侧。
- 如权利要求2至4中任一项所述的芯片模组，其中，所述芯片包括第一引脚和第二引脚，所述屏蔽板的材质包括导电材料，所述屏蔽板包括主体部和连接部，所述主体部盖合于所述开口，并将所述筒状屏蔽主体和所述第一引脚电性连接；所述通孔形成于所述主体部，所述连接部设置于所述通孔围合的区域内，并与所述第二引脚电性连接。
- 如权利要求5所述的芯片模组，其中，所述基板包括封装层，所述封装层包括内封装部和外封装部，所述内封装部设置于所述安装空间内，并抵接所述芯片和所述安装空间的腔壁，所述外封装部环绕所述屏蔽结构设置。
- 如权利要求6所述的芯片模组，其中，所述基板还包括第一绝缘层，所述第一绝缘层设于所述封装层的表面，所述第一绝缘层还形成有贯穿孔；所述天线结构为重布线层，所述重布线层设置于所述第一绝缘层内，至少部分所述重布线层穿设于所述贯穿孔。
- 如权利要求7所述的芯片模组，其中，所述芯片模组还包括信号线，所述信号线穿设于所述外封装部，所述信号线的一端电性连接于所述重布线层伸入所述贯穿孔的部分，另一端用于与所述芯片电性连接。
- 如权利要求8所述的芯片模组，其中，所述基板还包括支撑连接层，所述支撑连接层设于所述封装层背离所述第一绝缘层的表面，所述支撑连接层包括：第二绝缘层，所述第二绝缘层覆盖于所述信号线和所述屏蔽结构的屏蔽板，所述第二绝缘层还包括至少三个显露口，至少三个所述显露口分别用于显露至少部分所述信号线、所述屏蔽板的主体部和所述屏蔽板的连接部；和焊球，所述焊球的数量为至少三个，一所述焊球设置于一所述显露口内，一所述焊球与所述信号线电性连接，一所述焊球与所述屏蔽板的主体部电性连接，一所述焊球与所述屏蔽板的连接部电性连接。
- 一种芯片模组的制作方法，其中，包括以下步骤：提供天线结构，该天线结构安置于载板，在所述天线结构覆盖第一绝缘层，并在第一绝缘层对应天线结构的部分形成贯穿孔，以使天线结构与信号线连接；在第一绝缘层背离载板的一表面设置具有安装空间的筒状屏蔽主体，其中，该安装空间具有开口，将芯片通过开口设置于所述安装空间内；设置封装芯片和筒状屏蔽主体的封装层，并将芯片的引脚、筒状屏蔽主体的上端和信号线显露于所述封装层；设置盖合于所述开口并与筒状屏蔽主体连接的屏蔽板，以形成屏蔽结构。
- 如权利要求10所述的芯片模组的制作方法，其中，所述提供天线结构，该天线结构安置于载板，在所述天线结构覆盖第一绝缘层，并在第一绝缘层对应天线结构的部分形成贯穿孔，以使天线结构与信号线连接的步骤中，包括：在线路层组设置支撑层；在支撑层溅镀形成种子层；设置覆盖种子层的光刻胶，采用光刻技术，对光刻胶进行曝光和显影，以形成光刻胶层图形；电镀种子层以形成布线金属层；去除光刻胶，形成重布线层，其中，该重布线层为天线结构；通过沉积工艺沉积形成覆盖重布线层第一绝缘层；通过刻蚀工艺或激光打孔工艺，以使第一绝缘层形成显露重布线层的贯穿孔，所述贯穿孔显露部分重布线层。
- 如权利要求10所述的芯片模组的制作方法，其中，所述在第一绝缘层设置具有安装空间的筒状屏蔽主体，其中，该安装空间具有开口的步骤包括：在第一绝缘层背离天线结构的表面形成顶屏蔽层，其中，该顶屏蔽层的外轮廓与重布线层投影于第一绝缘层背面的外轮廓不重合；沿顶屏蔽层的外边缘形成侧屏蔽层，以使顶屏蔽层和侧屏蔽层形成具有安装空间的筒状屏蔽主体，其中，侧屏蔽层背离顶屏蔽层的一侧围合形成开口。
- 如权利要求10所述的芯片模组的制作方法，其中，所述将芯片通过开口设置于所述安装空间内的步骤包括：通过研磨工艺减小芯片的高度，以使芯片的高度小于安装空间的高度；将研磨后的芯片贴合设置在安装空间的内壁面。
- 如权利要求10所述的芯片模组的制作方法，其中，所述设置封装芯片和筒状屏蔽主体的封装层的步骤包括：在第一绝缘层背离天线结构的表面形成第一信号连接段，该第一信号连接段电性连接于天线结构；在第一信号连接段的表面沿高度方向形成第二信号连接段；在第一绝缘层背离所述天线结构的一侧设置覆盖第一信号连接段、第二信号连接段、芯片和筒状屏蔽主体的封装层。
- 如权利要求11所述的芯片模组的制作方法，其中，所述将芯片的引脚、筒状屏蔽主体的上端和天线结构的信号线显露于所述封装层的步骤包括：采用减薄工艺减薄所述封装层的厚度；检测封装层的被减薄而显露的表面；当检测到芯片的引脚、安装空间的侧腔壁和信号线的第二信号连接段背离的上端部均显露于所述被减薄而显露的表面时，停止减薄。
- 如权利要求15所述的芯片模组的制作方法，其中，所述当检测到芯片的引脚、安装空间的侧腔壁和信号线的第二信号连接段的上端部均显露于所述被减薄而显露的表面时，停止减薄的步骤之后还包括：在封装层表面铺设第三信号连接段，形成连接天线结构的信号线，其中，该第三信号连接段的一侧连接于信号线的第二信号连接段。
- 如权利要求16所述的芯片模组的制作方法，其中，所述设置盖合于所述开口的屏蔽板，形成屏蔽结构的步骤包括：在封装层形成连接筒状屏蔽主体和芯片引脚的金属层；对金属层进行刻蚀，形成连接筒状屏蔽主体和芯片第一引脚的主体部，以及形成连接芯片第二引脚的连接部，形成屏蔽板，以形成屏蔽结构。
- 如权利要求17所述的芯片模组的制作方法，其中，所述对金属层进行刻蚀，形成连接筒状屏蔽主体和芯片的第一引脚的主体部，以及形成连接芯片的第二引脚的连接部，形成屏蔽板，以形成屏蔽结构的步骤之后包括：通过沉积工艺或涂布工艺形成覆盖屏蔽结构和第三信号连接段的第二绝缘层；通过刻蚀工艺或激光打孔工艺，以使第二绝缘层形成显露信号线、屏蔽板的主体部和屏蔽板的连接部的至少三个显露口；在显露口形成焊球，以使一所述焊球与所述第三信号连接段电性连接，一所述焊球与屏蔽板的主体部电性连接，一所述焊球与所述屏蔽板的连接部电性连接。
- 一种电子设备，其中，包括如权利要求1至9中任一项所述的芯片模组；或者，包括如权利要求10至18中任一项所述的芯片模组的制作方法制作的芯片模组。
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