WO2021114251A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2021114251A1
WO2021114251A1 PCT/CN2019/125243 CN2019125243W WO2021114251A1 WO 2021114251 A1 WO2021114251 A1 WO 2021114251A1 CN 2019125243 W CN2019125243 W CN 2019125243W WO 2021114251 A1 WO2021114251 A1 WO 2021114251A1
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WIPO (PCT)
Prior art keywords
line
electrode
pixel drive
transistor
pixel
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Application number
PCT/CN2019/125243
Other languages
English (en)
French (fr)
Inventor
许晨
郝学光
乔勇
吴新银
Original Assignee
京东方科技集团股份有限公司
北京京东方技术开发有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 北京京东方技术开发有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2019/125243 priority Critical patent/WO2021114251A1/zh
Priority to CN201990000213.0U priority patent/CN212516502U/zh
Priority to JP2021571721A priority patent/JP7473568B2/ja
Priority to US17/255,502 priority patent/US11984070B2/en
Priority to EP19945456.2A priority patent/EP4075420A4/en
Publication of WO2021114251A1 publication Critical patent/WO2021114251A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present disclosure relates to the field of display technology, and more specifically, provides a display substrate and a display device.
  • OLED Organic light-emitting diode
  • the present disclosure provides a display substrate and a display device.
  • a display substrate including: a substrate and a display function layer disposed on the substrate, the display function layer including: a plurality of pixel driving circuits arranged along a first direction and a second direction that intersect , A plurality of power supply lines extending in the second direction, a plurality of compensation detection lines extending in the second direction, a plurality of gate lines extending in the first direction, and a plurality of gate lines extending in the second direction Data lines, a plurality of compensation scan lines extending along the first direction; the power line and the compensation detection line are alternately arranged at intervals, and any adjacent power line and one compensation detection line are between Two rows of pixel drive circuits extending along the second direction are provided; in any one of the plurality of pixel drive circuits, the power input of the pixel drive circuit is connected to the one closest to the pixel drive circuit.
  • the power line is electrically connected, and the compensation detection signal end of the pixel drive circuit is electrically connected to the compensation detection line closest to the pixel drive circuit
  • the power input end of the pixel drive circuit is directly connected to the power line closest to the pixel drive circuit, and the compensation detection signal end of the pixel drive circuit is connected to the distance from the pixel drive circuit through the compensation detection bridge line.
  • the nearest one of the compensation detection lines of the pixel drive circuit is connected; in any one of the pixel drive circuits in a row of the pixel drive circuits close to the compensation detection line, the power input of the pixel drive circuit passes through a power bridge line It is connected to the power line closest to the pixel drive circuit, and the compensation detection signal end of the pixel drive circuit is directly connected to the compensation detection line closest to the pixel drive circuit.
  • two data lines are arranged between the two rows of pixel driving circuits. In any one of the two rows of pixel drive circuits in the pixel drive circuit, the data signal input end of the pixel drive circuit is connected to the data line closest to the pixel drive circuit.
  • the display substrate further includes a light-shielding pattern, the light-shielding pattern is located between the base and the display function layer, the power bridge line, the compensation detection bridge line, and the light-shielding pattern The same layer is arranged; the power bridge line is connected with the corresponding power line and the corresponding power input terminal through a via; the compensation detection bridge line and the corresponding compensation detection line and the corresponding compensation detection signal terminal pass through the via connection.
  • any two adjacent power lines are electrically connected by a first conductive bridge line, and the first conductive bridge line extends along the first direction.
  • the display substrate further includes a plurality of light-emitting devices, the light-emitting devices are connected to the pixel driving circuit in a one-to-one correspondence, and the light-emitting devices include first electrodes sequentially stacked in a direction away from the substrate. , The light-emitting layer, the second electrode; the first conductive bridge line and the first electrode are arranged in the same layer
  • any two adjacent compensation detection lines are electrically connected by a second conductive bridge line, and the second conductive bridge line extends along the first direction.
  • the display substrate further includes a plurality of light-emitting devices, the light-emitting devices are connected to the pixel driving circuit in a one-to-one correspondence, and the light-emitting devices include first electrodes sequentially stacked in a direction away from the substrate. , A light-emitting layer, a second electrode; the second conductive bridge line and the first electrode are arranged in the same layer.
  • At least part of the ends of the power lines are connected to the same power bus.
  • the power bus and the gate line are provided in the same layer.
  • the pixel driving circuit includes a driving transistor, a switching transistor, a detection transistor, and a storage capacitor.
  • the gate of the switching transistor is connected to a corresponding gate line, and the first electrode of the switching transistor is connected to the corresponding data.
  • the signal input terminal is connected, the second electrode of the switching transistor is connected to the gate of the driving transistor and the first electrode of the storage capacitor, the first electrode of the driving transistor is connected to the corresponding power input terminal, and the driving The second electrode of the transistor is connected to the second electrode of the storage capacitor and the first electrode of the detection transistor, the gate of the detection transistor is connected to the corresponding compensation scan line, and the second electrode of the detection transistor is connected to the corresponding compensation scan line.
  • the compensation detection signal terminal is connected.
  • the driving transistor, the switching transistor, and the detection transistor are all top-gate transistors; the first electrode of the storage capacitor is connected to the driving transistor, the switching transistor, and the detection transistor.
  • the active layer of the storage capacitor is arranged in the same layer; the second electrode of the storage capacitor includes a first part and a second part, the first part is the light-shielding pattern, and the second part is in the same layer as the first electrode of the drive transistor Is provided and electrically connected to the first electrode of the driving transistor, and the first part is electrically connected to the second part.
  • the display substrate further includes a plurality of light-emitting devices, the light-emitting devices are connected to the pixel driving circuit in a one-to-one correspondence, and the light-emitting devices include first electrodes sequentially stacked in a direction away from the substrate.
  • a light-emitting layer, a second electrode; the second electrode of the storage capacitor further includes a third part, the third part is arranged in the same layer as the first electrode of the light-emitting device, and the third part is the same as the first part Electric connection.
  • a display device including the display substrate of the first aspect of the present disclosure.
  • FIG. 1 is a circuit diagram of a pixel driving circuit in a display substrate according to an embodiment of the disclosure
  • FIG. 2 is a layout diagram of a display substrate according to some embodiments of the present disclosure.
  • FIG. 3 is a layout diagram of a display substrate according to some other embodiments of the present disclosure.
  • FIG. 4 is a layout diagram of a display substrate according to some other embodiments of the present disclosure.
  • FIG. 5 is a layout diagram of a display substrate according to some other embodiments of the present disclosure.
  • FIG. 6 is a layout diagram of a pixel driving circuit of some embodiments of the disclosure.
  • Figure 7 is a cross-sectional view of the layout shown in Figure 6 along line AA;
  • the reference signs are: 100, substrate; DR1, first direction; DR2, second direction; 1, pixel drive circuit; VDD, power line; Sense, compensation detection line; Vdata, data line; GL, gate line; P1, power input terminal; P2, compensation detection signal terminal; P3, data signal input terminal; T1, drive transistor; T2, switch transistor; T3, detection transistor; C1, storage capacitor; C2, equivalent capacitance of light-emitting device; D1 Light-emitting device; BR1, power bridge line; BR2, compensation detection bridge line; BR3, first conductive bridge line; BR4, second conductive bridge line; VDDBUS, power bus; V1, first via; V2, second via Hole; V3, third via; V4, fourth via; V5, fifth via; V6, sixth via; V7, seventh via; V8, eighth via; V9, ninth via V10, the tenth via; T1g, the gate of the driving transistor; Cb1, the first part of the first pole of the storage capacitor; Cb2, the second part of the first pole of the storage capacitor;
  • the "same layer arrangement" of two structures means that they are formed by the same material layer, so they are in the same layer in the stacking relationship, but it does not mean that the distance between them and the substrate is equal, nor It means that they are exactly the same as the other layer structures between the substrates.
  • the "patterning process” refers to the step of forming a structure with a specific pattern, which can be a photolithography process.
  • the photolithography process includes forming a material layer, coating photoresist, exposing, developing, etching, and photolithography.
  • One or more of the steps such as resist stripping; of course, the “patterning process” can also be other processes such as imprinting process and inkjet printing process.
  • embodiments of the present disclosure provide a display substrate, including: a substrate 100 and a display function layer disposed on the substrate 100, the display function layer includes: along a first direction DR1 and a second direction DR2 that intersect A plurality of pixel driving circuits 1, a plurality of power supply lines VDD extending in the second direction DR2, a plurality of compensation detection lines Sense extending in the second direction DR2, a plurality of gate lines GL extending in the first direction DR1, Multiple data lines Vdata extending along the second direction DR2, multiple compensation scan lines (not shown) extending along the first direction DR1; the power line VDD and the compensation detection line Sense are alternately arranged at intervals, any adjacent power line Two rows of pixel driving circuits 1 extending in the second direction DR2 are arranged between VDD and a compensation detection line Sense; in any one of the plurality of pixel driving circuits 1, the power input terminal of the pixel driving circuit 1 P1 is electrically connected to the power line VDD closest to the substrate a
  • the display substrate is specifically, for example, an organic light emitting diode display substrate, or a quantum dot light emitting diode display substrate.
  • the pixel driving circuit 1 includes a driving transistor T1, a switching transistor T2, a detection transistor T3, and a storage capacitor C1.
  • the gate of the switching transistor T2 is connected to the corresponding gate line GL.
  • One pole is connected to the corresponding data signal input terminal P3, the second pole of the switching transistor T2 is connected to the gate of the driving transistor T1 and the first pole of the storage capacitor C1, and the first pole of the driving transistor T1 is connected to the corresponding power input terminal P1
  • the second pole of the drive transistor T1 is connected to the second pole of the storage capacitor C1 and the first pole of the detection transistor T3, the gate of the detection transistor T3 is connected to the corresponding compensation scan line, and the second pole of the detection transistor T3 is connected to the corresponding The compensation detection signal terminal P2 is connected.
  • the light-emitting device D1 is, for example, an organic light-emitting diode or a quantum dot light-emitting diode, and its equivalent capacitance is marked as a capacitor C2.
  • the pixel driving circuit 1 may further include more transistors, for example, a light emitting control transistor (not shown) is connected in series between the power input terminal P1 and the first pole of the driving transistor T1 to control the light emitting device. Whether D1 is lit.
  • a light emitting control transistor (not shown) is connected in series between the power input terminal P1 and the first pole of the driving transistor T1 to control the light emitting device. Whether D1 is lit.
  • the first direction DR1 is, for example, a row direction
  • the second direction DR2 is, for example, a column direction, which will be described below as an example.
  • each gate line GL is electrically connected to the gate of the switching transistor T2 in the pixel driving circuit 1 of a row
  • each data line Vdata is electrically connected to the first electrode of the switching transistor T2 in the pixel driving circuit 1 of a column.
  • the switching transistor T2 in the pixel drive circuit 1 of the row is turned on, so that each data line Vdata writes to the gate of the corresponding drive transistor T1 in the pixel circuit of the row
  • the data voltage is stored in the first pole of the storage capacitor C1.
  • each compensation scan line is electrically connected to the gate of the detection transistor T3 in a row of pixel drive circuit 1
  • each compensation detection line Sense is electrically connected to the compensation detection signal terminal P2 of a column of pixel drive circuit 1.
  • the compensation detection transistor T3 in the pixel driving circuit 1 of the row is turned on, so that each compensation detection line Sense can read the voltage of the second electrode of the storage capacitor C1 or the second electrode of the storage capacitor C1. The voltage of the two poles is compensated.
  • the second electrode voltage of the storage capacitor C1 is also the anode voltage of the light emitting diode.
  • a power supply line VDD extending in the column direction, a column of pixel driving circuits 1, two columns of data lines Vdata, a column of pixel driving circuits 1, and a column of compensation detection lines are sequentially arranged along the row direction.
  • Sense one column of pixel driving circuits 1, two columns of data lines Vdata, and one column of pixel driving circuits 1, are repeatedly set as a period.
  • One power line VDD supplies power to the four columns of pixel driving circuits 1 close to the power line VDD, which is also called a support four.
  • One compensation detection line Sense is electrically connected to the four-column pixel driving circuit 1 close to the compensation detection line Sense, which detects four adjacent pixel driving circuits 1 in the row direction at the same time, or detects the pixel driving circuits 1 adjacent in the row direction at the same time.
  • the four adjacent pixel driving circuits 1 perform compensation.
  • a data line Vdata provides data voltage signals for a column of pixel driving circuits 1 closest to the data line Vdata.
  • the power line VDD can be set relatively thick accordingly, and the voltage drop on it can be received even in the case of one to four. .
  • the compensation detection line Sense Since there is no data line Vdata or power line VDD on both sides of the compensation detection line Sense along the row direction, and the compensation detection line Sense itself does not require high equivalent resistance, the compensation detection line Sense is electrically connected to the four-column pixel driver. Circuit 1, the number of compensation detection lines Sense is reduced.
  • the power input terminal P1 of the pixel driving circuit 1 is directly connected to the power line VDD closest to the pixel driving circuit 1, and the compensation detection signal terminal P2 of the pixel driving circuit 1 passes through the compensation detection bridge line BR2 Connected to the compensation detection line Sense closest to the pixel drive circuit 1; at any one of the pixel drive circuits 1 in a row of pixel drive circuits 1 close to the compensation detection line Sense, the power input terminal P1 of the pixel drive circuit 1 passes the power supply
  • the bridge line BR1 is connected to the power line VDD closest to the pixel drive circuit 1, and the compensation detection signal terminal P2 of the pixel drive circuit 1 is directly connected to the compensation detection line Sense closest to the pixel drive circuit 1.
  • the power supply line VDD is directly connected to the power input terminal P1 of the pixel driving circuit 1 closest to the power supply line VDD, and is electrically connected to the next neighboring pixel driving circuit 1 through the power bridge line BR1; the compensation detection line Sense and the closest compensation
  • the compensation detection signal terminal P2 of the pixel driving circuit 1 of the detection line Sense is directly connected, and is electrically connected to the next neighboring pixel driving circuit 1 through the compensation detection bridge line BR2.
  • the compensation detection bridge line BR2 and the compensation detection line Sense belong to different layer structures
  • the power bridge line BR1 and the power supply line VDD belong to different layer structures.
  • two data lines are provided between the two rows of pixel driving circuits 1 Vdata;
  • the data signal input terminal P3 of the pixel driving circuit 1 is connected to the data line Vdata closest to the pixel driving circuit 1.
  • every two data lines Vdata are arranged between every two columns of pixel driving circuits 1. In this way, the size occupied by the data lines Vdata in the row direction can be further reduced.
  • the data line Vdata may also be arranged in a period of one column of pixel driving circuits 1 and one data line Vdata along the row direction.
  • each pixel in the display substrate further includes: a light-shielding pattern Cb1, the light-shielding pattern is located between the substrate 100 and the display functional layer, the power bridge line BR1, the compensation detection bridge line BR2, and the light-shielding pattern Cb1
  • the graphics are set on the same layer; the power bridge line BR1 is connected with the corresponding power line VDD and the corresponding power input terminal P1 through a via hole; the compensation detection bridge line BR2 is connected with the corresponding compensation detection line Sense and the corresponding compensation detection signal terminal P2 through a via hole .
  • the light-shielding pattern is used to shield the light from one side of the substrate 100 to prevent the active layer of each transistor on the light-shielding pattern from being degraded by light.
  • the light-shielding pattern, the power bridge line BR1, and the compensation detection bridge line BR2 can be formed in the same patterning process without increasing the number of masks required for manufacturing the display substrate.
  • any two adjacent power lines VDD are electrically connected by a first conductive bridge line BR3, and the first conductive bridge line BR3 extends along the first direction DR1.
  • the first conductive bridge line BR3 may be an independent layer structure, or may be provided on the same layer as other structures in the display substrate.
  • the display substrate further includes a plurality of light emitting devices D1, and the light emitting devices D1 are connected to the pixel driving circuit 1 in a one-to-one correspondence.
  • the light emitting device D1 includes a first electrode, a light emitting layer, and a first electrode that are sequentially stacked in a direction away from the substrate 100. Two electrodes; the first conductive bridge line BR3 and the first electrode are set in the same layer.
  • the light-emitting layer is, for example, an organic light-emitting layer or a quantum dot light-emitting layer.
  • a hole injection layer, a hole transport layer, an electron injection layer, an electron transport layer, etc. may also be provided on the light-emitting layer and the first electrode and the second electrode, which are not particularly limited in the present disclosure.
  • the first conductive bridge line BR3 can be simultaneously formed in the patterning process of forming the first electrode, thereby reducing the number of masks.
  • any two adjacent compensation detection lines Sense are electrically connected by a second conductive bridge line BR4, and the second conductive bridge line BR4 extends along the first direction DR1.
  • the second conductive bridge line BR4 may be an independent layer structure, or may be provided on the same layer as other structures in the display substrate.
  • the display substrate further includes a plurality of light emitting devices D1, and the light emitting devices D1 are connected to the pixel driving circuit 1 in a one-to-one correspondence.
  • the light emitting device D1 includes a first electrode, a light emitting layer, and a first electrode that are sequentially stacked in a direction away from the substrate 100. Two electrodes; the second conductive bridge line BR4 is set in the same layer as the first electrode.
  • the second conductive bridge line BR4 can be formed at the same time during the patterning process of forming the first electrode, thereby reducing the number of masks.
  • At least part of the ends of the power line VDD are connected to the same power bus VDDBUS, and two VDD lines may be electrically connected laterally, thereby reducing the resistance of the VDD line as a whole.
  • One or more power buses VDDBUS are provided in the display substrate of the present invention, and the driving chip driving the display substrate provides the same power supply voltages as possible for these power buses VDDBUS.
  • This setting can improve the consistency of the voltage on the power line VDD.
  • the power bus VDDBUS and the gate line GL are arranged in the same layer.
  • the same material layer is used to form the power bus VDDBUS at the same time, so as not to increase the number of masks.
  • the driving transistor T1, the switching transistor T2, and the detection transistor T3 are all top-gate transistors; the first electrode Ca of the storage capacitor C1 and the driving transistor T1, the switching transistor T2 and the detection transistor The active layer of T3 is arranged in the same layer; the second electrode of the storage capacitor C1 includes a first part Cb1 and a second part Cb2, the first part Cb1 is a light-shielding pattern, and the second part Cb2 is arranged in the same layer as the first electrode of the driving transistor T1 and is The first electrode of the driving transistor T1 is electrically connected, and the first part and the second part are electrically connected to have the same potential.
  • the top-gate transistor that is, its active layer, gate insulating layer, and gate are sequentially stacked in a direction away from the substrate 100.
  • the gate T2g of the switching transistor T2 is farther from the substrate 100 than the gate insulating layer T2a thereof.
  • the components of the storage capacitor C1 are a first part Cb1, a first pole Ca, and a second part Cb2 in order according to the direction away from the substrate 100.
  • a first equivalent capacitor is formed between the first portion Cb1 of the second pole and the first pole Ca
  • a second equivalent capacitor is formed between the second portion Cb2 of the second pole and the first pole Ca.
  • the capacitance value of the capacitor C1 is the sum of the first equivalent capacitance and the second equivalent capacitance, thereby increasing the capacitance value of the storage capacitor C1, which is beneficial to improving the stability of the light-emitting brightness of each light-emitting device D1.
  • the detailed connection relationship is as follows: the first pole of the switching transistor T2 is electrically connected to the corresponding data line Vdata through the first via V1; the second pole of the switching transistor T2 is electrically connected to the corresponding data line Vdata through the second via V2 and the third via V3.
  • the gate T1g of the driving transistor T1 is electrically connected, and is electrically connected to the first stage Ca of the corresponding storage capacitor C1 through the fourth via V4; one of the electrodes of the driving transistor T1 (the gate T1g is marked in FIG.
  • the fifth via hole V5 is electrically connected to the corresponding power line VDD
  • the other pole of the driving transistor T1 is electrically connected to the second portion Cb2 of the second pole of the corresponding storage capacitor C1 through the sixth via hole V6
  • the first part Cb1 and the second part Cb2 of the two poles are electrically connected through the seventh via V7
  • one pole of the detection transistor T3 is electrically connected to the corresponding compensation detection line Sense through the eighth via V8 and the ninth via V9
  • the detection transistor The other electrode of T3 is electrically connected to the second portion Cb2 of the second electrode of the corresponding storage capacitor C1 through the tenth via V10.
  • the display substrate further includes a plurality of light emitting devices D1, and the light emitting devices D1 are connected to the pixel driving circuit 1 in a one-to-one correspondence.
  • the light emitting device D1 includes a first electrode, a light emitting layer, and a first electrode that are sequentially stacked in a direction away from the substrate 100.
  • Two electrodes either shown; the second electrode of the storage capacitor C1 also includes a third part, the third part is arranged in the same layer as the first electrode of the light emitting device D1, and the third part is electrically connected to the first part.
  • the first electrode of the light emitting device D1 is farther away from the substrate than the second portion Cb2.
  • a third equivalent capacitance may also be formed between the third part of the second pole of the storage capacitor C1 and the first pole Ca, and the third equivalent capacitance is in a parallel relationship with the aforementioned first equivalent capacitance and second equivalent capacitance. , Can further improve the equivalent capacitance value of the storage capacitor C1.
  • the substrate 100 is, for example, an insulator substrate such as a glass substrate, a quartz substrate, or a sapphire substrate, or a semiconductor substrate such as a silicon substrate, a germanium substrate, a silicon carbide substrate, an indium phosphide substrate, etc.; of course, the substrate 100 may also be It is formed of flexible material or stretchable material, such as polyester, polyamide, polyimide, etc.
  • the active layer of each transistor for example, the material of the active layer T2b of the switching transistor T2 may be metal oxide, silicon (including strained silicon), germanium, silicon, silicon carbide, gallium arsenide, and arsenic. Aluminum gallium fluoride, indium phosphide, gallium nitride or organic semiconductors, etc.
  • the metal oxide may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten and indium and zinc, an oxide containing titanium and indium, and an oxide containing titanium and indium and tin. , Oxides containing indium and zinc, oxides containing silicon and indium and tin, oxides containing indium and gallium and zinc, etc.
  • the metal oxide may be an oxide semiconductor containing indium In, which can improve carrier mobility (electron mobility).
  • the oxide semiconductor preferably contains the element M.
  • the element M is preferably aluminum, gallium, yttrium, tin, or the like.
  • other elements that can be used as the element M there are boron, silicon, titanium, iron, nickel, germanium, yttrium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and the like.
  • the element M a plurality of the above-mentioned elements may be combined in some cases.
  • the element M is an element having a high bond energy with oxygen, for example.
  • the element M is an element whose bond energy with oxygen is higher than that of indium.
  • the element M is, for example, an element having a function of increasing the energy gap of an oxide semiconductor.
  • the metal oxide preferably contains zinc Zn, and crystallization is easy when the oxide semiconductor contains zinc.
  • the oxide semiconductor is not limited to an oxide semiconductor containing indium, and may also be an oxide semiconductor containing zinc, gallium, or tin that does not contain indium, such as zinc tin oxide or gallium tin oxide.
  • the metal oxide is In-M-Zn oxide
  • In-M-Zn oxide when the sum of In and M is 100 atomic%, it is preferable that In is less than 50 atomic%, and M is more than 50 atomic%.
  • the metal oxide an oxide with a large energy gap is used. For example, it is 2.5 eV or more and 4.2 eV or less, preferably 2.8 eV or more and 3.8 eV or less, and more preferably 3 eV or more and 3.5 eV or less.
  • the metal oxide is an oxide containing indium In, M, and zinc Zn, where M is aluminum Al, gallium Ga, or tin Sn.
  • the composition of the active layers of the three transistors in the pixel driving circuit may be the same or substantially the same to reduce the manufacturing cost.
  • This embodiment is not limited to this, and the compositions of the active layers of the three transistors may also be different from each other.
  • the active layers of the three transistors all have regions where the atomic percentage of In is greater than the atomic percentage of M, the field effect mobility of the switching transistor and the driving transistor can be improved.
  • one or both of the field-effect mobility of the switching transistor and the driving transistor may exceed 10 cm2/Vs, and preferably, exceed 30 cm2/Vs.
  • the display device when the above-mentioned transistor with high field-effect mobility is used in a gate driver for generating a gate signal of a display device, the display device may have a narrow bezel.
  • the above-mentioned transistor with high field-effect mobility is used in a source driver that supplies a signal from a signal line included in a display device, the number of wirings connected to the display device can be reduced.
  • the above-mentioned transistor with high field effect mobility is used for the transistor of the pixel circuit included in the display device, the display quality of the display device can be improved.
  • the metal oxide in this embodiment may be a single layer, or a double layer or multiple layers.
  • the metal oxide when it is a double layer, it includes a first oxide layer and a second oxide layer that are stacked.
  • the conductivity of the second oxide layer may be lower than that of the first oxide layer and the band gap may be larger than that of the first oxide layer.
  • the first oxide layer may be a main channel layer through which electrons move, and thus may be disposed close to the gate of each transistor.
  • indium gallium zinc oxide IGZO material is preferably used.
  • the channel direction and shape of different sub-pixels can be different.
  • the channel aspect ratio of the switching transistor is smaller than the channel aspect ratio of the driving transistor.
  • the metal oxide has different composition content to meet different electrical characteristics.
  • the aforementioned conductive treatment is to use these gates as a mask for plasma treatment after forming the pattern of the gates of each transistor to process the metal oxide in the corresponding area into a conductive layer.
  • the metal oxide can be divided into three regions. The first region includes the region overlapping with the gate of each transistor, which serves as the channel region of the transistor, and the second region includes the region adjacent to the first region, that is, the region adjacent to each transistor. The area adjacent to the gate but not covered by these gates serves as the source and drain area of the transistor, and the third area includes the plate area of the storage capacitor.
  • the composition of indium gallium zinc oxide IGZO in the three regions is different.
  • the oxygen content of the first region is within 30-50 atomic%
  • the oxygen content of the second region is within 50-60 atomic%
  • the oxygen content of the second region is within 60-70 atomic%.
  • the oxygen content of IGZO in the first region is less than the oxygen content of IGZO in the second region
  • the oxygen content of IGZO in the second region is less than the oxygen content of IGZO in the third region.
  • the zinc content of IGZO in the first region is greater than the oxygen content of IGZO in the second region, the zinc content of IGZO in the second region is greater than the zinc content of IGZO in the third region, and further, the oxygen and zinc in the first region
  • the element atomic ratio O/Zn is smaller than the second region O/Zn, and the O/Zn in the second region is smaller than the third region O/Zn.
  • the oxide in the first region is mainly semiconductor. The inventor found that increasing the content of In element can significantly increase the carrier concentration.
  • the content of In atoms in the first region is greater than The In atom content in the second region, and further the In atom content in the second region is greater than the In atom content in the third region.
  • the following table gives an example of the IGZO composition of indium gallium zinc oxide in the three regions.
  • Weight% represents the proportion of the element in the oxide
  • Atomic% represents the atomic percentage of the element in the oxide.
  • the first area is the channel area of at least one of the three transistors
  • the second area is the source and drain area of at least one of the three transistors
  • the third area is the plate area of the storage capacitor.
  • IGZO includes elements such as oxygen O, zinc Zn, gallium Ga, and indium In.
  • the first region is not plasma treated due to the shielding of the gate electrode.
  • the relative content of each element O:Zn:Ga:In by weight It is 11.82:25.68:28.38:34.12, and the relative atomic content is 40.24:21.40:22.18:16.18.
  • the weight relative content of each element O:Zn:Ga:In is 23.35:18.72:25.66:32.24, and the atomic relative content is 60.94:11.95:15.37:11.72.
  • the weight and atomic content of oxygen in the IGZO in the third region are greatly increased, and the weight and atomic content of zinc and Zn are reduced, which improves the conductivity of IGZO.
  • the second region is not blocked by the gate electrode, because this region is adjacent to the gate electrode and affected by the gate electrode, the weight and atomic content of oxygen in the IGZO in the second region is lower than that in the third region, and the weight and atomic content of zinc and Zn are higher than In the third region, the conductivity of IGZO in the second region is lower than that of IGZO in the third region.
  • the metal oxide layer in the third region serves as the first pole of the storage capacitor, it needs good electrical conductivity, that is, it needs a better degree of conductorization.
  • the gate electrode is used as a mask for plasma treatment, in theory, the further away from the gate electrode, the better the degree of conductorization and the better the conductivity. Therefore, in this embodiment, the minimum distance between the metal oxide layer (capacitor plate Ca) of the third region and the gate electrode T1g of the driving transistor is greater than L1, and the minimum distance between the capacitor plate Ca and the gate electrode T2g of the switching transistor is greater than L2.
  • the minimum distance between the capacitor plate Ca and the gate electrode T3g of the detection transistor is greater than L3, L1 is the width of the gate electrode T1g of the driving transistor, L2 is the width of the gate electrode T2g of the switching transistor, and L3 is the width of the gate electrode T3g of the detection transistor.
  • L1 is the width of the gate electrode T1g of the driving transistor
  • L2 is the width of the gate electrode T2g of the switching transistor
  • L3 is the width of the gate electrode T3g of the detection transistor.
  • the metal oxide layer (Ca) in the third region is The minimum distance between the gate electrode T1g of the driving transistor is greater than L1, the minimum distance between the capacitor plate Ca and the gate electrode T2g of the switching transistor is greater than L2, and the minimum distance between the capacitor plate Ca and the gate electrode T3g of the detection transistor is greater than L3,
  • L1g of the driving transistor is greater than L1
  • L2g of the switching transistor is greater than L2
  • L3g of the detection transistor is greater than L3
  • L1 is the width of the gate electrode T1g of the driving transistor
  • L2 is the width of the gate electrode T2g of the switching transistor
  • L3 is the width of the gate electrode T3g of the detection transistor.
  • the insulating structure such as the gate insulating layer of each transistor, for example, the material of the gate insulating layer T2a of the switching transistor T2 can be silicon oxide SiOx, silicon nitride SiNx, silicon oxynitride SiON, etc., or aluminum oxide.
  • the thickness of the first insulating layer is 3000-5000 angstroms
  • the thickness of the gate insulating layer is 1000-2000 angstroms
  • the thickness of the second insulating layer is 4500-7000 angstroms.
  • the power line VDD, the compensation detection line Sense, the data line Vdata, the gate line GL, the power bridge line BR1, the compensation detection bridge line BR2 and other circuit materials can use alloys or compounds, and can also use aluminum-containing conductors. , Conductors containing copper and titanium, conductors containing copper and manganese, conductors containing indium, tin and oxygen, conductors containing titanium and nitrogen, etc.
  • the materials of these circuits are, for example, chromium Cr, gold Au, zinc Zn, silver Ag, copper Cu, aluminum Al, molybdenum Mo, tantalum Ta, titanium Ti, tungsten W, manganese Mn, nickel Ni, iron Fe, cobalt Co, etc., or Alloys containing the above-mentioned metal elements as components or alloys containing a combination of the above-mentioned metal elements, such as aluminum neodymium alloy AlNd, molybdenum-niobium alloy MoNb, etc., may be multilayer metals, such as Mo/Cu/Mo.
  • a Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta or Ti) is used.
  • the thickness of the first metal layer is 800-1200 angstroms
  • the thickness of the gate metal layer is 3000-5000 angstroms
  • the thickness of the second metal layer is 3000-9000 angstroms.
  • the embodiment of the present disclosure also provides a display device including the aforementioned display substrate.
  • the display device is, for example, any product or component with a display function, such as an organic light emitting diode display panel, a quantum dot light emitting diode display panel, a mobile phone, a computer, and the like.
  • the organic light emitting diode in the organic light emitting diode display panel may include an anode electrode, a hole transport layer, an organic light emitting layer, an electron transport layer, and a cathode electrode.
  • the quantum dot light-emitting diode in the quantum dot light-emitting diode display panel may include an anode electrode, a quantum dot light-emitting layer, and a cathode electrode.

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Abstract

一种显示基板，其中，电源线（VDD）与补偿检测线（Sense）交替间隔设置，任意相邻的一条电源线（VDD）和一条补偿检测线（Sense）之间设置有沿第二方向（DR2）延伸的两排像素驱动电路（1）；在多个像素驱动电路（1）中的任意一个像素驱动电路（1）的电源输入端（P1）与距离该像素驱动电路（1）最近的一条电源线（VDD）电连接，该像素驱动电路（1）的补偿检测信号端（P2）与距离该像素驱动电路（1）最近的一条补偿检测线（Sense）电连接。还提供一种显示装置。

Description

显示基板和显示装置 技术领域
本公开涉及显示技术领域，更具体地，提供一种显示基板和一种显示装置。
背景技术
有机发光二极管(OLED)显示技术逐步成熟。需要进一步提高有机发光二极管显示装置的分辨率，这导致其中的显示基板内的线路越来越细，而其中电源线的线宽不能无线缩短，这阻碍了有机发光二极管显示装置的分辨率的提升。
发明内容
本公开提供一种显示基板和一种显示装置。
第一方面，提供一种显示基板，包括：基底和设置在所述基底上的显示功能层，所述显示功能层包括：沿相交的第一方向和第二方向排布的多个像素驱动电路、沿所述第二方向延伸的多条电源线、沿所述第二方向延伸的多条补偿检测线、沿所述第一方向延伸的多条栅线、沿所述第二方向延伸的多条数据线、沿所述第一方向延伸的多条补偿扫描线；所述电源线与所述补偿检测线交替间隔设置，任意相邻的一条所述电源线和一条所述补偿检测线之间设置有沿所述第二方向延伸的两排像素驱动电路；在所述多个像素驱动电路中的任意一个像素驱动电路，该像素驱动电路的电源输入端与距离该像素驱动电路最近的一条所述电源线电连接，该像素驱动电路的补偿检测信号端与距离该像素驱动电路最近的一条所述补偿检测线电连接。
在一些实施例中，在位于相邻的一条所述电源线和一条所述补偿检测线之间的两排所述像素驱动电路中，在靠近所述电源线的一排所述像素驱动电路中的任意一个所述像素驱动电路，该像素驱动电路的 电源输入端与距离该像素驱动电路最近的一条所述电源线直接连接，该像素驱动电路的补偿检测信号端通过补偿检测桥线与距离该像素驱动电路最近的一条所述补偿检测线连接；在靠近所述补偿检测线的一排所述像素驱动电路中的任意一个所述像素驱动电路，该像素驱动电路的电源输入端通过电源桥线与距离该像素驱动电路最近的一条所述电源线连接，该像素驱动电路的补偿检测信号端与距离该像素驱动电路最近的一条所述补偿检测线直接连接。
在一些实施例中，对于位于相邻的一条所述电源线和一条所述补偿检测线之间的两排所述像素驱动电路，该两排像素驱动电路之间设置有两条所述数据线；在该两排像素驱动电路中的任意一个所述像素驱动电路，该像素驱动电路的数据信号输入端与距离该像素驱动电路最近的一条所述数据线连接。
在一些实施例中，所述显示基板还包括：遮光图形，所述遮光图形位于所述基底和所述显示功能层之间，所述电源桥线、所述补偿检测桥线与所述遮光图形同层设置；所述电源桥线与对应的所述电源线和对应的所述电源输入端通过过孔连接；所述补偿检测桥线与对应的补偿检测线和对应补偿检测信号端通过过孔连接。
在一些实施例中，任意相邻的两条所述电源线通过第一导电桥线电连接，所述第一导电桥线沿所述第一方向延伸。
在一些实施例中，所述显示基板还包括多个发光器件，所述发光器件与所述像素驱动电路一一对应连接，所述发光器件包括沿远离所述基底方向依次叠置的第一电极、发光层、第二电极；所述第一导电桥线与所述第一电极同层设置
在一些实施例中，任意相邻的两条所述补偿检测线通过第二导电桥线电连接，所述第二导电桥线沿所述第一方向延伸。
在一些实施例中，所述显示基板还包括多个发光器件，所述发光器件与所述像素驱动电路一一对应连接，所述发光器件包括沿远离所述基底方向依次叠置的第一电极、发光层、第二电极；所述第二导电桥线与所述第一电极同层设置。
在一些实施例中，至少部分所述电源线的端部连接至同一电源总线。
在一些实施例中，所述电源总线与所述栅线同层设置。
在一些实施例中，所述像素驱动电路包括驱动晶体管、开关晶体管、检测晶体管和存储电容，所述开关晶体管的栅极与对应的栅线连接，所述开关晶体管的第一极与对应的数据信号输入端连接，所述开关晶体管第二极与所述驱动晶体管的栅极和所述存储电容的第一极连接，所述驱动晶体管的第一极与对应的电源输入端连接，所述驱动晶体管的第二极与所述存储电容的第二极、所述检测晶体管的第一极连接，所述检测晶体管的栅极与对应的补偿扫描线连接，所述检测晶体管的第二极与对应的补偿检测信号端连接。
在一些实施例中，所述驱动晶体管、所述开关晶体管、所述检测晶体管均为顶栅型晶体管；所述存储电容的第一极与所述驱动晶体管、所述开关晶体管、所述检测晶体管的有源层同层设置；所述存储电容的第二极包括第一部分和第二部分，所述第一部分为所述遮光图形，所述第二部分与所述驱动晶体管的第一极同层设置且与所述驱动晶体管的第一极电连接，所述第一部分与所述第二部分电连接。
在一些实施例中，所述显示基板还包括多个发光器件，所述发光器件与所述像素驱动电路一一对应连接，所述发光器件包括沿远离所述基底方向依次叠置的第一电极、发光层、第二电极；所述存储电容的第二极还包括第三部分，所述第三部分与所述发光器件的第一电极同层设置，所述第三部分与所述第一部分电连接。
第二方面，提供一种显示装置，包括本公开第一方面的显示基板。
附图说明
图1为本公开的实施例的显示基板中像素驱动电路的电路图；
图2为本公开的一些实施例的显示基板的版图；
图3为本公开的另外一些实施例的显示基板的版图；
图4为本公开的另外一些实施例的显示基板的版图；
图5为本公开的另外一些实施例的显示基板的版图；
图6为本公开的一些实施例的像素驱动电路的版图；
图7为图6所示版图沿AA线的剖视图；
其中，附图标记为：100、基底；DR1、第一方向；DR2、第二方向；1、像素驱动电路；VDD、电源线；Sense、补偿检测线；Vdata、数据线；GL、栅线；P1、电源输入端；P2、补偿检测信号端；P3、数据信号输入端；T1、驱动晶体管；T2、开关晶体管；T3、检测晶体管；C1、存储电容；C2、发光器件的等效电容；D1、发光器件；BR1、电源桥线；BR2、补偿检测桥线；BR3、第一导电桥线；BR4、第二导电桥线；VDDBUS、电源总线；V1、第一过孔；V2、第二过孔；V3、第三过孔；V4、第四过孔；V5、第五过孔；V6、第六过孔；V7、第七过孔；V8、第八过孔；V9、第九过孔；V10、第十过孔；T1g、驱动晶体管的栅极；Cb1、存储电容的第一极的第一部分；Cb2、存储电容的第一极的第二部分；Ca、存储电容的第二极；T2g、开关晶体管的栅极；T2a、开关晶体管的栅绝缘层；T2b、开关晶体管的有源层。
具体实施方式
为使本领域技术人员更好地理解本公开的技术方案，下面结合附图和具体实施方式对本公开作进一步详细描述。
在本公开中，两结构“同层设置”是指二者是由同一个材料层形成的，故它们在层叠关系上处于相同层中，但并不代表它们与基底间的距离相等，也不代表它们与基底间的其它层结构完全相同。
在本公开中，“构图工艺”是指形成具有特定的图形的结构的步骤，其可为光刻工艺，光刻工艺包括形成材料层、涂布光刻胶、曝光、显影、刻蚀、光刻胶剥离等步骤中的一步或多步；当然，“构图工艺”也可为压印工艺、喷墨打印工艺等其它工艺。
参见图1-图7，本公开的实施例提供一种显示基板，包括：基底100和设置在基底100上的显示功能层，显示功能层包括：沿相交的第一方 向DR1和第二方向DR2排布的多个像素驱动电路1、沿第二方向DR2延伸的多条电源线VDD、沿第二方向DR2延伸的多条补偿检测线Sense、沿第一方向DR1延伸的多条栅线GL、沿第二方向DR2延伸的多条数据线Vdata、沿第一方向DR1延伸的多条补偿扫描线(未示出)；电源线VDD与补偿检测线Sense交替间隔设置，任意相邻的一条电源线VDD和一条补偿检测线Sense之间设置有沿第二方向DR2延伸的两排像素驱动电路1；在多个像素驱动电路1中的任意一个像素驱动电路1，该像素驱动电路1的电源输入端P1与距离该像素驱动电路1最近的一条电源线VDD电连接，该像素驱动电路1的补偿检测信号端P2与距离该像素驱动电路1最近的一条补偿检测线Sense电连接。
该显示基板具体例如是有机发光二极管显示基板，也可以是量子点发光二极管显示基板。
参见图1，在一些实施例中，像素驱动电路1包括驱动晶体管T1、开关晶体管T2、检测晶体管T3和存储电容C1，开关晶体管T2的栅极与对应的栅线GL连接，开关晶体管T2的第一极与对应的数据信号输入端P3连接，开关晶体管T2第二极与驱动晶体管T1的栅极和存储电容C1的第一极连接，驱动晶体管T1的第一极与对应的电源输入端P1连接，驱动晶体管T1的第二极与存储电容C1的第二极、检测晶体管T3的第一极连接，检测晶体管T3的栅极与对应的补偿扫描线连接，检测晶体管T3的第二极与对应的补偿检测信号端P2连接。
参见图1，发光器件D1例如是有机发光二极管或者量子点发光二极管，其等效电容标记为电容C2。
在另外一些实施例中，像素驱动电路1还可以进一步包括更多的晶体管，例如在电源输入端P1与驱动晶体管T1第一极之间串联一发光控制晶体管(未示出)，以控制发光器件D1是否点亮。
第一方向DR1例如是行方向，第二方向DR2例如是列方向，以下均以此为例进行说明。
举例而言，每条栅线GL分别与一行像素驱动电路1中开关晶体管T2的栅极的电连接，每条数据线Vdata本别与一列像素驱动电路1中的开关晶体管T2的第一极电连接，以在栅线GL上被施加有效电压时，该 行像素驱动电路1中的开关晶体管T2导通，从而各数据线Vdata向该行像素电路中对应的的驱动晶体管T1的栅极写入数据电压，并存储在存储电容C1的第一极。
举例而言，每条补偿扫描线分别与一行像素驱动电路1中的检测晶体管T3的栅极电连接，每条补偿检测线Sense分别与一列像素驱动电路1中的补偿检测信号端P2电连接，以在补偿扫描线上被施加有效电压时，该行像素驱动电路1中的补偿检测晶体管T3导通，从而各补偿检测线Sense可以读取存储电容C1第二极的电压或者对存储电容C1第二极的电压进行补偿。
参加图1，存储电容C1的第二极电压也即是发光二极管的阳极电压。
参见图2，在本公开的实施例中，沿行方向依次设置有一条沿列方向延伸的电源线VDD、一列像素驱动电路1、两列数据线Vdata、一列像素驱动电路1、一列补偿检测线Sense、一列像素驱动电路1、两列数据线Vdata、一列像素驱动电路1、；并以此为周期重复设置。
一条电源线VDD为靠近该电源线VDD的四列像素驱动电路1供电，也称一托四。
一条补偿检测线Sense与靠近该补偿检测线Sense的四列像素驱动电路1电连接，其在同一时间对沿行方向相邻的四个像素驱动电路1进行检测，或者在同一时间对沿行方向相邻的四个像素驱动电路1进行补偿。
补偿检测线Sense如何对像素驱动电路1进行检测或补偿可依照现有技术进行设置。
一条数据线Vdata为最靠近该数据线Vdata的一列像素驱动电路1提供数据电压信号。
由于在电源线VDD沿行方向的两侧没有设置数据线Vdata或者补偿检测线Sense，电源线VDD相应地可以设置得比较粗，即使在一托四的情况下其上的电压降也是能够接收的。
由于在补偿检测线Sense沿行方向的两侧没有设置数据线Vdata或者电源线VDD，加之补偿检测线Sense本身对其等效电阻的要求并不高，进一步补偿检测线Sense电连接四列像素驱动电路1，补偿检测线Sense 的数量得到减少。
以上两方面的因素共同减少了电源线VDD和补偿检测线Sense占用的面积，有利于显示分辨率的提升。
在一些实施例中，参见图2，在位于相邻的一条电源线VDD和一条补偿检测线Sense之间的两排像素驱动电路1中，在靠近电源线VDD的一排像素驱动电路1中的任意一个像素驱动电路1，该像素驱动电路1的电源输入端P1与距离该像素驱动电路1最近的一条电源线VDD直接连接，该像素驱动电路1的补偿检测信号端P2通过补偿检测桥线BR2与距离该像素驱动电路1最近的一条补偿检测线Sense连接；在靠近补偿检测线Sense的一排像素驱动电路1中的任意一个像素驱动电路1，该像素驱动电路1的电源输入端P1通过电源桥线BR1与距离该像素驱动电路1最近的一条电源线VDD连接，该像素驱动电路1的补偿检测信号端P2与距离该像素驱动电路1最近的一条补偿检测线Sense直接连接。
换言之，电源线VDD与最靠近该电源线VDD的像素驱动电路1的电源输入端P1直接连接，与次近邻的像素驱动电路1通过电源桥线BR1电连接；补偿检测线Sense与最靠近该补偿检测线Sense的像素驱动电路1的补偿检测信号端P2直接连接，与次近邻的像素驱动电路1通过补偿检测桥线BR2电连接。
显然，补偿检测桥线BR2与补偿检测线Sense属于不同的层结构，电源桥线BR1与电源线VDD属于不同的层结构。
在一些实施例中，参见图2，对于位于相邻的一条电源线VDD和一条补偿检测线Sense之间的两排像素驱动电路1，该两排像素驱动电路1之间设置有两条数据线Vdata；在该两排像素驱动电路1中的任意一个像素驱动电路1，该像素驱动电路1的数据信号输入端P3与距离该像素驱动电路1最近的一条数据线Vdata连接。
即每两条数据线Vdata设置在每两列像素驱动电路1之间，如此，可以进一步减小数据线Vdata在行方向上占用的尺寸。
当然，在另外一些实施例中，数据线Vdata也可以是按照沿行方向一列像素驱动电路1、一条数据线Vdata为周期进行排布的。
在一些实施例中，参见图6和图7，显示基板中每个像素还包括： 遮光图形Cb1，遮光图形位于基底100和显示功能层之间，电源桥线BR1、补偿检测桥线BR2与遮光图形同层设置；电源桥线BR1与对应的电源线VDD和对应的电源输入端P1通过过孔连接；补偿检测桥线BR2与对应的补偿检测线Sense和对应补偿检测信号端P2通过过孔连接。
遮光图形用于遮挡来自于基底100一侧的光，避免遮光图形之上的各晶体管的有源层受光照而产生性质的退化。
如此，可在同一道构图工艺中形成遮光图形、电源桥线BR1、补偿检测桥线BR2，并不会增加制作该显示基板所需的掩模版的数量。
在一些实施例中，任意相邻的两条电源线VDD通过第一导电桥线BR3电连接，第一导电桥线BR3沿第一方向DR1延伸。
如此，可以降低电源线VDD的等效电阻。
第一导电桥线BR3可以是独立的一层结构，也可以是与显示基板中其他结构同层设置。
在一些实施例中，显示基板还包括多个发光器件D1，发光器件D1与像素驱动电路1一一对应连接，发光器件D1包括沿远离基底100方向依次叠置的第一电极、发光层、第二电极；第一导电桥线BR3与第一电极同层设置。
发光层例如是有机发光层或者是量子点发光层。在发光层与第一电极和第二电极还可以设置空穴注入层、空穴传输层、电子注入层、电子传输层等，本公开对此不做特别限定。
如此，可以在形成第一电极的构图工艺中同时形成第一导电桥线BR3，减少掩模版的数量。
在一些实施例中，参见图4，任意相邻的两条补偿检测线Sense通过第二导电桥线BR4电连接，第二导电桥线BR4沿第一方向DR1延伸。
如此，可降低补偿检测线Sense的等效电阻。
第二导电桥线BR4可以是独立的一层结构，也可以是与显示基板中其他结构同层设置。
在一些实施例中，显示基板还包括多个发光器件D1，发光器件D1与像素驱动电路1一一对应连接，发光器件D1包括沿远离基底100方向依次叠置的第一电极、发光层、第二电极；第二导电桥线BR4与第一电 极同层设置。
如此，可以在形成第一电极的构图工艺中同时形成第二导电桥线BR4，减少掩模版的数量。
在一些实施例中，参见图5，至少部分电源线VDD的端部连接至同一电源总线VDDBUS，可以横向电连接个VDD线，整体降低VDD线电阻。
本发明显示基板中会设置一个或多个电源总线VDDBUS，驱动该显示基板的驱动芯片为这些电源总线VDDBUS提供尽可能相同的电源电压。
如此设置，可以提高电源线VDD上电压的一致性。
在一些实施例中，电源总线VDDBUS与栅线GL同层设置。
即在形成栅线GL的构图工艺中，采用同一材料层同时形成电源总线VDDBUS，以不增加掩模版的数量。
在一些实施例中，参见图6和图7，驱动晶体管T1、开关晶体管T2、检测晶体管T3均为顶栅型晶体管；存储电容C1的第一极Ca与驱动晶体管T1、开关晶体管T2、检测晶体管T3的有源层同层设置；存储电容C1的第二极包括第一部分Cb1和第二部分Cb2，第一部分Cb1为遮光图形，第二部分Cb2与驱动晶体管T1的第一极同层设置且与驱动晶体管T1的第一极电连接，第一部分与第二部分电连接以具有相同的电位。
顶栅型晶体管即其有源层、栅绝缘层、栅极按照远离基底100的方向依次叠置。
参考图7，开关晶体管T2的栅极T2g较其栅绝缘层T2a更远离基底100。
存储电容C1的组成部分中，按照远离基底100的方向依次为第一部分Cb1、第一极Ca、第二部分Cb2。
在存储电容C1中，第二极的第一部分Cb1与第一极Ca之间形成第一等效电容，第二极的第二部分Cb2与第一极Ca之间形成第二等效电容，存储电容C1的电容值为第一等效电容与第二等效电容之和，从而增大了存储电容C1的电容值，有利于提高每一个发光器件D1发光亮度的稳定性。
详细的连接关系如下：开关晶体管T2的第一极通过第一过孔V1与对应的数据线Vdata电连接；开关晶体管T2的第二极通过第二过孔V2 和第三过孔V3与对应的驱动晶体管T1的栅极T1g电连接，且通过第四过孔V4与对应的存储电容C1的第一级Ca电连接；驱动晶体管T1(图6中标注了其栅极T1g)的其中一极通过第五过孔V5与对应的电源线VDD电连接，驱动晶体管T1的另一极通过第六过孔V6与对应的存储电容C1的第二极的第二部分Cb2电连接；存储电容C1的第二极的第一部分Cb1和第二部分Cb2通过第七过孔V7电连接；检测晶体管T3的一极通过第八过孔V8、第九过孔V9与对应的补偿检测线Sense电连接，检测晶体管T3的另一极通过第十过孔V10与对应的存储电容C1的第二电极的第二部分Cb2电连接。
在一些实施例中，显示基板还包括多个发光器件D1，发光器件D1与像素驱动电路1一一对应连接，发光器件D1包括沿远离基底100方向依次叠置的第一电极、发光层、第二电极(均未示出)；存储电容C1的第二极还包括第三部分，第三部分与发光器件D1的第一电极同层设置，第三部分与第一部分电连接。
发光器件D1的第一电极相较于第二部分Cb2更远离基底。
进一步，存储电容C1的第二极的第三部分与其第一极Ca之间还可以形成第三等效电容，第三等效电容与前述第一等效电容和第二等效电容是并联关系，可进一步提高存储电容C1的等效电容值。
在一些实施例中，基底100例如是玻璃基底、石英基底、蓝宝石基底等绝缘体基底，又例如也可以是硅基底、锗基底、碳化硅基底、磷化铟基底等半导体基底；当然基底100也可以是由柔性材料或者可伸缩材料形成，例如是聚酯、聚酰胺、聚酰亚胺等。
在一些实施例中，各晶体管的有源层，例如开关晶体管T2的有源层T2b的材料可以是金属氧化物、硅(包括应变硅)、锗、硅者、碳化硅、砷化镓、砷化铝镓、磷化铟、氮化镓或有机半导体等。
本实施例中，金属氧化物可以采用包含铟和锡的氧化物、包含钨和铟的氧化物、包含钨和铟和锌的氧化物、包含钛和铟的氧化物、包含钛和铟和锡的氧化物、包含铟和锌的氧化物、包含硅和铟和锡的氧化物、包含铟和镓和锌的氧化物等。
金属氧化物可以是包含铟In的氧化物半导体，可以提高载流子迁移 率(电子迁移率)。此外，氧化物半导体优选包含元素M。元素M优选是铝、镓、钇或锡等。作为可用作元素M的其他元素，有硼、硅、钛、铁、镍、锗、钇、锆、钼、镧、铈、钕、铪、钽、钨等。注意，作为元素M有时也可以组合多个上述元素。元素M例如是与氧的键能高的元素。元素M是与氧的键能高于铟的元素。或者，元素M例如是具有增大氧化物半导体的能隙的功能的元素。此外，金属氧化物优选包含锌Zn，当氧化物半导体包含锌时容易晶化。实际实施时，氧化物半导体不局限于包含铟的氧化物半导体，也可以是锌锡氧化物或镓锡氧化物等不包含铟且包含锌、镓或锡的氧化物半导体等。
在金属氧化物是In-M-Zn氧化物的情况下，在In和M的总和为100atomic％时，优选的是：In为低于50atomic％，M为高于50atomic％。金属氧化物使用能隙大的氧化物，例如是2.5eV以上且4.2eV以下，优选为2.8eV以上且3.8eV以下，更优选为3eV以上且3.5eV以下。优选地，金属氧化物是包含铟In、M及锌Zn的氧化物，其中M为铝Al、镓Ga或锡Sn。
本实施例中，像素驱动电路中的三个晶体管的有源层的组成可以相同或者大致相同，以降低制造成本。本实施例不局限于此，该三个晶体管的有源层的组成也可以彼此不同。当该三个晶体管的有源层都具有In的原子百分比大于M的原子百分比的区域时，可以提高开关晶体管和驱动晶体管的场效应迁移率。具体地说，开关晶体管和驱动晶体管的场效应迁移率中的一个或两个可以超过10cm2/Vs，优选的是，超过30cm2/Vs。例如，当将上述场效应迁移率高的晶体管用于显示装置的生成栅极信号的栅极驱动器时，该显示装置可以具有宽度窄的边框。当将上述场效应迁移率高的晶体管用于显示装置所包括的供应来自信号线的信号的源极驱动器时，可以减少与显示装置连接的布线数。当将上述场效应迁移率高的晶体管用于显示装置所包括的像素电路的晶体管时，可以提高显示装置的显示品质。
进一步地，本实施例的金属氧化物可以单层，也可以是双层或多层。当金属氧化物是双层时，包括叠设的第一氧化物层和第二氧化物层。第二氧化物层的导电性可比第一氧化物层低并且禁带宽度可比第一氧化物 层大。第一氧化物层可以是电子移动的主沟道层，因而可设置成靠近各晶体管的栅极。当金属氧化物是单层时，优选采用氧化铟镓锌IGZO材料。
本实施例中，由于金属氧化物一部分作为晶体管的有源层，另一部分作为存储电容的一极，因此在进行导体化处理时，一方面可以实现不同子像素的沟道方向和形状有所区别，以适应不同的宽长比设计，例如，通过设计开关晶体管的有源层和驱动晶体管的有源层的宽度，使开关晶体管的沟道宽长比小于驱动晶体管的沟道宽长比。另一方面可以在一个子像素内的不同区域，金属氧化物具有不同的成分含量，以适应不同的电特性需求。
前述所说的导体化处理，是在形成各晶体管的栅极的图案后，利用这些栅极作为掩膜进行等离子体处理，将相应区域的金属氧化物处理成导体化层。可以将金属氧化物划分为三个区域，第一区域包括与各晶体管的栅极重叠的区域，该区域作为晶体管的沟道区域，第二区域包括邻近第一区域的区域，即与各晶体管的栅极邻近但未被这些栅极覆盖的区域，该区域作为晶体管的源漏区域，第三区域包括储存电容的极板区域。本实施例中，三个区域中氧化铟镓锌IGZO的成分不同。本实施例中，所述第一区域氧含量范围在30-50atomaic％之内，所述第二区域氧含量范围在50-60atomaic％之内，所述第二区域氧含量范围在60-70atomaic％之内，优选的，第一区域中IGZO的氧含量小于第二区域中IGZO的氧含量，第二区域中IGZO的氧含量小于第三区域中IGZO的氧含量。第一区域中IGZO的锌含量大于第二区域中IGZO的氧含量，第二区域中IGZO的锌含量大于第三区域中IGZO的锌含量，更进一步的，所述第一区域中氧元素和锌元素原子比O/Zn小于第二区域O/Zn，所述第二区域中O/Zn小于第三区域O/Zn。此外第一区域氧化物主要为半导体特性，发明人发现，提升In元素含量能显著提升载流子浓度，为提升第一区域载流子浓度以提升晶体管的驱动能力，第一区域In原子含量大于第二区域In原子含量，进而第二区域In原子含量大于第三区域In原子含量。
下表给出了三个区域中氧化铟镓锌IGZO成分的一种示例，Weight％代表元素在氧化物中的所占比重，Atomic％代表该元素在氧化物中所占的原子百分比。
Figure PCTCN2019125243-appb-000001
其中，第一区域为三个晶体管中至少一个晶体管的沟道区域，第二区域为三个晶体管中的至少一个晶体管源漏区域，第三区域为存储电容的极板区域。如上表所示，IGZO中包括氧O、锌Zn、镓Ga和铟In等元素，第一区域由于栅电极的遮挡，未经等离子体处理，各元素O:Zn:Ga:In的重量相对含量为11.82：25.68：28.38：34.12，原子相对含量为40.24：21.40：22.18：16.18。第三区域由于未受遮挡，进行了等离子体处理，各元素O:Zn:Ga:In的重量相对含量为23.35：18.72：25.66：32.24，原子相对含量为60.94：11.95：15.37：11.72。通过等离子体处理后，第三区域的IGZO中氧的重量和原子含量大大增加，锌Zn的重量和原子含量减小，提高了IGZO的导电性。虽然第二区域未被栅电极遮挡，但由于该区域邻近栅电极，受栅电极影响，第二区域的IGZO中氧的重量和原子含量低于第三区域，锌Zn的重量和原子含量高于第三区域，因而第二区域的IGZO的导电性低于第三区域的IGZO。
由于第三区域的金属氧化物层作为存储电容的第一极，因而需要良好的导电特性，即需要较优导体化程度。在采用栅电极作为掩膜进行等离子体处理时，理论上离栅电极越远的区域，其导体化程度越好，导电特性越优。因此本实施例设置第三区域的金属氧化物层(电容极板Ca)与驱动晶体管栅电极T1g之间的最小距离大于L1，电容极板Ca与开关晶体管栅电极T2g之间的最小距离大于L2，电容极板Ca与检测晶体管栅电极T3g之间的最小距离大于L3，L1为驱动晶体管栅电极T1g的宽度，L2为开关晶体管栅电极T2g的宽度，L3为检测晶体管栅电极电极T3g的宽度。这样，第三区域的金属氧化物层的等离子体处理不会受到驱动晶体管栅电极T1g、开关 晶体管栅电极T2g和检测晶体管栅电极T3g的影响。需要说明的是，上述距离为在垂直于基板方向上二者的距离，此外，作为一种变形实施例，由于高分辨背板设计的需要，上述第三区域的金属氧化物层(Ca)与驱动晶体管栅电极T1g之间的最小距离大于L1，电容极板Ca与开关晶体管栅电极T2g之间的最小距离大于L2，以及电容极板Ca与检测晶体管栅电极T3g之间的最小距离大于L3，这三种设计可以满足其中的两种情况或者一种情况。更进一步的，可以设计成更优先考虑电容极板Ca与第一电极和第二电极三者交叠的图形满足上述关系。L1为驱动晶体管栅电极T1g的宽度，L2为开关晶体管栅电极T2g的宽度，L3为检测晶体管栅电极T3g的宽度。这样，第三区域的金属氧化物层的等离子体处理受到驱动晶体管栅电极T1g、开关晶体管栅电极T2g和检测晶体管栅电极T3g的影响较小，最大限度地提高第三区域的金属氧化物层的导体化程度。
在一些实施例中，各晶体管的栅绝缘层等绝缘结构，例如开关晶体管T2的栅绝缘层T2a的材料可以采用硅氧化物SiOx、硅氮化物SiNx、氮氧化硅SiON等，也可以采用氧化铝AlOx、氧化铪HfOx、氧化钽TaOx、氧化钇、氧化锆、氧化镓、氧化镁、氧化镧、氧化铈、氧化钕等。其中，第一绝缘层的厚度为3000～5000埃，栅绝缘层的厚度为1000～2000埃，第二绝缘层的厚度为4500～7000埃。
在一些实施例中，电源线VDD、补偿检测线Sense、数据线Vdata、栅线GL、电源桥线BR1、补偿检测桥线BR2等线路的材料可以使用合金或化合物，还可以使用含铝的导体、含铜及钛的导体、含铜及锰的导体、含铟、锡及氧的导体、含钛及氮的导体等。这些线路的材料例如是铬Cr、金Au、锌Zn、银Ag、铜Cu、铝Al、钼Mo、钽Ta、钛Ti、钨W、锰Mn、镍Ni、铁Fe、钴Co等，或包含上述金属元素作为成分的合金或者包含上述金属元素的组合的合金等，如铝钕合金AlNd、钼铌合金MoNb等，可以是多层金属，如Mo/Cu/Mo等。优选地采用Cu-X合金膜(X为Mn、Ni、Cr、Fe、Co、Mo、Ta或Ti)。通过使用Cu-X合金膜，由于可以通过湿蚀刻工序对薄膜进行加工，可以降低制造成本。进一步优选地，采用Cu-Mn合金膜。其中，第一金属层的厚度为800～1200埃，栅金属层的厚度为3000～5000埃，第二金属层的厚度为3000～9000埃。
本公开的实施例还提供一种显示装置，包括前述的显示基板。
该显示装置具体例如是有机发光二极管显示面板、量子点发光二极管显示面板、手机、电脑等任意具有显示功能的产品或部件。
有机发光二极管显示面板中的有机发光二极管可以包含阳极电极、空穴传输层、有机发光层、电子传输层和阴极电极。
量子点发光二极管显示面板中的量子点发光二极管可以包含阳极电极、量子点发光层、阴极电极。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

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  1. 一种显示基板，其中，包括：基底和设置在所述基底上的显示功能层，所述显示功能层包括：沿相交的第一方向和第二方向排布的多个像素驱动电路、沿所述第二方向延伸的多条电源线、沿所述第二方向延伸的多条补偿检测线、沿所述第一方向延伸的多条栅线、沿所述第二方向延伸的多条数据线、沿所述第一方向延伸的多条补偿扫描线；
    所述电源线与所述补偿检测线交替间隔设置，任意相邻的一条所述电源线和一条所述补偿检测线之间设置有沿所述第二方向延伸的两排像素驱动电路；
    在所述多个像素驱动电路中的任意一个像素驱动电路，该像素驱动电路的电源输入端与距离该像素驱动电路最近的一条所述电源线电连接，该像素驱动电路的补偿检测信号端与距离该像素驱动电路最近的一条所述补偿检测线电连接。
  2. 根据权利要求1所述的显示基板，其中，在位于相邻的一条所述电源线和一条所述补偿检测线之间的两排所述像素驱动电路中，
    在靠近所述电源线的一排所述像素驱动电路中的任意一个所述像素驱动电路，该像素驱动电路的电源输入端与距离该像素驱动电路最近的一条所述电源线直接连接，该像素驱动电路的补偿检测信号端通过补偿检测桥线与距离该像素驱动电路最近的一条所述补偿检测线连接；
    在靠近所述补偿检测线的一排所述像素驱动电路中的任意一个所述像素驱动电路，该像素驱动电路的电源输入端通过电源桥线与距离该像素驱动电路最近的一条所述电源线连接，该像素驱动电路的补偿检测信号端与距离该像素驱动电路最近的一条所述补偿检测线直接连接。
  3. 根据权利要求2所述的显示基板，其中，对于位于相邻的一条所述电源线和一条所述补偿检测线之间的两排所述像素驱动电路，该两排像素驱动电路之间设置有两条所述数据线；
    在该两排像素驱动电路中的任意一个所述像素驱动电路，该像素驱动电路的数据信号输入端与距离该像素驱动电路最近的一条所述数据线连接。
  4. 根据权利要求2所述的显示基板，其中，所述显示基板还包括：遮光图形，所述遮光图形位于所述基底和所述显示功能层之间，所述电源桥线、所述补偿检测桥线与所述遮光图形同层设置；
    所述电源桥线与对应的所述电源线和对应的所述电源输入端通过过孔连接；
    所述补偿检测桥线与对应的补偿检测线和对应补偿检测信号端通过过孔连接。
  5. 根据权利要求1所述的显示基板，其中，任意相邻的两条所述电源线通过第一导电桥线电连接，所述第一导电桥线沿所述第一方向延伸。
  6. 根据权利要求5所述的显示基板，其中，所述显示基板还包括多个发光器件，所述发光器件与所述像素驱动电路一一对应连接，所述发光器件包括沿远离所述基底方向依次叠置的第一电极、发光层、第二电极；
    所述第一导电桥线与所述第一电极同层设置
  7. 根据权利要求1所述的显示基板，其中，任意相邻的两条所述补偿检测线通过第二导电桥线电连接，所述第二导电桥线沿所述第一 方向延伸。
  8. 根据权利要求7所述的显示基板，其中，所述显示基板还包括多个发光器件，所述发光器件与所述像素驱动电路一一对应连接，所述发光器件包括沿远离所述基底方向依次叠置的第一电极、发光层、第二电极；
    所述第二导电桥线与所述第一电极同层设置。
  9. 根据权利要求1所述的显示基板，其中，至少部分所述电源线的端部连接至同一电源总线。
  10. 根据权利要求9所述的显示基板，其中，所述电源总线与所述栅线同层设置。
  11. 根据权利要求1-10任意一项所述的显示基板，其中，所述像素驱动电路包括驱动晶体管、开关晶体管、检测晶体管和存储电容，所述开关晶体管的栅极与对应的栅线连接，所述开关晶体管的第一极与对应的数据信号输入端连接，所述开关晶体管第二极与所述驱动晶体管的栅极和所述存储电容的第一极连接，所述驱动晶体管的第一极与对应的电源输入端连接，所述驱动晶体管的第二极与所述存储电容的第二极、所述检测晶体管的第一极连接，所述检测晶体管的栅极与对应的补偿扫描线连接，所述检测晶体管的第二极与对应的补偿检测信号端连接。
  12. 根据权利要求11所述的显示基板，其中，所述驱动晶体管、所述开关晶体管、所述检测晶体管均为顶栅型晶体管；
    所述存储电容的第一极与所述驱动晶体管、所述开关晶体管、所述检测晶体管的有源层同层设置；
    所述存储电容的第二极包括第一部分和第二部分，所述第一部分为所述遮光图形，所述第二部分与所述驱动晶体管的第一极同层设置且与所述驱动晶体管的第一极电连接，所述第一部分与所述第二部分电连接。
  13. 根据权利要求2所述的显示基板，其中，所述显示基板还包括多个发光器件，所述发光器件与所述像素驱动电路一一对应连接，所述发光器件包括沿远离所述基底方向依次叠置的第一电极、发光层、第二电极；
    所述存储电容的第二极还包括第三部分，所述第三部分与所述发光器件的第一电极同层设置，所述第三部分与所述第一部分电连接。
  14. 一种显示装置，其中，包括根据权利要求1-13任意一项所述的显示基板。
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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20220078778A (ko) * 2020-12-03 2022-06-13 삼성디스플레이 주식회사 발광 표시 장치
CN115346473B (zh) * 2022-05-25 2023-10-24 惠科股份有限公司 显示面板、驱动电路及驱动方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150130691A1 (en) * 2013-11-11 2015-05-14 Samsung Display Co., Ltd. Organic light emitting diode display
CN105528996A (zh) * 2016-01-29 2016-04-27 深圳市华星光电技术有限公司 像素补偿电路、方法、扫描驱动电路及平面显示装置
CN110164373A (zh) * 2019-05-27 2019-08-23 京东方科技集团股份有限公司 一种像素驱动电路及其制备方法、oled显示面板

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4846998B2 (ja) * 2004-10-08 2011-12-28 株式会社 日立ディスプレイズ 画像表示装置
US10522569B2 (en) * 2016-08-26 2019-12-31 Apple Inc. High SNR pixel design
KR20180024314A (ko) 2016-08-29 2018-03-08 엘지디스플레이 주식회사 표시장치
KR102584959B1 (ko) 2016-08-31 2023-10-06 엘지디스플레이 주식회사 표시장치
KR102568518B1 (ko) 2016-10-25 2023-08-18 엘지디스플레이 주식회사 고 개구율을 갖는 초고해상도 평판 표시장치
TWI645240B (zh) 2016-11-30 2018-12-21 南韓商Ｌｇ顯示器股份有限公司 顯示裝置
KR102603598B1 (ko) 2016-11-30 2023-11-21 엘지디스플레이 주식회사 표시장치
KR102627343B1 (ko) 2016-11-30 2024-01-22 엘지디스플레이 주식회사 표시장치
CN107331338B (zh) * 2017-08-28 2021-08-17 京东方科技集团股份有限公司 一种阵列基板、显示装置及其检测方法
KR102431929B1 (ko) 2017-10-31 2022-08-12 엘지디스플레이 주식회사 표시장치 및 그 제조방법
KR102367273B1 (ko) 2017-10-31 2022-02-23 엘지디스플레이 주식회사 유기 발광 표시 장치
KR102463737B1 (ko) 2017-12-04 2022-11-03 엘지디스플레이 주식회사 플렉서블 유기발광 다이오드 표시장치
KR102437180B1 (ko) 2017-12-06 2022-08-26 엘지디스플레이 주식회사 투명 유기발광 다이오드 표시장치
CN109087922B (zh) * 2018-09-19 2020-09-29 合肥鑫晟光电科技有限公司 阵列基板及其制作方法、显示面板
KR20210033683A (ko) * 2019-09-19 2021-03-29 엘지디스플레이 주식회사 표시 장치

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150130691A1 (en) * 2013-11-11 2015-05-14 Samsung Display Co., Ltd. Organic light emitting diode display
CN105528996A (zh) * 2016-01-29 2016-04-27 深圳市华星光电技术有限公司 像素补偿电路、方法、扫描驱动电路及平面显示装置
CN110164373A (zh) * 2019-05-27 2019-08-23 京东方科技集团股份有限公司 一种像素驱动电路及其制备方法、oled显示面板

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4075420A4 *

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