WO2021110043A1 - 信号整形电路及相应的栅极驱动电路 - Google Patents

信号整形电路及相应的栅极驱动电路 Download PDF

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Publication number
WO2021110043A1
WO2021110043A1 PCT/CN2020/133350 CN2020133350W WO2021110043A1 WO 2021110043 A1 WO2021110043 A1 WO 2021110043A1 CN 2020133350 W CN2020133350 W CN 2020133350W WO 2021110043 A1 WO2021110043 A1 WO 2021110043A1
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Prior art keywords
gate
resistor
nmos transistor
circuit
drain
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PCT/CN2020/133350
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English (en)
French (fr)
Inventor
刘卫中
张明丰
沈超
蒋亚平
牛瑞萍
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华润微集成电路(无锡)有限公司
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Priority to EP20896816.4A priority Critical patent/EP4016843B1/en
Publication of WO2021110043A1 publication Critical patent/WO2021110043A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/151—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs
    • H03K5/1515—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs non-overlapping
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS

Definitions

  • This application relates to the field of electricity, in particular to the field of circuit anti-interference technology, and specifically refers to a signal shaping circuit and a corresponding gate drive circuit.
  • Offset noise may also be transmitted as an input signal by the subsequent circuit, which may cause an error state and cause system failure. In the existing circuit structure, the difference signal cannot be identified and eliminated.
  • control circuits in the form of integrated circuits have gradually replaced traditional control systems composed of separate devices; through the use of high and low voltage control circuits, various protective devices, and high-voltage power devices and other devices or packaging Integration or process integration together greatly improves the integration and reliability of the complete system.
  • control circuit is very important.
  • This circuit that integrates high and low voltage is often called a half-bridge drive circuit. It is mainly used to drive the power tube of the external half-bridge topology; in the half-bridge drive circuit, Due to its simple structure, low cost, and high cost performance, the bootstrap capacitive structure is more convenient and more widely used.
  • the electrical signal of the high-voltage side control circuit is mainly generated by the way of dual short pulse circuits, and then the on and off pulses are converted into The control signal of the normal power tube.
  • the high-voltage side circuit adopts a floating power supply, in the process of fast switching and charging and discharging the parasitic capacitance, a displacement current will be formed in the high-voltage level conversion circuit, and a voltage drop will be formed on the resistance of the high-voltage side, that is, common mode Noise, the voltage signal is easy to trigger the subsequent circuit, causing the wrong state to cause the circuit to be damaged or burned.
  • a pulse filter circuit is generally used to eliminate the noise.
  • an analog filter circuit is generally used to filter out the noise signal.
  • Figure 1 is an anti-noise high-side drive circuit in the prior art, which includes a double pulse generating circuit and a noise filter circuit. , RS flip-flop and output drive circuit,
  • Figure 2 is a circuit diagram of the noise filter circuit in the anti-noise high-side drive circuit in Figure 1,
  • the device in order to filter out the noise more effectively, the device is generally matched as much as possible in the design to make the internal noise characteristics consistent and easier to filter. However, there will still be process deviations in the actual production. There is offset noise in the circuit.
  • the anti-noise high-side drive circuit in Figures 1 and 2 uses an exclusive OR function structure to eliminate common mode noise, it cannot suppress offset noise and may still be conducted to the subsequent stage, thereby affecting the accuracy of circuit control. Sex.
  • the purpose of this application is to overcome at least one of the above-mentioned disadvantages of the prior art and provide a signal shaping circuit with good anti-interference effect and stable performance and a corresponding gate drive circuit.
  • the signal shaping circuit and corresponding gate drive circuit of the present application are as follows:
  • the main feature of the signal shaping circuit is that it includes the turn-on signal shaping module and the turn-off signal shaping module;
  • the turn-on signal shaping module includes a first PMOS tube, a first NMOS tube, a second NMOS tube, a first resistor, a second resistor, a first capacitor, and a first inverter;
  • the gate of the first PMOS tube is connected to the first input signal, and the drain of the first PMOS tube is respectively connected to the first end of the first resistor and the first end of the first capacitor.
  • the terminal is connected to the gate of the second NMOS tube, and the source of the first PMOS tube is connected to the source of the first NMOS tube;
  • the gate of the first NMOS transistor is connected to a second input signal, and the drain of the first NMOS transistor and the first end of the second resistor are both connected to a reference voltage;
  • the drain of the second NMOS transistor is connected to the second end of the second resistor, the source of the second NMOS transistor, the second end of the first resistor, and the second end of the first resistor
  • the second ends of a capacitor are all grounded;
  • the input terminal of the first inverter is connected to the second terminal of the second resistor, the voltage terminal of the first inverter is connected to the reference voltage, and the first inverter is connected to the reference voltage.
  • the ground terminal of the inverter is grounded, and the output terminal of the first inverter constitutes the first output terminal of the signal shaping circuit;
  • the turn-off signal shaping module includes a second PMOS tube, a third NMOS tube, a fourth NMOS tube, a third resistor, a fourth resistor, a second capacitor, and a second inverter;
  • the gate of the second PMOS tube is connected to the second input signal, and the drain of the second PMOS tube is connected to the first end of the third resistor and the second capacitor respectively.
  • the first end of the second PMOS transistor is connected to the gate of the fourth NMOS transistor, and the source of the second PMOS transistor is connected to the source of the third NMOS transistor;
  • the gate of the third NMOS transistor is connected to the first input signal, and the drain of the third NMOS transistor and the first end of the fourth resistor are both connected to the reference voltage. connection;
  • the drain of the fourth NMOS transistor is connected to the second end of the fourth resistor, the source of the fourth NMOS transistor, the second end of the third resistor, and the second end of the fourth resistor
  • the second ends of the two capacitors are both grounded;
  • the input terminal of the second inverter is connected to the second terminal of the fourth resistor, the voltage terminal of the second inverter is connected to the reference voltage, and the second inverter is connected to the reference voltage.
  • the ground terminal of the inverter is grounded, and the output terminal of the second inverter constitutes the second output terminal of the signal shaping circuit.
  • the turn-on signal shaping module further includes a third PMOS tube, a fifth NMOS tube, a sixth NMOS tube, and a fifth resistor;
  • the gate of the third PMOS tube is connected to the second input signal, and the drain of the third PMOS tube is connected to the drain, gate, and gate of the fifth NMOS tube, respectively.
  • the gate of the sixth NMOS transistor is connected; the source of the third PMOS transistor is connected to the reference voltage through the fifth resistor;
  • the source of the fifth NMOS transistor and the source of the sixth NMOS transistor are both grounded;
  • the drain of the sixth NMOS transistor is connected to the drain of the first PMOS transistor
  • the turn-off signal shaping module further includes a fourth PMOS tube, a seventh NMOS tube, an eighth NMOS tube, and a sixth resistor;
  • the gate of the fourth PMOS tube is connected to the first input signal, and the drain of the fourth PMOS tube is connected to the drain, gate, and gate of the seventh NMOS tube, respectively.
  • the gate of the eighth NMOS transistor is connected; the source of the fourth PMOS transistor is connected to the reference voltage through the sixth resistor;
  • the source of the seventh NMOS transistor and the source of the eighth NMOS transistor are both grounded;
  • the drain of the eighth NMOS transistor is connected to the drain of the second PMOS transistor.
  • the main feature of the gate drive circuit with the signal shaping circuit is that the gate drive circuit further includes:
  • Pulse generating circuit used to generate open pulse signal and close pulse signal according to the input signal
  • a level shifting circuit for converting the on pulse signal and off pulse signal into the first input signal and the second input signal and sending them to the signal shaping circuit
  • a noise filter circuit for further eliminating short pulse noise in the signal output by the signal shaping circuit
  • the output stage drive circuit is connected with the noise filter circuit.
  • the level shift circuit includes a ninth NMOS tube and a tenth NMOS tube,
  • the gate of the ninth NMOS transistor is connected to the turn-on pulse signal, the source of the ninth NMOS transistor is grounded, and the drain of the ninth NMOS transistor is connected to the reference voltage through a seventh resistor.
  • the drain of the ninth NMOS transistor is also used as the first output terminal of the level shift circuit to output the first input signal;
  • the gate of the tenth NMOS transistor is connected to the off pulse signal, the source of the tenth NMOS transistor is grounded, and the drain of the tenth NMOS transistor is connected to the reference voltage through an eighth resistor.
  • the drain of the tenth NMOS transistor is also used as the second output terminal of the level shift circuit to output the second input signal.
  • the level shift circuit further includes a first Zener diode and a second Zener diode;
  • the anode of the first Zener diode is connected to the drain of the ninth NMOS tube, and the cathode of the first Zener diode is connected to the reference voltage;
  • the anode of the second Zener diode is connected to the drain of the tenth NMOS tube, and the cathode of the second Zener diode is connected to the reference voltage.
  • the noise filter circuit includes a first inverter chain, a ninth resistor, a third capacitor, a first Schmitt trigger, a second inverter chain, a tenth resistor, a fourth capacitor, and a first inverter chain.
  • the input end of the first inverter chain is connected to the first output end of the signal shaping circuit, and the output end of the first inverter chain is connected to the first end of the ninth resistor
  • the second end of the ninth resistor is respectively connected to the first end of the third capacitor and the input end of the first Schmitt trigger, and the first end of the third capacitor
  • the two ends are grounded, and the output end of the first Schmitt trigger constitutes the first output end of the noise filter circuit, and is connected to the first input end of the output stage drive circuit;
  • the input end of the second inverter chain is connected to the second output end of the signal shaping circuit, and the output end of the second inverter chain is connected to the first end of the tenth resistor
  • the second end of the tenth resistor is respectively connected to the first end of the fourth capacitor and the input end of the second Schmitt trigger, and the first end of the fourth capacitor
  • the two ends are grounded, and the output end of the second Schmitt trigger constitutes the second output end of the noise filter circuit, and is connected to the second input end of the output stage drive circuit;
  • the power terminals of the first inverter chain, the second inverter and the first Schmitt trigger are all connected to the reference voltage;
  • the ground terminals of the first inverter chain, the second inverter and the first Schmitt trigger are all grounded.
  • the output stage drive circuit includes a first NAND gate, a third inverter chain, a fifth PMOS tube, an eleventh resistor, a second NAND gate, a fourth inverter chain, and a tenth inverter chain.
  • the first terminal of the first NAND gate constitutes the first input terminal of the output stage drive circuit, and the output terminal of the first NAND gate is respectively connected to the input of the third inverter chain.
  • Terminal and the second terminal of the second NAND gate, the output terminal of the third inverter chain is connected to the gate of the fifth PMOS transistor, the fifth PMOS transistor
  • the source of is connected to the reference voltage, and the drain of the fifth PMOS transistor is connected to the first end of the eleventh resistor;
  • the first terminal of the second NAND gate constitutes the second input terminal of the output stage drive circuit, and the output terminal of the second NAND gate is respectively connected to the input of the fourth inverter chain. Terminal and the second terminal of the first NAND gate, the output terminal of the fourth inverter chain is connected to the gate of the eleventh NMOS transistor, and the eleventh The source of the NMOS transistor is grounded, and the drain of the eleventh NMOS transistor is connected to the first end of the twelfth resistor;
  • the second end of the eleventh resistor and the second end of the twelfth resistor together constitute the output end of the output stage driving circuit
  • the power terminals of the first NAND gate, the third inverter chain, the second NAND gate, and the fourth inverter chain are all connected to the reference voltage;
  • the ground terminals of the first NAND gate, the third inverter chain, the second NAND gate and the fourth inverter chain are all grounded.
  • the output stage drive circuit includes a third NAND gate, a fourth NAND gate, a fifth inverter chain, a sixth inverter chain, a twelfth NMOS transistor, a thirteenth NMOS transistor, The fourteenth NMOS tube, the fifteenth NMOS tube, the sixth PMOS tube, the seventh PMOS tube, the eighth PMOS tube, and the ninth PMOS tube;
  • the first terminal of the third NAND gate constitutes the first input terminal of the output stage drive circuit, and the output terminal of the third NAND gate is respectively connected to the input of the fifth inverter chain. Connected to the second end of the fourth NAND gate;
  • the first terminal of the fourth NAND gate constitutes the second input terminal of the output stage drive circuit, the output terminal of the fourth NAND gate and the second terminal of the third NAND gate Connected
  • the output end of the fifth inverter chain is respectively connected to the input end of the sixth inverter chain, the gate of the seventh PMOS transistor, and the gate of the fourteenth NMOS transistor;
  • the output terminal of the sixth inverter chain is respectively connected to the drain of the twelfth NMOS transistor, the gate of the thirteenth NMOS transistor, the drain of the sixth PMOS transistor, and the gate of the eighth PMOS transistor. Connected
  • the drain of the seventh PMOS transistor is respectively connected to the drain of the thirteenth NMOS transistor, the gate of the ninth PMOS transistor, and the gate of the sixth PMOS transistor;
  • the drain of the fourteenth NMOS transistor is connected to the drain of the eighth PMOS transistor, the gate of the fifteenth NMOS transistor, and the gate of the twelfth NMOS transistor respectively;
  • the source of the seventh PMOS tube, the source of the eighth PMOS tube, and the source of the ninth PMOS tube are all connected to the reference voltage;
  • the source of the twelfth NMOS transistor, the source of the thirteenth NMOS transistor, the source of the fourteenth NMOS transistor, and the source of the fifteenth NMOS transistor are all grounded;
  • the drain of the ninth PMOS transistor and the drain of the fifteenth NMOS transistor together constitute the output terminal of the output stage driving circuit
  • the power terminals of the third NAND gate, the fourth NAND gate, the fifth inverter chain, and the sixth inverter chain are all connected to the reference voltage;
  • the ground terminals of the third NAND gate, the fourth NAND gate, the fifth inverter chain and the sixth inverter chain are all grounded.
  • the signal shaping circuit adds an additional NMOS tube, which improves the requirements for the input differential signal amplitude, and by setting parallel resistors and capacitors in the circuit, the input differential signal amplitude needs to exceed a certain value and last for a certain time , Will be recognized as a trigger signal, which can effectively filter out some interference or offset noise caused by device mismatch.
  • the gate drive circuit using this signal shaping circuit also includes a pulse generator circuit, a level shift circuit, and a noise filter circuit. And the output stage drive circuit, through the cooperation of these circuits, the offset noise and common mode noise can be effectively filtered out. Using the signal shaping circuit of the present application and the corresponding gate drive circuit can make the circuit work more reliably and have more stable performance.
  • Fig. 1 is a schematic diagram of an anti-noise high-side drive circuit in the prior art
  • FIG. 2 is a circuit diagram of a noise filter circuit in the anti-noise high-side drive circuit in FIG. 1;
  • FIG. 3 is a schematic diagram of the structure of the signal shaping circuit of the present application in an embodiment
  • FIG. 5 is a schematic diagram of the gate driving circuit of the present application in an embodiment
  • FIG. 6 is a schematic diagram of the structure of the noise filter circuit and the output stage drive circuit in the gate drive circuit of the present application in an embodiment
  • FIG. 7 is a schematic structural diagram of an output stage driving circuit in the gate driving circuit of the present application in an embodiment.
  • the signal shaping circuit of the present application includes a turn-on signal shaping module and a turn-off signal shaping module;
  • the turn-on signal shaping module includes a first PMOS tube MP1, a first NMOS tube MN1, a second NMOS tube MN2, a first resistor R1, a second resistor R2, a first capacitor C1, and a first inverter INV1;
  • the gate of the first PMOS transistor MP1 is connected to the first input signal Vput1, and the drain of the first PMOS transistor MP1 is respectively connected to the first end of the first resistor R1 and the first end of the first resistor R1 and the first input signal Vput1.
  • the first end of the capacitor C1 is connected to the gate of the second NMOS transistor MN2, and the source of the first PMOS transistor MP1 is connected to the source of the first NMOS transistor MN1;
  • the gate of the first NMOS tube MN1 is connected to the second input signal Vput2, and the drain of the first NMOS tube MN1 and the first end of the second resistor R2 are both connected to the reference voltage VB ;
  • the drain of the second NMOS transistor MN2 is connected to the second end of the second resistor R2, the source of the second NMOS transistor MN2, the second end of the first resistor R1 and The second ends of the first capacitor C1 are all grounded;
  • the input terminal of the first inverter INV1 is connected to the second terminal of the second resistor R2, and the voltage terminal of the first inverter INV1 is connected to the reference voltage VB, so The ground terminal of the first inverter INV1 is grounded, and the output terminal of the first inverter INV1 constitutes the first output terminal of the signal shaping circuit;
  • the turn-off signal shaping module includes a second PMOS tube MP2, a third NMOS tube MN3, a fourth NMOS tube MN4, a third resistor R3, a fourth resistor R4, a second capacitor C2, and a second inverter INV2;
  • the gate of the second PMOS transistor MP2 is connected to the second input signal Vput2, and the drain of the second PMOS transistor MP2 is respectively connected to the first end of the third resistor R3 and the The first end of the second capacitor C2 is connected to the gate of the fourth NMOS transistor MN4, and the source of the second PMOS transistor MP2 is connected to the source of the third NMOS transistor MN3;
  • the gate of the third NMOS transistor MN3 is connected to the first input signal Vput1, and the drain of the third NMOS transistor MN3 and the first end of the fourth resistor R4 are both connected to the The reference voltage VB is connected;
  • the drain of the fourth NMOS transistor MN4 is connected to the second end of the fourth resistor R4, the source of the fourth NMOS transistor MN4, the second end of the third resistor R3 and The second ends of the second capacitor C2 are all grounded;
  • the input terminal of the second inverter INV2 is connected to the second terminal of the fourth resistor R4, and the voltage terminal of the second inverter INV2 is connected to the reference voltage VB, so The ground terminal of the second inverter INV2 is grounded, and the output terminal of the second inverter INV2 constitutes the second output terminal of the signal shaping circuit.
  • the signal shaping circuit of the present application is based on the circuit in FIG. 1, and the turn-on signal shaping module is further provided with a third PMOS transistor MP3 and a fifth NMOS transistor.
  • the gate of the third PMOS transistor MP3 is connected to the second input signal Vput2, and the drain of the third PMOS transistor MP3 is respectively connected to the drain and gate of the fifth NMOS transistor MN5. Connected to the gate of the sixth NMOS transistor MN6; the source of the third PMOS transistor MP3 is connected to the reference voltage VB through the fifth resistor R5;
  • the source of the fifth NMOS transistor MN5 and the source of the sixth NMOS transistor MN6 are both grounded;
  • the drain of the sixth NMOS transistor MN6 is connected to the drain of the first PMOS transistor MP1;
  • a fourth PMOS tube MP4, a seventh NMOS tube MN7, an eighth NMOS tube MN8, and a sixth resistor R6 are also provided in the turn-off signal shaping module;
  • the gate of the fourth PMOS transistor MP4 is connected to the first input signal Vput1, and the drain of the fourth PMOS transistor MP4 is respectively connected to the drain and gate of the seventh NMOS transistor MN7. Connected to the gate of the eighth NMOS transistor MN8; the source of the fourth PMOS transistor MP4 is connected to the reference voltage VB through the sixth resistor R6;
  • the source of the seventh NMOS transistor MN7 and the source of the eighth NMOS transistor MN8 are both grounded;
  • the drain of the eighth NMOS transistor MN8 is connected to the drain of the second PMOS transistor MP2.
  • the performance of the signal shaping circuit in the embodiment of FIG. 4 is better than the signal shaping circuit in the embodiment of FIG. 3.
  • the circuit in FIG. 3 can also output corresponding signals according to the first input signal Vput1 and the second input signal Vput2 to eliminate the offset noise
  • the circuit in FIG. 3 can only provide pull-down through the first resistor R1 and the third resistor R3, the pull-down capability is weak, and the anti-interference performance is not as good as the signal shaping circuit in the embodiment of FIG. 4.
  • the upper part of the circuit namely the turn-on signal shaping module, includes a first PMOS tube MP1, a first NMOS tube MN1, a second NMOS tube MN2, a first resistor R1, a second resistor R2, and a second resistor.
  • Input structure as shown in FIG. 4, a first NMOS tube MN1 is connected in series with the first PMOS tube MP1, and the same input signal is connected to the gates of the first NMOS tube MN1 and the third PMOS tube MP3;
  • the first input signal Vput1 and the second input signal Vput2 are input to form a differential signal, it is easy to be recognized and transmitted to the second stage to generate an output signal; and the first input signal is added to the circuit NMOS tube MN1, the difference between the first input signal Vput1 and the second input signal Vput2 must at least exceed the sum of the thresholds of the first PMOS tube MP1 and the first NMOS tube MN1 (assuming that the threshold of the first NMOS tube MN1 is Vthn1, the first PMOS tube
  • the threshold values of the tube MP1 and the third PMOS tube MP3 are both Vthp1, so the sum of the threshold values of the first PMOS tube MP1 and the first NMOS tube MN1 is Vthn1+Vthp1), so that the first PMOS tube MP1 and the first NMOS tube MN1 conduct at the same time.
  • the circuit is also provided with a first resistor R1 and a first capacitor C1. Therefore, the amplitude of the differential signal that needs to be input to the circuit exceeds the threshold sum of the first PMOS tube MP1 and the first NMOS tube MN1 and lasts for a certain time In order to generate the second-level input signal, the offset noise caused by some interference or device mismatch can be effectively filtered.
  • the first output terminal and the second output terminal of the signal shaping circuit in Figures 3 and 4 are both connected to the subsequent noise filter circuit.
  • the above signal shaping circuit can also be applied to other situations, and is combined with the latter.
  • the circuits corresponding to the levels are connected.
  • the gate driving circuit including the above-mentioned signal shaping circuit, it further includes:
  • the pulse generating circuit is used to generate the turn-on pulse signal Von and the turn-off pulse signal Voff according to the input signal Vi.
  • the pulse generation circuit is a double pulse generation circuit, wherein the turn-on pulse signal Von and the turn-off pulse signal Voff are respectively on the rising edge of the input signal Vi Or the falling edge is generated;
  • the level shift circuit is used to convert the turn-on pulse signal Von and turn-off pulse signal Voff into the first input signal Vput1 and the second input signal Vput2 and send them to the signal shaping circuit, that is, the turn-on pulse signal Von And the off pulse signal Voff is transferred to the high-level circuit side to become the first input signal Vput1 and the second input signal Vput2;
  • the level shift circuit includes a ninth NMOS tube MN9 and a tenth NMOS tube MN10, and the ninth NMOS tube MN9 and the tenth NMOS tube MN10 are two high-voltage NMOS tubes.
  • the gate of the nine NMOS transistor MN9 is connected to the turn-on pulse signal Von, the source of the ninth NMOS transistor MN9 is grounded, and the drain of the ninth NMOS transistor MN9 is connected to the seventh resistor R7.
  • the first end is connected to the anode of the first voltage regulator tube Z1, and the second end of the seventh resistor R7 and the cathode of the first voltage regulator tube Z1 are both connected to the reference voltage VB;
  • the drain of the ninth NMOS transistor MN9 also serves as the first output terminal of the level shift circuit to output the first input signal Vput1;
  • the gate of the tenth NMOS transistor MN10 is connected to the off pulse signal Voff, the source of the tenth NMOS transistor MN10 is grounded, and the drain of the tenth NMOS transistor MN10 is connected to the
  • the first end of the eight resistor R8 is connected to the anode of the second voltage regulator tube Z2, and the second end of the eighth resistor R8 and the cathode of the second voltage regulator tube Z2 are both connected to the reference voltage VB Connected
  • the drain of the tenth NMOS transistor MN10 is also used as the second output terminal of the level shift circuit to output the second input signal Vput2;
  • the working principle of the level shift circuit is:
  • the ninth NMOS transistor MN9 When the ninth NMOS transistor MN9 is turned on, a pull-down current is generated to pass through the seventh resistor R7 to generate a voltage signal relative to the reference voltage VB—the first input signal Vput1. When the tenth NMOS transistor MN10 is turned on, a pull-down current is generated to pass The eighth resistor R8 generates a voltage signal relative to the reference voltage VB—the second input signal Vput2.
  • the first voltage regulator tube Z1 and the second voltage regulator tube Z2 are used for clamping to prevent the first input signal Vput1 and the second input The signal Vput2 drops too much relative to the reference voltage VB, which damages the circuit.
  • a noise filter circuit for further eliminating short pulse noise in the signal output by the signal shaping circuit
  • the noise filter circuit includes a first inverter chain, a ninth resistor R9, a third capacitor C3, a first Schmitt trigger SIMT1, a second inverter chain, and a tenth resistor R10. ,
  • the input terminal of the first inverter chain is connected to the first output terminal of the signal shaping circuit, and the output terminal of the first inverter chain is connected to the first output terminal of the ninth resistor R9.
  • the second terminal of the ninth resistor R9 is connected to the first terminal of the third capacitor C3 and the input terminal of the first Schmitt trigger SIMT1, respectively, and the second terminal of the ninth resistor R9 is connected to the input terminal of the first Schmitt trigger SIMT1.
  • the second terminal of the three capacitor C3 is grounded, and the output terminal of the first Schmitt trigger SIMT1 constitutes the first output terminal of the noise filter circuit, and is connected to the first input terminal of the output stage drive circuit Connected
  • the input terminal of the second inverter chain is connected to the second output terminal of the signal shaping circuit, and the output terminal of the second inverter chain is connected to the first output terminal of the tenth resistor R10.
  • the second end of the tenth resistor R10 is connected to the first end of the fourth capacitor C4 and the input end of the second Schmitt trigger SIMT2 respectively, and the second end of the tenth resistor R10 is connected to the input end of the second Schmitt trigger SIMT2.
  • the second end of the four-capacitor C4 is grounded, and the output end of the second Schmitt trigger SIMT2 constitutes the second output end of the noise filter circuit, and is connected to the second input end of the output stage drive circuit Connected
  • the power terminals of the first inverter chain, the second inverter and the first Schmitt trigger SIMT1 are all connected to the reference voltage VB;
  • the ground terminals of the first inverter chain, the second inverter and the first Schmitt trigger SIMT1 are all grounded.
  • the ninth resistor R9 and the third capacitor C3 form a filter circuit to further filter the signal output by the previous-stage signal shaping circuit. Eliminate short-pulse noise signals.
  • the output stage drive circuit is connected to the noise filter circuit and outputs a gate drive signal OUT;
  • the output stage drive circuit includes a first NAND gate NAND1, a third inverter chain, a fifth PMOS transistor MP5, an eleventh resistor R11, a second NAND gate NAND2, and a fourth inverter chain. Phaser chain, the eleventh NMOS tube MN11 and the twelfth resistor R12;
  • the first terminal of the first NAND gate NAND1 constitutes the first input terminal of the output stage drive circuit, and the output terminal of the first NAND gate NAND1 is connected to the third inverter chain respectively.
  • the input terminal of the second NAND gate NAND2 is connected to the second terminal, the output terminal of the third inverter chain is connected to the gate of the fifth PMOS transistor MP5, and the The source of the fifth PMOS transistor MP5 is connected to the reference voltage VB, and the drain of the fifth PMOS transistor MP5 is connected to the first end of the eleventh resistor R11;
  • the first terminal of the second NAND gate NAND2 constitutes the second input terminal of the output stage drive circuit, and the output terminal of the second NAND gate NAND2 is connected to the fourth inverter chain respectively.
  • the input terminal of the first NAND gate NAND1 is connected to the second terminal, the output terminal of the fourth inverter chain is connected to the gate of the eleventh NMOS transistor MN11, and the The source of the eleventh NMOS transistor MN11 is grounded, and the drain of the eleventh NMOS transistor MN11 is connected to the first end of the twelfth resistor R12;
  • the second end of the eleventh resistor R11 and the second end of the twelfth resistor R12 together constitute the output end of the output stage driving circuit
  • the power terminals of the first NAND gate NAND1, the third inverter chain, the second NAND gate NAND2, and the fourth inverter chain are all connected to the reference voltage VB;
  • the ground terminals of the first NAND gate NAND1, the third inverter chain, the second NAND gate NAND2 and the fourth inverter chain are all grounded.
  • the RS trigger composed of the first NAND gate NAND1 and the second NAND gate NAND2 can effectively lock and save the effective pulse input signal, after the fifth PMOS tube, the eleventh NMOS tube, and the eleventh resistor R11 And the twelfth resistor R12 generates the final gate drive signal OUT.
  • the structure of the noise filter circuit and the output stage drive circuit in this embodiment can be referred to as shown in FIG. 6, where the first inverter chain, the second inverter chain, the third inverter chain, and the fourth inverter chain
  • the chain can be composed of cascaded inverters, and the two ends of A and B in the noise filter circuit in FIG. 6 are connected to the ends of A and B in FIG. 3 or FIG. 4 respectively.
  • the output stage driving circuit can also be implemented by the circuit trench shown in FIG. 7, which includes a third NAND gate NAND3, a fourth NAND gate NAND4, a fifth inverter chain, and a sixth inverter.
  • Phaser chain twelfth NMOS tube MN12, thirteenth NMOS tube MN13, fourteenth NMOS tube MN14, fifteenth NMOS tube MN15, sixth PMOS tube MP6, seventh PMOS tube MP7, eighth PMOS tube MP8 and The ninth PMOS tube MP9;
  • the first terminal of the third NAND gate NAND3 constitutes the first input terminal of the output stage drive circuit, and the output terminal of the third NAND gate NAND3 is connected to the fifth inverter chain respectively.
  • the input terminal of is connected to the second terminal of the fourth NAND gate NAND4;
  • the first terminal of the fourth NAND gate NAND4 constitutes the second input terminal of the output stage drive circuit, and the output terminal of the fourth NAND gate NAND4 is connected to the output terminal of the third NAND gate NAND3. The second end is connected;
  • the output terminal of the fifth inverter chain is respectively connected to the input terminal of the sixth inverter chain, the gate of the seventh PMOS transistor MP7 and the gate of the fourteenth NMOS transistor MN14;
  • the output end of the sixth inverter chain is respectively connected with the drain of the twelfth NMOS transistor MN12, the gate of the thirteenth NMOS transistor MN13, the drain of the sixth PMOS transistor MP6, and the eighth PMOS transistor.
  • the gate of MP8 is connected;
  • the drain of the seventh PMOS transistor MP7 is respectively connected to the drain of the thirteenth NMOS transistor MN13, the gate of the ninth PMOS transistor MP9, and the gate of the sixth PMOS transistor MP6;
  • the drain of the fourteenth NMOS transistor MN14 is respectively connected to the drain of the eighth PMOS transistor MP8, the gate of the fifteenth NMOS transistor MN15, and the gate of the twelfth NMOS transistor MN12;
  • the source of the seventh PMOS transistor MP7, the source of the eighth PMOS transistor MP8, and the source of the ninth PMOS transistor MP9 are all connected to the reference voltage VB;
  • the source of the twelfth NMOS transistor MN12, the source of the thirteenth NMOS transistor MN13, the source of the fourteenth NMOS transistor MN14, and the source of the fifteenth NMOS transistor MN15 are all grounded;
  • the drain of the ninth PMOS transistor MP9 and the drain of the fifteenth NMOS transistor MN15 jointly constitute the output terminal of the output stage driving circuit;
  • the power terminals of the third NAND gate NAND3, the fourth NAND gate NAND4, the fifth inverter chain, and the sixth inverter chain are all connected to the reference voltage VB;
  • the fifth inverter chain and the sixth inverter chain can be composed of cascaded inverters.
  • the output stage drive circuit in this embodiment respectively controls the ninth PMOS tube MP9 and the fifteenth NMOS tube MN9, which can prevent the through current from damaging the output stage circuit, and uses a two-stage inverter chain (the fifth inverter chain That is, the sixth inverter chain) generates a very short dead time, and the sixth PMOS tube MP6 and the twelfth NMOS tube MN12 play a clamping role to prevent the gate drive signals of the devices in the output stage circuit from crossing This brings about the problem of device damage caused by the punch-through current. While ensuring reliability, there is a very small transmission delay, and the circuit noise is small.
  • the control circuit can adapt to different application environments and has high reliability.
  • the gate drive circuit in this embodiment can address the insufficiency of common mode noise processing of the high-voltage gate drive circuit, achieve anti-noise interference, and reduce the influence of offset noise, so that the circuit can work more reliably, and the circuit has a simple structure and stable performance. Strong adaptability.
  • the signal shaping circuit adds an additional NMOS tube, which improves the requirements for the input differential signal amplitude, and by setting parallel resistors and capacitors in the circuit, the input differential signal amplitude needs to exceed a certain value and last for a certain time , Will be recognized as a trigger signal, which can effectively filter out some interference or offset noise caused by device mismatch.
  • the gate drive circuit using this signal shaping circuit also includes a pulse generator circuit, a level shift circuit, and a noise filter circuit. And the output stage drive circuit, through the cooperation of these circuits, the offset noise and common mode noise can be effectively filtered out. Using the signal shaping circuit of the present application and the corresponding gate drive circuit can make the circuit work more reliably and have more stable performance.

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Abstract

一种信号整形电路及相应的栅极驱动电路，所述信号整形电路加入了额外的NMOS管，提高了对输入差分信号幅度的要求，且通过在电路中设置并联的电阻与电容，使得输入的差分信号幅值需要超过一定的值，且持续一定时间，才会被认定为触发信号，将一些干扰或器件失配造成的失调噪声有效地滤除掉，采用该信号整形电路的栅极驱动电路还包括脉冲产生电路、电平移位电路、噪声滤波电路及输出级驱动电路，通过电路的配合可以有效滤除失调噪声和共模噪声。采用该信号整形电路及相应的栅极驱动电路，可以使得电路更可靠的工作，性能更稳定。

Description

信号整形电路及相应的栅极驱动电路
本申请要求于2019年12月02日提交中国专利局、申请号为201911212023.8、申请名称为“信号整形电路及相应的栅极驱动电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电学领域，尤其涉及电路抗干扰技术领域，具体是指一种信号整形电路及相应的栅极驱动电路。
背景技术
在一些控制电路中，时常会因为实际制作工艺的偏差，两路电平转移电路存在失配，在电平转移电路的输出信号中的产生幅度差异的噪声，这里将之称为失调噪声，该失调噪声也可能被后级电路作为输入信号传输，进而造成错误状态导致系统故障。在现有电路结构中对于该差异信号不能辨识并消除。
例如，在电力电子等高压应用领域，以集成电路形式的控制电路逐步取代了传统的分离器件组建的控制系统；通过将高低压控制电路、各类保护功能的器件以及高压功率器件等器件或封装集成或工艺集成一起，大大提高了整机系统的集成度、可靠性。
在此类应用中控制电路至关重要，这种将高低压集成一起的电路常被称为半桥驱动电路，它主要用来驱动外部半桥拓扑结构的功率管；在半桥驱动电路中，由于结构简单、成本低、性价比高等特点，自举电容式的结构更方便，应用更广泛。
为了降低电路自身的功率损耗，在自举电容式的半桥驱动电路中，主要通过双路短脉冲电路的方式产生高压侧控制电路的电信号，再通过RS触发器将开、关脉冲转换成正常的功率管的控制信号。因为高压侧电路采用浮动电源，在快速的开关转换中，对寄生电容的充放电过程中，高压电平转换电路中会形成位移电流，并在高压侧的电阻上形成压降，即共模噪声，该电压信号容易触发后级电路，造成错误状态导致电路损坏或烧毁，针对该情况，一般采用脉冲滤波电路将该噪声消除，像飞兆半导体一般采用模拟滤波电路来滤出噪声信号，其他一些公司如三菱等，采用数字滤波器来滤出噪声，等等。
无论采用上述哪种方式都对消除共模噪声有一定的效果，如图1所示，其为现有技术中的一种抗噪声的高侧驱动电路，其包括双脉冲产生电路、噪声滤波电路、RS触发器及输出驱动电路，图2为图1中的抗噪声的高侧驱动电路中的噪声滤波电路的电路图，
在实际电路实现中，为了使噪声更有效的被滤出，一般都在设计中尽可能的匹配器件，使的内部的噪声特性一致，更容易滤除，但实际制作还是会存在工艺偏差，导致电路中存在失调噪声。图1、2中的这种抗噪声的高侧驱动电路虽然采用一个异或功 能的结构来消除共模噪声，但对于失调噪声却不能抑制，仍可能传导到后级，从而影响电路控制的准确性。
发明内容
本申请的目的是克服至少一个上述现有技术的缺点，提供了一种抗干扰效果好、性能稳定的信号整形电路及相应的栅极驱动电路。
为了实现上述目的或其他目的，本申请的信号整形电路及相应的栅极驱动电路如下：
该信号整形电路，其主要特点是，包括开启信号整形模块及关断信号整形模块；
其中，所述的开启信号整形模块包括第一PMOS管、第一NMOS管、第二NMOS管、第一电阻、第二电阻、第一电容及第一反相器；
所述的第一PMOS管的栅极与第一输入信号相连接，所述的第一PMOS管的漏极分别与所述的第一电阻的第一端、所述的第一电容的第一端及所述的第二NMOS管的栅极相连接，所述的第一PMOS管的源极与所述的第一NMOS管的源极相连接；
所述的第一NMOS管的栅极与第二输入信号相连接，所述的第一NMOS管的漏极与所述的第二电阻的第一端均与参考电压相连接；
所述的第二NMOS管的漏极与所述的第二电阻的第二端相连接，所述的第二NMOS管的源极、所述的第一电阻的第二端及所述的第一电容的第二端均接地；
所述的第一反相器的输入端与所述的第二电阻的第二端相连接，所述的第一反相器的电压端与所述的参考电压相连接，所述的第一反相器的接地端接地，所述的第一反相器的输出端构成所述的信号整形电路的第一输出端；
所述的关断信号整形模块包括第二PMOS管、第三NMOS管、第四NMOS管、第三电阻、第四电阻、第二电容及第二反相器；
所述的第二PMOS管的栅极与所述的第二输入信号相连接，所述的第二PMOS管的漏极分别与所述的第三电阻的第一端、所述的第二电容的第一端及所述的第四NMOS管的栅极相连接，所述的第二PMOS管的源极与所述的第三NMOS管的源极相连接；
所述的第三NMOS管的栅极与所述的第一输入信号相连接，所述的第三NMOS管的漏极与所述的第四电阻的第一端均与所述的参考电压相连接；
所述的第四NMOS管的漏极与所述的第四电阻的第二端相连接，所述的第四NMOS管的源极、所述的第三电阻的第二端及所述的第二电容的第二端均接地；
所述的第二反相器的输入端与所述的第四电阻的第二端相连接，所述的第二反相器的电压端与所述的参考电压相连接，所述的第二反相器的接地端接地，所述的第二反相器的输出端构成所述的信号整形电路的第二输出端。
较佳地，所述的开启信号整形模块还包括第三PMOS管、第五NMOS管、第六NMOS管及第五电阻；
所述的第三PMOS管的栅极与所述的第二输入信号相连接，所述的第三PMOS管的漏极分别与所述的第五NMOS管的漏极、栅极及所述的第六NMOS管的栅极相连接；所述的第三PMOS管的源极通过所述的第五电阻与所述的参考电压相连接；
所述的第五NMOS管的源极和第六NMOS管的源极均接地；
所述的第六NMOS管的漏极与所述的第一PMOS管的漏极相连接；
所述的关断信号整形模块还包括第四PMOS管、第七NMOS管、第八NMOS管及第六电阻；
所述的第四PMOS管的栅极与所述的第一输入信号相连接，所述的第四PMOS管的漏极分别与所述的第七NMOS管的漏极、栅极及所述的第八NMOS管的栅极相连接；所述的第四PMOS管的源极通过所述的第六电阻与所述的参考电压相连接；
所述的第七NMOS管的源极和第八NMOS管的源极均接地；
所述的第八NMOS管的漏极与所述的第二PMOS管的漏极相连接。
该具有所述的信号整形电路的栅极驱动电路，其主要特点是，所述的栅极驱动电路还包括：
脉冲产生电路，用于根据输入信号产生开启脉冲信号及关闭脉冲信号；
电平移位电路，用于将所述的开启脉冲信号及关闭脉冲信号转换为所述的第一输入信号及第二输入信号输送给所述的信号整形电路；
噪声滤波电路，用于进一步消除所述的信号整形电路输出的信号中的短脉冲噪声；
输出级驱动电路与所述的噪声滤波电路相连接。
较佳地，所述的电平移位电路包括第九NMOS管及第十NMOS管，
所述的第九NMOS管的栅极接所述的开启脉冲信号，所述的第九NMOS管的源极接地，所述的第九NMOS管的漏极通过第七电阻与所述的参考电压相连接；
所述的第九NMOS管的漏极还作为所述的电平移位电路的第一输出端，输出所述的第一输入信号；
所述的第十NMOS管的栅极接所述的关闭脉冲信号，所述的第十NMOS管的源极接地，所述的第十NMOS管的漏极通过第八电阻与所述的参考电压相连接；
所述的第十NMOS管的漏极还作为所述的电平移位电路的第二输出端，输出所述的第二输入信号。
更佳地，所述的电平移位电路还包括第一稳压二极管及第二稳压二极管；
所述的第一稳压二极管的阳极与所述的第九NMOS管的漏极相连接，所述的第一稳压二极管的阴极与所述的参考电压相连接；
所述的第二稳压二极管的阳极与所述的第十NMOS管的漏极相连接，所述的第二稳压二极管的阴极与所述的参考电压相连接。
较佳地，所述的噪声滤波电路包括第一反相器链、第九电阻、第三电容、第一施密特触发器、第二反相器链、第十电阻、第四电容及第二施密特触发器；
所述的第一反相器链的输入端与所述的信号整形电路的第一输出端相连接，所述的第一反相器链的输出端与所述的第九电阻的第一端相连接，所述的第九电阻的第二端分别与所述的第三电容的第一端及所述的第一施密特触发器的输入端相连接，所述的第三电容的第二端接地，所述的第一施密特触发器的输出端构成所述的噪声滤波电路的第一输出端，并与所述的输出级驱动电路的第一输入端相连接；
所述的第二反相器链的输入端与所述的信号整形电路的第二输出端相连接，所述的第二反相器链的输出端与所述的第十电阻的第一端相连接，所述的第十电阻的第二 端分别与所述的第四电容的第一端及所述的第二施密特触发器的输入端相连接，所述的第四电容的第二端接地，所述的第二施密特触发器的输出端构成所述的噪声滤波电路的第二输出端，并与所述的输出级驱动电路的第二输入端相连接；
所述的第一反相器链、第二反相器及第一施密特触发器的电源端均与所述的参考电压相连接；
所述的第一反相器链、第二反相器及第一施密特触发器的接地端均接地。
更佳地，所述的输出级驱动电路包括第一与非门、第三反相器链、第五PMOS管、第十一电阻、第二与非门、第四反相器链、第十一NMOS管及第十二电阻；
所述的第一与非门的第一端构成所述的输出级驱动电路的第一输入端，所述的第一与非门的输出端分别与所述的第三反相器链的输入端及所述的第二与非门的第二端相连接，所述的第三反相器链的输出端与所述的第五PMOS管的栅极相连接，所述的第五PMOS管的源极与所述的参考电压相连接，所述的第五PMOS管的漏极与所述的第十一电阻的第一端相连接；
所述的第二与非门的第一端构成所述的输出级驱动电路的第二输入端，所述的第二与非门的输出端分别与所述的第四反相器链的输入端及所述的第一与非门的第二端相连接，所述的第四反相器链的输出端与所述的第十一NMOS管的栅极相连接，所述的第十一NMOS管的源极接地，所述的第十一NMOS管的漏极与所述的第十二电阻的第一端相连接；
所述的第十一电阻的第二端与所述的第十二电阻的第二端共同构成所述的输出级驱动电路的输出端；
所述的第一与非门、第三反相器链、第二与非门及第四反相器链的电源端均与所述的参考电压相连接；
所述的第一与非门、第三反相器链、第二与非门及第四反相器链的接地端均接地。
更佳地，所述的输出级驱动电路包括第三与非门、第四与非门、第五反相器链、第六反相器链、第十二NMOS管、第十三NMOS管、第十四NMOS管、第十五NMOS管、第六PMOS管、第七PMOS管、第八PMOS管及第九PMOS管；
所述的第三与非门的第一端构成所述的输出级驱动电路的第一输入端，所述的第三与非门的输出端分别与所述的第五反相器链的输入端及所述的第四与非门的第二端相连接；
所述的第四与非门的第一端构成所述的输出级驱动电路的第二输入端，所述的第四与非门的输出端与所述的第三与非门的第二端相连接；
所述的第五反相器链的输出端分别与所述的第六反相器链的输入端、第七PMOS管的栅极及第十四NMOS管的栅极相连接；
所述的第六反相器链的输出端分别与所述的第十二NMOS管的漏极、第十三NMOS管的栅极、第六PMOS管的漏极及第八PMOS管的栅极相连接；
所述的第七PMOS管的漏极分别与所述的第十三NMOS管的漏极、第九PMOS管的栅极及第六PMOS管的栅极相连接；
所述的第十四NMOS管的漏极分别与所述的第八PMOS管的漏极、第十五NMOS管的栅极及第十二NMOS管的栅极相连接；
所述的第七PMOS管的源极、第八PMOS管的源极及第九PMOS管的源极均与所述的参考电压相连接；
所述的第十二NMOS管的源极、第十三NMOS管的源极、第十四NMOS管的源极及第十五NMOS管的源极均接地；
所述的第九PMOS管的漏极及所述的第十五NMOS管的漏极共同构成所述的输出级驱动电路的输出端；
所述的第三与非门、第四与非门、第五反相器链及第六反相器链的电源端均与所述的参考电压相连接；
所述的第三与非门、第四与非门、第五反相器链及第六反相器链的接地端均接地。
该信号整形电路加入了额外的NMOS管，提高了对输入差分信号幅度的要求，且通过在电路中设置并联的电阻与电容，使得输入的差分信号幅值需要超过一定的值，且持续一定时间，才会被认定为触发信号，将一些干扰或器件失配造成的失调噪声有效地滤除掉，采用该信号整形电路的栅极驱动电路还包括脉冲产生电路、电平移位电路、噪声滤波电路及输出级驱动电路，通过这几个电路的配合可以有效滤除失调噪声和共模噪声。采用本申请的信号整形电路及相应的栅极驱动电路，可以使得电路更可靠的工作，性能更稳定。
附图说明
图1为现有技术中的抗噪声的高侧驱动电路的原理图；
图2为图1中的抗噪声的高侧驱动电路中的噪声滤波电路的电路图；
图3为一实施例中本申请的信号整形电路的结构示意图；
图4为另一实施例中本申请的信号整形电路的结构示意图；
图5为一实施例中本申请的栅极驱动电路的原理图；
图6为一实施例中本申请的栅极驱动电路中的噪声滤波电路及输出级驱动电路的结构示意图；
图7为一实施例中本申请的栅极驱动电路中的输出级驱动电路的结构示意图。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面结合具体实施例对本申请作进一步的详细描述。
如图3所示，在一实施例中，本申请的信号整形电路，包括开启信号整形模块及关断信号整形模块；
其中，所述的开启信号整形模块包括第一PMOS管MP1、第一NMOS管MN1、第二NMOS管MN2、第一电阻R1、第二电阻R2、第一电容C1及第一反相器INV1；
所述的第一PMOS管MP1的栅极与第一输入信号Vput1相连接，所述的第一PMOS管MP1的漏极分别与所述的第一电阻R1的第一端、所述的第一电容C1的第一端及所述的第二NMOS管MN2的栅极相连接，所述的第一PMOS管MP1的源极与所述的第一NMOS管MN1的源极相连接；
所述的第一NMOS管MN1的栅极与第二输入信号Vput2相连接，所述的第一NMOS管MN1的漏极和所述的第二电阻R2的第一端均与参考电压VB相连接；
所述的第二NMOS管MN2的漏极与所述的第二电阻R2的第二端相连接，所述的第二NMOS管MN2的源极、所述的第一电阻R1的第二端及所述的第一电容C1的第二端均接地；
所述的第一反相器INV1的输入端与所述的第二电阻R2的第二端相连接，所述的第一反相器INV1的电压端与所述的参考电压VB相连接，所述的第一反相器INV1的接地端接地，所述的第一反相器INV1的输出端构成所述的信号整形电路的第一输出端；
所述的关断信号整形模块包括第二PMOS管MP2、第三NMOS管MN3、第四NMOS管MN4、第三电阻R3、第四电阻R4、第二电容C2及第二反相器INV2；
所述的第二PMOS管MP2的栅极与所述的第二输入信号Vput2相连接，所述的第二PMOS管MP2的漏极分别与所述的第三电阻R3的第一端、所述的第二电容C2的第一端及所述的第四NMOS管MN4的栅极相连接，所述的第二PMOS管MP2的源极与所述的第三NMOS管MN3的源极相连接；
所述的第三NMOS管MN3的栅极与所述的第一输入信号Vput1相连接，所述的第三NMOS管MN3的漏极和所述的第四电阻R4的第一端均与所述的参考电压VB相连接；
所述的第四NMOS管MN4的漏极与所述的第四电阻R4的第二端相连接，所述的第四NMOS管MN4的源极、所述的第三电阻R3的第二端及所述的第二电容C2的第二端均接地；
所述的第二反相器INV2的输入端与所述的第四电阻R4的第二端相连接，所述的第二反相器INV2的电压端与所述的参考电压VB相连接，所述的第二反相器INV2的接地端接地，所述的第二反相器INV2的输出端构成所述的信号整形电路的第二输出端。
如图4所示，在另一实施例中，本申请的信号整形电路在图1中的电路的基础上，在所述的开启信号整形模块中还设有第三PMOS管MP3、第五NMOS管MN5、第六NMOS管MN6及第五电阻R5；
所述的第三PMOS管MP3的栅极与所述的第二输入信号Vput2相连接，所述的第三PMOS管MP3的漏极分别与所述的第五NMOS管MN5的漏极、栅极及所述的第六NMOS管MN6的栅极相连接；所述的第三PMOS管MP3的源极通过所述的第五电阻R5与所述的参考电压VB相连接；
所述的第五NMOS管MN5的源极和第六NMOS管MN6的源极均接地；
所述的第六NMOS管MN6的漏极与所述的第一PMOS管MP1的漏极相连接；
在所述的关断信号整形模块中还设有第四PMOS管MP4、第七NMOS管MN7、第八NMOS管MN8及第六电阻R6；
所述的第四PMOS管MP4的栅极与所述的第一输入信号Vput1相连接，所述的第四PMOS管MP4的漏极分别与所述的第七NMOS管MN7的漏极、栅极及所述的第八NMOS管MN8的栅极相连接；所述的第四PMOS管MP4的源极通过所述的第六电阻 R6与所述的参考电压VB相连接；
所述的第七NMOS管MN7的源极和第八NMOS管MN8的源极均接地；
所述的第八NMOS管MN8的漏极与所述的第二PMOS管MP2的漏极相连接。
图4实施例中的信号整形电路性能优于图3实施例中的信号整形电路，图3中的电路也能根据第一输入信号Vput1及第二输入信号Vput2输出对应的信号，实现消除失调噪音的效果，但由于图3中电路仅能通过第一电阻R1及第三电阻R3提供下拉，下拉能力较弱，抗干扰性不如图4实施例中的信号整形电路。
下面结合图4中的上半部分电路对信号整形电路的工作原理进行说明：
从图4可以看出，该电路的上半部分，即开启信号整形模块，包括第一PMOS管MP1、第一NMOS管MN1、第二NMOS管MN2、第一电阻R1、第二电阻R2、第一电容C1、第一反相器INV1、第三PMOS管MP3、第五NMOS管MN5、第六NMOS管MN6及第五电阻R5；其中，第一PMOS管MP1、第一NMOS管MN1、第三PMOS管MP3、第五NMOS管MN5及第六NMOS管MN6组成信号输入级结构，第五NMOS管MN5及第六NMOS管MN6组成电流镜，第一PMOS管MP1与第三PMOS管MP3构成差分对输入结构，如图4所示，在第一PMOS管MP1上串联一第一NMOS管MN1，并在第一NMOS管MN1与第三PMOS管MP3的栅极接入相同的输入信号；
如果电路中没有第一NMOS管MN1，那么第一输入信号Vput1及第二输入信号Vput2输入，构成差分信号时，很容易被识别并传送到第二级产生输出信号；而在电路中加入第一NMOS管MN1，第一输入信号Vput1及第二输入信号Vput2的差值至少需要超过第一PMOS管MP1与第一NMOS管MN1的阈值和(假设第一NMOS管MN1的阈值为Vthn1，第一PMOS管MP1与第三PMOS管MP3的阈值均为Vthp1，那么第一PMOS管MP1与第一NMOS管MN1的阈值和为Vthn1+Vthp1)，才能使得第一PMOS管MP1和第一NMOS管MN1同时导通，而电路中还设有第一电阻R1及第一电容C1，因此，需要输入到电路中的差分信号幅值超过第一PMOS管MP1与第一NMOS管MN1的阈值和，并持续一定时间才能产生第二级的输入信号，由此，一些干扰或器件失配造成的失调噪声可以有效被滤除。
由于，关断信号整形模块的结构及工作原理与开启信号整形模块的结构与工作原理近似，因此，在此不再赘述。
图3、4中的信号整形电路的第一输出端及第二输出端均与后级噪声滤波电路相连接，在其他实施例中，上述信号整形电路也可应用于其他情况中，并与后级对应的电路相连接。
如图5所示，在包括上述信号整形电路的栅极驱动电路中，还包括：
脉冲产生电路，用于根据输入信号Vi产生开启脉冲信号Von及关闭脉冲信号Voff，该脉冲产生电路为一双脉冲产生电路，其中，开启脉冲信号Von和关闭脉冲信号Voff分别在输入信号Vi的上升沿或下降沿产生；
电平移位电路，用于将所述的开启脉冲信号Von及关闭脉冲信号Voff转换为所述的第一输入信号Vput1及第二输入信号Vput2输送给所述的信号整形电路，即将开启脉冲信号Von及关闭脉冲信号Voff转移到高电平电路侧成为第一输入信号Vput1及第二输入信号Vput2，；
在该实施例中，所述的电平移位电路包括第九NMOS管MN9及第十NMOS管MN10，且第九NMOS管MN9及第十NMOS管MN10是两个高压的NMOS管，所述的第九NMOS管MN9的栅极接所述的开启脉冲信号Von，所述的第九NMOS管MN9的源极接地，所述的第九NMOS管MN9的漏极分别与所述的第七电阻R7的第一端及第一稳压管Z1的阳极相连接，所述的第七电阻R7的第二端及所述的第一稳压管Z1的阴极均与所述的参考电压VB相连接；
所述的第九NMOS管MN9的漏极还作为所述的电平移位电路的第一输出端，输出所述的第一输入信号Vput1；
所述的第十NMOS管MN10的栅极接所述的关闭脉冲信号Voff，所述的第十NMOS管MN10的源极接地，所述的第十NMOS管MN10的漏极分别与所述的第八电阻R8的第一端及第二稳压管Z2的阳极相连接，所述的第八电阻R8的第二端及所述的第二稳压管Z2的阴极均与所述的参考电压VB相连接；
所述的第十NMOS管MN10的漏极还作为所述的电平移位电路的第二输出端，输出所述的第二输入信号Vput2；
该电平移位电路的工作原理为：
当第九NMOS管MN9导通时，产生下拉电流通过第七电阻R7，产生相对于参考电压VB的电压信号——第一输入信号Vput1，当第十NMOS管MN10导通时，产生下拉电流通过第八电阻R8，产生相对于参考电压VB的电压信号——第二输入信号Vput2，第一稳压管Z1及第二稳压管Z2用于箝位，防止第一输入信号Vput1和第二输入信号Vput2相对于参考电压VB下降太多，损害电路。
噪声滤波电路，用于进一步消除所述的信号整形电路输出的信号中的短脉冲噪声；
在该实施例中，所述的噪声滤波电路包括第一反相器链、第九电阻R9、第三电容C3、第一施密特触发器SIMT1、第二反相器链、第十电阻R10、第四电容C4及第二施密特触发器SIMT2；
所述的第一反相器链的输入端与所述的信号整形电路的第一输出端相连接，所述的第一反相器链的输出端与所述的第九电阻R9的第一端相连接，所述的第九电阻R9的第二端分别与所述的第三电容C3的第一端及所述的第一施密特触发器SIMT1的输入端相连接，所述的第三电容C3的第二端接地，所述的第一施密特触发器SIMT1的输出端构成所述的噪声滤波电路的第一输出端，并与所述的输出级驱动电路的第一输入端相连接；
所述的第二反相器链的输入端与所述的信号整形电路的第二输出端相连接，所述的第二反相器链的输出端与所述的第十电阻R10的第一端相连接，所述的第十电阻R10的第二端分别与所述的第四电容C4的第一端及所述的第二施密特触发器SIMT2的输入端相连接，所述的第四电容C4的第二端接地，所述的第二施密特触发器SIMT2的输出端构成所述的噪声滤波电路的第二输出端，并与所述的输出级驱动电路的第二输入端相连接；
所述的第一反相器链、第二反相器及第一施密特触发器SIMT1的电源端均与所述的参考电压VB相连接；
所述的第一反相器链、第二反相器及第一施密特触发器SIMT1的接地端均接地。
在该实施例中的噪声滤波电路中，通过第九电阻R9与第三电容C3(第十电阻R10与第四电容C4)组成滤波电路，对前级信号整形电路输出的信号进行进一步地滤波，消除短脉冲噪声信号。
输出级驱动电路与所述的噪声滤波电路相连接，并输出栅极驱动信号OUT；
在该实施例中，所述的输出级驱动电路包括第一与非门NAND1、第三反相器链、第五PMOS管MP5、第十一电阻R11、第二与非门NAND2、第四反相器链、第十一NMOS管MN11及第十二电阻R12；
所述的第一与非门NAND1的第一端构成所述的输出级驱动电路的第一输入端，所述的第一与非门NAND1的输出端分别与所述的第三反相器链的输入端及所述的第二与非门NAND2的第二端相连接，所述的第三反相器链的输出端与所述的第五PMOS管MP5的栅极相连接，所述的第五PMOS管MP5的源极与所述的参考电压VB相连接，所述的第五PMOS管MP5的漏极与所述的第十一电阻R11的第一端相连接；
所述的第二与非门NAND2的第一端构成所述的输出级驱动电路的第二输入端，所述的第二与非门NAND2的输出端分别与所述的第四反相器链的输入端及所述的第一与非门NAND1的第二端相连接，所述的第四反相器链的输出端与所述的第十一NMOS管MN11的栅极相连接，所述的第十一NMOS管MN11的源极接地，所述的第十一NMOS管MN11的漏极与所述的第十二电阻R12的第一端相连接；
所述的第十一电阻R11的第二端与所述的第十二电阻R12的第二端共同构成所述的输出级驱动电路的输出端；
所述的第一与非门NAND1、第三反相器链、第二与非门NAND2及第四反相器链的电源端均与所述的参考电压VB相连接；
所述的第一与非门NAND1、第三反相器链、第二与非门NAND2及第四反相器链的接地端均接地。
该电路中通过第一与非门NAND1、第二与非门NAND2组成RS触发可以有效锁定并保存有效的脉冲输入信号，经过后级第五PMOS管、第十一NMOS管、第十一电阻R11及第十二电阻R12产生最终的栅极驱动信号OUT。
该实施例中的噪声滤波电路与输出级驱动电路的结构可参阅图6所示，其中，第一反相器链、第二反相器链、第三反相器链及第四反相器链均可由级联的反相器构成，图6中的噪声滤波电路中的A、B两端分别与图3或图4中的A、B两端对应连接。
在另一实施例中，所述的输出级驱动电路也可由图7中的电路沟槽，其包括第三与非门NAND3、第四与非门NAND4、第五反相器链、第六反相器链、第十二NMOS管MN12、第十三NMOS管MN13、第十四NMOS管MN14、第十五NMOS管MN15、第六PMOS管MP6、第七PMOS管MP7、第八PMOS管MP8及第九PMOS管MP9；
所述的第三与非门NAND3的第一端构成所述的输出级驱动电路的第一输入端，所述的第三与非门NAND3的输出端分别与所述的第五反相器链的输入端及所述的第四与非门NAND4的第二端相连接；
所述的第四与非门NAND4的第一端构成所述的输出级驱动电路的第二输入端，所述的第四与非门NAND4的输出端与所述的第三与非门NAND3的第二端相连接；
所述的第五反相器链的输出端分别与所述的第六反相器链的输入端、第七PMOS 管MP7的栅极及第十四NMOS管MN14的栅极相连接；
所述的第六反相器链的输出端分别与所述的第十二NMOS管MN12的漏极、第十三NMOS管MN13的栅极、第六PMOS管MP6的漏极及第八PMOS管MP8的栅极相连接；
所述的第七PMOS管MP7的漏极分别与所述的第十三NMOS管MN13的漏极、第九PMOS管MP9的栅极及第六PMOS管MP6的栅极相连接；
所述的第十四NMOS管MN14的漏极分别与所述的第八PMOS管MP8的漏极、第十五NMOS管MN15的栅极及第十二NMOS管MN12的栅极相连接；
所述的第七PMOS管MP7的源极、第八PMOS管MP8的源极及第九PMOS管MP9的源极均与所述的参考电压VB相连接；
所述的第十二NMOS管MN12的源极、第十三NMOS管MN13的源极、第十四NMOS管MN14的源极及第十五NMOS管MN15的源极均接地；
所述的第九PMOS管MP9的漏极及所述的第十五NMOS管MN15的漏极共同构成所述的输出级驱动电路的输出端；
所述的第三与非门NAND3、第四与非门NAND4、第五反相器链及第六反相器链的电源端均与所述的参考电压VB相连接；
所述的第三与非门NAND3、第四与非门NAND4、第五反相器链及第六反相器链的接地端均接地；
其中，第五反相器链及第六反相器链均可由级联的反相器构成。
该实施例中的输出级驱动电路分别对第九PMOS管MP9和第十五NMOS管MN9进行控制，可避免穿通电流损害输出级电路，并利用两级反相器链(第五反相器链即第六反相器链)产生极短的死区时间，且通过第六PMOS管MP6和第十二NMOS管MN12起到箝位作用，避免输出级电路中的器件的栅极驱动信号出现交叉而带来穿通电流导致器件损坏的问题，在保证可靠性的同时有极小的传输延时，电路噪声小，该控制电路可以适应不同的应用环境，可靠性高。
该实施例中的栅极驱动电路可针对高压栅驱动电路共模噪声处理的不足，实现抗噪声干扰，并降低失调噪声的影响，使得电路更可靠的工作，且该电路结构简单、性能稳定，适应性强。
该信号整形电路加入了额外的NMOS管，提高了对输入差分信号幅度的要求，且通过在电路中设置并联的电阻与电容，使得输入的差分信号幅值需要超过一定的值，且持续一定时间，才会被认定为触发信号，将一些干扰或器件失配造成的失调噪声有效地滤除掉，采用该信号整形电路的栅极驱动电路还包括脉冲产生电路、电平移位电路、噪声滤波电路及输出级驱动电路，通过这几个电路的配合可以有效滤除失调噪声和共模噪声。采用本申请的信号整形电路及相应的栅极驱动电路，可以使得电路更可靠的工作，性能更稳定。
在此说明书中，本申请已参照其特定的实施例作了描述。但是，很显然仍可以作出各种修改和变换而不背离本申请的精神和范围。因此，说明书和附图应被认为是说明性的而非限制性的。

Claims (8)

  1. 一种信号整形电路，其特征在于，包括开启信号整形模块及关断信号整形模块；
    其中，所述的开启信号整形模块包括第一PMOS管、第一NMOS管、第二NMOS管、第一电阻、第二电阻、第一电容及第一反相器；
    所述的第一PMOS管的栅极与第一输入信号相连接，所述的第一PMOS管的漏极分别与所述的第一电阻的第一端、所述的第一电容的第一端及所述的第二NMOS管的栅极相连接，所述的第一PMOS管的源极与所述的第一NMOS管的源极相连接；
    所述的第一NMOS管的栅极与第二输入信号相连接，所述的第一NMOS管的漏极和所述的第二电阻的第一端均与参考电压相连接；
    所述的第二NMOS管的漏极与所述的第二电阻的第二端相连接，所述的第二NMOS管的源极、所述的第一电阻的第二端及所述的第一电容的第二端均接地；
    所述的第一反相器的输入端与所述的第二电阻的第二端相连接，所述的第一反相器的电压端与所述的参考电压相连接，所述的第一反相器的接地端接地，所述的第一反相器的输出端构成所述的信号整形电路的第一输出端；
    所述的关断信号整形模块包括第二PMOS管、第三NMOS管、第四NMOS管、第三电阻、第四电阻、第二电容及第二反相器；
    所述的第二PMOS管的栅极与所述的第二输入信号相连接，所述的第二PMOS管的漏极分别与所述的第三电阻的第一端、所述的第二电容的第一端及所述的第四NMOS管的栅极相连接，所述的第二PMOS管的源极与所述的第三NMOS管的源极相连接；
    所述的第三NMOS管的栅极与所述的第一输入信号相连接，所述的第三NMOS管的漏极和所述的第四电阻的第一端均与所述的参考电压相连接；
    所述的第四NMOS管的漏极与所述的第四电阻的第二端相连接，所述的第四NMOS管的源极、所述的第三电阻的第二端及所述的第二电容的第二端均接地；
    所述的第二反相器的输入端与所述的第四电阻的第二端相连接，所述的第二反相器的电压端与所述的参考电压相连接，所述的第二反相器的接地端接地，所述的第二反相器的输出端构成所述的信号整形电路的第二输出端。
  2. 根据权利要求1所述的信号整形电路，其特征在于，
    所述的开启信号整形模块还包括第三PMOS管、第五NMOS管、第六NMOS管及第五电阻；
    所述的第三PMOS管的栅极与所述的第二输入信号相连接，所述的第三PMOS管的漏极分别与所述的第五NMOS管的漏极、栅极及所述的第六NMOS管的栅极相连接；所述的第三PMOS管的源极通过所述的第五电阻与所述的参考电压相连接；
    所述的第五NMOS管的源极和第六NMOS管的源极均接地；
    所述的第六NMOS管的漏极与所述的第一PMOS管的漏极相连接；
    所述的关断信号整形模块还包括第四PMOS管、第七NMOS管、第八NMOS管及第六电阻；
    所述的第四PMOS管的栅极与所述的第一输入信号相连接，所述的第四PMOS管的漏极分别与所述的第七NMOS管的漏极、栅极及所述的第八NMOS管的栅极相连 接；所述的第四PMOS管的源极通过所述的第六电阻与所述的参考电压相连接；
    所述的第七NMOS管的源极和第八NMOS管的源极均接地；
    所述的第八NMOS管的漏极与所述的第二PMOS管的漏极相连接。
  3. 一种具有权利要求1或2中所述的信号整形电路的栅极驱动电路，其特征在于，所述的栅极驱动电路还包括：
    脉冲产生电路，用于根据输入信号产生开启脉冲信号及关闭脉冲信号；
    电平移位电路，用于将所述的开启脉冲信号及关闭脉冲信号转换为所述的第一输入信号及第二输入信号输送给所述的信号整形电路；
    噪声滤波电路，用于进一步消除所述的信号整形电路输出的信号中的短脉冲噪声；
    输出级驱动电路与所述的噪声滤波电路相连接。
  4. 根据权利要求3所述的栅极驱动电路，其特征在于，所述的电平移位电路包括第九NMOS管及第十NMOS管，
    所述的第九NMOS管的栅极接所述的开启脉冲信号，所述的第九NMOS管的源极接地，所述的第九NMOS管的漏极通过第七电阻与所述的参考电压相连接；
    所述的第九NMOS管的漏极还作为所述的电平移位电路的第一输出端，输出所述的第一输入信号；
    所述的第十NMOS管的栅极接所述的关闭脉冲信号，所述的第十NMOS管的源极接地，所述的第十NMOS管的漏极通过第八电阻与所述的参考电压相连接；
    所述的第十NMOS管的漏极还作为所述的电平移位电路的第二输出端，输出所述的第二输入信号。
  5. 根据权利要求4所述的栅极驱动电路，其特征在于，所述的电平移位电路还包括第一稳压二极管及第二稳压二极管；
    所述的第一稳压二极管的阳极与所述的第九NMOS管的漏极相连接，所述的第一稳压二极管的阴极与所述的参考电压相连接；
    所述的第二稳压二极管的阳极与所述的第十NMOS管的漏极相连接，所述的第二稳压二极管的阴极与所述的参考电压相连接。
  6. 根据权利要求3所述的栅极驱动电路，其特征在于，所述的噪声滤波电路包括第一反相器链、第九电阻、第三电容、第一施密特触发器、第二反相器链、第十电阻、第四电容及第二施密特触发器；
    所述的第一反相器链的输入端与所述的信号整形电路的第一输出端相连接，所述的第一反相器链的输出端与所述的第九电阻的第一端相连接，所述的第九电阻的第二端分别与所述的第三电容的第一端及所述的第一施密特触发器的输入端相连接，所述的第三电容的第二端接地，所述的第一施密特触发器的输出端构成所述的噪声滤波电路的第一输出端，并与所述的输出级驱动电路的第一输入端相连接；
    所述的第二反相器链的输入端与所述的信号整形电路的第二输出端相连接，所述的第二反相器链的输出端与所述的第十电阻的第一端相连接，所述的第十电阻的第二端分别与所述的第四电容的第一端及所述的第二施密特触发器的输入端相连接，所述的第四电容的第二端接地，所述的第二施密特触发器的输出端构成所述的噪声滤波电路的第二输出端，并与所述的输出级驱动电路的第二输入端相连接；
    所述的第一反相器链、第二反相器及第一施密特触发器的电源端均与所述的参考电压相连接；
    所述的第一反相器链、第二反相器及第一施密特触发器的接地端均接地。
  7. 根据权利要求6所述的栅极驱动电路，其特征在于，所述的输出级驱动电路包括第一与非门、第三反相器链、第五PMOS管、第十一电阻、第二与非门、第四反相器链、第十一NMOS管及第十二电阻；
    所述的第一与非门的第一端构成所述的输出级驱动电路的第一输入端，所述的第一与非门的输出端分别与所述的第三反相器链的输入端及所述的第二与非门的第二端相连接，所述的第三反相器链的输出端与所述的第五PMOS管的栅极相连接，所述的第五PMOS管的源极与所述的参考电压相连接，所述的第五PMOS管的漏极与所述的第十一电阻的第一端相连接；
    所述的第二与非门的第一端构成所述的输出级驱动电路的第二输入端，所述的第二与非门的输出端分别与所述的第四反相器链的输入端及所述的第一与非门的第二端相连接，所述的第四反相器链的输出端与所述的第十一NMOS管的栅极相连接，所述的第十一NMOS管的源极接地，所述的第十一NMOS管的漏极与所述的第十二电阻的第一端相连接；
    所述的第十一电阻的第二端与所述的第十二电阻的第二端共同构成所述的输出级驱动电路的输出端；
    所述的第一与非门、第三反相器链、第二与非门及第四反相器链的电源端均与所述的参考电压相连接；
    所述的第一与非门、第三反相器链、第二与非门及第四反相器链的接地端均接地。
  8. 根据权利要求6所述的栅极驱动电路，其特征在于，所述的输出级驱动电路包括第三与非门、第四与非门、第五反相器链、第六反相器链、第十二NMOS管、第十三NMOS管、第十四NMOS管、第十五NMOS管、第六PMOS管、第七PMOS管、第八PMOS管及第九PMOS管；
    所述的第三与非门的第一端构成所述的输出级驱动电路的第一输入端，所述的第三与非门的输出端分别与所述的第五反相器链的输入端及所述的第四与非门的第二端相连接；
    所述的第四与非门的第一端构成所述的输出级驱动电路的第二输入端，所述的第四与非门的输出端与所述的第三与非门的第二端相连接；
    所述的第五反相器链的输出端分别与所述的第六反相器链的输入端、第七PMOS管的栅极及第十四NMOS管的栅极相连接；
    所述的第六反相器链的输出端分别与所述的第十二NMOS管的漏极、第十三NMOS管的栅极、第六PMOS管的漏极及第八PMOS管的栅极相连接；
    所述的第七PMOS管的漏极分别与所述的第十三NMOS管的漏极、第九PMOS管的栅极及第六PMOS管的栅极相连接；
    所述的第十四NMOS管的漏极分别与所述的第八PMOS管的漏极、第十五NMOS管的栅极及第十二NMOS管的栅极相连接；
    所述的第七PMOS管的源极、第八PMOS管的源极及第九PMOS管的源极均与所 述的参考电压相连接；
    所述的第十二NMOS管的源极、第十三NMOS管的源极、第十四NMOS管的源极及第十五NMOS管的源极均接地；
    所述的第九PMOS管的漏极及所述的第十五NMOS管的漏极共同构成所述的输出级驱动电路的输出端；
    所述的第三与非门、第四与非门、第五反相器链及第六反相器链的电源端均与所述的参考电压相连接；
    所述的第三与非门、第四与非门、第五反相器链及第六反相器链的接地端均接地。
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CN115328246A (zh) * 2022-08-12 2022-11-11 苏州大学 一种快速建立的低噪声基准电压源电路
CN115328246B (zh) * 2022-08-12 2023-09-29 苏州大学 一种快速建立的低噪声基准电压源电路
CN116827330A (zh) * 2022-12-12 2023-09-29 南京微盟电子有限公司 强抗干扰通讯端口电路
CN116827330B (zh) * 2022-12-12 2024-03-12 南京微盟电子有限公司 强抗干扰通讯端口电路
CN116346120A (zh) * 2023-05-29 2023-06-27 无锡市晶源微电子股份有限公司 电平转换电路
CN116346120B (zh) * 2023-05-29 2023-10-13 无锡市晶源微电子股份有限公司 电平转换电路
CN117498854A (zh) * 2023-09-20 2024-02-02 北京芯可鉴科技有限公司 Igbt驱动电路及芯片
CN117477918A (zh) * 2023-12-27 2024-01-30 成都氮矽科技有限公司 驱动信号输入检测电路、GaN栅驱动器和MOSFET栅驱动器
CN117477918B (zh) * 2023-12-27 2024-03-29 成都氮矽科技有限公司 驱动信号输入检测电路、GaN栅驱动器和MOSFET栅驱动器

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