WO2014171190A1 - レベルシフト回路 - Google Patents
レベルシフト回路 Download PDFInfo
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- WO2014171190A1 WO2014171190A1 PCT/JP2014/054837 JP2014054837W WO2014171190A1 WO 2014171190 A1 WO2014171190 A1 WO 2014171190A1 JP 2014054837 W JP2014054837 W JP 2014054837W WO 2014171190 A1 WO2014171190 A1 WO 2014171190A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
- H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
- H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
- H03K3/35613—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration
Definitions
- the present invention relates to a level shift circuit, and converts a voltage level of a control signal for controlling a switching element such as a MOSFET, IGBT, SiCFET, GaNFET or the like mainly used in an inverter circuit to a level appropriate for the control. It relates to the circuit to do.
- a switching element such as a MOSFET, IGBT, SiCFET, GaNFET or the like mainly used in an inverter circuit to a level appropriate for the control. It relates to the circuit to do.
- inverter systems that can be controlled with a high degree of microcontroller are widely used to improve energy-saving performance.
- wide band gap semiconductor devices such as SiCFET and GaNFET, their application to inverter circuits is being studied with the aim of improving efficiency by their low on-resistance and high-frequency characteristics.
- FIG. 6 shows a circuit configuration example of a conventional inverter circuit.
- FIG. 6 shows a configuration example of the inverter circuit INV including the driver circuit 30, the power switching elements 7 a and 7 b of the n-type MOSFET, the diode 8, and the capacitor 9.
- the driver circuit 30 has a function of a level shift circuit.
- the driver circuit 30 includes an external power supply terminal VCC and a ground terminal VSS, a control input terminal Inh on the high side circuit 36 side, a control input terminal Inl on the low side circuit, a positive voltage power supply terminal Vb on the high side circuit 36 side, and a reference.
- a power supply terminal Vs, an output terminal Vh, and a low-side output terminal Vl are provided.
- the power supply terminal VCC and the ground terminal VSS of the driver circuit 30 are connected to the power supply terminal VCC and the ground terminal VSS of the inverter circuit INV, respectively.
- the control input signal on the high-side circuit 36 side input from the control input terminal Inh is connected to the input terminal IN of the pulse generating circuit 31, and the first output terminal OUT1 has a first pulse width of about 100 ns after the rise of the control input signal.
- a second pulse having a pulse width of about 100 ns is generated after the control input signal falls from the second output terminal OUT2.
- FIG. 7 shows a circuit configuration example of the pulse generation circuit 31.
- the pulse generation circuit 31 includes six inverters 41a, 41b, 41c, 41d, 41e, and 41f cascaded, two NAND circuits 42a and 42b, two inverters 43a and 43b, and two pulse width setting terminals. Capacitors 44a and 44b are provided.
- the capacitor 44a 44b When the input of the first inverter 41a is connected to the input terminal IN and the output nodes of the inverters 41a, 41b, 41c, 41d, 41e, and 41f are N1, N2, N3, N4, N5, and N6 in order from the front, the capacitor 44a 44b are grounded, the other ends are connected to nodes N3 and N4, nodes N2 and N5 are connected to two inputs of the NAND circuit 42a, and nodes N1 and N6 are connected to the two inputs of the NAND circuit 42b.
- the outputs of the NAND circuits 42a and 42b are connected to the inputs of the inverters 43a and 43b, respectively, and the outputs of the inverters 43a and 43b are connected to the output terminals OUT1 and OUT2, respectively.
- FIG. 8 shows an operation waveform of the pulse generation circuit 31.
- a first pulse synchronized with the rising edge of the control input signal input to the input terminal IN is output from the first output terminal OUT1, and a second pulse synchronized with the falling edge is output from the second output terminal OUT2.
- the first pulse is input to the gate of the n-type high voltage MOSFET 32a, converted to a signal level-shifted by the resistor 33a, and input to the reset input R of the RS flip-flop 34.
- the second pulse is input to the gate of the n-type high voltage MOSFET 32b, converted into a signal level-shifted by the resistor 33b, and input to the set input S of the RS flip-flop 34.
- the output Q of the RS flip-flop 34 is connected to the input of the inverter 35, and the output of the inverter 35 is connected to the gate of the MOSFET 7a via the output terminal Vh.
- control input signal input to the control input terminal Inh is level-shifted and transmitted to the floating high side circuit 36, and is output to the gate of the MOSFET 7a as a high side output signal.
- control input signal on the low side input to the control input terminal Inl on the low side is output to the gate terminal of the MOSFET 7b via the output terminal Vl on the low side.
- a high voltage power supply of about 600 V, for example, is connected to the drain of the MOSFET 7a via a high voltage power supply terminal HV of the inverter circuit INV.
- the source of the MOSFET 7a and the drain of the MOSFET 7b are connected to the reference power supply terminal Vs of the driver circuit 30 and the output terminal OUT of the inverter circuit INV, respectively.
- the source of the MOSFET 7b is connected to the output ground terminal GND of the inverter circuit INV and grounded.
- the capacitor 9 has one end connected to the cathode terminal of the diode 8 and the positive voltage power supply terminal Vb, the other end connected to the reference power supply terminal Vs, and the anode terminal of the diode 8 connected to the power supply terminal VCC.
- the diode 8 and the capacitor 9 constitute a bootstrap circuit.
- the output terminal OUT of the inverter circuit INV connected to the reference power supply terminal Vs is connected to the power supply terminal HV of the inverter circuit INV.
- an output signal having an amplitude of a high voltage applied between the ground terminal GND and the ground terminal GND is input to the two control input terminals Inh and Inl.
- the use of the pulse generation circuit 31 and the RS flip-flop 34 is limited in the power supplied to the capacitor 9 by the bootstrap circuit, and the power consumption in the high side circuit 36 is reduced as much as possible. This is to suppress and maintain the output capability of the inverter 35.
- Patent Document 1 proposes a circuit configuration in which a filter by a logic circuit is installed before the RS flip-flop to prevent malfunction due to noise.
- a resistor for generating an input signal of the power switching element driving circuit is provided.
- a series circuit of n-type MOSFETs a method is proposed in which a resistor and an n-type MOSFET are each surrounded by a double isolation oxide film, and the potential of the Si active layer sandwiched between the double isolation oxide films is separately supplied. ing. Specifically, by this method, the voltage drop of the resistor is reduced when the time differentiation (dv / dt) of the low level power supply potential of the power switching element driving circuit connected to the source of the upper arm power switching element is generated. Thus, malfunction of the level shift circuit is suppressed.
- the constant current is allowed to flow so that a voltage difference corresponding to the input signal level is formed between the non-inverting input and the inverting input of the comparator and boosted by the bootstrap circuit.
- a phenomenon may occur in which a high voltage is temporarily divided and applied. As a result, due to this phenomenon, a high voltage is temporarily applied to the constant current generation circuit, and noise may be temporarily superimposed on the differential input between the non-inverting input and the inverting input of the comparator. There is a problem that the high-side circuit cannot control the power switching element.
- an object of the present invention is to provide a highly reliable level shift circuit with a low possibility of malfunction due to noise.
- a reverse phase input signal having a phase opposite to an input signal is input to a control terminal, and the amount of current flowing between the first and second terminals is controlled by the voltage of the control terminal.
- 1 current control element the input signal or an in-phase input signal in phase with the input signal is input to the control terminal, and the amount of current flowing between the first and second terminals is controlled by the voltage of the control terminal
- a first load circuit for generating a voltage drop according to the amount of current flowing between the terminals, one end of which is connected to the high-side power supply terminal and the other end is connected to the first terminal of the first current control element;
- a second load circuit having one end connected to the high-side power supply terminal and the other end connected to the first terminal of the second current control element, and generating a voltage drop corresponding to the amount of current flowing between the two terminals;
- One current output terminal of the first current control element The second current output terminal is connected to the second terminal of the second current control element, and the current flowing through the first current control element
- One of the pair of differential input terminals is connected to the first terminal of the first current control element, and the other of the pair of differential input terminals is the first of the second current control element.
- a comparator connected to one terminal, supplied with a power supply voltage from the high-side power supply terminal, supplied with a reference voltage from the high-side reference terminal, and generates an output signal according to a voltage difference between the pair of differential input terminals
- a voltage suppression circuit that is connected to each of the first and second current output terminals separately or in common and suppresses a voltage increase of each of the first and second current output terminals.
- a level shift circuit is provided.
- the voltage suppression circuit is configured by a two-terminal circuit, and one end of the two-terminal circuit is connected to the first and second current output terminals separately or in common, and the 2 A two-terminal switching element or a two-terminal switching circuit that is connected to a predetermined fixed potential at the other end of the terminal circuit and becomes conductive when an inter-terminal voltage exceeds a predetermined voltage between the one end and the other end of the two-terminal circuit.
- a capacitance element having a larger capacitance than each inter-terminal capacitance between the first terminal and the second terminal of the first and second current control elements is connected to one end of the two-terminal circuit. It is preferable to have at least one of the second circuit structures.
- the voltage suppression circuit is a circuit composed of a single Zener diode or a series circuit of a plurality of Zener diodes, a circuit composed of a single diode or a series circuit of a plurality of diodes, a diode and a voltage source.
- a circuit comprising a series circuit of the first, second current control element, a circuit comprising a capacitor element for voltage suppression having a larger capacitance than the inter-terminal capacitance between the first terminal and the second terminal of the first and second current control elements, and the voltage suppression And at least one of a circuit comprising a series circuit of a capacitive element and a resistive element, and a circuit comprising a parallel circuit of a diode and a resistive element and a series circuit of the voltage-suppressing capacitive element. It is preferable.
- the level shift circuit having the above characteristics includes a circuit power supply terminal for receiving a power supply voltage for circuit operation from the outside, a diode between the circuit power supply terminal and the high-side power supply terminal, and the high-side power supply terminal and the high-side power supply terminal.
- a capacitive element is provided between the side reference terminals, and the high side reference terminal and the output terminal of the high voltage circuit driven by the output signal are electrically connected.
- the first and second current control elements are each constituted by a high voltage MOSFET, the control terminal of the first and second current control elements is the gate of the MOSFET, and the first It is preferable that the first terminal and the second terminal of the first and second current control elements are a drain and a source of the MOSFET.
- the current generation circuit includes a plurality of low withstand voltage current control elements, and each of the plurality of low withstand voltage current control elements includes a first terminal, a second terminal, and a control terminal.
- the amount of current flowing between the first and second terminals is controlled by the voltage of the control terminal, and the withstand voltage between the first and second terminals is controlled by the first and second current control elements.
- One of the plurality of low withstand voltage current control elements is lower than the withstand voltage between the second terminals, and the first terminal of the plurality of low withstand voltage current control elements is connected to the first current output terminal. This is particularly suitable when one of the first terminals is connected to the second current output terminal.
- the terminal voltages of the high-side power supply terminal and the high-side reference terminal change so as to follow the change in the output level of the high-voltage circuit driven by the output signal. It is preferable to be configured.
- the high side circuit constituted by the first and second load circuits and the comparator is in a floating state with respect to the reference voltage (ground voltage) of the level shift circuit, and the first and second currents.
- an external bootstrap circuit is configured with a power switching element driven by the output signal.
- a high voltage supplied to the high voltage circuit is applied to the high side power supply terminal, and the level is shifted to a signal level necessary for driving the high voltage circuit.
- the divided high voltage is supplied from the high-side power supply terminal to each current output terminal of the current generation circuit via the first and second load circuits and the first and second current control elements. Will be applied.
- each current output terminal is provided with a voltage suppression circuit that suppresses the voltage rise at the terminal, the application of the divided high voltage is suppressed.
- a malfunction can be prevented in advance, so that a possibility of malfunction due to noise is low, and a highly reliable level shift circuit can be provided.
- FIG. 1 is a circuit diagram showing a circuit configuration example of a level shift circuit according to the present invention.
- Voltage waveform diagram showing changes in main terminal voltages when no voltage suppression circuit is provided in the circuit operation of the level shift circuit shown in FIG.
- the circuit diagram which shows the circuit structural example of the 1st circuit structure of the voltage suppression circuit shown in FIG.
- the circuit diagram which shows the circuit structural example of the 2nd circuit structure of the voltage suppression circuit shown in FIG.
- Circuit diagram showing another circuit configuration example of the level shift circuit according to the present invention
- Circuit diagram showing a circuit configuration example of a pulse generation circuit used in the conventional level shift circuit shown in FIG.
- FIG. 7 is a signal waveform diagram of the input signal and the first and second pulses showing the operation of the pulse generation circuit shown in FIG.
- the present invention circuit As appropriate, embodiments of a level shift circuit according to the present invention (hereinafter referred to as “the present invention circuit” as appropriate) will be described with reference to the drawings.
- the present invention circuit In the circuit of the present invention described in each of the following embodiments, elements that are the same as those of the conventional inverter circuit illustrated in FIG. To explain.
- FIG. 1 shows an example of the circuit configuration of the circuit of the present invention.
- the circuit 1 of the present invention includes a high-side circuit 2, a current generation circuit 3, two inverters 11a and 11b, a pair of n-type high voltage MOSFETs 12a and 12b (corresponding to first and second current control elements), and a pair of The voltage suppression circuits 15a and 15b, n-type high breakdown voltage MOSFETs 7a and 7b, a diode 8, and a capacitor 9 are provided.
- the basic part of the circuit 1 of the present invention is composed of a high side circuit 2, a current generating circuit 3, two inverters 11a and 11b, and a pair of n-type high voltage MOSFETs 12a and 12b. .
- the high side circuit 2 includes a high side power supply terminal Vb, a high side reference terminal Vs, a high side output terminal Vh, a pair of resistance elements 13a and 13b (corresponding to first and second load circuits), and a comparator 14. Configured. One end of each of the resistance elements 13a and 13b is connected to the high side power supply terminal Vb, the other end of the resistance element 13a is connected to the non-inverting input terminal Np of the comparator 14, and the other end of the resistance element 13b is inverted of the comparator 14. It is connected to the input terminal Nn.
- the comparator 14 is supplied with the power supply voltage from the high-side power supply terminal Vb, is supplied with the reference voltage from the high-side reference terminal Vs, and the high-side output terminal according to the voltage difference between the non-inverting input terminal Np and the inverting input terminal Nn. A high-side output signal level-shifted from Vh is output. Since the comparator 14 is a differential circuit having a non-inverting input terminal Np and an inverting input terminal Nn as a pair of differential input terminals, the comparator 14 has a high common-mode signal rejection ratio against common-mode noise caused by dv / dt. High resistance to malfunction caused by noise.
- the current generation circuit 3 includes a constant current circuit 4 and n-type MOSFETs 10a, 10b, and 10c.
- One end of the constant current circuit 4 is connected to, for example, the circuit power supply terminal VCC, and the other end of the constant current circuit 4 and the gates of the MOSFETs 10a, 10b, and 10c are connected to the drain of the MOSFET 10a.
- the sources of the MOSFETs 10a, 10b, and 10c are connected to the circuit reference terminal VSS.
- the drain of the MOSFET 10b is connected to the first current output terminal Na, and the drain of the MOSFET 10c is connected to the second current output terminal Nb.
- the n-type MOSFETs 10a and 10b constitute a first current mirror circuit
- the n-type MOSFETs 10a and 10c constitute a second current mirror circuit, which is substantially the same as the current Is supplied from the constant current circuit 4.
- Current flows from the first and second current output terminals Na and Nb to the circuit reference terminal VSS via the MOSFETs 10b and 10c, respectively.
- the input of the inverter 11a is connected to the control input terminal Inh
- the output of the inverter 11a is connected to the input of the inverter 11b and the gate of the MOSFET 12a
- the output of the inverter 11b is connected to the gate of the MOSFET 12b.
- the drain of the MOSFET 12a is connected to the other end of the resistance element 13a and the non-inverting input terminal Np of the comparator 14, and the drain of the MOSFET 12b is connected to the other end of the resistance element 13b and the inverting input terminal Nn of the comparator 14, and the source of the MOSFET 12a Is connected to the first current output terminal Na, and the source of the MOSFET 12b is connected to the second current output terminal Nb.
- the pair of n-type MOSFETs 12a and 12b and the pair of resistance elements 13a and 13b have the same electrical characteristics between the paired elements.
- the resistance elements 13a and 13b are elements that cause a voltage drop due to current flow, the material and the element structure are not limited, and the resistance elements 13a and 13b do not necessarily have to be single elements.
- the circuit power supply terminal VCC is connected to the positive electrode of the voltage source 5 for supplying the power supply voltage Vcc for operating the low voltage circuit to the circuit 1 of the present invention.
- the drain of the high voltage MOSFET 7a is connected to the positive electrode of the high voltage source 6 that supplies the high power supply voltage Vhh, and the source of the high voltage MOSFET 7a is connected to the drain of the high voltage MOSFET 7b to form a high voltage output terminal OUT.
- a high-side output signal output from the high-side output terminal Vh is input to the gate of the high-voltage MOSFET 7a, and a low-side input signal SIL having a phase opposite to that of the high-side input signal SIH is input to the gate of the high-voltage MOSFET 7b.
- the high voltage output terminal OUT and the high side reference terminal Vs are connected, and the voltage level of the high side reference terminal Vs changes following the output voltage level output from the high voltage output terminal OUT. That is, the high side circuit 2 is a floating circuit in which the reference voltage level changes as viewed from the circuit reference terminal VSS.
- the anode of the diode 8 is connected to the circuit power supply terminal VCC, the cathode of the diode 8 and one end of the capacitor 9 are connected to the high side power supply terminal Vb, and the other end of the capacitor 9 is connected to the high side reference terminal Vs. Is done.
- the terminal voltage of the high side power supply terminal Vb is supplied from the circuit power supply terminal VCC via the diode 8 when the output voltage level output from the high voltage output terminal OUT is low.
- the terminal voltage of the high side reference terminal Vs similarly transitions, and the terminal voltage of the high side power supply terminal Vb follows the change in the output voltage level via the capacitor 9.
- the voltage is boosted beyond the terminal voltage of the circuit power supply terminal VCC.
- the boosted terminal voltage of the high side power supply terminal Vb is not discharged to the circuit power supply terminal VCC side by the diode 8 in the reverse bias state, and the high voltage state is maintained. Further, since the boosted terminal voltage of the high-side power supply terminal Vb is supplied to the comparator 14 as a power supply voltage, the output level of the high-side output signal output from the high-side output terminal Vh is also boosted.
- the high side circuit 2 is configured as a floating circuit, so that the gate voltage of the high voltage MOSFET 7a can be driven to a sufficiently high voltage in cooperation with the bootstrap circuit.
- the pair of voltage suppression circuits 15a and 15b suppress the excessive increase of the terminal voltages of the first and second current output terminals Na and Nb of the current generation circuit 3 during the circuit operation. This prevents excessive stress from being applied to the MOSFETs 10b and 10c connected to the current output terminals Na and Nb. Details of the voltage suppression circuits 15a and 15b will be described later.
- the circuit operation of the circuit 1 of the present invention will be described.
- the operation when there is no pair of voltage suppression circuits 15a and 15b will be described with reference to the voltage waveform diagram shown in FIG. In FIG. 2, in order from the top, the high-side input signal SIH, the low-side input signal SIL, the non-inverting input terminal Np, the inverting input terminal Nn, the high-voltage output terminal OUT, the first current output terminal Na, and the second current output terminal Nb.
- Each voltage waveform is schematically shown.
- the voltage value shown in FIG. 2 does not accurately indicate a value proportional to the voltage value in actual circuit operation, but schematically shows an outline of the voltage change.
- the voltages at the high side input signal SIH, the low side input signal SIL, the high voltage output terminal OUT, the first current output terminal Na, and the second current output terminal Nb are voltages with reference to the circuit reference terminal VSS.
- the voltages at the non-inverting input terminal Np and the inverting input terminal Nn are voltages based on the high-side reference terminal Vs.
- the high side input signal SIH is at a high level
- the low side input signal SIL is at a low level
- the high voltage MOSFET 7a is in an on state
- the high voltage MOSFET 7b is in an off state.
- the high voltage Vhh is output to the high voltage output terminal OUT.
- the MOSFET 12a is in the off state with the low level reference voltage Vss applied to the gate
- the MOSFET 12b is in the on state with the high level power supply voltage Vcc applied to the gate.
- the gate-source voltage of the MOSFET 12b is automatically adjusted so that the same current as the current I2 flowing through the MOSFET 10c flows when the MOSFET 12b is on, the terminal voltage of the second current output terminal Nb is adjusted. This is the source voltage of the MOSFET 12b.
- the voltage of the high side power supply terminal Vb is substantially equal to the voltage obtained by subtracting the voltage drop of the diode 8 from the power supply voltage Vcc to the output voltage Vhh of the high voltage output terminal OUT. It is a voltage (Vhh + V ⁇ ) obtained by adding V ⁇ .
- the voltage of the high side power supply terminal Vb is also the output voltage Vhh of the high voltage output terminal OUT.
- the voltage at the non-inverting input terminal Np is substantially equal to the voltage V ⁇ at the high side power supply terminal Vb
- the voltage at the inverting input terminal Nn is from the voltage V ⁇ at the high side power supply terminal Vb. It becomes substantially equal to the voltage (V ⁇ V2) obtained by subtracting the voltage drop ⁇ V2 of the resistance element 13b.
- the comparator 14 since the voltage of the non-inverting input terminal Np is higher than the voltage of the inverting input terminal Nn, the comparator 14 outputs a high level voltage (V ⁇ ) with the high-side reference terminal Vs as a reference, and the voltage V ⁇ is By setting the threshold voltage higher than the threshold voltage of the high voltage MOSFET 7a, the high voltage Vhh is output to the high voltage output terminal OUT as shown in FIG.
- the high-side input signal SIH transitions from a high level to a low level at time t1.
- the MOSFET 12a changes from an off state to an on state by applying a high level voltage Vcc to the gate
- the MOSFET 12b changes from an on state to an off state by applying a low level voltage Vss to the gate.
- the current I1 flowing through the MOSFET 10b of the current generating circuit 3 flows through the MOSFET 12a and the resistance element 13a, and a voltage drop ⁇ V1 corresponding to the current I1 occurs at both ends of the resistance element 13a.
- the MOSFET 12b since the MOSFET 12b is turned off, no current flows through the resistance element 13b, and the voltage drop ⁇ V2 across the resistance element 13b is 0V.
- the low-side input signal SIL transits from the low level to the high level, so that the high voltage MOSFET 7b changes from the off state to the on state, and the voltage level of the high voltage output terminal OUT starts to decrease from the high voltage Vhh.
- the voltages at the high-side power supply terminal Vb and the high-side reference terminal Vs of the high-side circuit 2 also drop.
- the voltage drop ⁇ V1 and the voltage drop ⁇ V2 seen from the high-side power supply terminal Vb are maintained, the voltage at the non-inverting input terminal Np is lower than the voltage at the inverting input terminal Nn.
- a low level voltage (0 V) is output with reference to the high side reference terminal Vs.
- the voltage between the gate and the source of the high voltage MOSFET 7a becomes a low level, and transitions from the on state to the off state.
- the voltage of the high-side power supply terminal Vb is the voltage change (Vhh) from the voltage of the state H (Vhh + V ⁇ ) to the high-voltage output terminal OUT.
- the voltage V ⁇ As a result, the voltages at the non-inverting input terminal Np and the inverting input terminal Nn become the voltage (V ⁇ V1) and the voltage V ⁇ , respectively.
- the high side input signal SIH transitions from a low level to a high level and the low side input signal SIL transitions from a high level to a low level.
- the low side input signal SIL becomes low level, and the high voltage MOSFET 7b is turned off. Since the high side input signal SIH becomes high level, the MOSFET 12a is turned off by applying a low level reference voltage Vss to the gate, and the MOSFET 12b is turned on by applying high power supply voltage Vcc to the gate. As a result, the current I2 flowing through the MOSFET 10c of the current generating circuit 3 flows through the MOSFET 12b and the resistance element 13b, and a voltage drop ⁇ V2 corresponding to the current I2 occurs at both ends of the resistance element 13b. On the other hand, since the MOSFET 12a is turned off, no current flows through the resistance element 13a, and the voltage drop ⁇ V1 across the resistance element 13a becomes 0V.
- the voltage of the high-side power supply terminal Vb decreases to the voltage state (voltage V ⁇ ) in the steady state (state L) immediately before time t2, and the voltage of the high-side reference terminal Vs also changes to the state L immediately before time t2.
- the voltage of the non-inverting input terminal Np is substantially equal to the voltage V ⁇ of the high side power supply terminal Vb
- the voltage of the inverting input terminal Nn is obtained by subtracting the voltage drop ⁇ V2 of the resistance element 13b from the voltage V ⁇ of the high side power supply terminal Vb. It becomes substantially equal to the voltage (V ⁇ V2).
- the voltages of the non-inverting input terminal Np and the inverting input terminal Nn have the same voltage value with respect to the circuit reference terminal VSS.
- the comparator 14 outputs a high level voltage (V ⁇ ) with the high-side reference terminal Vs as a reference.
- the breakdown voltage MOSFET 7a is turned on.
- time t3 the time when the high voltage MOSFET 7a is turned on.
- the voltages at the high-side power supply terminal Vb and the high-side reference terminal Vs also rise in the same manner, so that the gate-source voltage of the on-state high voltage MOSFET 7a is maintained at the voltage V ⁇ higher than the threshold voltage. Then, the voltage level of the high voltage output terminal OUT rises to the high voltage Vhh.
- the voltage of the high side reference terminal Vs completely follows the voltage level of the high voltage output terminal OUT, and the voltage change of the high side power supply terminal Vb is also caused by electrostatic coupling via the capacitor 9 to the high voltage output terminal OUT.
- the voltage change of almost immediately The voltage at the non-inverting input terminal Np rises following the voltage change at the high-side power supply terminal Vb without causing a voltage drop due to the resistance element 13a because the MOSFET 12a is in the OFF state, but the voltage at the non-inverting input terminal Np A time delay corresponding to a time constant represented by the product of the parasitic capacitance and the resistance value of the resistance element 13a occurs.
- the voltage at the inverting input terminal Nn rises by following the voltage change at the high-side power supply terminal Vb by subtracting the voltage drop ( ⁇ V2) due to the resistance element 13b because the MOSFET 12b is on.
- a time delay corresponding to the time constant represented by the product of the capacitance parasitic on the input terminal Nn and the resistance value of the resistance element 13b occurs.
- the voltages of the non-inverting input terminal Np and the inverting input terminal Nn are the voltage (V ⁇ V1) and the voltage V ⁇ at time t2 with respect to the circuit reference terminal VSS, respectively, immediately after time t2.
- the magnitude relationship between the voltage V ⁇ and the voltage (V ⁇ V2) is reversed, and after time t3, the voltage V ⁇ and the voltage (V ⁇ + ⁇ V2) increase to the voltage (Vhh + V ⁇ V2).
- the MOSFET 12b and the MOSFET 10c are in the on state and pass the current I2.
- a large parasitic capacitance exists between the drain and source of the high breakdown voltage MOSFET 12b, and further, the drain-source capacitance is the source of the MOSFET 12b.
- the parasitic capacitance of the second current output terminal Nb on the side of the inverting input terminal Nn is considerably larger than the parasitic capacitance excluding the drain-source capacitance (for example, about 10 to 100 times or more).
- the voltage at the second current output terminal Nb also opposes the current I2 flowing through the MOSFET 10c by the electrostatic coupling via the drain-source capacitance.
- the MOSFET 12b From the source voltage of the MOSFET 12b). Since the MOSFET 10c connected to the second current output terminal Nb is in the ON state, the voltage of the second current output terminal Nb that has been increased at one end eventually decreases to the original voltage state.
- the MOSFET 12b that is originally on is in an off state during a period in which the voltage at the second current output terminal Nb is higher than a voltage that is lower than the gate voltage (power supply voltage Vcc) of the MOSFET 12b by the threshold voltage of the MOSFET 12b. That is, the voltage between the inverting input terminals Nn is not driven by the MOSFET 12b, and the operation of the comparator 14 may be temporarily susceptible to noise and may become unstable.
- the voltage suppression circuits 15a and 15b are provided. Thus, it is possible to suppress an excessive increase in the terminal voltage.
- each of the voltage suppression circuits 15a and 15b is configured by a two-terminal circuit, and one end (first terminal N1) of the two-terminal circuit is separately connected to the first and second current output terminals Na and Nb. The other end (second terminal N2) of the two-terminal circuit is connected to the circuit reference terminal VSS.
- the voltage suppression circuits 15a and 15b have at least one of the following first circuit structure and second circuit structure.
- the first circuit structure includes a two-terminal switching element or a two-terminal switching circuit that becomes conductive when the inter-terminal voltage exceeds a predetermined voltage between the first and second terminals N1 and N2.
- the voltage between the gate and the source of the MOSFET 12b is automatically adjusted so that the same current as the current I2 flowing through the MOSFET 10c flows while the MOSFET 12b is in the on state.
- the terminal voltage of the output terminal Nb is the source voltage of the adjusted MOSFET 12b.
- the voltage between the gate and the source of the MOSFET 12a is automatically adjusted so that the same current as the current I1 flowing through the MOSFET 10b flows while the MOSFET 12a is on, so the first current output terminal
- the terminal voltage of Na is the source voltage of the adjusted MOSFET 12a.
- one voltage of the first and second current output terminals Na and Nb is set higher than the source voltage of the MOSFETs 12a and 12b in the above-described steady states.
- the turn-on voltage of the two-terminal switching element or the two-terminal switching circuit is set so that the first and second terminals N1 and N2 become conductive.
- the terminal voltage of the first and second current output terminals Na and Nb is excessively increased without impeding the circuit operation of the circuit 1 of the present invention. Can be suppressed.
- one end of a capacitor having a larger capacitance than the drain-source capacitance of the high voltage MOSFETs 12a and 12b is connected to the first terminal N1, and the other end is directly or via a low impedance element or circuit. It is configured to be connected to the second terminal N2.
- the voltages of the non-inverting input terminal Np and the inverting input terminal Nn also rise, and further, the first and second current outputs are generated by electrostatic coupling via the drain-source capacitances of the MOSFETs 12a and 12b.
- the voltages at the terminals Na and Nb also temporarily increase.
- the parasitic capacitances of the first and second current output terminals Na and Nb are larger than the drain-source capacitances of the MOSFETs 12a and 12b. Due to the charge distribution effect of the suppression circuits 15a and 15b to the capacitors, an excessive voltage increase at the first and second current output terminals Na and Nb due to the electrostatic coupling is suppressed.
- FIG. 3 shows a circuit configuration example of the voltage suppression circuits 15a and 15b having the first circuit structure.
- the case where the above-described two-terminal switching element includes the Zener diode 21 and the diode 22 is illustrated.
- a Zener diode or a series circuit of diodes, or a series circuit of a Zener diode 21 or diode 22 and a constant voltage source 23 can be used.
- the two-terminal switching element is not limited to the Zener diode 21 or the diode 22, and if the switching element flows a current when the voltage between the two terminals exceeds a certain threshold voltage, the current flowing direction is one-sided. It can be used in either direction or bidirectional.
- the diode 22 is not limited to a PN junction diode, and various forms can be used.
- FIG. 4 shows a circuit configuration example of the voltage suppression circuits 15a and 15b having the second circuit structure.
- a series circuit in which a resistance element 25 is connected in series with the capacitor 24 is used.
- the capacitor 24 is constituted by a series circuit in which a parallel circuit of a resistance element 25 and a diode 22 is connected in series is illustrated.
- the voltage suppression circuits 15a and 15b may be configured by appropriately combining the circuits of the first circuit structure and the second circuit structure illustrated in FIGS. 3 and 4 in parallel or in series.
- the MOSFETs 10b and 10c are individually prepared at the first and second current output terminals Na and Nb, respectively, and currents flowing through the MOSFETs 12a and 12b are independently generated.
- the circuit configuration is shown, as shown in FIG. 5, the circuit configuration may be such that the first and second current output terminals Na and Nb are connected to the sources of the MOSFETs 12a and 12b as one current output terminal Nc.
- a second current mirror circuit composed of a combination of n-type MOSFETs 10a and 10c is not necessary.
- only one voltage suppression circuit 15c may be connected to it.
- the voltage suppression circuit 15c the one having the first circuit structure or the second circuit structure described above can be used.
- the current generation circuit 3 is not limited to the circuit configuration example illustrated in FIG. Various constant current generating circuits can be used as long as they can generate a constant current flowing through the MOSFETs 12a and 12b.
- the circuit configuration may be such that the current flowing through the MOSFET 10a shown in FIG. 1 is generated using another current mirror circuit.
- the voltage difference between the non-inverting input terminal Np and the inverting input terminal Nn is the difference in voltage drop generated between both ends of the resistance elements 13a and 13b, that is, the current flowing through the resistance elements 13a and 13b.
- a load circuit current-voltage conversion circuit
- the current-voltage characteristic may not be a linear resistance characteristic but may be a non-linear current-voltage characteristic.
- a diode or a transistor may be used instead of the resistance elements 13a and 13b.
- the MOSFETs 12a and 12b function as current control elements that control the current flowing between the drain and the source in accordance with the gate voltage, and any element that functions as a similar current control element.
- An element other than the MOSFET may be used, and the element is not necessarily a single element.
- the in-phase input signal is input to the gate of the MOSFET 12b and the reverse-phase input signal is input to the gate of the MOSFET 12a.
- the reverse-phase input signal is input to the gate of the MOSFET 12b. May be input to the gate of the MOSFET 12a.
- the high side input signal SIH and the low side input signal SIL must be in phase.
- the high side input signal SIH may be directly used instead of the in-phase input signal.
- the high voltage circuit driven by the high side output signal output from the comparator 14 is not limited to the circuit including the high voltage MOSFETs 7a and 7b illustrated in FIG.
- the level shift circuit according to the present invention can be used in a driver circuit that controls a high-side switching element to which a high voltage is applied by a half-bridge connection from a control signal having a low voltage level. It can be used extensively for level shifting to a certain circuit.
- Level shift circuit according to the present invention 2 High side circuit 3: Current generation circuit 4: Constant current circuit 5: Voltage source 6: High voltage source 7a, 7b: n-type high voltage MOSFET 8: Diode 9: Capacitor 10a to 10c: n-type MOSFET 11a, 11b: Inverters 12a, 12b: n-type high voltage MOSFET (first and second current control elements) 13a, 13b: Resistive elements (first and second load circuits) 14: Comparator 15a to 15c: Voltage suppression circuit 21: Zener diode 22: Diode 23: Constant voltage source 24: Capacitor 25: Resistance element 30: Conventional level shift circuit (driver circuit) 31: Pulse generation circuit 32a, 32b: n-type MOSFET 33a, 33b: Resistive element 34: RS flip-flop 35, 41a to 41f, 43a, 43b: Inverter 36: High side circuit 42a, 42b: NAND circuit 44a, 44b: Capacitive
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Abstract
Description
上記実施形態では、本発明回路の好適な実施形態の一例を詳細に説明した。本発明回路の回路構成は、上記実施形態に限定されるものではなく、本発明の要旨を逸脱しない範囲内において種々の変形実施が可能である。以下に、本発明回路の別実施形態につき説明する。
2: ハイサイド回路
3: 電流発生回路
4: 定電流回路
5: 電圧源
6: 高電圧源
7a,7b: n型の高耐圧MOSFET
8: ダイオード
9: コンデンサ
10a~10c: n型MOSFET
11a,11b: インバータ
12a,12b: n型の高耐圧MOSFET(第1及び第2電流制御素子)
13a,13b: 抵抗素子(第1及び第2負荷回路)
14: コンパレータ
15a~15c: 電圧抑制回路
21: ツェナーダイオード
22: ダイオード
23: 定電圧源
24: コンデンサ
25: 抵抗素子
30: 従来のレベルシフト回路(ドライバ回路)
31: パルス発生回路
32a,32b: n型MOSFET
33a,33b: 抵抗素子
34: RSフリップフロップ
35,41a~41f,43a,43b: インバータ
36: ハイサイド回路
42a,42b: NAND回路
44a,44b: コンデンサ
GND: インバータ回路の出力用接地端子
HV: インバータ回路の高電圧電源端子
IN: 電流制御回路の入力端子
INH: インバータ回路の制御入力端子
INL: インバータ回路の制御入力端子
INV: インバータ回路
Inh: 制御入力端子、ハイサイド回路側の制御入力端子
Inl: ローサイド側の制御入力端子
Nn: コンパレータの反転入力端子
Np: コンパレータの非反転入力端子
Na: 第1電流出力端子
Nb: 第2電流出力端子
Nc: 電流出力端子
N1: 電圧抑制回路の第1端子
N2: 電圧抑制回路の第2端子
OUT: 高電圧出力端子、インバータ回路の出力端子
OUT1,OUT2: 電流制御回路の出力端子
R: RSフリップフロップのリセット端子
S: RSフリップフロップのセット端子
Q: RSフリップフロップの出力端子
VCC: 回路電源端子、インバータ回路及びドライバ回路の電源端子
VSS: 回路基準端子、インバータ回路及びドライバ回路の接地端子
Vb: ハイサイド電源端子、ハイサイド回路側の正電圧電源端子
Vh: ハイサイド出力端子、ハイサイド回路側の出力端子
Vl: ローサイド側の出力端子
Vs: ハイサイド基準端子、ハイサイド回路側の基準電源端子
Claims (5)
- 入力信号と逆相の逆相入力信号が制御端子に入力し、当該制御端子の電圧によって第1及び第2端子間を流れる電流量が制御される第1電流制御素子、
前記入力信号または前記入力信号と同相の同相入力信号が制御端子に入力し、当該制御端子の電圧によって第1及び第2端子間を流れる電流量が制御される第2電流制御素子、
一端がハイサイド電源端子と接続し、他端が前記第1電流制御素子の前記第1端子と接続し、両端子間を流れる電流量に応じた電圧降下を発生する第1負荷回路、
一端が前記ハイサイド電源端子と接続し、他端が前記第2電流制御素子の前記第1端子と接続し、両端子間を流れる電流量に応じた電圧降下を発生する第2負荷回路、
第1電流出力端子が前記第1電流制御素子の前記第2端子と接続し、第2電流出力端子が前記第2電流制御素子の前記第2端子と接続し、前記第1電流制御素子と前記第2電流制御素子に夫々流れる電流を各別に発生する電流発生回路、
1対の差動入力端子の一方が前記第1電流制御素子の前記第1端子に接続し、前記1対の差動入力端子の他方が前記第2電流制御素子の前記第1端子に接続し、前記ハイサイド電源端子から電源電圧が供給され、ハイサイド基準端子から基準電圧が供給され、前記1対の差動入力端子間の電圧差に応じて出力信号を生成するコンパレータ、及び、
前記第1及び第2電流出力端子に各別または共通に接続して、前記第1及び第2電流出力端子夫々の電圧上昇を抑制する電圧抑制回路を、備えてなることを特徴とするレベルシフト回路。 - 前記電圧抑制回路が、
2端子回路で構成され、前記2端子回路の一端が前記第1及び第2電流出力端子に各別または共通に接続し、前記2端子回路の他端が所定の固定電位に接続し、
前記2端子回路の一端と他端の間に、端子間電圧が所定の電圧を超えると導通状態となる2端子スイッチング素子または2端子スイッチング回路を備える第1回路構造、及び、前記2端子回路の一端に前記第1及び第2電流制御素子の前記第1端子と前記第2端子間の各端子間容量より電気容量の大きい容量素子が接続する第2回路構造の内の少なくとも何れか一方の回路構造を有することを特徴とする請求項1に記載のレベルシフト回路。 - 前記電圧抑制回路が、単体のツェナーダイオードまたは複数のツェナーダイオードの直列回路からなる回路、単体のダイオードまたは複数のダイオードの直列回路からなる回路、ダイオードと電圧源の直列回路からなる回路、前記第1及び第2電流制御素子の前記第1端子と前記第2端子間の各端子間容量より電気容量の大きい電圧抑制用の容量素子からなる回路、前記電圧抑制用の容量素子と抵抗素子の直列回路からなる回路、及び、ダイオードと抵抗素子の並列回路と前記電圧抑制用の容量素子の直列回路からなる回路の内の少なくとも1つを備えて構成されていることを特徴とする請求項1または2に記載のレベルシフト回路。
- 回路動作用の電源電圧を外部から受け付ける回路電源端子を備え、
前記回路電源端子と前記ハイサイド電源端子間にダイオードを備え、
前記ハイサイド電源端子と前記ハイサイド基準端子間に容量素子を備え、
前記ハイサイド基準端子と前記出力信号によって駆動される高電圧回路の出力端子が電気的に接続していることを特徴とする請求項1~3の何れか1項に記載のレベルシフト回路。 - 前記第1及び第2電流制御素子が夫々高耐圧MOSFETで構成され、前記第1及び第2電流制御素子の前記制御端子が前記MOSFETのゲートで、前記第1及び第2電流制御素子の前記第1端子及び前記第2端子が前記MOSFETのドレインとソースであることを特徴とする請求項1~4の何れか1項に記載のレベルシフト回路。
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JP7412346B2 (ja) | 2018-10-25 | 2024-01-12 | 株式会社半導体エネルギー研究所 | 半導体装置 |
Also Published As
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JP5945629B2 (ja) | 2016-07-05 |
CN105144584B (zh) | 2017-07-18 |
CN105144584A (zh) | 2015-12-09 |
US20150358003A1 (en) | 2015-12-10 |
US9264022B2 (en) | 2016-02-16 |
JPWO2014171190A1 (ja) | 2017-02-16 |
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