WO2021109808A1 - 存储器及其制作方法 - Google Patents

存储器及其制作方法 Download PDF

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Publication number
WO2021109808A1
WO2021109808A1 PCT/CN2020/127780 CN2020127780W WO2021109808A1 WO 2021109808 A1 WO2021109808 A1 WO 2021109808A1 CN 2020127780 W CN2020127780 W CN 2020127780W WO 2021109808 A1 WO2021109808 A1 WO 2021109808A1
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layer
gate
metal layer
memory
source
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PCT/CN2020/127780
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English (en)
French (fr)
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戴强
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浙江驰拓科技有限公司
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N59/00—Integrated devices, or assemblies of multiple devices, comprising at least one galvanomagnetic or Hall-effect element covered by groups H10N50/00 - H10N52/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to the technical field of memory, in particular to a memory and a manufacturing method thereof.
  • the current MRAM basically uses the source to be parallel to the bit line and perpendicular to the word line to lay out the traces.
  • Metal vias are used to connect the source and drain of each memory cell.
  • the CMOS source of the bits of the common word line are connected to the same potential
  • the drain is connected to the magnetic tunnel junction (MTJ) and the bit lines are interconnected for addressing
  • the word lines (gates) are connected vertically. Used for site selection.
  • the metal traces of the source and the bit line (drain) are in the same direction and perpendicular to the bit line.
  • the source electrode shared by every two memory cells is connected to the interconnection metal layer through a through hole to achieve interconnection.
  • the memory and its manufacturing method provided by the present invention realize the source interconnection of the common-connected gate through the interconnection metal layer, and replace the through hole for interconnecting the source, thereby circumventing the constraints of related design rules and reducing the
  • the design size of the memory further increases the density of memory bits.
  • the present invention provides a memory including a memory cell, an active region, a gate, an interconnection metal layer, and a shallow trench isolation region;
  • the shallow trench isolation region and the active region are arranged horizontally spaced apart;
  • the gate is arranged above the active area, and the gate and the active area are perpendicular to each other;
  • Each of the active regions includes a plurality of sources and a plurality of drains, each gate and the plurality of active regions form a plurality of common-gate transistors, and adjacent transistors in the same active region share the same Source or drain;
  • the interconnection metal layer is located above the source and between adjacent gates to interconnect the sources of common-gate transistors.
  • the interconnection metal layer is located above the shallow trench isolation region.
  • both sides and bottom surfaces of the interconnection metal layer are wrapped with a buried layer.
  • the memory is provided with a source line, and the source line is the interconnection metal layer.
  • the memory is further provided with a bit line; the drains in the same active area are interconnected through the bit line.
  • the storage unit includes: a magnetic tunnel junction
  • Each of the drains is connected to one of the magnetic tunnel junctions.
  • the memory is further provided with word lines, and the word lines of the common gate are interconnected.
  • the present invention provides a method for manufacturing a memory, including:
  • Step S102 providing a substrate, and forming active regions and shallow trench isolation regions arranged at horizontal intervals on the substrate;
  • Step S104 After step S102 is completed, a gate is formed vertically above the active region, and the gates in the same column are interconnected.
  • the active region includes multiple sources and multiple drains, and interconnected gates. The two sides of the pole are respectively the source and the drain;
  • Step S106 After completing step S104, deposit a gold semi-contact alloy layer
  • Step S108 After completing step 106, deposit a passivation layer
  • Step S110 After completing step S108, deposit a first intermediate dielectric insulating layer
  • Step S112 After completing step S110, remove the first intermediate dielectric insulating layer directly above the source electrode and the passivation layer at the corresponding position to expose the gold half-contact alloy layer directly above the source electrode;
  • Step S114 After step S112 is completed, a buried layer and an interconnection metal layer are sequentially deposited to interconnect the sources of the same gate and define a source line connecting the sources;
  • Step S116 After completing step S114, grind the buried layer and the interconnection metal layer to expose the passivation layer;
  • Step S118 After completing step S116, deposit an insulating interconnection metal layer passivation layer;
  • Step S120 After completing step S118, deposit a second intermediate dielectric insulating layer
  • Step S122 After step S120 is completed, a first through hole that penetrates the second intermediate dielectric insulating layer and is connected to the gate is opened, and a first through hole that penetrates the second intermediate dielectric insulating layer and is connected to the drain is opened.
  • the second through hole is provided with a first metal layer that passes through the first through hole and is connected to the gate, that is, a word line, and a first metal layer that passes through the second through hole and is connected to the drain Two metal layers;
  • Step S124 After step S122 is completed, a magnetic tunnel junction connected to the second metal layer is arranged above the second intermediate dielectric insulating layer, and a second common metal layer is arranged above the magnetic tunnel junction , Which is the bit line.
  • the method further includes: removing the passivation layer directly above the gate and the passivation layer directly above the gate through a photolithography and etching process. A gold half-contact alloy layer and the top of the gate, obtaining a sacrificial oxide layer directly above the gate through a deposition process;
  • the step of removing the first intermediate dielectric insulating layer directly above the source electrode and the passivation layer directly above the source electrode to expose the gold semi-contact alloy layer includes:
  • the sequential deposition of the buried layer and the interconnection metal layer includes: adopting a self-aligned process and using the passivation layer as an etching stop layer, and sequentially depositing the buried layer and the interconnection metal layer.
  • the source interconnection of the common-connected gate is realized only through the interconnection metal layer, and the through hole for interconnecting the source is replaced, thereby circumventing the constraints of related design rules and reducing
  • the design size of the memory is improved, thereby increasing the density of memory bits.
  • FIG. 1 is a partial three-dimensional schematic structural diagram of a memory according to an embodiment of the application
  • FIG. 2 is a partial three-dimensional schematic structural diagram showing the connection relationship between source lines, word lines, and bit lines according to an embodiment of the application;
  • 3 to 7 are partial two-dimensional schematic process diagrams of a memory according to an embodiment of the application.
  • 8 to 11 are partial two-dimensional schematic process diagrams of a memory according to an embodiment of the application.
  • FIG. 12 is a schematic structural diagram showing the positional relationship between the active region, the shallow trench isolation region, and the interconnection metal layer according to an embodiment of the application.
  • the present invention provides a memory, the memory includes: MRAM memory, RRAM memory, PCRAM memory and flash structure memory.
  • the memory is a non-volatile magnetic random access memory, namely STT-MRAM memory.
  • the STT-MRAM memory bit adopts a method including 2T1J or 1T1J to provide the drive current required by MRAM for reading and writing.
  • the STT-MRAM memory bit adopts a 2T1J method to provide the drive current required by MRAM. Read and write.
  • the memory includes a substrate 1, a gate 2, an interconnection metal layer 5, and a storage unit; the storage unit may be a magneto-rotary memory (STT-MRAM), a phase change memory (PCRAM), Resistive random access memory (RRAM), but not limited to this.
  • the top of the substrate 1 includes an active region 11 and a shallow trench isolation region 12.
  • the shallow trench isolation region 12 and the active region 11 are arranged horizontally and spaced apart on the upper surface of the substrate 1 along the lateral direction.
  • the gate 2 is arranged above the active region 11, and the gate 2 and the active region 11 are perpendicular to each other.
  • the active region includes a plurality of sources 111 and a plurality of drains 112.
  • the number of the source 111 and the drain 112 of the active region in each row is the same, and they are arranged at intervals; each gate 2 and The multiple active regions 11 form multiple common-gate transistors, and adjacent transistors in the same active region 11 share the source 111 or the drain 112.
  • the interconnection metal layer 5 is located above the source 111 and between adjacent gates 2 to interconnect the sources 111 of common-gate transistors.
  • common-gate transistors are transistors with interconnected gates 2, that is, transistors sharing one gate 2; the same active region 11 is an active region 11 located in an adjacent shallow trench isolation region 12.
  • the memory realizes the interconnection of the source 111 of the common gate 2 through the interconnection metal layer 5, that is, the interconnection of two adjacent bit source 111 separated by a shallow trench.
  • the through hole for interconnecting the source 111 is replaced, thereby circumventing the constraints of related design rules, and reducing the design size of the memory, thereby increasing the density of memory bits.
  • the design rule size of the through hole of the interconnection source 111 and the design rule size of the through hole of the interconnection source 111 to the gate 2 are avoided, the distance between adjacent gates 2 can be further reduced, thereby reducing the size of the memory. Bit size.
  • the material of the interconnection metal layer 5 includes copper, tungsten, tantalum or titanium, but not limited thereto. In this embodiment, the material of the interconnection metal layer 5 is copper.
  • the interconnection metal layer 5 is located above the shallow trench isolation region 12. Specifically, the upper surface of the shallow trench isolation region 12 is at the same level as the upper surface of the active region 11, and the bottom surface of the shallow trench isolation region 12 is at the same level as the bottom surface of the active region 11. The same level.
  • the interconnection metal layer 5 is located above the horizontal plane formed by the upper surface of the shallow trench isolation region 12 and the upper surface of the active region 11, which not only saves the processing technology of the interconnection metal layer 5, but also The material consumption of the interconnection metal layer 5 is saved.
  • the distance between adjacent gates can be set according to process requirements. In this embodiment, for example, under a 40nm platform, the distance between adjacent gates is 120 nm, but it is not limited to this. Other process platforms can also set other characteristic values.
  • the pitch of the gate 2 is the shortest distance between the side walls 4 of the gate 2. Since the interconnection of the source 111 of the common-connected gate 2 is realized only through the interconnection metal layer 5, the design rule size of the via hole of the interconnection source 111 and the design rule size of the via hole of the interconnection source 111 to the gate 2 can be avoided. The distance between adjacent gates 2 is reduced. In this embodiment, the distance between adjacent gates 2 is 120 nm, but it is not limited to this.
  • the buried layer 6 wraps the side surface and the bottom surface of the interconnection metal layer 5 to prevent the metal in the interconnection metal layer 5 from diffusing.
  • the memory is provided with a source line SL, the source line SL is the interconnection metal layer, and the sources 111 between adjacent gates are interconnected by the source line SL. Specifically, the source line SL corresponding to the common-connected source 111 is interconnected through the interconnection metal layer 5.
  • the memory is also provided with a word line WL, and the word lines WL of the common gate 2 are interconnected. Specifically, the memory further includes a first common metal layer 50 located above the gate 2, and the word lines WL of the common gate 2 are interconnected through the first common metal layer 50.
  • the storage unit includes: a magnetic tunnel junction 20 (MTJ, Magnetic Tunnel Junctions). Each drain 112 is connected to one magnetic tunnel junction 20. Specifically, a bottom electrode 201 connected to the bottom of the magnetic tunnel junction 20 is provided under the magnetic tunnel junction 20, and the material of the bottom electrode 201 is copper; the bottom electrode 201 is located in the first common connection.
  • MTJ Magnetic Tunnel Junctions
  • the magnetic tunnel junction 20 is a stack structure, and the magnetic tunnel junction 20 includes: a fixed layer for fixing the magnetic pole direction, a tunneling layer on the side of the fixed layer close to the bottom electrode 201, and a The free layer on the side of the tunneling layer away from the pinned layer; wherein the magnetic pole of the free layer is determined by electron spin magnetization to define the storage state of the magnetic tunnel junction 20.
  • the memory is also provided with a bit line BL.
  • the drains 112 in the same active region 11 are interconnected by the bit line BL.
  • the memory further includes a second common metal layer 60 located above the gate 2, and the bit line BL corresponding to the drain 112 in the same active region 11 passes through the second through hole 32 and the first
  • the common metal layer 50 is connected to the second common metal layer 60 through the magnetic tunnel junction 20 to achieve interconnection.
  • the first common metal layer 50 includes a plurality of metal strips, the metal strips are arranged at intervals along the horizontal direction, and among the two adjacent metal strips, one metal strip is connected to the word line L, and the other metal strip is connected to the word line L.
  • a bit line BL is connected to each.
  • the present invention provides a method for fabricating a memory, in conjunction with FIG. 1, FIG. 3 to FIG. 7, including:
  • Step S102 A substrate 1 is provided, and active regions 11 and shallow trench isolation regions 12 arranged at horizontal intervals along the lateral direction are formed above the substrate 1.
  • the material of the substrate 1 is silicon single crystal.
  • Step S104 After step S102 is completed, a gate 2 and a sidewall 4 connecting adjacent active regions 11 are formed vertically above the active region 11, and the active regions on both sides of the gate 2 11 are the source 111 and the drain 112 respectively.
  • the material of the sidewall spacer 4 includes silicon nitride or silicon oxide.
  • the material of the sidewall spacer 4 is silicon nitride; the material of the gate 2 is non-single crystal silicon.
  • Step S106 After step S104 is completed, a gold semi-contact alloy layer 7 is deposited.
  • the material of the gold half-contact alloy layer 7 includes cobalt, nickel, or a cobalt-nickel alloy, but is not limited thereto. In this embodiment, the material of the gold half-contact alloy layer 7 is cobalt.
  • Step S108 After step 106 is completed, a passivation layer 8 is deposited.
  • the material of the passivation layer 8 includes silicon nitride or silicon oxide, but is not limited thereto. In this embodiment, the material of the passivation layer 8 is silicon nitride.
  • the arrangement of the passivation layer 8 can increase the distance between the gate 2 and the first common metal layer 50, thereby reducing the risk of leakage of the sidewall 4 of the gate 2; at the same time, it can also be used as a chemical mechanical polishing (CMP , Chemical Mechanical Polishing) process barrier layer.
  • CMP Chemical Mechanical Polishing
  • Step S110 After step S108 is completed, a first intermediate dielectric insulating layer 91 is deposited.
  • Step S112 After completing step S110, remove the first intermediate dielectric insulating layer 91 directly above the source electrode 111 and the passivation layer 8 at the corresponding position to expose the gold half-contact alloy layer directly above the source electrode 111 7.
  • Step S114 After step S112 is completed, the buried layer 6 and the interconnection metal layer 5 are sequentially deposited to interconnect the sources 111 of the same gate 2 and define a source line SL connecting the sources 111.
  • the material of the buried layer 6 includes: tantalum, tantalum nitride, titanium, titanium nitride, tantalum and tantalum nitride alloy, or an alloy of titanium and titanium nitride, but not limited thereto; the material of the interconnection metal layer 5 Including: but not limited to copper, silver or aluminum.
  • the material of the buried layer 6 is titanium as a barrier layer of the interconnection metal layer 5; the material of the interconnection metal layer 5 is copper.
  • Step S116 After completing step S114, the buried layer 6 and the interconnection metal layer 5 are polished to expose the passivation layer 8.
  • Step S118 After step S116 is completed, an insulating interconnection metal layer passivation layer 10 is deposited.
  • the material of the interconnection metal layer passivation layer 10 includes silicon nitride or silicon oxynitride, but is not limited thereto. In this embodiment, the material of the interconnect metal passivation layer 10 is silicon nitride, and the thickness of the Hualian metal passivation layer 8 is 40 nm.
  • Step S120 After step S118 is completed, a second intermediate dielectric insulating layer 92 is deposited.
  • the materials of the first intermediate dielectric insulating layer 91 and the second intermediate dielectric insulating layer 92 are both silicon oxide.
  • Step S122 After step S120 is completed, a first through hole 31 penetrating the second intermediate dielectric insulating layer 92 and connected to the gate electrode 2 is opened, and a first through hole 31 penetrating the second intermediate dielectric insulating layer 92 and connected to the gate electrode 2 is opened.
  • the second through hole 32 of the drain 112 is provided with a first metal layer 501 passing through the first through hole 31 and connected to the gate 2, which is the word line WL, and passing through the second through hole 31.
  • the second metal layer 502 connected to the drain 112 through the hole 32.
  • a first common metal layer 50 is obtained above the second intermediate dielectric insulating layer 92.
  • the first common metal layer 50 includes a plurality of metal strips arranged at intervals in the horizontal direction, and of the two adjacent metal strips, one metal strip passes through the first through hole 31 and is The metal layer connected to the gate 2, that is, the first metal layer 501, is the word line WL; the other metal strip is a metal layer that passes through the second through hole 32 and is connected to the drain 112, namely The second metal layer 502.
  • Step S124 After the step S122 is completed, a magnetic tunnel junction 20 connected to the metal layer connected to the drain electrode 112 through the third through hole 33 is provided above the second intermediate dielectric insulating layer 92, and the magnetic tunnel junction 20 is connected to the second intermediate dielectric insulating layer 92.
  • a second common metal layer 60 is provided above the tunnel junction 20, which is the bit line BL.
  • the first through hole 31, the second through hole 32, and the third through hole 33 are all filled with copper, but it is not limited thereto.
  • the manufacturing method of the memory only realizes the interconnection of the source 111 of the common gate 2 through the interconnection metal layer 5, avoids the design rule requirements of the distance between the via hole and the polysilicon gate and the size of the via hole, reduces the design area and increases the density.
  • the method further includes: obtaining the gate oxide layer 30 through deposition and photolithography processes.
  • the material of the gate oxide layer 30 includes silicon oxide or hafnium oxide, but is not limited thereto. In this embodiment, the material of the gate oxide layer 30 is silicon oxide.
  • the present invention provides a method for manufacturing a memory, in conjunction with FIG. 1, FIG. 8 to FIG. 11, including:
  • Step S202 providing a substrate 1 and forming active regions 11 and shallow trench isolation regions 12 arranged horizontally and spaced above the substrate 1.
  • the material of the substrate 1 is silicon single crystal.
  • Step S204 After step S102 is completed, a gate 2 and a sidewall 4 connecting adjacent active regions 11 are formed above the active region 11, and the active regions 11 on both sides of the gate 2 are respectively formed It is the source 111 and the drain 112.
  • the material of the sidewall spacer 4 includes silicon nitride or silicon oxide, but is not limited thereto.
  • the material of the sidewall spacer 4 is silicon nitride; the material of the gate 2 is non-single crystal silicon.
  • Step S206 After step S204 is completed, a gold semi-contact alloy layer 7 is deposited.
  • the material of the gold half-contact alloy layer 7 includes cobalt, nickel, or a cobalt-nickel alloy, but is not limited thereto. In this embodiment, the material of the gold half-contact alloy layer 7 is cobalt.
  • Step S208 After step S206 is completed, a passivation layer 8 is deposited.
  • the material of the passivation layer 8 includes silicon nitride or silicon oxide, but is not limited thereto. In this embodiment, the material of the passivation layer 8 is silicon nitride.
  • Step S210 After step S208 is completed, the passivation layer 8 directly above the gate 2, the gold half-contact alloy layer 7 directly above the gate 2 and the gate 2 are removed by photolithography and etching processes. On the top of the gate electrode 2, a sacrificial oxide layer 40 is obtained by a deposition process.
  • Step S212 After step S210 is completed, a first intermediate dielectric insulating layer 91 is deposited.
  • Step S214 After completing step S212, remove the first intermediate dielectric insulating layer 91 directly above the source electrode 111 and the passivation layer 8 at the corresponding position to expose the gold half-contact alloy layer directly above the source electrode 111 7. The first intermediate dielectric insulating layer 91 and the sacrificial oxide layer 40 directly above the gate 2 are removed.
  • Step S216 After step S214 is completed, the buried layer 6 and the interconnection metal layer 5 are sequentially deposited to interconnect the sources 111 of the same gate 2 and define a source line SL connecting the sources 111.
  • the material of the buried layer 6 includes: tantalum, tantalum nitride, titanium, titanium nitride, tantalum and tantalum nitride alloy, or an alloy of titanium and titanium nitride, but not limited thereto; the material of the interconnection metal layer 5 Including: but not limited to copper, silver or aluminum.
  • the material of the buried layer 6 is titanium as the barrier layer of the interconnection metal layer 5; the material of the interconnection metal layer 5 is copper.
  • Step S218 After the step S216 is completed, the buried layer 6 and the interconnection metal layer 5 are polished to expose the passivation layer 8.
  • Step S220 After step S218 is completed, an insulating interconnection metal layer passivation layer 10 is deposited.
  • the material of the interconnection metal layer passivation layer 10 includes silicon nitride or silicon oxynitride, but is not limited thereto. In this embodiment, the material of the interconnect metal passivation layer 10 is silicon nitride, and the thickness of the Hualian metal passivation layer 8 is 40 nm.
  • Step S222 After step S220 is completed, a second intermediate dielectric insulating layer 92 is deposited.
  • the materials of the first intermediate dielectric insulating layer 91 and the second intermediate dielectric insulating layer 92 are both silicon oxide.
  • Step S224 After step S222 is completed, a first through hole 31 penetrating through the second intermediate dielectric insulating layer 92 and connected to the gate electrode 2 is opened, and a first through hole 31 penetrating through the second intermediate dielectric insulating layer 92 and connected to the gate electrode 2 is opened.
  • the second through hole 32 of the drain 112 is provided with a metal layer that passes through the first through hole 31 and is connected to the gate 2, that is, the word line WL, and passes through the second through hole 32 and A metal layer connected to the drain 112.
  • Step S226 After completing step S224, a magnetic tunnel junction 20 connected to the metal layer connected to the drain 112 is provided above the second intermediate dielectric insulating layer 92, and is provided above the magnetic tunnel junction 20
  • the second common metal layer 60 is the bit line BL.
  • the first through hole 31, the second through hole 32, and the third through hole 33 are all filled with copper.
  • the method further includes: obtaining a first common metal layer 50 above the second intermediate dielectric insulating layer 92.
  • the first common metal layer 50 includes a plurality of metal strips arranged at intervals along the horizontal direction, and among two adjacent metal strips, one of the metal strips is connected to the word line ZL, that is, the first metal Layer 501; another metal strip is connected to the bit line BL, that is, the second metal layer 502.
  • a second common metal layer 60 is obtained directly above the magnetic tunnel junction 20.
  • the manufacturing method of the memory only realizes the interconnection of the source 111 of the common gate 2 through the interconnection metal layer 5, avoids the design rules of the distance between the polysilicon gate and the through hole and the through hole size, reduces the bit area and improves the storage density.
  • depositing the buried layer 6 and the interconnection metal layer 5 on the gate 2 can reduce the delay caused by the resistance of the word line WL.
  • the step of sequentially depositing the buried layer 6 and the interconnection metal layer 5 includes: adopting a self-aligned process and using the passivation layer 8 as an etching stop layer, and depositing the buried layer 6 and the interconnection metal layer 5 in sequence.
  • the method further includes: obtaining the gate oxide layer 30 through deposition and photolithography processes.
  • the material of the gate oxide layer 30 includes silicon oxide or hafnium oxide, but is not limited thereto. In this embodiment, the material of the gate oxide layer 30 is silicon oxide.

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Abstract

本发明提供一种存储器及其制作方法。其中，所述存储器包括存储单元、有源区、栅极、互联金属层和浅沟道隔离区；所述浅沟道隔离区与有源区水平间隔排列；栅极设置在有源区上方，栅极与有源区相互垂直；每个有源区包括多个源极和多个漏极，每一个栅极与多个有源区形成多个共栅的晶体管，同一有源区中的相邻晶体管共用源极或漏极；互联金属层位于源极上方以及相邻的栅极之间，以将共栅的晶体管的源极互联。本发明通过互联金属层实现共联栅极的源极互联，替换掉了用于互联源极的通孔，从而规避了相关设计规则的束缚，并降低了存储器的设计尺寸，进而提高了存储器的密度。

Description

存储器及其制作方法 技术领域
本发明涉及存储器技术领域，尤其涉及一种存储器及其制作方法。
背景技术
当前的MRAM基本采用源极与位线平行，与字线垂直的方式布局走线。并用金属通孔连接每个存储单元的源极和漏极。在通常的MRAM单元结构中，共字线的位元其CMOS源极互联接同电位，漏极连接磁性隧道结(MTJ)并将位线互联用以选址，字线(栅极)纵向互联用以选址。源极及位线(漏极)的金属走线为同一方向并与位线垂直。其中，每两个存储单元共用的源极通过通孔连接至互联金属层以实现互联。
但是由于设计规则的限制，通孔至通孔的间距、通孔至多晶硅的间距难以进一步微缩。
发明内容
本发明提供的存储器及其制作方法，通过互联金属层实现共联栅极的源极互联，替换掉了用于互联源极的通孔，从而规避了相关设计规则的束缚，并降低了所述存储器的设计尺寸，进而提高了存储器位元的密度。
第一方面，本发明提供一种存储器，包括存储单元、有源区、栅极、互联金属层和浅沟道隔离区；
所述浅沟道隔离区与所述有源区水平间隔排列；
所述栅极设置在所述有源区上方，所述栅极与所述有源区相互垂直；
每个所述有源区包括多个源极和多个漏极，每一个栅极与多个所述有源区形成多个共栅的晶体管，同一所述有源区中的相邻晶体管共用源极或漏极；
所述互联金属层位于所述源极上方以及相邻的栅极之间，以将共栅的晶体管的源极互联。
可选地，所述互联金属层位于所述浅沟道隔离区的上方。
可选地，所述互联金属层的侧面和底面均包裹有掩埋层。
可选地，所述存储器设置有源极线，所述源极线为所述互联金属层。
可选地，所述存储器还设置有位线；同一有源区中的漏极通过所述位线互联。
可选地，所述存储单元包括：磁性隧道结；
每一所述漏极均连接一个所述磁性隧道结。
可选地，所述存储器还设置有字线，且共联栅极的字线互联。
第二方面，本发明提供一种存储器的制作方法，包括：
步骤S102：提供衬底，并在所述衬底的上方形成水平间隔排列的有源区和浅沟道隔离区；
步骤S104：在完成步骤S102后，在所述有源区的上方沿纵向形成栅极，且同一列的栅极互联，所述有源区包括多个源极和多个漏极，互联的栅极两侧分别为源极和漏极；
步骤S106：在完成步骤S104后，沉积金半接触合金层；
步骤S108：在完成步骤106后，沉积钝化层；
步骤S110：在完成步骤S108后，沉积第一中间介质绝缘层；
步骤S112：在完成步骤S110后，去除所述源极正上方的第一中间介质绝缘层和对应位置处的钝化层，以露出所述源极正上方的金半接触合金层；
步骤S114：在完成步骤S112后，依次沉积掩埋层和互联金属层，以将同一栅极的源极互联，并定义出连接源极的源极线；
步骤S116：在完成步骤S114后，研磨所述掩埋层和所述互联金属层，以露出所述钝化层；
步骤S118：在完成步骤S116后，沉积绝缘的互联金属层钝化层；
步骤S120：在完成步骤S118后，沉积第二中间介质绝缘层；
步骤S122：在完成步骤S120后，开设贯穿所述第二中间介质绝缘层且连通至所述栅极的第一通孔，和贯穿所述第二中间介质绝缘层且连通至所述漏极的第二通孔，并设置通过所述第一通孔且与所述栅极连接的第一金属层，即为字线，和穿过所述第二通孔且与所述漏极连接的第二金属层；
步骤S124：在完成步骤S122后，在所述第二中间介质绝缘层上方设置有与所述第二金属层连接的磁性隧道结，并在所述磁性隧道结的上方设置第二共接金属层，即为位线。
可选地，在所述沉积第一中间介质绝缘层的步骤前，所述方法进一步包括：通过光刻及刻蚀工艺去除所述栅极正上方的钝化层、所述栅极正上方的金半接触合金层和所述栅极的顶部，在所述栅极正上方通过沉积工艺得到牺牲氧化层；
所述去除所述源极正上方的第一中间介质绝缘层和所述源极正上方的钝化层，以露出所述金半接触合金层的步骤包括：
去除所述源极正上方的第一中间介质绝缘层和所述源极正上方的钝化层，以露出所述源极正上方的金半接触合金层，并去除所述栅极正上方的第一中间介质绝缘层和牺牲氧化层。
可选地，所述依次沉积掩埋层和互联金属层，包括：采用自对准工艺，并利用所述钝化层作为刻蚀阻挡层，依次沉积掩埋层和互联金属层。
本发明实施例提供的存储器及其制作方法，仅通过互联金属层实现共联栅 极的源极互联，替换掉了用于互联源极的通孔，从而规避了相关设计规则的束缚，并降低了所述存储器的设计尺寸，进而提高了存储器位元的密度。
附图说明
图1为本申请实施例的存储器的局部三维示意性结构图；
图2为本申请实施例的为体现源极线、字线和位线连接关系的局部三维示意性结构图；
图3至图7为本申请实施例的一存储器的局部二维示意性工艺图；
图8至图11为本申请实施例的一存储器的局部二维示意性工艺图；
图12为本申请实施例的为体现有源区、浅沟道隔离区和互联金属层位置关系的示意性结构简图。
1、衬底；11、有源区；111、源极；112、漏极；12、浅沟道隔离区；2、栅极；31、第一通孔；32、第二通孔；33、第三通孔；4、侧墙；5、互联金属层；6、掩埋层；7、金半接触合金层；8、钝化层；91、第一中间介质绝缘层；92、第二中间介质绝缘层；10、互联金属层钝化层；20、磁性隧道结；201、底电极；30、栅极氧化层；40、牺牲氧化层；50、第一共接金属层；501、第一金属层；502、第二金属层；60、第二共接金属层。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
第一方面，本发明提供一种存储器，所述存储器包括：MRAM存储器， RRAM存储器，PCRAM存储器和flash结构的存储器。在本实施例中所述存储器为非易失性磁随机存储器，即STT-MRAM存储器。其中，所述STT-MRAM存储器位元采用包括2T1J或1T1J的方式提供MRAM需要的驱动电流进行读写，在本实施例中所述STT-MRAM存储器位元采用2T1J的方式提供MRAM需要的驱动电流进行读写。结合图1和图2，所述存储器包括衬底1、栅极2、互联金属层5以及存储单元；所述存储单元，可以是磁旋存储器(STT-MRAM)、相变存储器(PCRAM)、阻变存储器(RRAM)，但不限于此。所述衬底1的顶部包括：有源区11和浅沟道隔离区12。结合图12，所述浅沟道隔离区12与所述有源区11沿横向在所述衬底1的上表面水平间隔排列。所述栅极2设置在所述有源区11上方，所述栅极2与所述有源区11相互垂直。所述有源区包括多个源极111和多个漏极112，具体的，每一行所述有源区的源极111和漏极112的数量相同，且间隔排列；每一个栅极2与多个所述有源区11形成多个共栅的晶体管，同一所述有源区11中的相邻晶体管共用源极111或漏极112。所述互联金属层5位于所述源极111上方以及相邻的栅极2之间，以将共栅的晶体管的源极111互联。其中，共栅的晶体管为栅极2互联的晶体管，即共用一个栅极2的晶体管；同一所述有源区11为位于相邻的浅沟道隔离区12的有源区11。
所述存储器通过互联金属层5实现共联栅极2的源极111互联，即实现被浅沟道隔离的相邻两个位元源极111互联。替换掉了用于互联源极111的通孔，从而规避了相关设计规则的束缚，并降低了所述存储器的设计尺寸，进而提高了存储器位元的密度。具体的，由于规避了互联源极111的通孔的设计规则尺寸和互联源极111的通孔至栅极2的设计规则尺寸，进一步可缩小相邻的栅极2的间距，从而缩小存储器的位元尺寸。
所述互联金属层5的材料包括：铜、钨、钽或钛等，但不限于此。在本实施例中，所述互联金属层5的材料为铜。所述互联金属层5位于所述浅沟道隔离区12的上方。具体的，所述浅沟道隔离区12的上表面与所述有源区11的上表面处于同一水平面，所述浅沟道隔离区12的下表面与所述有源区11的下表面处于同一水平面。所述互联金属层5位于由所述浅沟道隔离区12的上表面和所述有源区11的上表面共同构成的水平面的上方，如此既节省了互联金属层5的加工工艺，同时又节省了互联金属层5的材料用量。
其中，结合图7和图11，相邻的栅极的间距可根据工艺要求进行设置，在本实施例中，如在40nm平台下，相邻的栅极的间距为120nm，但不限于此。其他工艺平台亦可设置其他特征值。具体的，所述栅极2的间距为所述栅极2的侧墙4间的最近距离。由于仅通过互联金属层5实现共联栅极2的源极111互联，规避了互联源极111的通孔的设计规则尺寸和互联源极111的通孔至栅极2的设计规则尺寸，能够缩小相邻的栅极2的间距。在本实施例中，相邻的栅极2的间距为120nm，但不限于此。所述掩埋层6包裹所述互联金属层5的侧面和底面，以防止所述互联金属层5内的金属扩散。
所述存储器设置有源极线SL，所述源极线SL为所述互联金属层，且相邻的栅极之间的源极111通过所述源极线SL互联。具体的，所述共联源极111对应的源极线SL通过互联金属层5实现互联。所述存储器还设置有字线WL，且共联栅极2的字线WL互联。具体的，所述存储器还包括位于所述栅极2上方的第一共接金属层50，且共联栅极2的字线WL通过第一共接金属层50实现互联。
所述存储单元包括：磁性隧道结20(MTJ、Magnetic Tunnel Junctions)。每一所述漏极112均连接一个所述磁性隧道结20。具体的，所述磁性隧道结 20的下方设置有与所述磁性隧道结20的底部连接的底电极201，所述底电极201的材料为铜；所述底电极201位于所述第一共接金属层50的上方，并通过第三通孔33与第一金属层501连接，第一金属层501通过第二通孔32与栅极2连接，进而所述底电极201与对应的漏极112连接；所述磁性隧道结20为堆栈结构，且所述磁性隧道结20包括：一个用于固定磁极方向的固定层、一个位于所述固定层靠近底电极201一侧的隧穿层以及一个位于所述隧穿层远离所述固定层一侧的自由层；其中，所述自由层的磁极通过电子自旋磁化确定，以定义所述磁性隧道结20的存储状态。
所述存储器还设置有位线BL。同一有源区11中的漏极112通过所述位线BL互联。具体的，所述存储器还包括位于所述栅极2上方的第二共接金属层60，同一有源区11中的漏极112对应的位线BL穿过第二通孔32和所述第一共接金属层50并通过所述磁性隧道结20在第二共接金属层60实现互联。
具体的，所述第一共接金属层50包括多个金属条，所述金属条沿水平方向间隔排列，且相邻的两个金属条中，一个金属条连接有字线L，另一个金属条连接有位线BL。
第二方面，本发明提供一种存储器的制作方法，结合图1、图3至图7，包括：
步骤S102：提供衬底1，并在所述衬底1的上方形成沿横向水平间隔排列的有源区11和浅沟道隔离区12。
其中，所述衬底1的材料为硅单晶。
步骤S104：在完成步骤S102后，在所述有源区11的上方沿纵向形成连接相邻的有源区11的栅极2和侧墙4，且所述栅极2两侧的有源区11分别为源极111和漏极112。
所述侧墙4的材料包括：氮化硅或氧化硅。在本实施例中，所述侧墙4的材料为氮化硅；所述栅极2的材料为非单晶硅。
步骤S106：在完成步骤S104后，沉积金半接触合金层7。
所述金半接触合金层7的材料包括：钴、镍或钴镍合金，但不限于此，在本实施例中所述金半接触合金层7的材料为钴。
步骤S108：在完成步骤106后，沉积钝化层8。
所述钝化层8的材料包括：氮化硅或氧化硅，但不限于此，在本实施例中所述钝化层8的材料为氮化硅。所述钝化层8的设置能够增加所述栅极2与所述第一共接金属层50的间距，从而能够降低栅极2的侧墙4漏电的风险；同时也作为化学机械抛光(CMP、Chemical Mechanical Polishing)工艺的阻挡层。
步骤S110：在完成步骤S108后，沉积第一中间介质绝缘层91。
步骤S112：在完成步骤S110后，去除所述源极111正上方的第一中间介质绝缘层91和对应位置处的钝化层8，以露出所述源极111正上方的金半接触合金层7。
步骤S114：在完成步骤S112后，依次沉积掩埋层6和互联金属层5，以将同一栅极2的源极111互联，并定义出连接源极111的源极线SL。
所述掩埋层6的材料包括：钽、氮化钽、钛、氮化钛、钽和氮化钽合金，或钛和氮化钛的合金，但不限于此；所述互联金属层5的材料包括：铜、银或铝，但不限于此。在本实施例中，所述掩埋层6的材料为钛作为所述互联金属层5的阻挡层；所述互联金属层5的材料为铜。
步骤S116：在完成步骤S114后，研磨所述掩埋层6和所述互联金属层5，以露出所述钝化层8。
步骤S118：在完成步骤S116后，沉积绝缘的互联金属层钝化层10。
所述互联金属层钝化层10的材料包括：氮化硅或氮氧化硅，但不限于此。在本实施例中所述互联金属层钝化层10的材料为氮化硅，且所述华联金属钝化层8的厚度为40nm。
步骤S120：在完成步骤S118后，沉积第二中间介质绝缘层92。
其中，所述第一中间介质绝缘层91和第二中间介质绝缘层92的材料均为氧化硅。
步骤S122：在完成步骤S120后，开设贯穿所述第二中间介质绝缘层92且连通至所述栅极2的第一通孔31，和贯穿所述第二中间介质绝缘层92且连通至所述漏极112的第二通孔32，并设置穿过所述第一通孔31且所述栅极2连接的第一金属层501，即为字线WL，和穿过所述第二通孔32且与所述漏极112连接的第二金属层502。
具体的，在所述第二中间介质绝缘层92的上方得到第一共接金属层50。所述第一共接金属层50包括多个金属条，所述金属条沿水平方向间隔排列，且相邻的两个金属条中，一个金属条为穿过所述第一通孔31且所述栅极2连接的金属层，即所述第一金属层501，为字线WL；另一个金属条为穿过所述第二通孔32且与所述漏极112连接的金属层，即所述第二金属层502。
步骤S124：在完成步骤S122后，在所述第二中间介质绝缘层92上方设置有与所述漏极112连接的金属层通过第三通孔33连接的磁性隧道结20，并在所述磁性隧道结20的上方设置第二共接金属层60，即为位线BL。
在本实施例中，所述第一通孔31、所述第二通孔32和所述第三通孔33中均填充有铜，但不限于此。
所述存储器的制作方法仅通过互联金属层5实现共联栅极2的源极111互联，规避了通孔与多晶硅栅极的间距以及通孔尺寸的设计规则要求，减小设计 面积提升密度。
在所述有源区11的上方形成连接相邻的有源区11的栅极2的步骤之前，所述方法还包括：通过沉积和光刻工艺得到栅极氧化层30。其中，所述栅极氧化层30的材料包括：氧化硅或氧化铪，但不限于此，在本实施例中所述栅极氧化层30的材料为氧化硅。
第三方面，本发明提供一种存储器的制作方法，结合图1、图8至图11，包括：
步骤S202：提供衬底1，并在所述衬底1的上方形成水平间隔排列的有源区11和浅沟道隔离区12。
其中，所述衬底1的材料为硅单晶。
步骤S204：在完成步骤S102后，在所述有源区11的上方形成连接相邻的有源区11的栅极2和侧墙4，且所述栅极2两侧的有源区11分别为源极111和漏极112。
所述侧墙4的材料包括：氮化硅或氧化硅，但不限于此。在本实施例中，所述侧墙4的材料为氮化硅；所述栅极2的材料为非单晶硅。
步骤S206：在完成步骤S204后，沉积金半接触合金层7。
所述金半接触合金层7的材料包括：钴、镍或钴镍合金，但不限于此，在本实施例中所述金半接触合金层7的材料为钴。
步骤S208：在完成步骤S206后，沉积钝化层8。
所述钝化层8的材料包括：氮化硅或氧化硅，但不限于此，在本实施例中所述钝化层8的材料为氮化硅。
步骤S210：在完成步骤S208后，通过光刻及刻蚀工艺去除所述栅极2正上方的钝化层8、所述栅极2正上方的金半接触合金层7和所述栅极2的顶部， 在所述栅极2正上方通过沉积工艺得到牺牲氧化层40。
步骤S212：在完成步骤S210后，沉积第一中间介质绝缘层91。
步骤S214：在完成步骤S212后，去除所述源极111正上方的第一中间介质绝缘层91和对应位置处的钝化层8，以露出所述源极111正上方的金半接触合金层7，并去除所述栅极2正上方的第一中间介质绝缘层91和牺牲氧化层40。
步骤S216：在完成步骤S214后，依次沉积掩埋层6和互联金属层5，以将同一栅极2的源极111互联，并定义出连接源极111的源极线SL。
所述掩埋层6的材料包括：钽、氮化钽、钛、氮化钛、钽和氮化钽合金，或钛和氮化钛的合金，但不限于此；所述互联金属层5的材料包括：铜、银或铝，但不限于此。在本实施例中所述掩埋层6的材料为钛作为所述互联金属层5的阻挡层；所述互联金属层5的材料为铜。
步骤S218：在完成步骤S216后，研磨所述掩埋层6和所述互联金属层5，以露出所述钝化层8。
步骤S220：在完成步骤S218后，沉积绝缘的互联金属层钝化层10。
所述互联金属层钝化层10的材料包括：氮化硅或氮氧化硅，但不限于此。在本实施例中所述互联金属层钝化层10的材料为氮化硅，且所述华联金属钝化层8的厚度为40nm。
步骤S222：在完成步骤S220后，沉积第二中间介质绝缘层92。
其中，所述第一中间介质绝缘层91和第二中间介质绝缘层92的材料均为氧化硅。
步骤S224：在完成步骤S222后，开设贯穿所述第二中间介质绝缘层92且连通至所述栅极2的第一通孔31，和贯穿所述第二中间介质绝缘层92且连 通至所述漏极112的第二通孔32，并设置穿过所述第一通孔31且所述栅极2连接的金属层，即为字线WL，和穿过所述第二通孔32且与所述漏极112连接的金属层。
步骤S226：在完成步骤S224后，在所述第二中间介质绝缘层92上方设置有与所述漏极112连接的金属层连接的磁性隧道结20，并在所述磁性隧道结20的上方设置第二共接金属层60，即为位线BL。
在本实施例中，所述第一通孔31、所述第二通孔32和所述第三通孔33中均填充有铜。
所述方法还包括：在所述第二中间介质绝缘层92的上方得到第一共接金属层50。所述第一共接金属层50包括多个金属条，所述金属条沿水平方向间隔排列，且相邻的两个金属条中，一个金属条连接有字线ZL，即所述第一金属层501；另一个金属条连接有位线BL，即所述第二金属层502。在所述磁性隧道结20的正上方得到第二共接金属层60。
所述存储器的制作方法仅通过互联金属层5实现共联栅极2的源极111互联，规避了多晶硅栅极与通孔间距和通孔尺寸的设计规则，缩小了位元面积提升存储密度。
同时，在栅极2的上方沉积掩埋层6和互联金属层5能够减小因字线WL的阻值带来的延迟。
所述依次沉积掩埋层6和互联金属层5的步骤，包括：采用自对准工艺，并利用所述钝化层8作为刻蚀阻挡层，依次沉积掩埋层6和互联金属层5。
在所述有源区11的上方形成连接相邻的有源区11的栅极2的步骤之前，所述方法还包括：通过沉积和光刻工艺得到栅极氧化层30。其中，所述栅极氧化层30的材料包括：氧化硅或氧化铪，但不限于此，在本实施例中所述栅 极氧化层30的材料为氧化硅。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应该以权利要求的保护范围为准。

Claims (10)

  1. 一种存储器，其特征在于，包括存储单元、有源区、栅极、互联金属层和浅沟道隔离区；
    所述浅沟道隔离区与所述有源区水平间隔排列；
    所述栅极设置在所述有源区上方，所述栅极与所述有源区相互垂直；
    每个所述有源区包括多个源极和多个漏极，每一个栅极与多个所述有源区形成多个共栅的晶体管，同一所述有源区中的相邻晶体管共用源极或漏极；
    所述互联金属层位于所述源极上方以及相邻的栅极之间，以将共栅的晶体管的源极互联。
  2. 根据权利要求1所述的存储器，其特征在于，所述互联金属层位于所述浅沟道隔离区的上方。
  3. 根据权利要求1所述的存储器，其特征在于，所述互联金属层的侧面和底面均包裹有掩埋层。
  4. 根据权利要求1所述的存储器，其特征在于，所述存储器设置有源极线，所述源极线为所述互联金属层。
  5. 根据权利要求1所述的存储器，其特征在于，所述存储器还设置有位线，
    同一有源区中的漏极通过所述位线互联。
  6. 根据权利要求5所述的存储器，其特征在于，所述存储单元包括：磁性隧道结；
    每一所述漏极均连接一个所述磁性隧道结。
  7. 根据权利要求1所述的存储器，其特征在于，所述存储器还设置有字 线，且共联栅极的字线互联。
  8. 一种如权利要求1至7任一项所述的存储器的制作方法，其特征在于，包括：
    步骤S102：提供衬底，并在所述衬底的上方形成水平间隔排列的有源区和浅沟道隔离区；
    步骤S104：在完成步骤S102后，在所述有源区的上方沿纵向形成栅极，且同一列的栅极互联，所述有源区包括多个源极和多个漏极，互联的栅极两侧分别为源极和漏极；
    步骤S106：在完成步骤S104后，沉积金半接触合金层；
    步骤S108：在完成步骤106后，沉积钝化层；
    步骤S110：在完成步骤S108后，沉积第一中间介质绝缘层；
    步骤S112：在完成步骤S110后，去除所述源极正上方的第一中间介质绝缘层和对应位置处的钝化层，以露出所述源极正上方的金半接触合金层；
    步骤S114：在完成步骤S112后，依次沉积掩埋层和互联金属层，以将同一栅极的源极互联，并定义出连接源极的源极线；
    步骤S116：在完成步骤S114后，研磨所述掩埋层和所述互联金属层，以露出所述钝化层；
    步骤S118：在完成步骤S116后，沉积绝缘的互联金属层钝化层；
    步骤S120：在完成步骤S118后，沉积第二中间介质绝缘层；
    步骤S122：在完成步骤S120后，开设贯穿所述第二中间介质绝缘层且连通至所述栅极的第一通孔，和贯穿所述第二中间介质绝缘层且连通至所述漏极的第二通孔，并设置通过所述第一通孔且与所述栅极连接的第一金属层，即为字线，和穿过所述第二通孔且与所述漏极连接的第二金属层；
    步骤S124：在完成步骤S122后，在所述第二中间介质绝缘层上方设置有与所述第二金属层连接的磁性隧道结，并在所述磁性隧道结的上方设置第二共接金属层，即为位线。
  9. 根据权利要求8所述的方法，其特征在于，在所述沉积第一中间介质绝缘层的步骤前，所述方法进一步包括：
    通过光刻及刻蚀工艺去除所述栅极正上方的钝化层、所述栅极正上方的金半接触合金层和所述栅极的顶部，在所述栅极正上方通过沉积工艺得到牺牲氧化层；
    所述去除所述源极正上方的第一中间介质绝缘层和所述源极正上方的钝化层，以露出所述金半接触合金层的步骤包括：
    去除所述源极正上方的第一中间介质绝缘层和所述源极正上方的钝化层，以露出所述源极正上方的金半接触合金层，并去除所述栅极正上方的第一中间介质绝缘层和牺牲氧化层。
  10. 根据权利要求8所述的方法，其特征在于，所述依次沉积掩埋层和互联金属层，包括：采用自对准工艺，并利用所述钝化层作为刻蚀阻挡层，依次沉积掩埋层和互联金属层。
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