WO2021109073A1 - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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WO2021109073A1
WO2021109073A1 PCT/CN2019/123298 CN2019123298W WO2021109073A1 WO 2021109073 A1 WO2021109073 A1 WO 2021109073A1 CN 2019123298 W CN2019123298 W CN 2019123298W WO 2021109073 A1 WO2021109073 A1 WO 2021109073A1
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semiconductor layer
type semiconductor
gan
manufacturing
type
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PCT/CN2019/123298
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English (en)
French (fr)
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程凯
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苏州晶湛半导体有限公司
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Priority to US17/632,209 priority Critical patent/US20220285585A1/en
Priority to PCT/CN2019/123298 priority patent/WO2021109073A1/zh
Priority to CN201980102497.9A priority patent/CN114730703A/zh
Priority to TW109142502A priority patent/TWI792110B/zh
Publication of WO2021109073A1 publication Critical patent/WO2021109073A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/16—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape

Definitions

  • This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof.
  • III-Nitride is the third-generation new semiconductor material after the first and second-generation semiconductor materials such as Si and GaAs.
  • GaN has many advantages as a wide-gap semiconductor material, such as high saturation drift speed, high breakdown voltage, It has excellent carrier transport performance and can form AlGaN, InGaN ternary alloys and AlInGaN quaternary alloys, and it is easy to fabricate GaN-based PN junctions.
  • GaN-based materials and semiconductor devices have received extensive and in-depth research in recent years, and the growth of GaN-based materials by MOCVD technology is becoming more and more mature.
  • optoelectronic devices such as GaN-based LEDs and LDs and microelectronics such as GaN-based HEMTs The research on the device has made remarkable achievements and considerable development.
  • One of the problems is that it is difficult to fabricate contact electrodes on the P-type GaN-based semiconductor layer.
  • the purpose of the present invention is to provide a semiconductor structure and a manufacturing method thereof to improve the performance of a GaN-based semiconductor device.
  • one aspect of the present invention provides a manufacturing method of a semiconductor structure, including:
  • a P-type semiconductor layer is provided, the P-type semiconductor layer includes a GaN-based material, and the upper surface is a Ga surface;
  • the first N-type semiconductor layer includes a GaN-based material, and the upper surface is an N-face;
  • a part of the first N-type semiconductor layer is removed by wet etching, exposing the P-type semiconductor layer.
  • GaN crystal has a brazine structure, in which the Ga and N atomic layers are stacked in ABABAB hexagonal layers, and each Ga(N) atom forms a bond with the surrounding 4 N(Ga) atoms in a diamond-like tetrahedral structure. It should be noted that, taking Ga-N bonds parallel to the C axis ([0001] crystal orientation) as a reference, if the Ga atoms in each Ga-N bond are farther away from the lower surface, the upper surface is the Ga plane; The N atoms in a Ga-N bond are farther away from the lower surface, and the upper surface is the N surface.
  • P-type doping ions in the P-type semiconductor layer are activated.
  • the P-type semiconductor layer is located on the second N-type semiconductor layer; wet-etched is the first N-type semiconductor layer in the base region;
  • the manufacturing method further includes: removing the first N-type semiconductor layer and the P-type semiconductor layer in the collector region by dry etching, and exposing the second N-type semiconductor layer.
  • providing a P-type semiconductor layer includes: providing a semiconductor substrate, and forming a second N-type semiconductor layer on the semiconductor substrate; and forming the P-type semiconductor layer on the second N-type semiconductor layer;
  • a collector is formed on the second N-type semiconductor layer in the collector region, a base is formed on the P-type semiconductor layer in the base region, and an emitter is formed on the first N-type semiconductor layer in the emitter region .
  • forming a first N-type semiconductor layer with an N-side upper surface on the P-type semiconductor layer is achieved by connecting the Ga surface of the first N-type semiconductor layer directly with the Ga surface of the P-type semiconductor layer. Bond.
  • forming a first N-type semiconductor layer whose upper surface is an N-side on the P-type semiconductor layer is passed: in the process of forming the first N-type semiconductor layer, the first N-type semiconductor layer is reversed by polarity. The N side of the N-type semiconductor layer faces upward.
  • Another aspect of the present invention provides a semiconductor structure, including:
  • the P-type semiconductor layer and the first N-type semiconductor layer distributed from bottom to top; among them:
  • the P-type semiconductor layer includes a GaN-based material, and the upper surface is a Ga surface; the first N-type semiconductor layer includes a GaN-based material, and the upper surface is an N-plane; a partial region of the Ga surface of the P-type semiconductor layer exposed.
  • it further includes a second N-type semiconductor layer, the P-type semiconductor layer is located on the second N-type semiconductor layer; the second N-type semiconductor layer in the collector region and the P-type semiconductor layer in the base region are exposed .
  • the exposed second N-type semiconductor layer has a collector, the P-type semiconductor layer has a base, and the first N-type semiconductor layer has an emitter.
  • the present invention has the following beneficial effects:
  • a P-type semiconductor layer is provided first, the P-type semiconductor layer includes a GaN-based material; and then a first N-type semiconductor layer is formed on the P-type semiconductor layer, and the first N-type semiconductor layer includes GaN Base material; wherein, in the provided P-type semiconductor layer, the control upper surface is a Ga surface; when forming the first N-type semiconductor layer, the control upper surface is an N surface.
  • the etching starts from the N surface of the first N-type semiconductor layer and automatically stops on the Ga surface of the P-type semiconductor layer, thereby avoiding over-etching.
  • the P-type dopant ions in the P-type semiconductor layer are activated.
  • This solution can provide an escape path for the released H atoms and improve the quality of the PN junction. This is because: MOCVD (Metal-organic Chemical Vapor Deposition) technology grows P-type GaN-based materials, MOCVD growth There are a large number of H atoms in the environment.
  • MOCVD Metal-organic Chemical Vapor Deposition
  • the acceptor dopant Mg in GaN will be passivated by a large number of H atoms without generating holes; in addition, a large number of passivated and unbonded Mg ions will enter
  • the N-type GaN-based material layer grown on it causes the PN junction junction to be blurred, and part of the N-type GaN-based material layer is compensated and the electron concentration is reduced. In severe cases, the PN junction will fail.
  • the P-type semiconductor layer is located on the second N-type semiconductor layer; the first N-type semiconductor layer in the base region is wet-etched;
  • the manufacturing method further includes: dry etching removing the first N-type semiconductor layer and the P-type semiconductor layer in the collector region, and exposing the second N-type semiconductor layer.
  • the semiconductor structure fabricated in the present invention can be a PN junction or an NPN bipolar transistor.
  • a first N-type semiconductor layer with an N-side upper surface is formed on the P-type semiconductor layer through: a) The Ga surface of the first N-type semiconductor layer is directly bonded to the Ga surface of the P-type semiconductor layer ⁇ ; or b) in the process of forming the first N-type semiconductor layer, the N side of the first N-type semiconductor layer is facing upwards by means of polarity inversion. Studies have shown that the above two methods are reliable.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure according to a first embodiment of the present invention
  • FIG. 2 is a flowchart of a manufacturing method of the semiconductor structure in FIG. 1;
  • FIG. 3 is a schematic structural diagram of a semiconductor structure according to a second embodiment of the present invention.
  • FIG. 4 is a flowchart of a manufacturing method of the semiconductor structure in FIG. 3;
  • FIG. 5 is a flowchart of a manufacturing method of a semiconductor structure according to a third embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a semiconductor structure according to a fourth embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a semiconductor structure according to a fifth embodiment of the present invention.
  • FIG. 8 is a flowchart of a manufacturing method of the semiconductor structure in FIG. 7;
  • FIG. 9 is a schematic structural diagram of a semiconductor structure according to a sixth embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram of a semiconductor structure according to a seventh embodiment of the present invention.
  • P-type semiconductor layer 11 The upper surface 11a of the P-type semiconductor layer
  • the upper surface 12a of the first N-type semiconductor layer The first N-type semiconductor layer 12
  • FIG. 1 is a schematic structural diagram of a semiconductor structure according to a first embodiment of the present invention.
  • the semiconductor structure 1 includes:
  • the semiconductor substrate 10, the P-type semiconductor layer 11 and the first N-type semiconductor layer 12 distributed from bottom to top; among them:
  • the P-type semiconductor layer 11 includes a GaN-based material, and the upper surface 11a is a Ga surface; the first N-type semiconductor layer 12 includes a GaN-based material, and the upper surface 12a is an N-surface; a part of the Ga surface of the P-type semiconductor layer 11 is exposed .
  • the P-type semiconductor layer 11 and the first N-type semiconductor layer 12 in this embodiment form a PN junction.
  • the semiconductor substrate 10 may be sapphire, silicon carbide, silicon, GaN, or diamond.
  • the GaN-based material may be at least one of GaN, AlGaN, InGaN, and AlInGaN.
  • the upper surface 11a of the P-type semiconductor layer 11 being a Ga plane means that the Ga-N bond parallel to the C axis ([0001] crystal orientation) is used as a reference, and the Ga atoms in each Ga-N bond are farther away from the semiconductor substrate 10. It can be understood that, at this time, the lower surface of the P-type semiconductor layer 11 is an N-plane.
  • the upper surface 12a of the first N-type semiconductor layer 12 being an N-plane means that the Ga-N bond parallel to the C axis ([0001] crystal orientation) is used as a reference, and the N atoms in each Ga-N bond are farther away from the semiconductor The substrate 10. It can be understood that, at this time, the lower surface of the first N-type semiconductor layer 12 is a Ga surface.
  • the exposed area of the upper surface 11a of the P-type semiconductor layer 11 and the upper surface 12a of the first N-type semiconductor layer 12 may form an electrical connection structure, such as a metal interconnection structure, to separately connect the P-type semiconductor layer 11 and the first N-type semiconductor layer 12 The electrical signal of layer 12 is led out.
  • Figure 2 is a flow chart of the manufacturing method.
  • step S1 referring to FIG. 2 and FIG. 1, a P-type semiconductor layer 11 is formed on the semiconductor substrate 10.
  • the P-type semiconductor layer 11 includes a GaN-based material, and the upper surface 11a is a Ga surface.
  • the semiconductor substrate 10 may be sapphire, silicon carbide, silicon, GaN, or diamond, etc., which is not limited in this embodiment.
  • the GaN-based material of the P-type semiconductor layer 11 may be at least one of GaN, AlGaN, InGaN, and AlInGaN, which is not limited in this embodiment.
  • the material of the P-type semiconductor layer 11 is GaN as an example, and it can be grown by MOCVD technology.
  • NH 3 and TMGa are N source and Ga source, respectively, and H 2 is a carrier gas.
  • P-type ion doping can be performed while growing GaN, the P-type ion can be Mg, and the Mg source can be CP 2 Mg.
  • the P-type doping ion may be at least one of calcium, carbon, beryllium, yttrium, and zinc.
  • a buffer layer may be grown on the semiconductor substrate 10 first, and then a P-type semiconductor layer 11 may be grown on the buffer layer.
  • the arrangement of the buffer layer can reduce the screw dislocation (TD) density in the P-type semiconductor layer 11 and the TD bending due to the lateral growth mechanism.
  • the upper surface 11a of the P-type semiconductor layer 11 can be realized as a Ga surface by: in the process of forming the P-type semiconductor layer 11, the Ga surface of the P-type semiconductor layer 11 faces upward through epitaxial growth.
  • step S2 still referring to FIG. 2 and FIG. 1, a first N-type semiconductor layer 12 is formed on the P-type semiconductor layer 11, the first N-type semiconductor layer 12 includes a GaN-based material, and the upper surface 12a is an N-face .
  • the GaN-based material of the first N-type semiconductor layer 12 refers to the GaN-based material of the P-type semiconductor layer 11, and the two materials may be the same or different.
  • the material of the first N-type semiconductor layer 12 is GaN as an example, which can be grown by MOCVD technology.
  • NH 3 and TMGa are N source and Ga source, respectively, and H 2 is a carrier gas.
  • the N-type dopant ion may be at least one of silicon, germanium, and oxygen.
  • the upper surface 12a of the first N-type semiconductor layer 12 can be realized as an N-surface by directly bonding the Ga surface of the first N-type semiconductor layer 12 with the Ga surface of the P-type semiconductor layer 11.
  • the first N-type semiconductor layer 12 epitaxial layer for bonding can be prepared by the following method: a sacrificial layer is provided during the process of preparing an epitaxial layer of GaN-based material with a Ga surface on the upper surface, and then the sacrificial layer Continue to prepare an epitaxial layer of GaN-based material with a predetermined thickness on the upper surface of the Ga surface.
  • the sacrificial layer can be, for example, porous GaN, H-implanted GaN, or the like.
  • the GaN-based material epitaxial layer with the upper surface of the sacrificial layer can be peeled from the sacrificial layer, and the GaN-based material epitaxial layer with the upper surface of the Ga surface after the peeling is in contact with the sacrificial layer
  • the face is the N face.
  • the upper surface 12a of the first N-type semiconductor layer 12 can be realized as an N-face: in the process of forming the first N-type semiconductor layer 12, the first N-type semiconductor layer 12 is reversed by polarity. The N side is facing up.
  • the polarity reversal method refers to: first epitaxially grow the first N-type semiconductor layer 12 whose upper surface 12a is a Ga surface; then add a polarity reversal element during the epitaxial growth, such as Mg, etc., to achieve The N side is facing up.
  • step S3 still referring to FIG. 2 and FIG. 1, the first N-type semiconductor layer 12 in a part of the area is removed by wet etching, and the P-type semiconductor layer 11 is exposed.
  • the wet etching solution is, for example, a KOH solution, which is corrosive on the N surface but non-corrosive on the Ga surface. Since the upper surface of the P-type semiconductor layer 11 is a Ga surface, the etching process can automatically stop on the upper surface of the P-type semiconductor layer 11 without over-etching the P-type semiconductor layer 11.
  • dry etching is generally used to pattern the first N-type semiconductor layer 12.
  • the P-type semiconductor layer 11 will be over-etched.
  • nitrogen atoms in the GaN-based material preferentially escape, resulting in an increase in the number of electron carriers in the P-type semiconductor layer 11, which will neutralize part of the hole carriers, resulting in hole carriers The sub-concentration drops, and even the surface inversion appears. Therefore, compared to dry etching, wet etching can avoid the above-mentioned problems in the patterning process.
  • an electrical connection structure such as a metal interconnection structure, on the exposed area of the upper surface 11a of the P-type semiconductor layer 11 and the upper surface 12a of the first N-type semiconductor layer 12 to connect the P-type semiconductor layer 11 and the electrical signal of the first N-type semiconductor layer 12 are led out.
  • FIG. 3 is a schematic structural diagram of a semiconductor structure according to a second embodiment of the present invention.
  • the semiconductor structure 2 of the second embodiment is substantially the same as the semiconductor structure 1 of the first embodiment, except that the semiconductor substrate 10 is omitted.
  • FIG. 4 is a flowchart of a manufacturing method of the semiconductor structure in FIG. 3. 4, the manufacturing method of the second embodiment is substantially the same as the manufacturing method of the first embodiment. The only difference is: Step S1': a P-type semiconductor layer 11 is provided, and the P-type semiconductor layer 11 includes a GaN-based material. The surface 11a is a Ga surface. In other words, the P-type semiconductor layer 11 of this embodiment may be a ready-made semiconductor intermediate structure.
  • FIG. 5 is a flowchart of a manufacturing method of a semiconductor structure according to a third embodiment of the present invention.
  • the manufacturing method of the third embodiment is substantially the same as the manufacturing methods of the first and second embodiments. The only difference is that a step S11 is added to activate the P-type dopant ions in the P-type semiconductor layer 11. Step S11 is performed between steps S1 and S2.
  • the P-type dopant ion can be magnesium, and the activation can be achieved by high-temperature annealing.
  • MOCVD technology grows P-type GaN-based materials, because there are a large number of H atoms in the MOCVD growth environment, if H atoms cannot be released, the acceptor dopant Mg in GaN easily forms covalent bonds with H atoms and cannot generate holes , Which is passivated by H atoms. In this step, the upper surface 11a of the P-type semiconductor layer 11 is not blocked, so H atoms are easily released.
  • a large number of P-type doped ions Mg can form covalent bonds with atoms in the GaN-based material, that is, are activated to avoid passivation.
  • a large amount of Mg forms covalent bonds with atoms in the GaN-based material, which can also prevent free Mg ions from entering the first N-type GaN-based material layer grown on it, thereby improving the quality of the PN junction.
  • FIG. 6 is a schematic structural diagram of a semiconductor structure according to a fourth embodiment of the present invention.
  • the semiconductor structure 3 of the fourth embodiment is substantially the same as the semiconductor structures 1 and 2 of the first, second, and third embodiments. The only difference is: the exposed area of the upper surface 11a of the P-type semiconductor layer 11 has a positive electrode 131, and the first N-type The upper surface 12 a of the semiconductor layer 12 has a negative electrode 132.
  • Both the positive electrode 131 and the P-type semiconductor layer 11, and the negative electrode 132 and the first N-type semiconductor layer 12 are in ohmic contact.
  • the material of the positive electrode 131 and the negative electrode 132 can be a metal or a semiconductor material with good conductivity after doping.
  • the manufacturing method includes: step S4, forming a positive electrode 131 on the exposed area of the upper surface 11a of the P-type semiconductor layer 11, and forming a negative electrode 132 on the upper surface 12a of the first N-type semiconductor layer 12.
  • the formation method of the positive electrode 131 and the negative electrode 132 may be electroplating or metal deposition.
  • FIG. 7 is a schematic structural diagram of a semiconductor structure according to a fifth embodiment of the present invention.
  • the semiconductor structure 4 of the fifth embodiment is substantially the same as the semiconductor structures 1 and 3 of the first, second, and fourth embodiments.
  • the semiconductor substrate 10 is a second N-type semiconductor layer 14;
  • the N-type semiconductor layer 12 is located in the emitter region 1c, and the second N-type semiconductor layer 14 in the collector region 1a and the P-type semiconductor layer 11 in the base region 1b are exposed.
  • the semiconductor structure 4 includes:
  • the second N-type semiconductor layer 14, the P-type semiconductor layer 11 and the first N-type semiconductor layer 12 are distributed from bottom to top.
  • the second N-type semiconductor layer 14, the P-type semiconductor layer 11 and the first N-type semiconductor layer 12 form an NPN bipolar transistor.
  • FIG. 8 is a flowchart of a manufacturing method of the semiconductor structure in FIG. 7. Referring to FIG. 8 and FIG. 2, the only difference lies in: step S01, providing a second N-type semiconductor layer 14; step S1", forming a P-type semiconductor layer 11 on the second N-type semiconductor layer 14, and a P-type semiconductor layer 11 It includes a GaN-based material, and the upper surface 11a is a Ga surface; step S21, dry etching removes the first N-type semiconductor layer 12 and the P-type semiconductor layer 11 in the collector region 1a, and exposes the second N-type semiconductor layer 14; step S3', the first N-type semiconductor layer 12 of the base region 1b is wet-etched to expose the P-type semiconductor layer 11.
  • the second N-type semiconductor layer 14 may be a GaN-based material, and the GaN-based material may be at least one of GaN, AlGaN, InGaN, and AlInGaN. This embodiment does not limit the direction of the GaN covalent bond in the second N-type semiconductor layer 14.
  • Step S21 is performed first, and then step S3' is performed.
  • the dry etching may be an ICP etching method
  • the reaction gas may be Cl2
  • the auxiliary gas may be N2.
  • the second N-type semiconductor layer 14 When the dry etching stops, the second N-type semiconductor layer 14 will be over-etched. However, during the dry etching process, nitrogen atoms in the GaN-based material preferentially escape, resulting in an increase in the number of electron carriers. The second N-type semiconductor layer 14 reduces the resistivity of the surface, which is beneficial to reduce the contact resistance of the electrical connection structure on the second N-type semiconductor layer 14.
  • FIG. 9 is a schematic structural diagram of a semiconductor structure according to a sixth embodiment of the present invention.
  • the semiconductor structure 5 of the sixth embodiment is substantially the same as the semiconductor structure 4 of the fifth embodiment. The only difference is: the exposed second N-type semiconductor layer 14 has a collector C, and the P-type semiconductor layer 11 has a base B. An N-type semiconductor layer 12 has an emitter E on it.
  • the materials of the collector C, the base B and the emitter E can all be metals or semiconductor materials with good conductivity after being doped.
  • FIG. 10 is a schematic structural diagram of a semiconductor structure according to a seventh embodiment of the present invention.
  • the semiconductor structure 6 of the seventh embodiment is substantially the same as the semiconductor structure 5 of the sixth embodiment and the semiconductor structure 4 of the fifth embodiment. The only difference is that it also includes a second N-type semiconductor layer 14, and a second N-type semiconductor layer 14 is included.
  • the type semiconductor layer 14 is located on the semiconductor substrate 10.
  • the method of forming the second N-type semiconductor layer 14 on the semiconductor substrate 10 may be the MOCVD method. This embodiment does not limit the direction of the GaN covalent bond in the second N-type semiconductor layer 14.

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Abstract

一种半导体结构及其制作方法，提供P型半导体层(11)，P型半导体层包括GaN基材料，且上表面(11a)为Ga面；在P型半导体层上形成第一N型半导体层(12)，第一N型半导体层包括GaN基材料，且上表面(12a)为N面；湿法刻蚀去除部分区域的第一N型半导体层，暴露所述P型半导体层。

Description

半导体结构及其制作方法 技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体结构及其制作方法。
背景技术
III-氮化物是继Si、GaAs等第一、第二代半导体材料之后的第三代新型半导体材料，其中GaN作为宽禁带半导体材料有许多优点，诸如饱和漂移速度高、击穿电压大、载流子输运性能优异以及能够形成AlGaN、InGaN三元合金和AlInGaN四元合金等，容易制作GaN基的PN结。鉴于此，近几年来GaN基材料和半导体器件得到了广泛和深入的研究，MOCVD技术生长GaN基材料日趋成熟；在半导体器件研究方面，GaN基LED、LDs等光电子器件以及GaN基HEMT等微电子器件方面的研究都取得了显著的成绩和长足的发展。
目前GaN基半导体器件仍有改进空间。问题之一在于：P型GaN基半导体层上的接触电极较难制作。
有鉴于此，实有必要提供一种新的半导体结构及其制作方法，以解决上述技术问题。
发明内容
本发明的发明目的是提供一种半导体结构及其制作方法，提高GaN基半导体器件的性能。
为实现上述目的，本发明一方面提供一种半导体结构的制作方法，包括：
提供P型半导体层，所述P型半导体层包括GaN基材料，且上表面为Ga面；
在所述P型半导体层上形成第一N型半导体层，所述第一N型半导体层包括GaN基材料，且上表面为N面；
湿法刻蚀去除部分区域的第一N型半导体层，暴露所述P型半导体层。
GaN晶体为钎锌矿结构，其中Ga、N原子层呈ABABAB六方层堆垛，每个Ga(N)原子都与周围的4个N(Ga)原子呈类金刚石四面体结构成键。需要说明的是，以平行于C轴([0001]晶向)的Ga-N键作为参照，若每一个Ga-N键中的Ga原子更远离下表面，则上表面为Ga面；若每一个Ga-N键中的N原子更远离下表面，则上表面为N面。
可选地，在所述P型半导体层上形成第一N型半导体层前，激活所述P型半导体层中的P型掺杂离子。
可选地，所述P型半导体层位于第二N型半导体层上；湿法刻蚀的为基极区域的所述第一N型半导体层；
所述制作方法还包括：干法刻蚀去除集电极区域的第一N型半导体层与P型半导体层，暴露第二N型半导体层。
可选地，提供P型半导体层包括：提供半导体衬底，在所述半导体衬底上形成第二N型半导体层；在所述第二N型半导体层上形成所述P型半导体层；
或包括：提供第二N型半导体层；在所述第二N型半导体层上形成所述P型半导体层。
可选地，在集电极区域的第二N型半导体层上形成集电极、在基极区 域的P型半导体层上形成基极，以及在发射极区域的第一N型半导体层上形成发射极。
可选地，在所述P型半导体层上形成上表面为N面的第一N型半导体层通过：将所述第一N型半导体层的Ga面直接与所述P型半导体层的Ga面键合。
可选地，在所述P型半导体层上形成上表面为N面的第一N型半导体层通过：形成第一N型半导体层的过程中，通过极性反转的方式使所述第一N型半导体层的N面朝上。
本发明另一方面提供一种半导体结构，包括：
自下而上分布的P型半导体层与第一N型半导体层；其中：
所述P型半导体层包括GaN基材料，且上表面为Ga面；所述第一N型半导体层包括GaN基材料，且上表面为N面；所述P型半导体层的Ga面的部分区域裸露。
可选地，还包括第二N型半导体层，所述P型半导体层位于所述第二N型半导体层上；集电极区域的第二N型半导体层与基极区域的P型半导体层裸露。
所述裸露的第二N型半导体层上具有集电极，P型半导体层上具有基极，所述第一N型半导体层上具有发射极。
与现有技术相比，本发明的有益效果在于：
1)本发明的半导体结构制作方法中，先提供P型半导体层，P型半导体层包括GaN基材料；再在P型半导体层上形成第一N型半导体层，第一N型半导体层包括GaN基材料；其中，所提供的P型半导体层中，控制上表面为Ga面；形成第一N型半导体层时，控制上表面为N面。利用湿法刻蚀的方向性，使得从第一N型半导体层的N面开始刻蚀，自动停止于P型半导体层的Ga面，从而避免过刻蚀。若采用干法刻蚀，干法刻蚀停止时，会对P型 半导体层过刻蚀；由于干法刻蚀过程中，GaN基材料中的氮原子优先逸出，造成电子载流子数量变多，对于P型半导体层，会中和部分空穴载流子，造成空穴载流子浓度下降，甚至出现表面反型；因而相对于干法刻蚀，湿法刻蚀可以避免形成P型半导体层的电连接结构过程中的上述问题。
2)可选方案中，在P型半导体层上形成第一N型半导体层前，激活P型半导体层中的P型掺杂离子。本方案可以为释放的H原子提供逸出路径，提高PN结的质量，这是因为：MOCVD(Metal-organic Chemical Vapor Deposition，金属有机化合物化学气相沉积)技术生长P型GaN基材料时，MOCVD生长环境中存在大量的H原子，若不移除，GaN中的受主掺杂剂Mg会被大量H原子钝化而不产生空穴；此外，大量的被钝化、未成键的Mg离子会进入其上面生长的N型GaN基材料层，造成PN结结面模糊并使得部分N型GaN基材料层被补偿、电子浓度降低，严重时会造成PN结失效。
3)可选方案中，P型半导体层位于第二N型半导体层上；湿法刻蚀的为基极区域的第一N型半导体层；
制作方法还包括：干法刻蚀去除集电极区域的第一N型半导体层与P型半导体层，暴露第二N型半导体层。换言之，本发明制作的半导体结构可以为PN结，也可以为NPN双极晶体管。
4)可选方案中，在P型半导体层上形成上表面为N面的第一N型半导体层通过：a)将第一N型半导体层的Ga面直接与P型半导体层的Ga面键合；或b)形成第一N型半导体层的过程中，通过极性反转的方式使第一N型半导体层的N面朝上。研究表明，上述两种方法工艺可靠。
附图说明
图1是本发明第一实施例的半导体结构的结构示意图；
图2是图1中的半导体结构的制作方法的流程图；
图3是本发明第二实施例的半导体结构的结构示意图；
图4是图3中的半导体结构的制作方法的流程图；
图5是本发明第三实施例的半导体结构的制作方法的流程图；
图6是本发明第四实施例的半导体结构的结构示意图；
图7是本发明第五实施例的半导体结构的结构示意图；
图8是图7中的半导体结构的制作方法的流程图；
图9是本发明第六实施例的半导体结构的结构示意图；
图10是本发明第七实施例的半导体结构的结构示意图。
为方便理解本发明，以下列出本发明中出现的所有附图标记：
半导体结构1、2、3、4、5、6  半导体衬底10
P型半导体层11               P型半导体层的上表面11a
第一N型半导体层的上表面12a  第一N型半导体层12
正电极131                   负电极132
第二N型半导体层14           集电极区域1a
基极区域1b                  发射极区域1c
集电极C                     基极B
发射极E
具体实施方式
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图1是本发明第一实施例的半导体结构的结构示意图。
参照图1所示，半导体结构1包括：
自下而上分布的半导体衬底10、P型半导体层11以及第一N型半导体层12；其中：
P型半导体层11包括GaN基材料，且上表面11a为Ga面；第一N型半导体层12包括GaN基材料，且上表面12a为N面；P型半导体层11的Ga面的部分区域裸露。
可以看出，本实施例中的P型半导体层11与第一N型半导体层12形成PN结。
半导体衬底10可以为蓝宝石、碳化硅、硅、GaN或金刚石。
GaN基材料可以为GaN、AlGaN、InGaN、AlInGaN中的至少一种。
P型半导体层11的上表面11a为Ga面是指：以平行于C轴([0001]晶向)的Ga-N键作为参照，每一个Ga-N键中的Ga原子更远离半导体衬底10。可以理解的是，此时，P型半导体层11的下表面为N面。
第一N型半导体层12的上表面12a为N面是指：以平行于C轴([0001]晶向)的Ga-N键作为参照，每一个Ga-N键中的N原子更远离半导体衬底10。可以理解的是，此时，第一N型半导体层12的下表面为Ga面。
P型半导体层11的上表面11a的裸露区域与第一N型半导体层12的上表面12a可以形成电连接结构，例如金属互连结构，以分别将P型半导体层11与第一N型半导体层12的电信号引出。
对于图1中的半导体结构1，本发明一实施例中提供了对应的制作方法。图2为制作方法的流程图。
首先，步骤S1：参照图2与图1所示，在半导体衬底10上形成P型半导体层11，P型半导体层11包括GaN基材料，且上表面11a为Ga面。
半导体衬底10可以为蓝宝石、碳化硅、硅、GaN或金刚石等，本实施例对此不加以限制。
P型半导体层11的GaN基材料可以为GaN、AlGaN、InGaN、AlInGaN中的至少一种，本实施例对此也不加以限制。
P型半导体层11的材料以GaN为例，可以通过MOCVD技术生长。示例性地，NH 3、TMGa分别为N源和Ga源，H 2为载气。具体地，可以边生长GaN，边进行P型离子掺杂，P型离子可以为Mg，Mg源可以为CP 2Mg。其它可选方案中，P型掺杂离子可以为钙、碳、铍、钇和锌中的至少一种。
一个可选方案中，可以先在半导体衬底10上生长缓冲层，再在缓冲层上生长P型半导体层11。缓冲层的设置可以减小P型半导体层11中的螺位错(TD)密度以及由于横向生长机制导致的TD弯曲。
一个可选方案中，实现P型半导体层11的上表面11a为Ga面可以通过：形成P型半导体层11的过程中，通过外延生长方式使P型半导体层11的Ga面朝上。
接着，步骤S2：仍参照图2与图1所示，在P型半导体层11上形成第一N型半导体层12，第一N型半导体层12包括GaN基材料，且上表面12a为N面。
第一N型半导体层12的GaN基材料参照P型半导体层11的GaN基材料，两者材料可以相同，也可以不同。
第一N型半导体层12的材料以GaN为例，可以通过MOCVD技术生长。示例性地，NH 3、TMGa分别为N源和Ga源，H 2为载气。N型掺杂离子可以为硅、锗和氧中的至少一种。
一个可选方案中，实现第一N型半导体层12的上表面12a为N面可以通过：将第一N型半导体层12的Ga面直接与P型半导体层11的Ga面键合。
在一个可选方案中，用于键合的第一N型半导体层12外延层，可通过 如下方法制备：制备上表面为Ga面的GaN基材料外延层过程中设置牺牲层，然后在该牺牲层上继续制备预定厚度的上表面为Ga面的GaN基材料外延层。该牺牲层可例如多孔GaN、H注入后的GaN等。制备完成后，通过退火等工艺，该牺牲层上方的上表面为Ga面的GaN基材料外延层可从牺牲层处剥离，剥离后的上表面为Ga面的GaN基材料外延层与牺牲层接触的面即为N面。
一个可选方案中，实现第一N型半导体层12的上表面12a为N面可以通过：形成第一N型半导体层12的过程中，通过极性反转方式使第一N型半导体层12的N面朝上。
极性反转方式是指：首先外延生长上表面12a为Ga面的第一N型半导体层12；接着在外延生长的同时添加极性反转元素，极性反转元素例如为Mg等，实现N面朝上。
此外，还可以：首先在P型半导体层11上制作极性反转层，材料例如为Al 2O 3；接着在极性反转层上继续生长GaN基材料，实现N面朝上。
再接着，步骤S3：仍参照图2与图1所示，湿法刻蚀去除部分区域的第一N型半导体层12，暴露P型半导体层11。
湿法刻蚀溶液例如为KOH溶液，它在N表面上是腐蚀性的，但在Ga表面上是非腐蚀性的。由于P型半导体层11的上表面为Ga面，因而刻蚀工序可以自动停止在P型半导体层11的上表面，不会出现对P型半导体层11的过刻蚀。
现有技术中，一般采用干法刻蚀对第一N型半导体层12进行图形化。干法刻蚀停止时，会对P型半导体层11过刻蚀。由于干法刻蚀过程中，GaN基材料中的氮原子优先逸出，造成P型半导体层11中的电子载流子数量变多，会中和部分空穴载流子，造成空穴载流子浓度下降，甚至出现表面反型。因而相对于干法刻蚀，湿法刻蚀可以避免图形化过程中的上述问题。
后续工序中，还可以继续在P型半导体层11的上表面11a的裸露区域 与第一N型半导体层12的上表面12a形成电连接结构，例如金属互连结构，以分别将P型半导体层11与第一N型半导体层12的电信号引出。
图3是本发明第二实施例的半导体结构的结构示意图。参照图3所示，本实施例二的半导体结构2与实施例一的半导体结构1大致相同，区别仅在于：省略了半导体衬底10。
需要说明的是，以平行于C轴([0001]晶向)的Ga-N键作为参照，若每一个Ga-N键中的Ga原子更远离下表面，则上表面为Ga面。
图4是图3中的半导体结构的制作方法的流程图。参照图4所示，本实施例二的制作方法与实施例一的制作方法大致相同，区别仅在于：步骤S1'：提供P型半导体层11，P型半导体层11包括GaN基材料，且上表面11a为Ga面。换言之，本实施例的P型半导体层11可以为现成的半导体中间结构。
图5是本发明第三实施例的半导体结构的制作方法流程图。参照图5与图2所示，本实施例三的制作方法与实施例一、二的制作方法大致相同，区别仅在于：增加步骤S11，激活P型半导体层11中的P型掺杂离子。步骤S11在步骤S1与S2之间进行。
P型掺杂离子可以为镁，激活可以通过高温退火实现。MOCVD技术生长P型GaN基材料时，由于MOCVD生长环境中存在大量的H原子，若H原子无法释放，则GaN中的受主掺杂剂Mg容易与H原子形成共价键而无法产生空穴，即被H原子钝化。本步骤P型半导体层11上表面11a无遮挡，因而容易释放H原子，大量P型掺杂离子Mg可与GaN基材料中的原子形成共价键，即被激活而避免钝化。
此外，大量的Mg与GaN基材料中的原子形成共价键，也能避免游离态的Mg离子进入其上面生长的第一N型GaN基材料层，提高PN结质量。
图6是本发明第四实施例的半导体结构的结构示意图。本实施例四的半导体结构3与实施例一、二、三的半导体结构1、2大致相同，区别仅在于： P型半导体层11的上表面11a的裸露区域具有正电极131，第一N型半导体层12的上表面12a具有负电极132。
正电极131与P型半导体层11之间，负电极132与第一N型半导体层12之间都为欧姆接触。
正电极131与负电极132的材料都可以为金属或经掺杂后导电性能佳的半导体材料。
对应地，对于制作方法，包括：步骤S4，在P型半导体层11的上表面11a的裸露区域形成正电极131，第一N型半导体层12的上表面12a形成负电极132。
正电极131与负电极132的形成方法可以为电镀或金属沉积法。
图7是本发明第五实施例的半导体结构的结构示意图。参照图7所示，本实施例五的半导体结构4与实施例一、二、四的半导体结构1、3大致相同，区别仅在于：半导体衬底10为第二N型半导体层14；第一N型半导体层12位于发射极区域1c，集电极区域1a的第二N型半导体层14与基极区域1b的P型半导体层11裸露。
其它实施例中，若省略半导体衬底10，则半导体结构4包括：
自下而上分布的第二N型半导体层14、P型半导体层11以及第一N型半导体层12。
可以看出，第二N型半导体层14、P型半导体层11与第一N型半导体层12形成NPN双极晶体管。
图8是图7中的半导体结构的制作方法的流程图。参照图8与图2所示，区别仅在于：步骤S01，提供第二N型半导体层14；步骤S1"，在第二N型半导体层14上形成P型半导体层11，P型半导体层11包括GaN基材料，且上表面11a为Ga面；步骤S21，干法刻蚀去除集电极区域1a的第一N型半导体层12与P型半导体层11，暴露第二N型半导体层14；步骤S3'，湿法 刻蚀基极区域1b的第一N型半导体层12，暴露P型半导体层11。
步骤S01中，第二N型半导体层14可以为GaN基材料，GaN基材料可以为GaN、AlGaN、InGaN、AlInGaN中的至少一种。本实施例不限定第二N型半导体层14中GaN共价键的方向。
先执行步骤S21，后执行步骤S3'。步骤S21中，干法刻蚀可以为ICP刻蚀法，反应气体可以为Cl2，辅助气体可以为N2。
干法刻蚀停止时，会对第二N型半导体层14过刻蚀，但由于干法刻蚀过程中，GaN基材料中的氮原子优先逸出，造成电子载流子数量变多，对于第二N型半导体层14，会降低表面的电阻率，有利于降低第二N型半导体层14上的电连接结构的接触电阻。
图9是本发明第六实施例的半导体结构的结构示意图。本实施例六的半导体结构5与实施例五的半导体结构4大致相同，区别仅在于：裸露的第二N型半导体层14上具有集电极C，P型半导体层11上具有基极B，第一N型半导体层12上具有发射极E。
集电极C与第二N型半导体层14之间，基极B与P型半导体层11之间，发射极E与第一N型半导体层12之间都为欧姆接触。
集电极C、基极B与发射极E的材料都可以为金属或经掺杂后导电性能佳的半导体材料。
图10是本发明第七实施例的半导体结构的结构示意图。参照图10所示，本实施例七的半导体结构6与实施例六的半导体结构5、实施例五的半导体结构4大致相同，区别仅在于：还包括第二N型半导体层14，第二N型半导体层14位于半导体衬底10上。
在半导体衬底10上形成第二N型半导体层14的方法，可以为MOCVD法。本实施例不限定第二N型半导体层14中GaN共价键的方向。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员， 在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (10)

  1. 一种半导体结构的制作方法，其特征在于，包括：
    提供P型半导体层(11)，所述P型半导体层(11)包括GaN基材料，且上表面(11a)为Ga面；
    在所述P型半导体层(11)上形成第一N型半导体层(12)，所述第一N型半导体层(12)包括GaN基材料，且上表面(12a)为N面；
    湿法刻蚀去除部分区域的第一N型半导体层(12)，暴露所述P型半导体层(11)。
  2. 根据权利要求1所述的半导体结构的制作方法，其特征在于，在所述P型半导体层(11)上形成第一N型半导体层(12)前，激活所述P型半导体层(11)中的P型掺杂离子。
  3. 根据权利要求1所述的半导体结构的制作方法，其特征在于，所述P型半导体层(11)位于第二N型半导体层(14)上；湿法刻蚀的为基极区域(1b)的所述第一N型半导体层(12)；
    所述制作方法还包括：干法刻蚀去除集电极区域(1a)的第一N型半导体层(12)与P型半导体层(11)，暴露第二N型半导体层(14)。
  4. 根据权利要求1所述的半导体结构的制作方法，其特征在于，提供P型半导体层(11)包括：提供半导体衬底(10)，在所述半导体衬底(10)上形成第二N型半导体层(14)；在所述第二N型半导体层(14)上形成所述P型半导体层(11)；
    或包括：提供第二N型半导体层(14)；在所述第二N型半导体层(14)上形成所述P型半导体层(11)。
  5. 根据权利要求3或4所述的半导体结构的制作方法，其特征在于，在集电极区域(1a)的第二N型半导体层(14)上形成集电极(C)、在基极区域(1b)的P型半导体层(11)上形成基极(B)，以及在发射极区域(1c)的第一N型半导体层(12)上形成发射极(E)。
  6. 根据权利要求1至4任一项所述的半导体结构的制作方法，其特征在于，在所述P型半导体层(11)上形成上表面(12a)为N面的第一N型半导体层(12)通过：将所述第一N型半导体层(12)的Ga面直接与所述P型半导体层(11)的Ga面键合。
  7. 根据权利要求1至4任一项所述的半导体结构的制作方法，其特征在于，在所述P型半导体层(11)上形成上表面(12a)为N面的第一N型半导体层(12)通过：形成第一N型半导体层(12)的过程中，通过极性反转的方式使所述第一N型半导体层(12)的N面朝上。
  8. 一种半导体结构，其特征在于，包括：
    自下而上分布的P型半导体层(11)与第一N型半导体层(12)；其中：
    所述P型半导体层(11)包括GaN基材料，且上表面(11a)为Ga面；所述第一N型半导体层(12)包括GaN基材料，且上表面(12a)为N面；所述P型半导体层(11)的Ga面的部分区域裸露。
  9. 根据权利要求8所述的半导体结构，其特征在于，还包括第二N型半导体层(14)，所述P型半导体层(11)位于所述第二N型半导体层(14)上；集电极区域(1a)的第二N型半导体层(14)与基极区域(1b)的P型半导体层(11)裸露。
  10. 根据权利要求9所述的半导体结构，其特征在于，所述裸露的第二N型半导体层(14)上具有集电极(C)，P型半导体层(11)上具有基极(B)，所述第一N型半导体层(12)上具有发射极(E)。
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