WO2021103500A1 - 比较器 - Google Patents

比较器 Download PDF

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Publication number
WO2021103500A1
WO2021103500A1 PCT/CN2020/097020 CN2020097020W WO2021103500A1 WO 2021103500 A1 WO2021103500 A1 WO 2021103500A1 CN 2020097020 W CN2020097020 W CN 2020097020W WO 2021103500 A1 WO2021103500 A1 WO 2021103500A1
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WO
WIPO (PCT)
Prior art keywords
tube
voltage
operational amplifier
stage operational
output terminal
Prior art date
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PCT/CN2020/097020
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English (en)
French (fr)
Inventor
季汝敏
Original Assignee
长鑫存储技术有限公司
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Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/287,496 priority Critical patent/US11683027B2/en
Priority to EP20892667.5A priority patent/EP3923473A4/en
Publication of WO2021103500A1 publication Critical patent/WO2021103500A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference
    • H03K5/1254—Suppression or limitation of noise or interference specially adapted for pulses generated by closure of switches, i.e. anti-bouncing devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H03K5/1506—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages
    • H03K5/15073—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages using a plurality of comparators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00156—Layout of the delay element using opamps, comparators, voltage multipliers or other analog building blocks

Definitions

  • This application relates to the field of integrated circuit technology, and in particular to a comparator.
  • the circuit at the output terminal of the first-stage operational amplifier circuit will pull down from a higher potential.
  • the potential of the output terminal of the first-stage operational amplifier circuit will be pulled up to a high potential again.
  • the rapid change of the output signal of the first-stage operational amplifier circuit in the comparator will be coupled to the first voltage VP to be compared, forming kickback noise, which will not only interfere with the voltage to be compared, but may also cause output errors.
  • the present invention provides a comparator including:
  • the first-stage operational amplifier circuit, the second-stage operational amplifier circuit, the bias circuit and the clamp circuit among them,
  • the first-stage operational amplifier circuit includes two voltage input terminals and one voltage output terminal; the two voltage input terminals of the first-stage operational amplifier circuit are used for inputting voltages to be compared;
  • the second-stage operational amplifier circuit is connected to the bias circuit and the voltage output terminal of the first-stage operational amplifier circuit
  • the clamping circuit is connected to the voltage output terminal of the first-stage operational amplifier circuit, and is used to clamp the highest voltage of the voltage output terminal of the first-stage operational amplifier circuit to a preset voltage.
  • the highest voltage of the voltage output terminal of the first-stage operational amplifier circuit can be clamped to the preset voltage.
  • the voltage variation range of the first-stage operational amplifier circuit's voltage output terminal Smaller can reduce the discharge delay of the voltage output terminal of the first-stage operational amplifier circuit, thereby improving the flip speed of the comparator; in addition, because the voltage change range of the voltage output terminal of the first-stage operational amplifier circuit is small, the first-stage The coupling effect of the voltage change of the voltage output terminal of the op amp circuit on the input voltage to be compared is also reduced accordingly, which can reduce the kickback noise of the input voltage to be compared, avoid interference to the voltage to be compared, and ensure the correctness of the output; at the same time;
  • the above-mentioned comparator also has the advantages of simple structure, low cost and easy implementation.
  • the first-stage operational amplifier circuit includes: a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, and a second NMOS tube; wherein,
  • the gate of the first PMOS tube is connected to the first voltage to be compared;
  • the gate of the second PMOS tube is connected to the second voltage to be compared;
  • the gate of the third PMOS tube is connected to the bias circuit, and the drain of the third PMOS tube is connected to the source of the first PMOS tube and the source of the second PMOS tube;
  • the gate and drain of the first NMOS tube are short-circuited and connected to the drain of the first PMOS tube, and the source of the first NMOS tube is grounded;
  • the gate of the second NMOS tube is connected to the gate of the first NMOS tube, and the drain of the second NMOS tube is connected to the drain of the second PMOS tube as the first stage operation.
  • the voltage output terminal of the amplifier circuit, and the source of the second NMOS transistor is grounded.
  • the clamp circuit includes a first switch tube, the control terminal and current input terminal of the first switch tube are connected to the voltage output terminal of the first stage operational amplifier circuit, and the first The current output terminal of a switch tube is connected with the gate of the second NMOS.
  • the first switch tube includes an NMOS tube.
  • the clamping circuit further includes a second switch tube, the control terminal and current input terminal of the second switch tube are connected to the voltage output terminal of the first stage operational amplifier, and the first The current output terminal of the second switch tube is connected with the voltage output terminal of the second-stage operational amplifier.
  • the second-stage operational amplifier circuit includes: a fourth PMOS tube and a third NMOS tube; wherein,
  • the gate of the fourth PMOS tube is connected to the bias circuit
  • the gate of the third NMOS tube is connected to the voltage output terminal of the first-stage operational amplifier circuit, and the drain of the third NMOS tube is connected to the drain of the fourth PMOS tube as the For the voltage output terminal of the second-stage operational amplifier circuit, the source of the third NMOS transistor is grounded.
  • the bias circuit includes: a fifth PMOS tube and a current source; wherein,
  • the gate of the fifth PMOS transistor is connected to the first-stage operational amplifier circuit and the second-stage operational amplifier circuit, and the drain of the fifth PMOS transistor is connected to the current source.
  • the clamp circuit includes a switch tube, the control terminal and current input terminal of the switch tube are connected to the voltage output terminal of the first-stage operational amplifier circuit, and the current output of the switch tube The terminal is connected with the output terminal of the second-stage operational amplifier circuit.
  • the switch tube includes an NMOS tube.
  • the clamp circuit includes a switch tube, the current input terminal of the switch tube is connected to the voltage output terminal of the first-stage operational amplifier circuit, and the control terminal of the switch tube is connected to the bias The voltage is connected, and the current output terminal of the switch tube is grounded.
  • the switch tube includes a PMOS tube or a PNP type transistor.
  • the clamping circuit includes: a first switching tube, a second switching tube, and a third switching tube; wherein,
  • the current input terminal of the first switch tube is connected to the voltage output terminal of the first-stage operational amplifier circuit, the control terminal of the first switch tube is connected to the current output terminal of the second switch tube and the first The current input ends of the three switch tubes are connected;
  • the control terminal of the second switch tube is connected to the bias circuit
  • the control terminal of the third switch tube is short-circuited with the current input terminal of the third switch tube, and the circuit output terminal of the third switch tube is grounded.
  • the first switch tube includes a PMOS tube or a PNP type transistor
  • the second switch tube includes a PMOS tube
  • the third switch tube includes an NMOS tube.
  • 1 to 5 are circuit diagrams of comparators in different embodiments of the invention.
  • a comparator of the present invention includes: a first-stage operational amplifier circuit 10, a second-stage operational amplifier circuit 11, a bias circuit 12, and a clamp circuit 13;
  • the first-stage operational amplifier circuit 10 includes two voltage input terminals and one voltage output terminal; the two voltage input terminals of the first-stage operational amplifier circuit 10 are used for inputting the voltage to be compared; the second-stage operational amplifier circuit 11 and the bias
  • the setting circuit 12 is connected to the voltage output terminal of the first-stage operational amplifier circuit 10; the clamping circuit 13 is connected to the voltage output terminal of the first-stage operational amplifier circuit 10, and the clamping circuit 13 is used to connect the first-stage operational amplifier circuit The highest voltage of the voltage output terminal of 10 is clamped to the preset voltage.
  • one input terminal of the first operational amplifier circuit 10 is used to input the first voltage VN to be compared, and the other input terminal of the first operational amplifier circuit 10 is used to input the second voltage VP to be compared.
  • the first-stage operational amplifier circuit 10 includes: a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a first NMOS tube MN1, and a second NMOS tube Tube MN2; wherein the gate of the first PMOS tube MP1 is connected to the first voltage to be compared VN; the gate of the second PMOS tube MP2 is connected to the second voltage to be compared VP; the gate of the third PMOS tube MP3 is connected to The bias circuit 12 is connected, the drain of the third PMOS tube MP3 is connected with the source of the first PMOS tube MP1 and the source of the second PMOS tube MP2; the gate of the first NMOS tube MN1 is shorted to the drain, And connected with the drain of the first PMOS tube MP1, the source of the first NMOS tube MN1 is grounded; the gate of the second NMOS tube MN2 is connected with the gate of the first NMOS tube MN1, and the drain of the
  • the second-stage operational amplifier circuit 11 includes: a fourth PMOS tube MP4 and a third NMOS tube MN3; wherein the gate of the fourth PMOS tube MP4 is connected to the bias circuit 12; the third NMOS tube MN3 The gate is connected to the voltage output terminal of the first-stage operational amplifier circuit 10, and the drain of the third NMOS transistor MN3 is connected to the drain of the fourth PMOS transistor MP4 as the voltage output terminal of the second-stage operational amplifier circuit 11. For outputting the second output signal VOUT2, the source of the third NMOS transistor MN3 is grounded.
  • the bias circuit 12 includes: a fifth PMOS tube MP5 and a current source IBIAS; wherein the gate of the fifth PMOS tube MP5 is connected to the first-stage operational amplifier circuit 10 and the second-stage operational amplifier circuit 11, The gate and drain of the fifth PMOS tube MP5 are connected to the current source with IBIAS. Specifically, the gate of the fifth PMOS transistor MP5 is connected to the gate of the third PMOS transistor MP3 and the gate of the fourth PMOS transistor MP4.
  • the clamping circuit 13 may include a first switch tube M, a control terminal and a current input terminal of the first switch tube M, and a voltage output terminal of the first-stage operational amplifier circuit 10.
  • the current output terminal of the first switch tube M is connected to the gate of the second NMOS tube MN2.
  • the clamping circuit 13 can clamp the output terminal of the first-stage operational amplifier circuit 10, and can clamp the highest voltage of the output terminal of the first-stage operational amplifier circuit 10 to Vgs (the first switch tube M Gate-source voltage)+Vgsn1 (the gate-source voltage of the first NMOS transistor MN1), so that when the second to-be-compared voltage VP is greater than the first to-be-compared voltage VN, the voltage VOUT1 of the output terminal of the first-stage operational amplifier circuit 10 will be It is no longer necessary to pull from a high potential (VDD-Vonp3-Vonp2, Vonp3 and Vonp2 are the on-voltage values of the MP3 tube and MP2 tube respectively) to the ground potential, but from a voltage of approximately Vgs+Vgsn1 (Vgs+Vgsn1 is less than VDD- Vonp3-Vonp2) pulls down, so that the discharge delay to the first-stage operational amplifier circuit 10 is reduced, thereby increasing the flipping voltage of the comparator;
  • the first switch tube M may include an NMOS tube.
  • the clamping circuit 13 may include a first switching tube M1, a control terminal and a current input terminal of the first switching tube M1, and the voltage output of the first-stage operational amplifier circuit 10.
  • the current output terminal of the first switch tube M1 is connected to the gate of the second NMOS tube MN2; the control terminal and current input terminal of the second switch tube M2 are connected to the voltage output terminal of the first stage operational amplifier circuit 10.
  • the current output terminal of the second switch tube M2 is connected to the voltage output terminal of the second-stage operational amplifier circuit 11.
  • the first switching tube M1 may include an NMOS tube
  • the second switching tube M2 may include an NMOS tube.
  • the clamp circuit may include a switch tube M.
  • the control terminal and current input terminal of the switch tube M are connected to the voltage output terminal of the first-stage operational amplifier circuit 10, and the switch The current output terminal of the tube M is connected to the output terminal of the second-stage operational amplifier circuit 11.
  • the clamping circuit 13 can clamp the output terminal of the first-stage operational amplifier circuit 10, and can clamp the highest voltage of the output terminal of the first-stage operational amplifier circuit 10 to Vgs (the gate source of the switch tube M). Voltage)+Vdsn3 (the drain-source voltage of the third NMOS transistor MN3).
  • the voltage VOUT1 at the output terminal of the first-stage operational amplifier circuit 10 will no longer be It needs to be pulled from the high potential (VDD-Vonp3-Vonp2, Vonp3 and Vonp2 are the on-voltage values of the MP3 tube and MP2 tube respectively) to the ground potential, but from a voltage of about Vgs+Vdsn3, which is a good way for the first stage of operation.
  • the discharge delay of the amplifier circuit 10 is reduced, thereby increasing the switching voltage of the comparator; at the same time, the amplitude of the change of the first-stage operational amplifier voltage 10 is smaller, so the change of the first-stage operational amplifier circuit 10 is more important to the first-to-be-compared
  • the coupling effect of the voltage VN and the second voltage to be compared VP is also reduced accordingly, and the first voltage to be compared VN and the second voltage to be compared VP are less disturbed by kickback noise.
  • Vgsm1 is the gate-source voltage of the M1 tube
  • Vgsn1 is The smaller value between the gate-source voltage of the MN1 tube
  • Vgsm2 is the gate-source voltage of the M2 tube
  • Vdsn3 is the drain-source voltage of the MN3 tube
  • the switch tube M may include an NMOS tube.
  • the clamping circuit 13 may include a switch tube M.
  • the current input terminal of the switch tube M is connected to the voltage output terminal of the first-stage operational amplifier circuit 10.
  • the control terminal is connected with the bias voltage VBIAS, and the current output terminal of the switch tube M is grounded.
  • the clamping circuit 13 can clamp the output terminal of the first-stage operational amplifier circuit 10, and can clamp the highest voltage of the output terminal of the first-stage operational amplifier circuit 10 to Vgs1 (the gate source of the switch tube M).
  • VDD-Vonp3-Vonp2 Vonp3 and Vonp2 are the turn-on voltage values of MP3 and MP2 tubes respectively
  • Vgs1+VBIAS Vgs1+VBIAS is less than VDD-Vonp3-Vonp2
  • the voltage clamped to the output terminal of the amplifier circuit 10 can be changed by adjusting VBIAS, so that the discharge delay of the first-stage op-amp circuit 10 is reduced, thereby increasing the flip speed of the comparator; at the same time, the first-stage operation
  • the variation amplitude of the discharge voltage 10 is smaller, so the coupling effect of the variation of the first-stage operational amplifier circuit 10 on the first to
  • the switch tube M may include a PMOS tube or a PNP type transistor.
  • the clamping circuit 13 may include: a first switching tube M1, a second switching tube M2, and a third switching tube M3; wherein, the current input of the first switching tube M1 The terminal is connected with the voltage output terminal of the first-stage operational amplifier circuit 10, the control terminal of the first switch tube M1 is connected with the current output terminal of the second switch tube M2 and the current input terminal of the third switch tube M3;
  • the control terminal of the tube M2 is connected to the bias circuit 12, specifically, the control terminal of the second switching tube M2 is connected to the gate of the fifth PMOS tube; the control terminal of the third switching tube M3 is short with the current input terminal of the third switching tube M3 Connected, the circuit output terminal of the third switch tube M3 is grounded.
  • the bias voltage VBIAS connected to the gate of the first switching tube M1 is the gate-source voltage of the third switching tube M3.
  • the clamping circuit 13 can be adjusted to clamp the voltage output terminal of the first-stage operational amplifier circuit 10 to The preset clamping voltage; for example, increasing the aspect ratio of the first switch tube M1, the second switch M2, or the third switch M3 can reduce the bias voltage VBIAS, thereby reducing the clamping voltage; reducing the first switch tube
  • the aspect ratio of M1, the second switch M2, or the third switch M3 can increase the bias voltage VBIAS, thereby increasing the clamping voltage.
  • the first switching tube M1 includes a PMOS tube or a PNP type transistor
  • the second switching tube M2 includes a PMOS tube
  • the third switching tube M3 includes an NMOS tube.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

本发明涉及一种比较器，包括：第一级运放电路、第二级运放电路、偏置电路及钳位电路；第一级运放电路包括两个电压输入端及一个电压输出端；第二级运放电路与偏置电路及第一级运放电路的电压输出端相连接；钳位电路与第一级运放电路的电压输出端相连接。上述比较器中通过增设钳位电路，可以将第一级运放电路的电压输出端的最高电压钳位至预设电压，在比较器工作过程中第一级运放电路的电压输出端的电压变化幅度较小，可以减小第一级运放电路的电压输出端的放电延时，从而提高比较器的翻转速度。。

Description

比较器 技术领域
本申请涉及集成电路技术领域，特别是涉及一种比较器。
背景技术
现有的比较器被广泛应用于各个领域，比较器的一个要求为能够快速得到比较的结果，以便于快速进行下一步处理，例如，当检测到过流异常时，希望尽快对该异常情况处理。但由于比较器本身固有的延时，经常会导致处理的速度滞后，比较器的翻转速度较慢，这个延时主要是比较器中第一级运放电路的输出端及第二级运放电路的输出端的节点充放电的延时所导致，譬如，当第一待比较电压VP大于第二待比较电压VN时，第一级运放电路的输出端的电路下拉，会从一个较高的电位下拉至地电位，当第一待比较电压VP小于第二待比较电压VN时，第一级运放电路的输出端的电位会被重新上拉至高电位。此外，比较器中第一级运放电路的输出信号的快速变化会耦合到第一待比较电压VP，形成回踢噪声(kick back noise)，不仅会对待比较电压造成干扰，还可能导致输出错误翻转。
发明内容
基于此，有必要针对现有技术中的比较器存在的由于输出端充放电延时而导致的比较器处理速度滞后、翻转速度较慢的问题，及会形成回踢噪声，对待比较电压造成干扰，导致输出错误翻转等问题进行改进。
为了实现上述目的，一方面，本发明提供了一种比较器，包括：
第一级运放电路、第二级运放电路、偏置电路及钳位电路；其中，
所述第一级运放电路包括两个电压输入端及一个电压输出端；所述第一级运放电路的两个电压输入端用于输入待比较电压；
所述第二级运放电路与所述偏置电路及所述第一级运放电路的电压输出端相连接；
所述钳位电路与所述第一级运放电路的电压输出端相连接，用于将所述第一级运放电路的电压输出端的最高电压钳位至预设电压。
上述比较器中通过增设钳位电路，可以将第一级运放电路的电压输出端的最高电压钳位至预设电压，在比较器工作过程中第一级运放电路的电压输出端的电压变化幅度较小，可以减小第一级运放电路的电压输出端的放电延时，从而提高比较器的翻转速度；此外，由于第一级运放电路的电压输出端的电压变化幅度较小，第一级运放电路的电压输出端的电压变化对输入的待比较电压的耦合作用也相应减小，可以减小输入的待比较电压的回踢噪声，避免对待比较电压造成干扰，确保输出的正确性；同时，上述比较器还具有结构简单，成本低及容易实现等优点。
在其中一个实施例中，所述第一级运放电路包括：第一PMOS管、第二PMOS管、第三PMOS管、第一NMOS管及第二NMOS管；其中，
所述第一PMOS管的栅极与第一待比较电压相连接；
所述第二PMOS管的栅极与第二待比较电压相连接；
所述第三PMOS管的栅极与所述偏置电路相连接，所述第三PMOS管的漏极与所述第一PMOS管的源极及所述第二PMOS管的源极相连接；
所述第一NMOS管的栅极与漏极短接，并与所述第一PMOS管的漏极相连接，所述第一NMOS管的源极接地；
所述第二NMOS管的栅极与所述第一NMOS管的栅极相连接，所述第二NMOS管的漏极与所述第二PMOS管的漏极相连接作为所述第一级运放电路的电压输出端，所述第二NMOS管的源极接地。
在其中一个实施例中，所述钳位电路包括第一开关管，所述第一开关管的控制端及电流输入端与所述第一级运放电路的电压输出端相连接，所述第一开关管的电流输出端与所述第二NMOS的栅极相连接。
在其中一个实施例中，所述第一开关管包括NMOS管。
在其中一个实施例中，所述钳位电路还包括第二开关管，所述第二开关管的控制端及电流输入端与所述第一级运放的电压输出端相连接，所述第二开关管的电流输出端与所述第二级运放的电压输出端相连接。
在其中一个示例中，所述第二级运放电路包括：第四PMOS管及第三NMOS管；其中，
所述第四PMOS管的栅极与所述偏置电路相连接；
所述第三NMOS管的栅极与所述第一级运放电路的电压输出端相连接，所述第三NMOS管的漏极与所述第四PMOS管的漏极相连接后作为所述第二级运放电路的电压输出端，所述第三NMOS管的源极接地。
在其中一个示例中，所述偏置电路包括：第五PMOS管及电流源；其中，
所述第五PMOS管的栅极与所述第一级运放电路及所述第二级运放电路相连接，所述第五PMOS管的漏极与所述电流源相连接。
在其中一个实施例中，所述钳位电路包括开关管，所述开关管的控制端及电流输入端与所述第一级运放电路的电压输出端相连接，所述开关管的电流输出端与所述第二级运放电路的输出端相连接。
在其中一个实施例中，所述开关管包括NMOS管。
在其中一个实施例中，所述钳位电路包括开关管，所述开关管的电流输入端与所述第一级运放电路的电压输出端相连接，所述开关管的控制端与偏置电压相连接，所述开关管的电流输出端接地。
在其中一个实施例中，所述开关管包括PMOS管或PNP型晶体管。
在其中一个实施例中，所述钳位电路包括：第一开关管、第二开关管及第三开关管；其中，
所述第一开关管的电流输入端与所述第一级运放电路的电压输出端相连接，所述第一开关管的控制端与所述第二开关管的电流输出端及所述第三开关管的电流输入端相连接；
所述第二开关管的控制端接所述偏置电路；
所述第三开关管的控制端与所述第三开关管的电流输入端短接，所述第三开关管的电路输出端接地。
在其中一个实施例中，所述第一开关管包括PMOS管或PNP型晶体管，所述第二开关管包括PMOS管，所述第三开关管包括NMOS管。
附图说明
图1至图5为本发明不同实施例中的比较器的电路图。
附图标记说明：
10        第一级运放电路
11        第二级运放电路
12        偏置电路
13        钳位电路
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
需要说明的是，当一个元件被认为是“连接”另一个元件，它可以是直接连接到另一个元件并与之结合为一体，或者可能同时存在居中元件。本文所使用的术语“安装”、“一端”、“另一端”以及类似的表述只是为了说明的目的。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
在一个实施例中，如图1至图5所示，本发明一种比较器，包括：第一级运放电路10、第二级运放电路11、偏置电路12及钳位电路13；其中，第一级运放电路10包括两个电压输入端及一个电压输出端；第一级运放电路10的两个电压输入端用于输入待比较电压；第二级运放电路11与偏置电路12及第一级运放电路10的电压输出端相连接；钳位电路13与第一级运放电路10的电压输出端相连接，钳位电路13用于将第一级运放电路10的电压输出端的最高电压钳位至预设电压。
具体的，第一运放电路10的一个输入端用于输入第一待比较电压VN，第一运放电路10的另一个输入端用于输入第二待比较电压VP。
在一个示例中，请继续参阅图1至图5，第一级运放电路10包括：第一PMOS管MP1、第二PMOS管MP2、第三PMOS管MP3、第一NMOS管MN1及第 二NMOS管MN2；其中，第一PMOS管MP1的栅极与第一待比较电压VN相连接；第二PMOS管MP2的栅极与第二待比较电压VP相连接；第三PMOS管MP3的栅极与偏置电路12相连接，第三PMOS管MP3的漏极与第一PMOS管MP1的源极及第二PMOS管MP2的源极相连接；第一NMOS管MN1的栅极与漏极短接，并与第一PMOS管MP1的漏极相连接，第一NMOS管MN1的源极接地；第二NMOS管MN2的栅极与第一NMOS管MN1的栅极相连接，第二NMOS管MN2的漏极与第二PMOS管MP2的漏极相连接作为第一级运放电路10的电压输出端，用于输出第一输出信号VOUT1，第二NMOS管MN 2的源极接地。
在一个示例中，第二级运放电路11包括：第四PMOS管MP4及第三NMOS管MN3；其中，第四PMOS管MP4的栅极与偏置电路12相连接；第三NMOS管MN3的栅极与第一级运放电路10的电压输出端相连接，第三NMOS管MN3的漏极与第四PMOS管MP4的漏极相连接后作为第二级运放电路11的电压输出端，用于输出第二输出信号VOUT2，第三NMOS管MN3的源极接地。
在一个示例中，偏置电路12包括：第五PMOS管MP5及电流源IBIAS；其中，第五PMOS管MP5的栅极与第一级运放电路10及第二级运放电路11相连接，第五PMOS管MP5的栅极、漏极与电流源相连接IBIAS。具体的，第五PMOS管MP5的栅极与第三PMOS管MP3的栅极及第四PMOS管MP4的栅极相连接。
在一个可选的示例中，如图1所示，钳位电路13可以包括第一开关管M，第一开关管M的控制端及电流输入端与第一级运放电路10的电压输出端相连接，第一开关管M的电流输出端与第二NMOS管MN2的栅极相连接。该示例中，钳位电路13可以实现对第一级运放电路10的输出端进行钳位，可以将第 一级运放电路10的输出端的最高电压钳位至Vgs(第一开关管M的栅源电压)+Vgsn1(第一NMOS管MN1的栅源电压)，这样，当第二待比较电压VP大于第一待比较电压VN的时候，第一级运放电路10的输出端的电压VOUT1将不再需要从高电位(VDD-Vonp3-Vonp2，Vonp3和Vonp2分别为MP3管和MP2管的导通电压值)拉到地电位，而是从大约Vgs+Vgsn1的电压(Vgs+Vgsn1小于VDD-Vonp3-Vonp2)向下拉，这样对第一级运放电路10的放电延时就被减小，从而提高比较器的翻转电压；同时，第一级运放电压10的变化幅度更小，故第一级运放电路10的变化对第一待比较电压VN及第二待比较电压VP的耦合作用也相应减小，第一待比较电压VN及第二待比较电压VP受到回踢噪声的干扰更小。
在一个示例中，第一开关管M可以包括NMOS管。
在另一个可选的示例中，如图3所示，钳位电路13可以包括第一开关管M1，第一开关管M1的控制端及电流输入端与第一级运放电路10的电压输出端相连接，第一开关管M1的电流输出端与第二NMOS管MN2的栅极相连接；第二开关管M2的控制端及电流输入端与第一级运放电路10的电压输出端相连接，第二开关管M2的电流输出端与第二级运放电路11的电压输出端相连接。
在一个示例中，第一开关管M1可以包括NMOS管，第二开关管M2可以包括NMOS管。
在又一个可选的示例中，如图2所示，钳位电路可以包括开关管M，开关管M的控制端及电流输入端与第一级运放电路10的电压输出端相连接，开关管M的电流输出端与第二级运放电路11的输出端相连接。该示例中，钳位电路13可以实现对第一级运放电路10的输出端进行钳位，可以将第一级运放电路10的输出端的最高电压钳位至Vgs(开关管M的栅源电压)+Vdsn3(第三NMOS 管MN3的漏源电压)，这样，当第二待比较电压VP大于第一待比较电压VN的时候，第一级运放电路10的输出端的电压VOUT1将不再需要从高电位(VDD-Vonp3-Vonp2，Vonp3和Vonp2分别为MP3管和MP2管的导通电压值)拉到地电位，而是从大约Vgs+Vdsn3的电压向下拉，这样对第一级运放电路10的放电延时就被减小，从而提高比较器的翻转电压；同时，第一级运放电压10的变化幅度更小，故第一级运放电路10的变化对第一待比较电压VN及第二待比较电压VP的耦合作用也相应减小，第一待比较电压VN及第二待比较电压VP受到回踢噪声的干扰更小。
再回到图3的结构，结合对图1和图2的分析可知，第一级运放电路10的输出端的电压VOUT1被钳位到Vgsm1+Vgsn1(Vgsm1为M1管的栅源电压，Vgsn1为MN1管的栅源电压)与Vgsm2+Vdsn3(Vgsm2为M2管的栅源电压，Vdsn3为MN3管的漏源电压)之间更小的那个值，进一步减小了第一级运放电路10的输出端的电压VOUT1的变化幅度，从而进一步提高了比较器的翻转速度并减小了回踢噪声。
在一个示例中，开关管M可以包括NMOS管。
在又一可选的示例中，如图4所示，钳位电路13可以包括开关管M，开关管M的电流输入端与第一级运放电路10的电压输出端相连接，开关管的控制端与偏置电压VBIAS相连接，开关管M的电流输出端接地。该示例中，钳位电路13可以实现对第一级运放电路10的输出端进行钳位，可以将第一级运放电路10的输出端的最高电压钳位至Vgs1(开关管M的栅源电压)+VBIAS，这样，当第二待比较电压VP大于第一待比较电压VN的时候，第一级运放电路10的输出端的电压VOUT1将不再需要从高电位(VDD-Vonp3-Vonp2，Vonp3和Vonp2分别为MP3管和MP2管的导通电压值)拉到地电位，而是从大约Vgs1+VBIAS 的电压向下拉(Vgs1+VBIAS小于VDD-Vonp3-Vonp2)，且将第一级运放电路10的输出端钳位至的电压可以通过调节VBIAS进行改变，这样对第一级运放电路10的放电延时就被减小，从而提高比较器的翻转速度；同时，第一级运放电压10的变化幅度更小，故第一级运放电路10的变化对第一待比较电压VN及第二待比较电压VP的耦合作用也相应减小，第一待比较电压VN及第二待比较电压VP受到回踢噪声的干扰更小。
在一个示例中，开关管M可以包括PMOS管或PNP型晶体管。
在又一可选的示例中，如图5所示，钳位电路13可以包括：第一开关管M1、第二开关管M2及第三开关管M3；其中，第一开关管M1的电流输入端与第一级运放电路10的电压输出端相连接，第一开关管M1的控制端与第二开关管M2的电流输出端及第三开关管M3的电流输入端相连接；第二开关管M2的控制端接偏置电路12，具体的，第二开关管M2的控制端接第五PMOS管的栅极；第三开关管M3的控制端与第三开关管M3的电流输入端短接，第三开关管M3的电路输出端接地。在该示例中，第一开关管M1的栅极连接的偏置电压VBIAS即为第三开关管M3的栅源电压。通过选择具有不同的沟道宽长比的第一开关管M1、第二开关管M2或第三开关管M3可以调节钳位电路13将第一级运放电路10的电压输出端钳位至的预设的钳位电压；譬如，增加第一开关管M1、第二开关M2或第三开关M3的宽长比，可以降低偏置电压VBIAS，进而减小钳位电压；减小第一开关管M1、第二开关M2或第三开关M3的宽长比，可以增加偏置电压VBIAS，进而增加钳位电压。
在一个示例中，第一开关管M1包括PMOS管或PNP型晶体管，第二开关管M2包括PMOS管，第三开关管M3包括NMOS管。
上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上 述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (13)

  1. 一种比较器，其特征在于，包括：第一级运放电路、第二级运放电路、偏置电路及钳位电路；其中，
    所述第一级运放电路包括两个电压输入端及一个电压输出端；所述第一级运放电路的两个电压输入端用于输入待比较电压；
    所述第二级运放电路与所述偏置电路及所述第一级运放电路的电压输出端相连接；
    所述钳位电路与所述第一级运放电路的电压输出端相连接，用于将所述第一级运放电路的电压输出端的最高电压钳位至预设电压。
  2. 根据权利要求1所述的比较器，其特征在于，所述第一级运放电路包括：第一PMOS管、第二PMOS管、第三PMOS管、第一NMOS管及第二NMOS管；其中，
    所述第一PMOS管的栅极与第一待比较电压相连接；
    所述第二PMOS管的栅极与第二待比较电压相连接；
    所述第三PMOS管的栅极与所述偏置电路相连接，所述第三PMOS管的漏极与所述第一PMOS管的源极及所述第二PMOS管的源极相连接；
    所述第一NMOS管的栅极与漏极短接，并与所述第一PMOS管的漏极相连接，所述第一NMOS管的源极接地；
    所述第二NMOS管的栅极与所述第一NMOS管的栅极相连接，所述第二NMOS管的漏极与所述第二PMOS管的漏极相连接作为所述第一级运放电路的电压输出端，所述第二NMOS管的源极接地。
  3. 根据权利要求2所述的比较器，其特征在于，所述钳位电路包括第一开关管，所述第一开关管的控制端及电流输入端与所述第一级运放电路的电压输出端相连接，所述第一开关管的电流输出端与所述第二NMOS的栅极相连接。
  4. 根据权利要求3所述的比较器，其特征在于，所述第一开关管包括NMOS管。
  5. 根据权利要求3所述的比较器，其特征在于，所述钳位电路还包括第二开关管，所述第二开关管的控制端及电流输入端与所述第一级运放电路的电压输出端相连接，所述第二开关管的电流输出端与所述第二级运放电路的电压输出端相连接。
  6. 根据权利要求1所述的比较器，其特征在于，所述第二级运放电路包括：第四PMOS管及第三NMOS管；其中，
    所述第四PMOS管的栅极与所述偏置电路相连接；
    所述第三NMOS管的栅极与所述第一级运放电路的电压输出端相连接，所述第三NMOS管的漏极与所述第四PMOS管的漏极相连接后作为所述第二级运放电路的电压输出端，所述第三NMOS管的源极接地。
  7. 根据权利要求1所述的比较器，其特征在于，所述偏置电路包括：第五PMOS管及电流源；其中，
    所述第五PMOS管的栅极与所述第一级运放电路及所述第二级运放电路相连接，所述第五PMOS管的漏极与所述电流源相连接。
  8. 根据权利要求1、2、6或7所述的比较器，其特征在于，所述钳位电路包括开关管，所述开关管的控制端及电流输入端与所述第一级运放电路的电压输出端相连接，所述开关管的电流输出端与所述第二级运放电路的输出端相连接。
  9. 根据权利要求8所述的比较器，其特征在于，所述开关管包括NMOS管。
  10. 根据权利要求1、2、6或7所述的比较器，其特征在于，所述钳位电 路包括开关管，所述开关管的电流输入端与所述第一级运放电路的电压输出端相连接，所述开关管的控制端与偏置电压相连接，所述开关管的电流输出端接地。
  11. 根据权利要求10所述的比较器，其特征在于，所述开关管包括PMOS管或PNP型晶体管。
  12. 根据权利要求1、2、6或7所述的比较器，其特征在于，所述钳位电路包括：第一开关管、第二开关管及第三开关管；其中，
    所述第一开关管的电流输入端与所述第一级运放电路的电压输出端相连接，所述第一开关管的控制端与所述第二开关管的电流输出端及所述第三开关管的电流输入端相连接；
    所述第二开关管的控制端接所述偏置电路；
    所述第三开关管的控制端与所述第三开关管的电流输入端短接，所述第三开关管的电路输出端接地。
  13. 根据权利要求12所述的比较器，其特征在于，所述第一开关管包括PMOS管或PNP型晶体管，所述第二开关管包括PMOS管，所述第三开关管包括NMOS管。
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US11683027B2 (en) 2023-06-20
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CN112865763A (zh) 2021-05-28
US20220311429A1 (en) 2022-09-29

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