WO2021083032A1 - 封装结构及其制作方法 - Google Patents

封装结构及其制作方法 Download PDF

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Publication number
WO2021083032A1
WO2021083032A1 PCT/CN2020/122946 CN2020122946W WO2021083032A1 WO 2021083032 A1 WO2021083032 A1 WO 2021083032A1 CN 2020122946 W CN2020122946 W CN 2020122946W WO 2021083032 A1 WO2021083032 A1 WO 2021083032A1
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WO
WIPO (PCT)
Prior art keywords
carrier board
flow
electronic component
carrier
column
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PCT/CN2020/122946
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English (en)
French (fr)
Inventor
张伟杰
张强波
宋关强
Original Assignee
天芯互联科技有限公司
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Publication of WO2021083032A1 publication Critical patent/WO2021083032A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • This application relates to the field of semiconductor packaging technology, and in particular to a packaging structure and a manufacturing method thereof.
  • SiP package-in-package
  • PoP package-on-package
  • System in Package System in Package
  • the present application provides a packaging structure and a manufacturing method thereof, which not only reduces the volume of the product, but also effectively improves the heat dissipation and flow capacity of the product.
  • a technical solution adopted in this application is to provide a packaging structure that includes a first carrier board, a first electronic component, a second electronic component, a second carrier board, and a first communication device.
  • the first carrier has a first surface and a second surface opposite to the first surface; the first electronic components are mounted on the first surface of the first carrier; the second electronic components are mounted on The second surface of the first carrier board; the second carrier board is arranged opposite to the second surface of the first carrier board, and the surface of the second carrier board facing the first carrier board is provided with a communicating piece; one end of the first flow-through column is connected to The second surface of the first carrier board is connected, and the other end is connected with the communicating piece on the second carrier board; and the lateral dimension of the first flow-through column is smaller than the lateral dimension of the communicating piece.
  • another technical solution adopted in this application is to provide a method for manufacturing a package structure, the method includes: providing a first carrier board and a second carrier board; wherein the second carrier board is provided with a communication
  • the first electronic component is mounted on the first surface of the first carrier board, and the second electronic component and the first flow-through column are mounted on the second surface of the first carrier board to form a first package;
  • the first package body is mounted on the second carrier board and connects the first flow-through column with the communicating member; wherein, the lateral size of the first flow-through column is smaller than the lateral size of the communicating member.
  • the packaging structure and the manufacturing method thereof provided in the present application, the packaging structure by mounting the first electronic component and the second electronic component on the first surface and the second surface of the first carrier board, so as to greatly reduce the cost of the product Volume; at the same time, by setting the communicating piece on the second carrier board, and making the lateral size of the communicating piece larger than that of the first flow-through column, so that the first flow-through column and the communicating piece can achieve better performance in the mounting process Alignment of the product, thereby effectively improving the flow capacity of the product.
  • FIG. 1 is a schematic structural diagram of a package structure provided by an embodiment of the application.
  • FIG. 2 is a schematic structural diagram of a first package provided by an embodiment of the application.
  • FIG. 3 is a schematic structural diagram of a second carrier board provided by an embodiment of the application.
  • FIG. 4 is a schematic diagram of the structure of the power supply bare chip mounted on the first carrier board according to the first embodiment of the application;
  • FIG. 5 is a schematic diagram of the structure of the power supply bare chip mounted on the first carrier board according to the second embodiment of the application;
  • FIG. 6 is a schematic diagram of the structure of the power supply bare chip mounted on the first carrier board according to the third embodiment of the application;
  • FIG. 7 is a schematic flowchart of a manufacturing method of a package structure provided by an embodiment of the application.
  • FIG. 8 is a schematic diagram of a specific flow of step S13 in FIG. 7;
  • FIG. 9a is a schematic diagram of the product structure corresponding to step S130 in FIG. 8;
  • Fig. 9b is a schematic diagram of the product structure corresponding to step S131 in Fig. 8.
  • first”, “second”, and “third” in this application are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first”, “second”, and “third” may explicitly or implicitly include at least one of the features.
  • “multiple” means at least two, such as two, three, etc., unless otherwise specifically defined. All directional indicators (such as up, down, left, right, front, back%) in the embodiments of this application are only used to explain the relative positional relationship between the components in a specific posture (as shown in the drawings) , Movement status, etc., if the specific posture changes, the directional indication will also change accordingly.
  • FIG. 1 is a schematic structural diagram of a package structure provided by an embodiment of the application
  • FIG. 2 is a schematic structural diagram of a first package provided by an embodiment of the application
  • a package structure 1 which includes a first package body 10, a second carrier board 11, and a second package layer 12.
  • the first package body 10 includes a first carrier board 100, electronic components 101 and a first package layer 102.
  • the electronic component 101 is mounted on at least one surface of the first carrier board 100.
  • the first packaging layer 102 covers the side surface of the electronic component 101 away from the first carrier board 100, and cooperates with the first carrier board 100 to encapsulate the electronic component 101 to protect the electronic component 101.
  • the first carrier board 100 is provided with signal lines that are electrically connected to the pins of the electronic components 101, and the first carrier board 100 is provided with pads, the pads are connected with the signal lines, and the lead of the electronic components 101
  • the pin can be printed by connecting the solder paste to the pad.
  • the electronic component 101 includes one or any combination of resistors, inductors, capacitors, chips, and power bare chips 1010.
  • the electronic component 101 may also include diodes and transistors, which is not limited in this embodiment.
  • the upper and lower surfaces of the first carrier board 100 are mounted with electronic components 101 to reduce floor space and product volume.
  • the first carrier board 100 is far away from the second carrier board 11 on the side surface, that is, the first surface, where the first electronic components are attached.
  • the first electronic components may specifically include resistors, capacitors, chips, and power supplies.
  • One or more of the chip 1010 and part of the inductance, the first carrier 100 is close to the second carrier 11 on one side surface, that is, the second surface, on which the second electronic components are attached.
  • the second electronic components can specifically be Including inductance.
  • FIG. 4 is a schematic diagram of the power supply bare chip mounted on the first carrier board according to the first embodiment of the application
  • FIG. 5 is the power supply bare chip mounted according to the second embodiment of the application
  • FIG. 6 is a schematic diagram of the structure of the power bare chip mounted on the first carrier according to the third embodiment of the application.
  • the power source bare chip 1010 can be mounted on the first carrier board 100 through an adhesive, and the following embodiments are all taken as examples.
  • the aforementioned adhesive may be glue.
  • bonding wires are provided on the power bare chip 1010, and the bonding wires are connected to the pads on the first carrier board 100 to realize the electrical connection between the power bare chip 1010 and the signal wires on the first carrier board 100. connection.
  • the power bare chip 1010 can also be mounted on the first carrier board 100 through solder balls or copper pillars.
  • the prior art for mounting on the first carrier board 100 through solder balls or copper pillars refer to the prior art for mounting on the first carrier board 100 through solder balls or copper pillars.
  • the mounting on the carrier board 100 can achieve the same or similar technical effects, which will not be repeated here in this embodiment.
  • the power bare chip 1010 when the power bare chip 1010 is mounted on the first carrier board 100 through solder balls or copper pillars, the power bare chip 1010 passes through the solder balls or copper pillars at the same time to realize its connection with the first carrier board 100. Electrical connection between signal lines.
  • the first carrier board 100 may specifically be a printed circuit board (Printed Circuit Board, PCB for short), a package substrate, or a Quad Flat No-lead Package (QFN) type frame.
  • Printed Circuit Board PCB for short
  • package substrate a package substrate
  • QFN Quad Flat No-lead Package
  • the second carrier board 11 is disposed opposite to the second surface of the first carrier board 100 for mounting the first package body 10 so that the first package body 10 communicates with external devices through the second carrier board 11.
  • the first carrier board 100 is close to the side surface of the second carrier board 11, that is, the second surface is also provided with a first flow-through column 103a, and the second carrier board 11 is positioned opposite to the first flow-through column 103a.
  • the connecting member 110 in the specific implementation process, one end of the first flow-through column 103a is connected to the first carrier board 100, and the other end is attached to the connecting member 110 on the first carrier board 100 to connect the first package body 10 It is mounted on the second carrier board 11 and allows the electronic components 101 on the first package body 10 to communicate with external equipment through the first through-flow column 103a and the connecting member 110 on the second carrier board 11.
  • the first flow-through column 103a is in communication with the signal line on the first carrier board 100, and the electronic component 101 communicates with external equipment through the first carrier board 100 and the first flow-through column 103a.
  • the electronic components 101 on the first package body 10 are in communication with the connecting member 110 on the second carrier 11 through the first through-flow column 103a, and external equipment is also connected with the connecting member 110 on the second carrier 11 Connected, so that the electronic components 101 on the first package body 10 communicate with external equipment through the first flow-through column 103a and the connecting member 110 on the second carrier board 11.
  • the second carrier board 11 may be a metal plate; specifically, the second carrier board 11 may be a copper plate.
  • the lateral size of the communicating member 110 in the present application is larger, which effectively improves the heat dissipation efficiency; and the lateral size of the communicating member 110 in the present application is larger than that of the first communicating member.
  • the lateral size of the flow column 103a can effectively improve the alignment accuracy between the two during a specific mounting process, thereby improving the flow capacity.
  • the second packaging layer 12 covers the side surface of the first packaging body 10 away from the second carrier board 11 and cooperates with the second carrier board 11 to encapsulate the first package body 10 to protect the first package body 10.
  • the material of the first encapsulation layer 102 and the second encapsulation layer 12 may be a mixture of epoxy resin and silicon dioxide.
  • the first package body 10 is provided, and the first package body 10 is configured to include a first carrier board 100 and electronic components 101 mounted on both surfaces of the first carrier board 100 And the first encapsulation layer 102, where the first encapsulation layer 102 covers the surface of the electronic component 101 away from the first carrier board 100, and cooperates with the first carrier board 100 to encapsulate the electronic component 101, which can effectively prevent
  • the electronic component 101 is in direct contact with the atmosphere, thereby protecting the electronic component 101; at the same time, by providing a second carrier board 11, a first flow through is provided on the side surface of the first carrier board 100 close to the second carrier board 11 Column 103a, a connecting member 110 is provided at a position where the second carrier 11 is opposite to the first flow-through column 103a, so as to be mounted on the connecting member 110 through the first flow-through column 103a, so that the first package body 10 can be mounted on On the second carrier board 11, the electronic components 101 on the first package body 10 are connected to external equipment through the connecting
  • the above-mentioned connecting member 110 may specifically be a pad, and the pad includes a first pad 1100 and a second pad 1101.
  • the first pad 1100 is used to mount the first through-flow pillar 103a to mount the first package body 10 on the second carrier board 11.
  • the lateral size of the first pad 1100 is greater than the lateral size of the first flow-through pillar 103a, so as to improve the alignment accuracy of the first flow-through pillar 103a and the first pad 1100 during the mounting process, thereby improving the flow-through ability.
  • first flow-through pillars 103a there are at least two first flow-through pillars 103a, and the number of the first flow-through pillars 103a is the same as the number of the first pads 1100.
  • the second pad 1101 is used to mount the electronic component 101 arranged on the side surface of the first carrier board 100 close to the second carrier board 11, that is, to mount the second electronic component. Specifically, referring to FIG. 1, in one embodiment, the second pad 1101 is used to mount an inductor provided on a surface of the first carrier board 100 close to the second carrier board 11.
  • the thickness of the second electronic component is the same as the thickness of the first through-hole 103a, and the surface of the second electronic component facing away from the first carrier 100 exposes the second encapsulation layer 12 so as to interact with the first
  • the two carrier boards 11 are connected; it can be understood that, in this embodiment, the electronic components 101 mounted on the surface of the first carrier board 100 close to the second carrier board 11 are directly mounted on the second pad 1101
  • the above can play a certain role in current flow, so as to conduct the electronic component 101 with external equipment to further improve the current flow capability.
  • the thickness of the second electronic component is less than the length of the first flow-through pillar 103a; the package structure 1 further includes a second flow-through pillar 103b; one end of the second flow-through pillar 103b It is connected to the side surface of the second electronic component away from the first carrier board 100, and the other end is connected to the connecting member 110 on the second carrier board 11, that is, connected to the second pad 1101 on the second carrier board 11 to The second electronic component and the second carrier 11 are directly connected through the second flow-through column 103b, thereby improving the flow conductivity; wherein, the lateral size of the second flow-through column 103b is also smaller than the lateral size of the connecting member 10, so Improve the alignment accuracy and flow capacity of the two.
  • a part of the inductor is mounted on the surface of the first carrier board 100 close to the second carrier board 11, and a part of the inductor is mounted on the second pad 1101 to further improve the flow capacity.
  • the lateral size of the second pad 1101 is larger than the lateral size of the electronic component 101 mounted on the surface of the first carrier board 100 on the side close to the second carrier board 11.
  • the lateral size of the second pad 1101 The size is larger than the lateral size of the part of the inductor mounted on the side surface of the first carrier board 100 close to the second carrier board 11, so that not only can the heat dissipation capacity be improved, but also the electronic component 101 and the second pad 1101 can be separated Achieve better alignment, and further improve the flow capacity.
  • first flow-through pillars 103a there are at least two first flow-through pillars 103a, and at least two first flow-through pillars 103a are arranged along the edge of the first carrier board 100; and in a specific embodiment, referring to FIG. 3, at least two first flow-through pillars 103a The flow-through pillars 103a are distributed on opposite sides of the second flow-through pillar 103b.
  • the connecting members 110 are formed by a PCB etching process, and the number and positions of the connecting members 110 correspond to the numbers and positions of the first flow-through pillars 103a and the second flow-through pillars 103b; in a specific embodiment, the first welding There are at least two pads 1100, and at least two first pads 1100 are evenly distributed on both sides of the second pad 1101.
  • first pads 1100 there are specifically eight first pads 1100, and the eight first pads 1100 are evenly distributed on both sides of the second pad 1101 in two rows. It can be understood that, in this embodiment, there are eight first flow-through pillars 103a correspondingly, and the number and positions of the eight first flow-through pillars 103a correspond to the first pads 1100 in a one-to-one correspondence.
  • FIG. 7 is a schematic flowchart of a manufacturing method of a package structure provided by an embodiment of the application; in this embodiment, a manufacturing method of a package structure is provided.
  • the package structure 1 is specifically manufactured by the following manufacturing method of the package structure.
  • the production method includes:
  • Step S11 Provide a first carrier board and a second carrier board, wherein a connecting piece is provided on the second carrier board.
  • the first carrier board 100 may be a printed circuit board
  • the second carrier board 11 may be a metal plate, such as a copper plate.
  • the structure of the second carrier board 11 can be seen in FIG. 3; in the specific implementation process, a metal copper plate is provided, Then, a PCB etching process is used to etch the second carrier 11 according to a preset pattern to obtain a metal copper frame with a connecting piece 110; using this method to make a metal copper frame, the size of the connecting piece 110 is easier to realize, and the processing cost is relatively low. Low, high reliability of the finished product after plastic packaging.
  • the connecting member 110 is a pad, and the pad includes a first pad 1100 and a second pad 1101.
  • the pad includes a first pad 1100 and a second pad 1101.
  • the first carrier board 100 is provided with signal lines and pads that are electrically connected to the pins of the electronic component 101.
  • the first carrier board 100 and the second carrier board 11 are stacked and arranged.
  • Step S12 Mount the first electronic component on the first surface of the first carrier board, and mount the second electronic component and the first flow-through pillar on the second surface of the first carrier board to form a first package.
  • step S12 the structure diagram of the product produced by step S12 can be seen in FIG. 2.
  • the first electronic component is mounted on the first surface of the first carrier 100, the first electronic component is plastically sealed for the first time to form the first encapsulation layer 102; and then on the first surface of the first carrier 100
  • the second electronic components and the first flow-through pillar 103a are mounted on the two surfaces, and then the first packaging layer 102 and the first carrier 100 are cut to form a plurality of first packaging bodies 10; wherein, the first electronic components
  • the device includes one or any combination of resistors, inductors, capacitors, chips, and power bare chips; the second electronic component may include inductors.
  • the thickness of the second electronic component is the same as the length of the first through-hole 103a, and the end of the second electronic component away from the first carrier 100 exposes the second encapsulation layer 12 to be in contact with the second carrier.
  • the board 11 is connected.
  • the thickness of the second electronic component is less than the length of the first flow-through pillar 103a; the second electronic component and the first flow-through pillar 103a are mounted on the second surface of the first carrier board 100 After the step, it further includes: mounting the second flow-through pillar 103b on the surface of the second electronic component away from the first carrier 100 to form the first package body 10; wherein, the lateral dimension of the second flow-through pillar 103b It is smaller than the lateral dimension of the connecting member 110.
  • Step S13 Mount the first package body on the second carrier board, and connect the first flow-through column to the communicating member; wherein the lateral size of the first flow-through column is smaller than the lateral size of the communicating member.
  • step S13 the schematic diagram of the structure of the product produced by step S13 can be seen in FIG. 1.
  • the multiple first packages 10 are mounted on the second carrier 11 and the multiple first packages 10 are plastically sealed for the second time to form the second package layer 12, and then the second package layer 12 And the second carrier board 11 are cut to form a plurality of packaging structures 1; wherein, the first carrier board 100 is provided with a first flow-through pillar 103a and/or a second flow-through pillar on a side surface close to the second carrier board 11 103b, the second carrier plate 11 is provided with a communicating member 110 at a position opposite to the first flow-through column 103a and/or the second flow-through column 103b, and the lateral size of the first flow-through column 103a and/or the second flow-through column 103b It is smaller than the lateral dimension of the communicating member 110, and the first flow-through pillar 103a and/or the second flow-through pillar 103b are mounted on the communicating member 110 to mount the first package body 10 on the second carrier board 11.
  • the multiple first packages 10 can be mounted on the second carrier 11 by soldering.
  • the above-mentioned injection molding equipment may be used for the second plastic sealing of the first package body 10; and the above-mentioned first plastic sealing and the second plastic sealing can both use a mixture of epoxy resin and silicon dioxide for plastic sealing.
  • the electronic component 101 may be connected to the pads on the first carrier board 100 through solder paste, so as to realize the mounting of the electronic component 101 on the first carrier board 100.
  • the above-mentioned injection molding equipment can be used to plasticize the electronic component 101 for the first time.
  • the number and positions of the first flow-through pillars 103a and/or the second flow-through pillars 103b correspond to the number and positions of the first pads 1100.
  • step S13 specifically includes:
  • Step S130 Mount the first package body on the second carrier board through the first flow-through pillar and perform a second plastic encapsulation to form a second package layer.
  • step S130 the product structure produced through step S130 can be specifically seen in FIG. 9a.
  • the first flow-through pillar 103a of the first package 10 is mounted on the first pad 1100, and the first carrier 100 is close to the electronic component 101 on the side surface of the second carrier 11, that is, the second
  • the electronic components are mounted on the second pad 1101 to mount the first package body 10 on the second carrier 11; of course, when the thickness of the second electronic component is less than the length of the first through-hole 103a , The second electronic component is mounted on the second pad 1101 through the second through-flow pillar 103b.
  • the lateral size of the first flow-through pillar 103a is smaller than that of the first pad 1100, and the second flow-through pillar 103b is smaller than the lateral size of the second pad 1101, so as to improve the gap between the two in the specific mounting process. Alignment accuracy, and then improve the flow capacity.
  • metallurgical treatment is performed on the surface of the second carrier board 11 away from the first carrier board 100 to prevent the second carrier board 11 from being oxidized when exposed to the atmosphere.
  • Step 131 cutting the second packaging layer and the second carrier board to form a plurality of packaging structures.
  • step S131 the product structure produced by step S131 can be specifically seen in FIG. 9b.
  • each first package 10 corresponds to a set of pads.
  • the multiple first packages 10 are first mounted on the first package.
  • the multiple first packages 10 are then molded a second time to form a second package, and finally the second package is cut at the positions corresponding to each set of pads to form multiple Package structure 1.
  • the manufacturing method of the package structure provided in this embodiment provides a first carrier board 100 and a second carrier board 11, and mounts the electronic components 101 on the first carrier board 100 and plasticizes them to form the first package body 10 , Can effectively prevent the electronic component 101 from contacting the atmosphere, thereby protecting the electronic component 101; at the same time, by encapsulating the first package body 10 on the second carrier board 11, it can effectively prevent the first package body 10 from contacting the atmosphere , The second package body can be protected; in addition, since the first carrier board 100 is provided with a first flow-through pillar 103a on the side surface close to the second carrier board 11, the second carrier board 11 and the first flow-through pillar 103a The connecting member 110 is provided at the opposite position, and the first through-flow column 103a is mounted on the connecting member 110 to realize the mounting of the first package body 10 on the second carrier board 11, and make the first package body 10.
  • the electronic component 101 communicates with external devices through the connecting member 110 on the second carrier 11; in addition, since the transverse size of the connecting member 110 in the present application is larger than that in the prior art, Effectively improve the heat dissipation capacity; and because the lateral size of the communicating member 110 is larger than that of the first flow-through column 103a, the first flow-through column 103a and the communicating member 110 can achieve better alignment during the mounting process, And then effectively improve the flow capacity.

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Abstract

一种封装结构（1）及其制作方法，该封装结构（1）包括第一载板（100）、第一电子元器件（101）、第二电子元器件（101）、第二载板（11）及第一通流柱（103a）；其中，第一载板（100）具有第一表面和与第一表面相背的第二表面；第一电子元器件（101）贴装在第一载板（100）的第一表面；第二电子元器件（101）贴装在第一载板（100）的第二表面；第二载板（11）与第一载板（100）的第二表面相对设置，且第二载板（11）朝向第一载板（100）的表面设置有连通件（110）；第一通流柱（103a）的一端与第一载板（100）的第二表面连接，另一端与第二载板（11）上的连通件（110）连接；且第一通流柱（103a）的横向尺寸小于连通件（110）的横向尺寸。

Description

封装结构及其制作方法 【技术领域】
本申请涉及半导体封装技术领域，尤其涉及一种封装结构及其制作方法。
【背景技术】
现今的信息社会下，人类对电子产品的依赖性与日俱增，电子产品正朝着高集成度、小型化、微型化的方向蓬勃发展。
目前，为了实现产品的高集成度、小型化及微型化，一般会采用封装内堆叠封装(package in package，PiP)、封装上堆叠封装(package on package，PoP)或系统级封装(System in Package，SiP)对各个零部件进行封装；然而，现有技术中的封装结构类型，其散热和通流能力较弱。
【发明内容】
本申请提供一种封装结构及其制作方法，不仅减小了产品体积，且有效提高了产品的散热和通流能力。
为解决上述技术问题，本申请采用的一个技术方案是：提供一种封装结构，该封装结构包括第一载板、第一电子元器件、第二电子元器件、第二载板及第一通流柱；其中，第一载板具有第一表面和与第一表面相背的第二表面；第一电子元器件贴装在第一载板的第一表面；第二电子元器件贴装在第一载板的第二表面；第二载板与第一载板的第二表面相对设置，且第二载板朝向第一载板的表面设置有连通件；第一通流柱的一端与第一载板的第二表面连接，另一端与第二载板上的连通件连接；且第一通流柱的横向尺寸小于连通件的横向尺寸。
为解决上述技术问题，本申请采用的另一个技术方案是：提供一种封装结构的制作方法，该方法包括：提供第一载板和第二载板；其中，第二载板上设置有连通件；在第一载板的第一表面贴装第一电子元器 件，在第一载板的第二表面贴装第二电子元器件和第一通流柱，以形成第一封装体；将第一封装体贴装在第二载板上，并使第一通流柱与连通件连接；其中，第一通流柱的横向尺寸小于连通件的横向尺寸。
本申请提供的封装结构及其制作方法，该封装结构通过将第一电子元器件和第二电子元器件分别贴装在第一载板的第一表面和第二表面，以大大减小产品的体积；同时，通过在第二载板上设置连通件，并使连通件的横向尺寸大于第一通流柱的横向尺寸，以使第一通流柱和连通件在贴装过程中实现较好的对位，进而有效提高产品的通流能力。
【附图说明】
图1为本申请一实施例提供的封装结构的结构示意图；
图2为本申请一实施例提供的第一封装体的结构示意图；
图3为本申请一实施例提供的第二载板的结构示意图；
图4为本申请第一实施例提供的电源裸芯片贴装在第一载板上的结构示意图；
图5为本申请第二实施例提供的电源裸芯片贴装在第一载板上的结构示意图；
图6为本申请第三实施例提供的电源裸芯片贴装在第一载板上的结构示意图；
图7为本申请一实施例提供的封装结构的制作方法的流程示意图；
图8为图7中步骤S13的具体流程示意图；
图9a为图8中步骤S130对应的产品结构示意图；
图9b为图8中步骤S131对应的产品结构示意图。
【具体实施方式】
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本 申请保护的范围。
本申请中的术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”、“第三”的特征可以明示或者隐含地包括至少一个该特征。本申请的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。本申请实施例中所有方向性指示(诸如上、下、左、右、前、后……)仅用于解释在某一特定姿态(如附图所示)下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
下面结合附图和实施例对本申请进行详细的说明。
请参阅图1至图3，其中，图1为本申请一实施例提供的封装结构的结构示意图；图2为本申请一实施例提供的第一封装体的结构示意图；图3为本申请一实施例提供的第二载板的结构示意图。
在本实施例中，提供一种封装结构1，包括第一封装体10、第二载板11和第二封装层12。
其中，第一封装体10包括第一载板100、电子元器件101以及第一封装层102。其中，电子元器件101贴装在第一载板100的至少一表面上。具体的，第一封装层102覆盖于电子元器件101远离第一载板100的一侧表面，并配合第一载板100将电子元器件101封装，以对电子元器件101进行保护。
具体的，第一载板100上设置有与电子元器件101的引脚电连接的信号线，且第一载板100上设置有焊盘，焊盘与信号线连通，电子元器件101的引脚可通过锡膏与焊盘连接印制。
具体的，电子元器件101包括电阻、电感、电容、芯片、电源裸芯片1010中的一种或任意组合。当然，在其它实施方式中，电子元器件101还可包括二极管、晶体管，本实施例对此并不加以限制。
在具体实施过程中，第一载板100的上下表面(即第一表面和与第一表面相对的第二表面)均贴装有电子元器件101，以减小占地面积，减小产品体积；具体的，第一载板100远离第二载板11的一侧表面，即第一表面，贴装有第一电子元器件，第一电子元器件具体可包括电阻、电容、芯片、电源裸芯片1010及部分电感中的一种或多种，第一载板100靠近第二载板11的一侧表面，即第二表面，贴装有第二电子元器件，第二电子元器件具体可包括电感。
参见图4至图6，其中，图4为本申请第一实施例提供的电源裸芯片贴装在第一载板上的结构示意图；图5为本申请第二实施例提供的电源裸芯片贴装在第一载板上的结构示意图；图6为本申请第三实施例提供的电源裸芯片贴装在第一载板上的结构示意图。
在一实施方式中，电源裸芯片1010可通过粘合剂贴装在第一载板100上，以下实施例均以此为例。
具体的，上述粘合剂可为胶水。
在具体实施过程中，电源裸芯片1010上设置有焊线，焊线与第一载板100上的焊盘连接，以实现电源裸芯片1010与第一载板100上的信号线之间的电连接。
当然，在其它实施方式中，电源裸芯片1010也可通过锡球或铜柱贴装在第一载板100上，具体的，可参见现有技术中通过锡球或铜柱贴装在第一载板100上的方式进行贴装，且可实现相同或相似的技术效果，本实施例在此不再一一赘述。
可以理解的是，当电源裸芯片1010通过锡球或铜柱贴装在第一载板100上时，电源裸芯片1010同时通过该锡球或铜柱以实现其与第一 载板100上的信号线之间的电连接。
具体的，第一载板100具体可为印制电路板(Printed Circuit Board，简称PCB)，封装基板或方形扁平无引脚封装(Quad Flat No-leadPackage，QFN)类框架。
其中，第二载板11与第一载板100的第二表面相对设置，用于贴装第一封装体10，使第一封装体10通过第二载板11与外界设备连通。具体的，第一载板100靠近第二载板11的一侧表面，即第二表面还设置有第一通流柱103a，第二载板11与第一通流柱103a相对的位置设置与连通件110，在具体实施过程中，第一通流柱103a的一端与第一载板100连接，另一端贴装在第一载板100上的连通件110上，以将第一封装体10贴装在第二载板11上，并可使第一封装体10上的电子元器件101通过第一通流柱103a和第二载板11上的连通件110与外界设备连通。
具体的，第一通流柱103a与第一载板100上的信号线连通，电子元器件101通过第一载板100和第一通流柱103a以与外界设备连通。
可以理解的是，第一封装体10上的电子元器件101通过第一通流柱103a与第二载板11上的连通件110连通，外界设备也与第二载板11上的连通件110连通，以使第一封装体10上的电子元器件101通过第一通流柱103a和第二载板11上的连通件110与外界设备连通。
具体的，第二载板11可为金属板；具体的，第二载板11可为铜板。
其中，与现有技术中的连通件的横向尺寸相比，本申请中的连通件110的横向尺寸较大，有效提高了散热效率；且本申请中的连通件110的横向尺寸大于第一通流柱103a的横向尺寸，从而能够在具体贴装过程中，有效提高二者之间的对位精度，进而提高通流能力。
其中，第二封装层12覆盖于第一封装体10远离第二载板11的一侧表面，并配合第二载板11将第一封装体10封装，以对第一封装体10进行保护。
具体的，第一封装层102和第二封装层12的材料可为环氧树脂和二氧化硅的混合物。
本实施例提供的封装结构1，通过设置第一封装体10，将第一封装体10设置成包括第一载板100、贴装在第一载板100的两个表面上的电子元器件101以及第一封装层102，其中，由于第一封装层102覆盖于电子元器件101远离第一载板100的一侧表面，并配合第一载板100将电子元器件101封装，从而能够有效防止电子元器件101直接与大气接触，进而可对电子元器件101进行保护；同时，通过设置第二载板11，在第一载板100靠近第二载板11的一侧表面设置第一通流柱103a，在第二载板11与第一通流柱103a相对的位置设置连通件110，以通过第一通流柱103a贴装在连通件110上，实现将第一封装体10贴装在第二载板11上，使第一封装体10上的电子元器件101通过第二载板11上的连通件110与外界设备连通；另外，由于本申请中的连通件110的横向尺寸相比于现有技术中的连通件的横向尺寸较大，从而有效提高了散热能力；且由于连通件110的横向尺寸大于第一通流柱103a的横向尺寸，从而能够使第一通流柱103a和连通件110在贴装过程中实现较好的对位，进而可有效提高产品的通流能力；此外，通过在第一封装体10远离第二载板11的一侧表面设置第二封装层12，并使第二封装层12配合第二载板11将第一封装体10封装，以对第一封装体10进行保护。
在本实施例中，上述连通件110具体可为焊盘，焊盘包括第一焊盘1100和第二焊盘1101。
其中，第一焊盘1100用于贴装第一通流柱103a，以将第一封装体10贴装在第二载板11上。具体的，第一焊盘1100的横向尺寸大于第一通流柱103a的横向尺寸，以提高第一通流柱103a与第一焊盘1100在贴装过程中的对位精度，进而提高通流能力。
具体的，第一通流柱103a至少为两个，且第一通流柱103a的数量与第一焊盘1100的数量一致。
其中，第二焊盘1101用于贴装设置在第一载板100靠近第二载板11的一侧表面上的电子元器件101，即，用于贴装第二电子元器件。具体的，参见图1，在一实施方式中，第二焊盘1101用于贴装设置在第一载板100靠近第二载板11的一侧表面上的电感。
在具体实施例中，第二电子元器件的厚度与第一通流柱103a的厚度相同，且第二电子元器件背离第一载板100的一侧表面露出第二封装层12，以与第二载板11连接；可以理解的是，在该实施例中，贴装在第一载板100靠近第二载板11的一侧表面上的电子元器件101直接贴装在第二焊盘1101上以起到一定的通流作用，从而将电子元器件101与外界设备导通，以进一步提高通流能力。
在另一具体实施例中，参见图1，第二电子元器件的厚度小于第一通流柱103a的长度；封装结构1进一步还包括第二通流柱103b；第二通流柱103b的一端与第二电子元器件背离第一载板100的一侧表面连接，另一端与第二载板11上的连通件110连接，即与第二载板11上的第二焊盘1101连接，以通过第二通流柱103b将第二电子元器件与第二载板11直接导通，进而提高导流能力；其中，第二通流柱103b的横向尺寸也小于连通件10的横向尺寸，以提高二者的对位精度及通流能力。
在具体实施过程中，通过在第一载板100靠近第二载板11的一侧表面上贴装部分电感，通过将部分电感贴装在第二焊盘1101上，以进一步提高通流能力。
具体的，第二焊盘1101的横向尺寸大于贴装在第一载板100靠近第二载板11的一侧表面上的电子元器件101的横向尺寸，具体的，第二焊盘1101的横向尺寸大于贴装在第一载板100靠近第二载板11的一侧表面上的部分电感的横向尺寸，从而不仅能够提高散热能力，且可使电子元器件101与第二焊盘1101之间实现较好的对位，进而进一步提高通流能力。
具体的，第一通流柱103a至少为两个，至少两个第一通流柱103a沿第一载板100的边缘设置；且在一具体实施例中，参见图3，至少两个第一通流柱103a分布在第二通流柱103b的相对两侧。
具体的，连通件110通过PCB蚀刻工艺形成，且连通件110的数量及位置与第一通流柱103a和第二通流柱103b的数量及位置对应；在一具体实施例中，第一焊盘1100至少为两个，且至少两个第一焊盘1100均匀分布在第二焊盘1101的两侧。
参见图3，在一实施方式中，第一焊盘1100具体有八个，八个第一焊盘1100呈两列均匀分布在第二焊盘1101的两侧。可以理解的是，在本实施方式中，第一通流柱103a也相应的设置有八个，八个第一通流柱103a的数量及位置与第一焊盘1100一一对应。
请参阅图1至图7，其中，图7为本申请一实施例提供的封装结构的制作方法的流程示意图；在本实施例中，提供一种封装结构的制作方法，上述实施例所涉及的封装结构1具体通过以下封装结构的制作方法所制得。
具体的，该制作方法包括：
步骤S11：提供第一载板和第二载板，其中，第二载板上设置有连通件。
其中，第一载板100可为印制电路板，第二载板11可为金属板，比如铜板，第二载板11的结构具体可参见图3；在具体实施过程中，提供金属铜板，然后采用PCB蚀刻工艺按照预设图形对第二载板11进行蚀刻处理以得到具有连通件110的金属铜框架；采用该方法制作金属铜框架，连通件110的尺寸较易实现，且加工成本较低，塑封后成品可靠性较高。
具体的，连通件110为焊盘，焊盘包括第一焊盘1100和第二焊盘1101。在具体实施过程中，第一焊盘1100至少为两个，至少两个第一焊盘1100均匀分布在第二焊盘1101的两侧。
具体的，第一载板100上设置有与电子元器件101的引脚电连接的信号线和焊盘。
在具体实施过程中，第一载板100和第二载板11层叠设置。
步骤S12：在第一载板的第一表面贴装第一电子元器件，在第一载板的第二表面贴装第二电子元器件和第一通流柱，以形成第一封装体。
具体的，经步骤S12制作所得的产品的结构示意图可参见图2。
具体的，在第一载板100的第一表面贴装第一电子元器件之后对第一电子元器件进行第一次塑封，以形成第一封装层102；然后在第一载板100的第二表面贴装第二电子元器件及第一通流柱103a，之后，对第 一封装层102及第一载板100进行切割，以形成多个第一封装体10；其中，第一电子元器件包括电阻、电感、电容、芯片、电源裸芯片中的一种或任意组合；第二电子元器件可包括电感。
在一实施例中，第二电子元器件的厚度与第一通流柱103a的长度相同，且第二电子元器件背离第一载板100的一端露出第二封装层12，以与第二载板11连接。
在另一具体实施例中，第二电子元器件的厚度小于第一通流柱103a的长度；在第一载板100的第二表面贴装第二电子元器件和第一通流柱103a的步骤之后，还包括：在第二电子元器件远离第一载板100的一侧表面贴装第二通流柱103b，以形成第一封装体10；其中，第二通流柱103b的横向尺寸小于连通件110的横向尺寸。
步骤S13：将第一封装体贴装在第二载板上，并使第一通流柱与连通件连接；其中，第一通流柱的横向尺寸小于连通件的横向尺寸。
具体的，经步骤S13制作所得的产品的结构示意图可参见图1。
具体的，将多个第一封装体10贴装在第二载板11上并对多个第一封装体10进行第二次塑封，以形成第二封装层12，之后对第二封装层12及第二载板11进行切割，以形成多个封装结构1；其中，第一载板100靠近第二载板11的一侧表面设置有第一通流柱103a和/或第二通流柱103b，第二载板11与第一通流柱103a和/或第二通流柱103b相对的位置设置有连通件110，第一通流柱103a和/或第二通流柱103b的横向尺寸小于连通件110的横向尺寸，且第一通流柱103a和/或第二通流柱103b贴装在连通件110上，以将第一封装体10贴装在第二载板11上。
具体的，可采用焊接的方式将多个第一封装体10贴装在第二载板11上。
具体的，上述可采用注塑设备对第一封装体10进行第二次塑封；且上述第一次塑封和第二次塑封均可采用环氧树脂和二氧化硅的混合物进行塑封。
在具体实施例中，电子元器件101可通过锡膏与第一载板100上的焊盘连接，以实现将电子元器件101贴装在第一载板100上。且上述可 采用注塑设备对电子元器件101进行第一次塑封。
具体的，第一通流柱103a和/或第二通流柱103b的数量和位置与第一焊盘1100的数量和位置对应。
可以理解的是，第一载板100上可贴装有多组电子元器件101，在具体实施过程中，需要对每组电子元器件101所在的位置进行切割以形成多个第一封装体10。
参见图8、图9a和图9b，其中，图8为图7中步骤S13的具体流程示意图，图9a为图8中步骤S130对应的产品结构示意图；图9b为图8中步骤S131对应的产品结构示意图；步骤S13具体包括：
步骤S130：将第一封装体通过第一通流柱贴装在第二载板上并进行第二次塑封，以形成第二封装层。
具体的，经步骤S130制作所得的产品结构具体可参见图9a。
具体的，第一封装体10的第一通流柱103a贴装在第一焊盘1100上，第一载板100靠近第二载板11的一侧表面上的电子元器件101，即第二电子元器件贴装在第二焊盘1101上，以将第一封装体10贴装在第二载板11上；当然，当第二电子元器件的厚度小于第一通流柱103a的长度时，第二电子元器件通过第二通流柱103b贴装在第二焊盘1101上。
具体的，第一通流柱103a的横向尺寸小于第一焊盘1100的横向尺寸，第二通流柱103b小于第二焊盘1101的横向尺寸，以在具体贴装过程中提高二者之间的对位精度，进而提高通流能力。
具体的，对第二载板11远离第一载板100的一侧表面进行冶金处理，以防第二载板11暴露在大气中发生氧化。
步骤131：对第二封装层及第二载板进行切割，以形成多个封装结构。
具体的，经步骤S131制作所得的产品结构具体可参见图9b。
可以理解的是，第二载板11上设置有多组焊盘，每个第一封装体10对应一组焊盘，在具体制作过程中，先将多个第一封装体10贴装到第二载板11上，然后对多个第一封装体10进行第二次塑封以形成第二封装体，最后对该第二封装体在每组焊盘所对应的位置进行切割，以形 成多个封装结构1。
本实施例提供的封装结构的制作方法，通过提供第一载板100和第二载板11，在第一载板100上贴装电子元器件101并对其进行塑封以形成第一封装体10，能够有效防止电子元器件101与大气接触，从而对电子元器件101进行保护；同时，通过将第一封装体10封装在第二载板11上，能够有效防止第一封装体10与大气接触，进而可对第二封装体进行保护；另外，由于第一载板100靠近第二载板11的一侧表面设置有第一通流柱103a，第二载板11与第一通流柱103a相对的位置设置有连通件110，第一通流柱103a贴装在连通件110上，以实现将第一封装体10贴装在第二载板11上，并使第一封装体10上的电子元器件101通过第二载板11上的连通件110与外界设备连通；此外，由于本申请中的连通件110的横向尺寸相比于现有技术中的连通件的横向尺寸较大，从而有效提高了散热能力；且由于连通件110的横向尺寸大于第一通流柱103a的横向尺寸，从而能够使第一通流柱103a和连通件110在贴装过程中实现较好的对位，进而有效提高通流能力。
以上仅为本申请的实施方式，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (18)

  1. 一种封装结构，其中，包括：
    第一载板，具有第一表面和与所述第一表面相背的第二表面；
    第一电子元器件，贴装在所述第一载板的第一表面；
    第二电子元器件，贴装在所述第一载板的第二表面；
    第二载板，与所述第一载板的第二表面相对设置，且所述第二载板朝向所述第一载板的表面设置有连通件；
    第一通流柱，一端与所述第一载板的第二表面连接，另一端与所述第二载板上的连通件连接；且所述第一通流柱的横向尺寸小于所述连通件的横向尺寸。
  2. 根据权利要求1所述的封装结构，其中，还包括：
    第一封装层，设置在所述第一载板的第一表面，并配合所述第一载板将所述第一电子元器件封装；
    第二封装层，设置在所述第二载板朝向所述第一载板的一侧表面，并配合所述第二载板将所述第二电子元器件、所述第一通流柱及所述第一封装层封装。
  3. 根据权利要求2所述的封装结构，其中，所述第二电子元器件的厚度与所述第一通流柱的长度相同，且所述第二电子元器件背离所述第一载板的一侧表面露出所述第二封装层，以与所述第二载板连接。
  4. 根据权利要求2所述的封装结构，其中，所述第二电子元器件的厚度小于所述第一通流柱的长度；
    所述封装结构还包括第二通流柱；所述第二通流柱的一端与所述第二电子元器件背离所述第一载板的一侧表面连接，另一端与所述第二载板上的连通件连接；且所述第二通流柱的横向尺寸小于所述连通件的横向尺寸。
  5. 根据权利要求4所述的封装结构，其中，所述第一通流柱至少为两个，至少两个所述第一通流柱沿所述第一载板的边缘设置。
  6. 根据权利要求5所述的封装结构，其中，至少两个所述第一通流柱分布在所述第二通流柱的相对两侧。
  7. 根据权利要求6所述的封装结构，其中，所述连通件通过蚀刻工艺形成，且所述连通件的数量及位置与所述第一通流柱和所述第二通流柱的数量及位置对应。
  8. 根据权利要求1所述的封装结构，其中，所述第一电子元器件包括电阻、电容、芯片、电源裸芯片及电感中的一种或多种；所述第二电子元器件包括电感。
  9. 根据权利要求1所述的封装结构，其中，所述第一载板为印制电路板，所述第二载板为金属板。
  10. 一种封装结构的制作方法，其中，包括：
    提供第一载板和第二载板；其中，所述第二载板上设置有连通件；
    在所述第一载板的第一表面贴装第一电子元器件，在所述第一载板的第二表面贴装第二电子元器件和第一通流柱，以形成第一封装体；
    将所述第一封装体贴装在所述第二载板上，并使所述第一通流柱与所述连通件连接；其中，所述第一通流柱的横向尺寸小于所述连通件的横向尺寸。
  11. 根据权利要求10所述的封装结构的制作方法，其中，所述提供第一载板和第二载板的步骤具体包括：按照预设图形对所述第二载板进行蚀刻处理以形成连通件。
  12. 根据权利要求10所述的封装结构的制作方法，其中，所述在所述第一载板的第一表面贴装第一电子元器件，在所述第一载板的第二表面贴装第二电子元器件和第一通流柱，以形成第一封装体的步骤具体包括：
    在所述第一载板的第一表面贴装第一电子元器件；
    对所述第一电子元器件进行第一次塑封，以形成第一封装层；
    在所述第一载板的第二表面贴装第二电子元器件及第一通流柱；
    对所述第一封装层及所述第一载板进行切割，以形成多个第一封装体。
  13. 根据权利要求12所述的封装结构的制作方法，其中，所述将所述第一封装体贴装在所述第二载板上，并使所述第一通流柱与所述连 通件连接的步骤具体包括：
    将所述第一封装体通过所述第一通流柱贴装在所述第二载板上并进行第二次塑封，以形成第二封装层；
    对所述第二封装层及所述第二载板进行切割，以形成多个封装结构。
  14. 根据权利要求13所述的封装结构的制作方法，其中，所述第二电子元器件的厚度与所述第一通流柱的长度相同，且所述第二电子元器件背离所述第一载板的一端露出所述第二封装层，以与所述第二载板连接。
  15. 根据权利要求13所述的封装结构的制作方法，其中，所述第二电子元器件的厚度小于所述第一通流柱的长度；所述在所述第一载板的第二表面贴装第二电子元器件和第一通流柱的步骤之后，还包括：在所述第二电子元器件远离所述第一载板的一侧表面贴装第二通流柱；其中，所述第二通流柱的横向尺寸小于所述连通件的横向尺寸。
  16. 根据权利要求15所述的封装结构的制作方法，其中，所述第一通流柱至少为两个，至少两个所述第一通流柱沿所述第一载板的边缘设置。
  17. 根据权利要求16所述的封装结构的制作方法，其中，至少两个所述第一通流柱分布在所述第二通流柱的相对两侧。
  18. 根据权利要求10所述的封装结构的制作方法，其中，所述第一电子元器件包括电阻、电容、芯片、电源裸芯片及电感中的一种或多种；所述第二电子元器件包括电感。
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