WO2021077778A1 - 读操作电路、半导体存储器和读操作方法 - Google Patents

读操作电路、半导体存储器和读操作方法 Download PDF

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WO2021077778A1
WO2021077778A1 PCT/CN2020/097406 CN2020097406W WO2021077778A1 WO 2021077778 A1 WO2021077778 A1 WO 2021077778A1 CN 2020097406 W CN2020097406 W CN 2020097406W WO 2021077778 A1 WO2021077778 A1 WO 2021077778A1
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Prior art keywords
data
dbi
global bus
read
output
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PCT/CN2020/097406
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English (en)
French (fr)
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张良
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长鑫存储技术有限公司
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Priority to EP20878146.8A priority Critical patent/EP3926631B1/en
Priority to US17/242,258 priority patent/US11762579B2/en
Publication of WO2021077778A1 publication Critical patent/WO2021077778A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Definitions

  • This application relates to the technical field of semiconductor memory, and in particular to a read operation circuit, a semiconductor memory and a read operation method.
  • Semiconductor memory includes Static Random-Access Memory (SRAM), Dynamic Random Access Memory (DRAM), and Synchronous Dynamic Random Access Memory (SDRAM) , Read-Only Memory (ROM), flash memory, etc.
  • SRAM Static Random-Access Memory
  • DRAM Dynamic Random Access Memory
  • SDRAM Synchronous Dynamic Random Access Memory
  • ROM Read-Only Memory
  • the embodiments of the present application provide a read operation circuit, a semiconductor memory, and a read operation method to solve or alleviate one or more technical problems in the prior art.
  • an embodiment of the present application provides a read operation circuit, which is applied to a semiconductor memory.
  • the semiconductor memory includes a DQ port, a DBI port, and a memory block.
  • the read operation circuit includes:
  • the DBI encoding module connected to the storage block, is used to read the read data from the storage block, and determine whether to flip the read data according to the number of bits in the read data that is low, so as to output the global data for global bus transmission Bus data and DBI data for DBI signal line transmission, DBI port is used to receive DBI data;
  • the parallel-to-serial conversion circuit is connected between the DQ port and the DBI encoding module through the global bus, and is used to perform parallel-to-serial conversion on the global bus data to generate the output data of the DQ port;
  • the data buffer module is connected to the storage block through the global bus;
  • the precharge module is connected to the precharge signal line and is used to set the initial state of the global bus to high.
  • the DBI encoding module is used to output the inverted data of the read data as global bus data when the number of bits of the low data in the read data is greater than a preset value, and set the DBI data to Is high; and when the number of bits of the data that is low in the read data is less than or equal to the preset value, the original read data is output as global bus data, and the DBI data is set low.
  • both the read data and the global bus data are divided into M groups, the DBI data is M bits, the M bits of DBI data corresponds to the M groups of read data, and the M bits of DBI data correspond to the M groups of global data.
  • the bus data has a one-to-one correspondence, and the parallel-serial conversion circuit is also connected between the DBI encoding module and the DBI port for parallel-serial conversion of M-bit DBI data and output to the DBI port, where M is an integer greater than 1.
  • each set of read data is N bits, where N is an integer greater than 1, and the DBI encoding module is used to input a set of read data with a low number of bits greater than N/2
  • the input set of read data flip data as a corresponding set of global bus data output, and set the input set of read data corresponding to one bit of DBI data high; and in the input set of When the number of bits of the low data in the read data is less than or equal to N/2, the input set of read data is output as a corresponding set of global bus data, and the input set of read data corresponds to one Bit DBI data is set low.
  • the DBI encoding module includes:
  • the DBI encoding unit the input end of the DBI encoding unit is connected to the storage block, the output end of the DBI encoding unit is connected to the DBI signal line, and the DBI encoding unit is used when the number of bits of the data that is low in the read data is greater than the preset value Set the DBI data to high; and set the DBI data to low when the number of bits of the low data in the read data is less than or equal to the preset value;
  • Data selector the input end of the data selector is connected to the DBI encoding unit, and is used to receive the read data through the DBI encoding unit.
  • the input end of the data selector also receives the DBI data through the DBI signal line, and the output end of the data selector passes the global
  • the bus is connected to the parallel-serial conversion circuit, and the data selector is used to output the flipped data of the read data as the global bus data when the DBI data is high; and when the DBI data is high, the original read data Output as global bus data.
  • the data selector includes a plurality of data selection units, and the data selection unit includes:
  • the first inverter the input terminal of the first inverter receives DBI data through the DBI signal line;
  • the second inverter the input terminal of the second inverter is connected to the DBI encoding unit, and is used to receive read data from the DBI encoding unit;
  • the first transmission gate the input terminal of the first transmission gate is connected to the output terminal of the second inverter, the output terminal of the first transmission gate is connected to the global bus for outputting global bus data, and the anti-control terminal of the first transmission gate Connected to the output terminal of the first inverter, the positive control terminal of the first transmission gate receives DBI data through the DBI signal line;
  • the second transmission gate The input end of the second transmission gate is connected to the DBI encoding unit and is used to receive read data from the DBI encoding unit.
  • the output end of the second transmission gate is connected to the global bus for outputting global bus data.
  • the negative control terminal of the transmission gate receives DBI data through the DBI signal line, and the positive control terminal of the second transmission gate is connected to the output terminal of the first inverter.
  • the data selector includes a plurality of data selection units, and the data selection unit includes:
  • the third inverter the input terminal of the third inverter receives DBI data through the DBI signal line;
  • the fourth inverter the input terminal of the fourth inverter is connected to the DBI encoding unit, and is used to receive read data from the DBI encoding unit;
  • the first logic AND gate the first input terminal of the first logic AND gate is connected to the DBI encoding unit for receiving read data from the DBI encoding unit, and the second input terminal of the first logic AND gate is connected to the third inverter The output terminal;
  • a second logic AND gate the first input terminal of the second logic AND gate receives DBI data through the DBI signal line, and the second input terminal of the second logic AND gate is connected to the output terminal of the fourth inverter;
  • Logic OR gate the two input terminals of the logic OR gate are respectively connected to the output terminal of the first logic AND gate and the output terminal of the second logic AND gate, and the output terminal of the logic OR gate is connected to the global bus for outputting global bus data .
  • the data buffer module includes a plurality of NMOS transistors, the gate of the NMOS transistor is connected to the memory block, and the drain of the NMOS transistor is connected to the global bus; and the precharge module includes a plurality of PMOS transistors and a plurality of holding circuits , The gate of the PMOS transistor is connected to the precharge signal line, the drain of the PMOS transistor is connected to the global bus, and the input and output terminals of the holding circuit are connected to the global bus.
  • an embodiment of the present application provides a semiconductor memory including a DQ port, a DBI port, a memory block, and a read operation circuit of any one of the above
  • an embodiment of the present application provides a read operation method, which is applied to a semiconductor memory.
  • the semiconductor memory includes a DQ port, a DBI port, and a memory block.
  • the read operation method includes:
  • the number of bits of the low data in the read data determine whether to flip the read data to output the global bus data for global bus transmission and the DBI data for DBI signal line transmission;
  • Parallel-serial conversion is performed on the global bus data to generate the output data of the DQ port.
  • determining whether to invert the read data according to the number of bits of data that is low in the read data to output the global bus data for global bus transmission and the DBI data for DBI signal line transmission includes:
  • the flip data of the read data is output as the global bus data, and the DBI data is set high;
  • the original read data is output as the global bus data, and the DBI data is set low.
  • determining whether to invert the read data according to the number of bits of data that is low in the read data to output the global bus data for global bus transmission and the DBI data for DBI signal line transmission includes:
  • the inverted data of the input set of read data is output as the corresponding set of global bus data, and the input one Set one bit of DBI data corresponding to the group read data to high;
  • the input set of read data is output as the corresponding set of global bus data, and the input set of read data is output.
  • the DBI data corresponding to the fetched data is set low.
  • the embodiment of the application adopts the above technical solution to realize that more data is transmitted as "1" on the global bus of the Precharge pull-up architecture, thereby reducing the number of internal global bus flips, greatly compressing current, and reducing power consumption.
  • FIG. 1 schematically shows a block diagram of a part of the structure of a semiconductor memory in an implementation manner of this embodiment
  • FIG. 2 schematically shows a block diagram of a partial structure of a semiconductor memory in another implementation manner of this embodiment
  • FIG. 3 schematically shows a circuit diagram (corresponding to a storage block) of a data buffer module in an implementation manner of this embodiment
  • FIG. 4 schematically shows a circuit diagram (corresponding to multiple storage blocks) of a data buffer module in an implementation manner of this embodiment
  • Figure 5 schematically shows a schematic diagram of the DBI function
  • FIG. 6 schematically shows a block diagram of a DBI encoding module in an implementation manner of this embodiment
  • Figure 7-1 schematically shows a block diagram of a data selection unit in an implementation manner of this embodiment
  • Figure 7-2 schematically shows a block diagram of a data selection unit in another implementation manner of this embodiment
  • FIG. 8 schematically shows a flowchart of a read operation method in an implementation manner of this embodiment.
  • FIG. 1 schematically shows a block diagram of a part of the structure of a semiconductor memory in an implementation manner of this embodiment.
  • the semiconductor memory 20 includes a DQ port 24, a Data Bus Inversion (DBI) port 25, a bank 26, and a read operation circuit.
  • the read operation circuit includes a global bus (Global Bus), a DBI signal line, a parallel-to-serial conversion circuit 21, a data buffer module (Data Buffer) 22, and a DBI encoding module (Encoder) 23.
  • the semiconductor memory 20 is a DRAM, such as a fourth-generation double-rate synchronous dynamic random access memory (D'uble Data Rate SDRAM 4, DDR4 for short).
  • D'uble Data Rate SDRAM 4 fourth-generation double-rate synchronous dynamic random access memory
  • an Active command opens the only designated storage block 26, and the read operation can only be performed on one storage block 26.
  • the read operation circuit Through the read operation circuit, the read data D ⁇ 127:0> in the memory block 26 outputs 8-bit output data DQ ⁇ 7:0> through the DQ port 24.
  • the number of storage blocks 26, the number of data bits of each storage block 26, and the number and number of data bits of the DQ port 24 are not limited in this embodiment. For example, there may be one DQ port 24, which is used to output 16-bit output data; there may also be two DQ ports 24, that is, each DQ port 24 is used to output 8-bit output data.
  • the output data DQ ⁇ 7:0> is obtained by performing a read operation on a group of memory blocks Bank ⁇ 7:0> through the above-mentioned read operation circuit; the output data DQ ⁇ 15:8> is obtained through the above-mentioned read operation.
  • the other read operation circuit is obtained by performing a read operation on another group of memory blocks Bank ⁇ 15:8>.
  • the eight memory blocks 26 ie Bank ⁇ 15:8>
  • DQ ⁇ 15:8> when one Bank is working, the other Banks do not work.
  • the semiconductor memory 20 has an array structure, and the structure of each unit may be the same, but due to different input data, the output data of each unit may be different.
  • the following takes one of the memory blocks as an example to introduce the read operation circuit of this embodiment.
  • the DBI encoding module 23 is connected to the storage block 26, and is used to read the read data from the storage block 26, such as D ⁇ 127:0>, and determine whether to flip the read according to the number of bits in the read data that is low Data to output global bus data for global bus transmission and DBI data for DBI signal line transmission.
  • the data being high can mean that the data is equal to "1”
  • the data being "low” can be that the data is equal to "0”.
  • Data flipping can be understood as changing from “0” to "1", or from "1" to "0”.
  • the inversion of the data line or the signal line can be understood as a high level changing to a low level, or a low level changing to a high level.
  • the DBI encoding module 23 is used to output the inverted data of the read data as global bus data when the number of bits of the low data in the read data is greater than the preset value, and output the DBI data Set to high; and when the number of bits of the low data in the read data is less than or equal to the preset value, output the original read data as global bus data, and set the DBI data to low.
  • the multi-bit read data is not grouped, that is, the DBI data can be one bit, and the DBI data output by the DBI encoding module 23 can be directly output to the DBI port 25 without passing through the parallel-to-serial conversion circuit 21.
  • multiple bits of read data can be grouped.
  • the read data and global bus data are divided into M groups, the DBI data is M bits, the M bits of DBI data corresponds to the M groups of read data, and the M bits of DBI data correspond to M groups.
  • One-to-one correspondence between the group global bus data, and the parallel-serial conversion circuit 21 is also connected between the DBI encoding module 23 and the DBI port 25 for parallel-serial conversion of M-bit DBI data and output to the DBI port, where M is greater than 1. Integer. It should be noted that the parallel-to-serial conversion circuit 21 may include two parallel-to-serial conversion modules, which are respectively used to perform parallel-to-serial conversion on the global bus data and the DBI data, which is not limited in this embodiment.
  • each set of read data can be N bits, where N is an integer greater than 1, and the DBI encoding module 23 is used in the case where the number of bits of the data that is low in the input set of read data is greater than N/2
  • the input flip data of a set of read data is output as a corresponding set of global bus data, and one bit of DBI data corresponding to the input set of read data is set to high; and in the input set of read
  • the input set of read data is output as a corresponding set of global bus data, and the input set of read data corresponds to one bit of DBI The data is set low.
  • the read data D ⁇ 127:0> is divided into 16 groups, each group of read data is 8 bits, and each group of read data corresponds to one bit of DBI data.
  • the DBI data is 16 bits, such as DBI ⁇ 15:0>.
  • the global bus data D' ⁇ 127:0> will also be divided into 16 groups accordingly, and each bit of DBI data corresponds to a group of global bus data.
  • the global bus data D' ⁇ 127:120> output from the DBI encoding module 23 is the flip data of the read data D ⁇ 127:120> of the memory block 26 (such as Bank0);
  • the global bus data D' ⁇ 15:8> output from the DBI encoding module 23 is the flip data of the read data D ⁇ 15:8> of the memory block 26 (such as Bank0) ;
  • each global bus transmits one bit of the global bus data.
  • M is an integer greater than 1
  • each global bus transmits one bit of the global bus data.
  • Global bus ⁇ 0> transmits global bus data D' ⁇ 0>;
  • global bus ⁇ 1> transmits global bus data D' ⁇ 1>;
  • global bus ⁇ 127> transmits global bus data D' ⁇ 127>.
  • each DBI signal line transmits 1 bit of DBI data.
  • the DBI signal line ⁇ 0> transmits DBI data DBI ⁇ 0>, and is connected to the global bus data D′ ⁇ 0:7>
  • DBI signal line ⁇ 1> transmits DBI data DBI ⁇ 1>, and corresponds to the global bus data D′ ⁇ 8:15>, which represents D′ ⁇ 8 :15>Whether it is the flipped data
  • DBI signal line ⁇ 15> transmits DBI data DBI ⁇ 15>, and corresponds to the global bus data D′ ⁇ 120:127>, indicating whether D′ ⁇ 120:127> It is the data after flipping.
  • the parallel-to-serial conversion circuit 21 is connected between the DQ port 24 and the DBI encoding module 23 through the global bus, and is used to perform parallel-to-serial conversion on the global bus data to generate the output data of the DQ port 24.
  • the parallel-serial conversion circuit 21 performs parallel-serial conversion on the 128-bit global bus data D' ⁇ 127:0> of Bank0, and then generates 8-bit output data DQ ⁇ 7:0>, and passes the data bus (data bus) Transmitted to DQ port 24. Therefore, among the global bus data D' ⁇ 127:0> transmitted on the global bus, there are more data that are "1". Accordingly, in the semiconductor memory 20 shown in FIG. 2, the 256-bit global bus data (including the 128-bit global bus data corresponding to DQ ⁇ 7:0> and the 128-bit global bus data corresponding to DQ ⁇ 15:8> In the data), there are many data with "1".
  • the data buffer module 22 is connected to the storage block 26 through the global bus, and the precharge module 27 is connected to the precharge signal line (Precharge) for setting the initial state of the global bus to high. That is to say, in this embodiment, the semiconductor memory 20 adopts the global bus transmission structure of Precharge pull-up.
  • FIG. 3 schematically shows a circuit diagram (corresponding to a storage block 26) of the data buffer module 22 and the precharge module 27 in an implementation of this embodiment.
  • FIG. 4 schematically shows a circuit diagram (corresponding to 8 storage blocks 26) of the data buffer module 22 and the precharge module 27 in an implementation of this embodiment.
  • the data buffer module 22 includes a plurality of NMOS (Negative Channel Metal Oxide Semiconductor) transistors 222
  • the precharge module 27 includes a plurality of PMOS (Positive Channel Metal Oxide Semiconductor) transistors 221 and a plurality of holding ( hold) Circuit 223.
  • the gate of the PMOS transistor 221 is connected to the precharge signal line, the drain of the PMOS transistor 221 is connected to the global bus; the gate of the NMOS transistor 222 is connected to the memory block 26, and the drain of the NMOS transistor 222 is connected to the global bus (Global Bus);
  • the input and output terminals of the holding circuit 223 are connected to the global bus, thereby forming a positive feedback circuit.
  • Precharge is to set the initial state of each global bus to high.
  • the specific process is that Precharge generates a pull-up pulse (pulse, about 2ns), pulls the corresponding global bus for a while, and the holding circuit 223 forms a positive feedback And lock the global bus at high level, but the ability of the holding circuit 223 to pull up and pull down the current is relatively weak; when a global bus needs to be turned to low level, it will represent the corresponding global bus
  • the data line (that is, the data line connected to the gate of the corresponding NMOS transistor 222) is pulled high (also a pulse, about 2ns), so that the corresponding NMOS transistor 222 will pull down the global bus for a while (the pull-down capability is greater than The pull-up capability of the circuit 223 is maintained), and then the global bus is locked to a low level through positive feedback, and the data line is flipped. Since there are more data "1" in the global bus data D' ⁇ 127:0>, fewer flipping actions are required. Therefore,
  • the function of DBI port 25 is described below in conjunction with FIG. 5.
  • the data output from the semiconductor memory 20 includes the DBI data of the DBI port 25 and the output data of the DQ port 24.
  • the DBI data of DBI port 25 is equal to 1
  • the output data such as DQ ⁇ 7:0> needs to be inverted and output to the controller 10;
  • the DBI data of DBI port 25 is equal to 0, the original output data can be directly sent to the control ⁇ 10.
  • the on-die termination (ODT) of the semiconductor memory 20 can absorb the current of the DQ port 24 to prevent the signal from being reflected on the internal circuit of the semiconductor memory 20.
  • the size of the ODT is adjusted to match the controller 10.
  • the ODT structure is a pull-up structure.
  • the module for inverting and encoding data is set at the position where the data is about to exit the semiconductor memory, that is, in the parallel-serial conversion. After the module. Therefore, in the related art, there are more data "0"s transmitted by the global bus inside the semiconductor memory, which will cause the IDD4R to be too large and the power consumption to be higher.
  • the semiconductor memory 20 of this embodiment in the process of reading data from the semiconductor memory 20, when the global bus data is 256 bits, if the 256-bit global bus data needs to be inverted, only 32-bit DBI data will be inverted. IDD4R current will be greatly compressed.
  • the DBI encoding module includes a DBI encoding unit 231 and a data selector 232.
  • the input end of the DBI encoding unit 231 is connected to the storage block 26 through a local bus, and the output end of the DBI encoding unit 231 is connected to the DBI signal line and is connected to the input end of the data selector 232.
  • the DBI encoding unit 231 is used for setting the DBI data to high when the number of bits of the low data in the read data is greater than the preset value; and the number of bits of the low data in the read data is less than or equal to the preset value In the case of the value, the DBI data is set to low.
  • the DBI encoding unit 231 may include multiple DBI encoding subunits, and each DBI encoding subunit is used to process a set of read data, and then output one bit of DBI data.
  • the data selection unit DBI encoding subunits may have 16, respectively corresponding to 16 groups of read data, and then output 16-bit DBI data, where each group of read data may have 8 bits.
  • the input end of the data selector 232 is connected to the DBI encoding unit 231 for receiving read data through the DBI encoding unit 231, the input end of the data selector 232 also receives DBI data through the DBI signal line, and the output end of the data selector 232 passes
  • the global bus is connected to the parallel-serial conversion circuit 21.
  • the data selector 232 is used for outputting the flipped data of the read data as global bus data when the DBI data is high; and for outputting the original read data as global bus data when the DBI data is high.
  • the data selector 232 includes a plurality of data selection units 232', and each data selection unit 232' is used to process one bit of DBI data and a set of read data. For example, there may be 16 data selection units 232', corresponding to 16 groups of read data and one bit of DBI data, and each group of read data has 8 bits.
  • Figure 7-1 and Figure 7-2 show two different implementations of the data selection unit 232'.
  • the data selector 232 includes a first inverter 232A, a second inverter 232B, a first transmission gate 232C, and a second transmission gate 232D.
  • the input terminal of the first inverter 232A receives DBI data through the DBI signal line;
  • the input terminal of the second inverter 232B is connected to the DBI encoding unit 231 for receiving read data from the DBI encoding unit 231;
  • the first transmission gate 232C The input terminal is connected to the output terminal of the second inverter 232B, the output terminal of the first transmission gate 232C is connected to the global bus for outputting global bus data, and the anti-control terminal of the first transmission gate 232C ( Figure 7-1
  • the upper control terminal is connected to the output terminal of the first inverter 232A, the positive control terminal of the first transmission gate 232C (the lower control terminal in Figure 7-1) receives DBI data through the DBI signal line;
  • the second transmission gate 232D The input terminal of is connected
  • the output terminal of the second transmission gate 232D is connected to the global bus for outputting global bus data.
  • the second transmission gate 232D reverses the control The terminal receives the DBI data through the DBI signal line, and the positive control terminal of the second transmission gate 232D is connected to the output terminal of the first inverter 232A.
  • a set of second inverter 232B, first transmission gate 232C, and second transmission gate 232D are used to process one bit of read data and output one bit of corresponding global bus data.
  • the second inverter 232A, the first transmission gate 232C, and the second transmission gate 232D should also have 8 groups, and then output the 8-bit global Bus data D ⁇ 7:0>.
  • the data selector 232 includes a third inverter 232E, a fourth inverter 232F, a first logical AND gate 232G, a second logical AND gate 232H, and a logical OR gate 232K.
  • the input terminal of the third inverter 232E receives DBI data through the DBI signal line; the input terminal of the fourth inverter 232F is connected to the DBI encoding unit 231 for receiving the read data from the DBI encoding unit 231; the first logical AND gate The first input terminal of 232G is connected to the DBI encoding unit 231 for receiving read data from the DBI encoding unit 231, and the second input terminal of the first logical AND gate 232G is connected to the output terminal of the third inverter 232E;
  • the first input terminal of the logic AND gate 232H receives DBI data through the DBI signal line, the second input terminal of the second logic AND gate 232H is connected to the output terminal of the fourth inverter 232F; the two input terminals of the logic OR gate 232K are respectively It is connected to the output terminal of the first logic AND gate 232G and the output terminal of the second logic AND gate 232H, and the output terminal of the logic OR gate 232K is connected to the global bus for
  • a set of fourth inverter 232F, first logical AND gate 232G, second logical AND gate 232H, and logical OR gate 232K are used to process one bit of read data and output one bit of corresponding global bus data.
  • the gate 232K should also have 8 groups, and then output 8-bit global bus data D ⁇ 7:0>.
  • the semiconductor memory 20 of this embodiment also includes other structures such as a sense amplifier, a precharge circuit, etc., because they are all the prior art, and this embodiment will not be repeated here.
  • FIG. 8 shows a flowchart schematically showing a read operation method in an implementation manner of this embodiment.
  • the read operation method can be applied to the semiconductor memory 20 described above.
  • the read operation method may include:
  • Step S801 Set the initial state of the global bus to high
  • Step S802 Read data from the storage block
  • Step S803 Determine whether to flip the read data according to the number of bits of the data that is low in the read data, so as to output the global bus data for global bus transmission and the DBI data for DBI signal line transmission;
  • Step S804 Perform parallel-to-serial conversion on the global bus data to generate output data of the DQ port.
  • step S803 may include: in the case where the number of bits of the low data in the read data is greater than the preset value, output the inverted data of the read data as the global bus data, and output the DBI The data is set to high; when the number of bits of the low data in the read data is less than or equal to the preset value, the original read data is output as global bus data, and the DBI data is set to low.
  • step S803 may include: dividing the read data into M groups, where each group of read data is N bits, and M and N are both integers greater than 1; When the number of bits of the high data in the data is greater than N/2, the inversion data of the input set of read data is output as the corresponding set of global bus data, and the input set of read data corresponds to One bit of DBI data is set to high; when the number of bits of the input data that is high in a set of read data is less than or equal to N/2, the input set of read data is output as a corresponding set of global bus data , And set one bit of DBI data corresponding to a set of input data to be low.
  • the read operation circuit provided by the embodiment of this application is applied to a semiconductor memory whose global bus transmission structure is Precharge pull-up.
  • the transmission on the global bus can be realized as "1". "There are more data, thereby reducing the number of internal global bus flips, which can greatly compress current and reduce power consumption.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the present application, "a plurality of” means two or more than two, unless otherwise specifically defined.

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Abstract

本申请实施例提供一种读操作电路、半导体存储器和读操作方法，包括：DBI编码模块，用于从存储块中读出读取数据，并根据读取数据中为低的数据的位数，确定是否翻转读取数据，以输出供全局总线传输的全局总线数据和供DBI信号线传输的DBI数据，DBI端口用于接收DBI数据；并串转换电路，用于对全局总线数据进行并串转换，以生成DQ端口的输出数据；数据缓冲模块，通过全局总线连接于存储块；预充电模块，连接于预充电信号线，用于将全局总线的初始态设置为高。本申请实施例的技术方案可以实现在上拉架构的全局总线上传输"1"的数据较多，从而可以减少内部全局总线翻转次数，大幅压缩电流，降低功耗。

Description

读操作电路、半导体存储器和读操作方法
本申请要求于2019年10月25日提交中国专利局、申请号为201911021478.1、发明名称为“读操作电路、半导体存储器和读操作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体存储器技术领域，尤其涉及一种读操作电路、半导体存储器和读操作方法。
背景技术
本部分旨在为权利要求书中陈述的本申请的实施例提供背景或上下文。此处的描述不因为包括在本部分中就承认是现有技术。
半导体存储器包括静态随机存取存储器(Static Random-Access Memory，简称SRAM)、动态随机存取存储器(Dynamic Random Access Memory，简称DRAM)、同步动态随机存取内存(Synchronous Dynamic Random Access Memory，简称SDRAM)、只读存储器(Read-Only Memory，简称ROM)、闪存等。
在固态技术协会(Joint Electron Device Engineering Council，JEDEC)的DRAM协议中，对DRAM的速度、省电都有具体要求。如何使DRAM更省电的同时，亦能保证信号的完整性以及数据传输和存储的可靠性，是行业内亟待解决的问题。
发明内容
本申请实施例提供一种读操作电路、半导体存储器和读操作方法，以解决或缓解现有技术中的一项或更多项技术问题。
第一方面，本申请实施例提供一种读操作电路，应用于半导体存储器，半导体存储器包括DQ端口、DBI端口和存储块，读操作电路包括：
DBI编码模块，连接于存储块，用于从存储块中读出读取数据，并根据读取数据中为低的数据的位数，确定是否翻转读取数据，以输出供全局总线传输的全局总线数据和供DBI信号线传输的DBI数据，DBI端口用于接收DBI数据；
并串转换电路，通过全局总线连接于DQ端口和DBI编码模块之间，用于对全局总线数据进行并串转换，以生成DQ端口的输出数据；
数据缓冲模块，通过全局总线连接于存储块；
预充电模块，连接于预充电信号线，用于将全局总线的初始态设置为高。
在一种实施方式中，DBI编码模块用于在读取数据中为低的数据的位数大于预设值的情况下，将读取数据的翻转数据作为全局总线数据输出，并将DBI数据置为高；以及在读取数据中为低的数据的位数小于等于预设值的情况下，将原始的读取数据作为全局总线数据输出，并将DBI数据置为低。
在一种实施方式中，读取数据和全局总线数据均被划分为M组，DBI数据为M位，M位DBI数据与M组读取数据一一对应，并且M位DBI数据与M组全局总线数据一一对应，并串转换电路还连接于DBI编码模块和DBI端口之间，用于将M位DBI数据并串转换后输出至DBI端口，其中，M为大于1的整数。
在一种实施方式中，每组读取数据为N位，其中，N为大于1的整数，DBI编码模块用于在输入的一组读取数据中为低的数据的位数大于N/2的情况下，将输入的一组读取数据的翻转数据作为对应的一组全局总线数据输出，并将输入的一组读取数据对应的一位DBI数据置为高；以及在输入的一组读取数据中为低的数据的位数小于等于N/2的情况下，将输入的一组读取数据作为对应的一组全局总线数据输出，并将输入的一组读取数据对应的一位DBI数据置为低。
在一种实施方式中，DBI编码模块包括：
DBI编码单元，DBI编码单元的输入端连接于存储块，DBI编码单元的输出端与DBI信号线连接，DBI编码单元用于在读取数据中为低的数据的位数大于预设值的情况下，将DBI数据置为高；以及在读取数据中为低的数据的位数小于等于预设值的情况下，将DBI数据置为低；
数据选择器，数据选择器的输入端连接于DBI编码单元，用于通过DBI编码单元接收读取数据，数据选择器的输入端还通过DBI信号线接收DBI数据，数据选择器的输出端通过全局总线连接于并串转换电路，数据选择器用于在DBI数据为高的情况下，将读取数据的翻转数据作为全局总线数据输出；以及在DBI数据为高的情况下，将原始的读取数据作为全局总线数据输出。
在一种实施方式中，数据选择器包括多个数据选择单元，数据选择单元包括：
第一反相器，第一反相器的输入端通过DBI信号线接收DBI数据；
第二反相器，第二反相器的输入端连接于DBI编码单元，用于从DBI编码单元接收读取数据；
第一传输门，第一传输门的输入端连接于第二反相器的输出端，第一传输门的输出端与全局总线连接，用于输出全局总线数据，第一传输门的反控制端连接于第一反相器的输出端，第一传输门的正控制端通过DBI信号线接收DBI数据；
第二传输门，第二传输门的输入端连接于DBI编码单元，用于从DBI编码单元接收读取数据，第二传输门的输出端与全局总线连接，用于输出全局总线数据，第二传输门的反控制端通过DBI信号线接收DBI数据，第二传输门的正控制端连接于第一反相器的输出端。
在一种实施方式中，数据选择器包括多个数据选择单元，数据选择单元包括：
第三反相器，第三反相器的输入端通过DBI信号线接收DBI数据；
第四反相器，第四反相器的输入端连接于DBI编码单元，用于从DBI 编码单元接收读取数据；
第一逻辑与门，第一逻辑与门的第一输入端连接于DBI编码单元，用于从DBI编码单元接收读取数据，第一逻辑与门的第二输入端连接于第三反相器的输出端；
第二逻辑与门，第二逻辑与门的第一输入端通过DBI信号线接收DBI数据，第二逻辑与门的第二输入端连接于第四反相器的输出端；
逻辑或门，逻辑或门的两个输入端分别连接于第一逻辑与门的输出端和第二逻辑与门的输出端，逻辑或门的输出端与全局总线连接，用于输出全局总线数据。
在一种实施方式中，数据缓冲模块包括多个NMOS晶体管，NMOS晶体管的栅极连接于存储块，NMOS晶体管的漏极连接于全局总线；以及预充电模块包括多个PMOS晶体管和多个保持电路，PMOS晶体管的栅极连接于预充电信号线，PMOS晶体管的漏极连接于全局总线，保持电路的输入和输出端连接于全局总线。
第二方面，本申请实施例提供一种半导体存储器，包括DQ端口、DBI端口、存储块以及以上任一项的读操作电路
第三方面，本申请实施例提供一种读操作方法，应用于半导体存储器，半导体存储器包括DQ端口、DBI端口和存储块，读操作方法包括：
将全局总线的初始态设置为高；
从存储块中读出读取数据；
根据读取数据中为低的数据的位数，确定是否翻转读取数据，以输出供全局总线传输的全局总线数据和供DBI信号线传输的DBI数据；
对全局总线数据进行并串转换，以生成DQ端口的输出数据。
在一种实施方式中，根据读取数据中为低的数据的位数，确定是否翻转读取数据，以输出供全局总线传输的全局总线数据和供DBI信号线传输的DBI数据，包括：
在读取数据中为低的数据的位数大于预设值的情况下，将读取数据的 翻转数据作为全局总线数据输出，并将DBI数据置为高；
在读取数据中为低的数据的位数小于等于预设值的情况下，将原始的读取数据作为全局总线数据输出，并将DBI数据置为低。
在一种实施方式中，根据读取数据中为低的数据的位数，确定是否翻转读取数据，以输出供全局总线传输的全局总线数据和供DBI信号线传输的DBI数据，包括：
将读取数据划分为M组，其中，每组读取数据为N位，M和N均为大于1的整数；
在输入的一组读取数据中为低的数据的位数大于N/2的情况下，将输入的一组读取数据的翻转数据作为对应的一组全局总线数据输出，并将输入的一组读取数据对应的一位DBI数据置为高；
在输入的一组读取数据中为低的数据的位数小于等于N/2的情况下，将输入的一组读取数据作为对应的一组全局总线数据输出，并将输入的一组读取数据对应的一位DBI数据置为低。
本申请实施例采用上述技术方案，可以实现在Precharge上拉架构的全局总线上传输为“1”的数据较多，从而可以减少内部全局总线翻转次数，大幅压缩电流，降低功耗。
上述概述仅仅是为了说明书的目的，并不意图以任何方式进行限制。除上述描述的示意性的方面、实施方式和特征之外，通过参考附图和以下的详细描述，本申请进一步的方面、实施方式和特征将会是容易明白的。
附图说明
在附图中，除非另外规定，否则贯穿多个附图相同的附图标记表示相同或相似的部件或元素。这些附图不一定是按照比例绘制的。应该理解，这些附图仅描绘了根据本申请公开的一些实施方式，而不应将其视为是对本申请范围的限制。
图1示意性地示出了本实施例一种实施方式的半导体存储器部分结构 的框图；
图2示意性地示出了本实施例另一种实施方式的半导体存储器部分结构的框图；
图3示意性地示出了本实施例一种实施方式的数据缓冲模块的电路图(对应于一个存储块)；
图4示意性地示出了本实施例一种实施方式的数据缓冲模块的电路图(对应于多个存储块)；
图5示意性地示出了DBI功能的原理图；
图6示意性地示出了本实施例一种实施方式的DBI编码模块的框图；
图7-1示意性地示出了本实施例一种实施方式的数据选择单元的框图；
图7-2示意性地示出了本实施例另一种实施方式的数据选择单元的框图；
图8示意性地示出了本实施例一种实施方式的读操作方法的流程图。
附图标记说明：
10：控制器；
20：半导体存储器；
21：并串转换电路；
22：数据缓冲模块；
23：DBI编码模块；
24：DQ端口；
25：DBI端口；
26：存储块；
27：预充电模块；
221：PMOS管；
222：NMOS管；
223：保持电路；
231：DBI编码单元；
232：数据选择器；
232′：数据选择单元；
232A：第一反相器；
232B：第二反相器；
232C：第一传输门；
232D：第二传输门；
232E：第三反相器；
232F：第四反相器；
232G：第一逻辑与门；
232F：第二逻辑与门；
232K：逻辑或门。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的实施例；相反，提供这些实施例使得本申请将全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。在图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。
图1示意性地示出了本实施例一种实施方式的半导体存储器部分结构的框图。如图1所示，半导体存储器20包括DQ端口24、数据线翻转(Data Bus Inversion，DBI)端口25、存储块(Bank)26以及读操作电路。其中，读操作电路包括全局总线(Global Bus)、DBI信号线、并串转换电路21、数据缓冲模块(Data Buffer)22和DBI编码模块(Encoder)23。在一种实施方式中，半导体存储器20为DRAM，如第四代双倍速率同步动态随机存储器(D′uble Data Rate SDRAM 4，简称DDR4)。
在一个示例中，如图1所示，一次激活(Active)命令打开唯一指定 的存储块26，读操作也只能针对一个存储块26进行。也就是说，当八个存储块26(即Bank<7:0>)中有一个Bank工作的时候，其他Bank不工作。通过读操作电路，存储块26中的读取数据D<127:0>通过DQ端口24输出8位输出数据DQ<7:0>。需要说明的是，存储块26的数量、每个存储块26的数据位数以及DQ端口24的数据位数和数量，本实施例不作限定。例如：DQ端口24也可以为一个，用作输出16位输出数据；DQ端口24也可以为两个，即每个DQ端口24用作输出8位输出数据。
例如，如图2所示，输出数据DQ<7:0>通过上述的一个读操作电路对一组存储块Bank<7:0>执行读操作而得到；输出数据DQ<15:8>通过上述的另一个读操作电路对另一组存储块Bank<15:8>执行读操作而得到。相应地，与DQ<15:8>对应的八个存储块26(即Bank<15:8>)中，当有一个Bank工作的时候，其他Bank不工作。
半导体存储器20为阵列式结构，各单元结构可以相同，但因输入的数据不同，各单元输出的数据可能不同。下面以其中一个存储块为例，介绍本实施例的读操作电路。
DBI编码模块23连接于存储块26，用于从存储块26中读出读取数据，如D<127:0>，并根据读取数据中为低的数据的位数，确定是否翻转读取数据，以输出供全局总线传输的全局总线数据和供DBI信号线传输的DBI数据。其中，数据为高可以是数据等于“1”，数据为“低”可以是数据等于“0”。数据的翻转可以理解为从“0”变为“1”，或者，从“1”变为“0”。数据线或信号线的翻转可以理解为高电平变为低电平，或低电平变为高电平。
在一种实施方式中，DBI编码模块23用于在读取数据中为低的数据的位数大于预设值的情况下，将读取数据的翻转数据作为全局总线数据输出，并将DBI数据置为高；以及在读取数据中为低的数据的位数小于等于预设值的情况下，将原始的读取数据作为全局总线数据输出，并将DBI数据置为低。
在一个示例中，多位读取数据没有被分组，即DBI数据可以为一位，DBI编码模块23输出的DBI数据可以不经过并串转换电路21，而直接输出至DBI端口25中。在一个示例中，多位读取数据可以被分组。例如：在一种实施方式中，读取数据和全局总线数据均被划分为M组，DBI数据为M位，M位DBI数据与M组读取数据一一对应，并且M位DBI数据与M组全局总线数据一一对应，并串转换电路21还连接于DBI编码模块23和DBI端口25之间，用于将M位DBI数据并串转换后输出至DBI端口，其中，M为大于1的整数。需要说明的是，并串转换电路21可以包括两个并串转换模块，分别用于对全局总线数据和DBI数据进行并串转换，本实施例不作限定。
进一步地，每组读取数据可以为N位，其中，N为大于1的整数，DBI编码模块23用于在输入的一组读取数据中为低的数据的位数大于N/2的情况下，将输入的一组读取数据的翻转数据作为对应的一组全局总线数据输出，并将输入的一组读取数据对应的一位DBI数据置为高；以及在输入的一组读取数据中为低的数据的位数小于等于N/2的情况下，将输入的一组读取数据作为对应的一组全局总线数据输出，并将输入的一组读取数据对应的一位DBI数据置为低。
例如：读取数据D<127:0>被划分为16组，每组读取数据为8位，每组读取数据与一位DBI数据对应。相应地，DBI数据为16位，如DBI<15:0>。全局总线数据D′<127:0>相应也会被划分为16组，每一位DBI数据与一组全局总线数据对应。对于一组读取数据D<127:120>，如果D<127:120>中等于“0”的位数大于4位，则对应的DBI<15>＝1，输出的一组全局总线数据D′<120:127>等于D<127:120>的翻转数据；如果读取数据中等于“1”的位数小于等于4位，则对应的DBI<15>＝0，输出的一组全局总线数据D′<120:127>即为D<127:120>。
于是，当DBI<15>＝1时，从DBI编码模块23输出的全局总线数据D′<127：120>为存储块26(如Bank0)的读取数据D<127:120>的翻转数据； 当DBI<15>＝0时，从DBI编码模块23输出的全局总线数据D′<127：120>即为存储块26(如Bank0)的读取数据D<127:120>，即读取数据D′<127:120>＝D<127:120>。类似地，当DBI<1>＝1时，从DBI编码模块23输出的全局总线数据D′<15:8>为存储块26(如Bank0)的读取数据D<15:8>的翻转数据；当DBI<1>＝0时，从DBI编码模块23输出的全局总线数据D′<15:8>即为存储块26(如Bank0)的读取数据D<15:8>，即全局总线数据D′<15:8>＝D<15:8>。当DBI<0>＝1时，从DBI编码模块23输出的全局总线数据D′<7:0>为存储块26(如Bank0)的读取数据D<7:0>的翻转数据；当DBI<0>＝0时，从DBI编码模块23输出的全局总线数据D′<7：0>即为存储块26(如Bank0)的读取数据D<7:0>，即全局总线数据D′<7:0>＝D<7:0>。
在一个示例中，全局总线为多根且被划分为M(M为大于1的整数)组，每根全局总线传输一位所述全局总线数据。例如：全局总线为128根，128根全局总线分为16组。全局总线<0>传输全局总线数据D′<0>；全局总线<1>传输全局总线数据D′<1>；……；全局总线<127>传输全局总线数据D′<127>。
在一个示例中，DBI信号线为16根，每根DBI信号线传输1位DBI数据，如DBI信号线<0>传输DBI数据DBI<0>，并且与全局总线数据D′<0:7>对应，表征D′<0:7>是否为翻转后的数据；DBI信号线<1>传输DBI数据DBI<1>，并且与全局总线数据D′<8:15>对应，表征D′<8:15>是否为翻转后的数据；……；DBI信号线<15>传输DBI数据DBI<15>，并且与全局总线数据D′<120:127>对应，表征D′<120:127>是否为翻转后的数据。
并串转换电路21通过全局总线连接于DQ端口24和DBI编码模块23之间，用于对全局总线数据进行并串转换，以生成DQ端口24的输出数据。例如：并串转换电路21对Bank0的128位的全局总线数据D′<127:0>进行并串转换，进而生成8位的输出数据DQ<7:0>，并通过数据总线(data bus)传输给DQ端口24。从而，在全局总线上传输的全局总线数据D′<127:0> 中，为“1”的数据较多。相应地，在图2所示的半导体存储器20中，256位的全局总线数据(包括与DQ<7:0>对应的128位全局总线数据和与DQ<15:8>对应的128位全局总线数据)中，为“1”的数据较多。
数据缓冲模块22通过全局总线连接于存储块26，预充电模块27连接于预充电信号线(Precharge)，用于将全局总线的初始态设置为高。也就是说，本实施例中，半导体存储器20采用的是Precharge上拉的全局总线传输结构。
图3示意性地示出了本实施例一种实施方式的数据缓冲模块22和预充电模块27的电路图(对应于一个存储块26)。图4示意性地示出了本实施例一种实施方式的数据缓冲模块22和预充电模块27的电路图(对应于8个存储块26)。
如图3和图4所示，数据缓冲模块22包括多个NMOS(Negative Channel Metal Oxide Semiconductor)晶体管222，预充电模块27包括多个PMOS(Positive Channel Metal Oxide Semiconductor)晶体管221、和多个保持(hold)电路223。其中，PMOS晶体管221的栅极连接于预充电信号线，PMOS晶体管221的漏极连接于全局总线；NMOS晶体管222的栅极连接于存储块26，NMOS晶体管222的漏极连接于全局总线(Global Bus)；保持电路223的输入和输出端连接于全局总线，从而形成正反馈电路。
Precharge的作用是将每根全局总线的初始态设置为高，具体过程为Precharge产生一个上拉脉冲(pulse，大约2ns左右)，将相应的某根全局总线上拉片刻，保持电路223形成正反馈并将这根全局总线锁在高电平，但是该保持电路223的上拉和下拉电流的能力比较弱；当某根全局总线需要变为低电平的时候，将代表这根全局总线对应的数据线(即对应的NMOS晶体管222的栅极上连接的数据线)拉高一下(也是一个pulse，大约2ns左右)，这样相应的NMOS晶体管222就会将这根全局总线下拉片刻(下拉能力大于保持电路223的上拉能力)，然后会通过正反馈将这根全局总线锁到低电平，完成数据线的翻转动作。由于全局总线数据D′<127:0>中， 为“1”的数据较多，因此需要的翻转动作就会较少。因此，半导体存储器的IDD4R(读出电流)将会被降低，从而可以降低半导体存储器的功耗。
下面结合图5介绍DBI端口25的作用。从半导体存储器20输出的数据包括DBI端口25的DBI数据和DQ端口24的输出数据。当DBI端口25的DBI数据等于1时，输出数据如DQ<7:0>需要进行翻转后输出给控制器10；当DBI端口25的DBI数据等于0时，原始的输出数据可以直接发送给控制器10。半导体存储器20的片上终结电阻(On-Die Termination，ODT)可以将DQ端口24的电流吸收掉，防止信号在半导体存储器20的内部电路上形成反射。在半导体存储器20的工作过程中调节ODT的大小使之与控制器10匹配。在一个示例中，ODT结构为上拉结构，当DQ端口24的数据为“0”时，通过ODT的漏电流较大，这会增加功耗。在本实施例中，由于DQ端口24的输出数据中，为“1”的数据较多，因此可以进一步降低半导体存储器的功耗。
而相关技术中，DBI功能被使能(enable)的情况下，当半导体存储器在执行读操作时，对数据的翻转和编码的模块设置在数据快要出半导体存储器的位置，即位于并串转换的模块之后。因此，在相关技术中，半导体存储器内部全局总线传输的数据“0”较多，会造成IDD4R过大，功耗较高。
根据本实施例的半导体存储器20，在从半导体存储器20读出数据的过程中，当全局总线数据为256位时，如果需要256位全局总线数据翻转，将变成只有32位DBI数据在翻转，IDD4R电流将会大幅压缩。
在一种实施方式中，如图6所示，DBI编码模块包括DBI编码单元231和数据选择器232。
DBI编码单元231的输入端通过局部总线(local Bus)连接于存储块26，DBI编码单元231的输出端与DBI信号线连接，并与数据选择器232的输入端连接。DBI编码单元231用于在读取数据中为低的数据的位数大于预设值的情况下，将DBI数据置为高；以及在读取数据中为低的数据的 位数小于等于预设值的情况下，将DBI数据置为低。
在一个示例中，DBI编码单元231可以包括多个DBI编码子单元，每个DBI编码子单元用于处理一组读取数据，进而输出一位DBI数据。例如：数据选择单元DBI编码子单元可以有16个，分别对应于16组读取数据，进而输出16位DBI数据，其中，每组读取数据可以有8位。
数据选择器232的输入端连接于DBI编码单元231，用于通过DBI编码单元231接收读取数据，数据选择器232的输入端还通过DBI信号线接收DBI数据，数据选择器232的输出端通过全局总线连接于并串转换电路21。数据选择器232用于在DBI数据为高的情况下，将读取数据的翻转数据作为全局总线数据输出；以及在DBI数据为高的情况下，将原始的读取数据作为全局总线数据输出。
在一种实施方式中，数据选择器232包括多个数据选择单元232′，每个数据选择单元232′用于处理一位DBI数据和一组读取数据。例如：数据选择单元232′可以有16个，分别对应于16组读取数据和一位DBI数据，每组读取数据有8位。
图7-1和图7-2示出了数据选择单元232′两种不同的实现方式。
如图7-1所示，数据选择器232包括第一反相器232A、第二反相器232B、第一传输门232C和第二传输门232D。第一反相器232A的输入端通过DBI信号线接收DBI数据；第二反相器232B的输入端连接于DBI编码单元231，用于从DBI编码单元231接收读取数据；第一传输门232C的输入端连接于第二反相器232B的输出端，第一传输门232C的输出端与全局总线连接，用于输出全局总线数据，第一传输门232C的反控制端(图7-1中的上方控制端)连接于第一反相器232A的输出端，第一传输门232C的正控制端(图7-1中的下方控制端)通过DBI信号线接收DBI数据；第二传输门232D的输入端连接于DBI编码单元231，用于从DBI编码单元231接收读取数据，第二传输门232D的输出端与全局总线连接，用于输出全局总线数据，第二传输门232D的反控制端通过DBI信号线接收DBI数 据，第二传输门232D的正控制端连接于第一反相器232A的输出端。
以DBI<0>和读取数据D<7:0>为例，如图7-1所示，当DBI＝1时，全局总线数据D′<7:0>为读取数据D<7:0>的翻转数据；当DBI＝0时，全局总线数据D′<7:0>即为读取数据D<7:0>。
需要说明的是，一组第二反相器232B、第一传输门232C和第二传输门232D用于处理一位读取数据，输出一位对应的全局总线数据。也就说说，对应于8位的读取数据D<7:0>，第二反相器232A、第一传输门232C和第二传输门232D也应当有8组，进而输出8位的全局总线数据D<7:0>。
如图7-2所示，数据选择器232包括第三反相器232E、第四反相器232F、第一逻辑与门232G、第二逻辑与门232H和逻辑或门232K。第三反相器232E的输入端通过DBI信号线接收DBI数据；第四反相器232F的输入端连接于DBI编码单元231，用于从DBI编码单元231接收读取数据；第一逻辑与门232G的第一输入端连接于DBI编码单元231，用于从DBI编码单元231接收读取数据，第一逻辑与门232G的第二输入端连接于第三反相器232E的输出端；第二逻辑与门232H的第一输入端通过DBI信号线接收DBI数据，第二逻辑与门232H的第二输入端连接于第四反相器232F的输出端；逻辑或门232K的两个输入端分别连接于第一逻辑与门232G的输出端和第二逻辑与门232H的输出端，逻辑或门232K的输出端与全局总线连接，用于输出全局总线数据。
以DBI<0>和读取数据D<7:0>为例，如图7-2所示，当DBI＝1时，全局总线数据D′<7:0>为读取数据D<7:0>的翻转数据；当DBI＝0时，全局总线数据D′<7:0>即为读取数据D<7:0>。
需要说明的是，一组第四反相器232F、第一逻辑与门232G、第二逻辑与门232H和逻辑或门232K用于处理一位读取数据，输出一位对应的全局总线数据。也就说说，对应于8位的读取数据D<7:0>，第三反相器232E、第四反相器232F、第一逻辑与门232G、第二逻辑与门232H和逻辑或门232K也应当有8组，进而输出8位的全局总线数据D<7:0>。
本实施例的半导体存储器20在实际应用中还包括灵敏放大器、预充电电路等其他结构，因其均为现有技术本实施例在此不复赘述。
图8示出示意性地示出了本实施例一种实施方式的读操作方法的流程图。该读操作方法可以应用上述的半导体存储器20中。如图8所示，该读操作方法可以包括：
步骤S801、将全局总线的初始态设置为高；
步骤S802、从存储块中读出读取数据；
步骤S803、根据读取数据中为低的数据的位数，确定是否翻转读取数据，以输出供全局总线传输的全局总线数据和供DBI信号线传输的DBI数据；
步骤S804、对全局总线数据进行并串转换，以生成DQ端口的输出数据。
在一种实施方式中，在步骤S803中可以包括：在读取数据中为低的数据的位数大于预设值的情况下，将读取数据的翻转数据作为全局总线数据输出，并将DBI数据置为高；在读取数据中为低的数据的位数小于等于预设值的情况下，将原始的读取数据作为全局总线数据输出，并将DBI数据置为低。
在一种实施方式中，在步骤S803中可以包括：将读取数据划分为M组，其中，每组读取数据为N位，M和N均为大于1的整数；在输入的一组读取数据中为高的数据的位数大于N/2的情况下，将输入的一组读取数据的翻转数据作为对应的一组全局总线数据输出，并将输入的一组读取数据对应的一位DBI数据置为高；在输入的一组读取数据中为高的数据的位数小于等于N/2的情况下，将输入的一组读取数据作为对应的一组全局总线数据输出，并将输入的一组读取数据对应的一位DBI数据置为低。
本申请实施例提供的读操作电路，应用于全局总线传输结构为Precharge上拉的半导体存储器，通过将DBI编码模块设置在并串转换电路与存储块之间，可以实现全局总线上传输为“1”的数据较多，从而减少内 部全局总线翻转次数，可以大幅压缩电流，降低功耗。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施例或示例中。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
此外，所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。然而，本领域技术人员将意识到，可以实践本申请的技术方案而没有所述特定细节中的一个或更多，或者可以采用其它的方法、组元、材料、装置、步骤等。在其它情况下，不详细示出或描述公知结构、方法、装置、实现、材料或者操作以避免模糊本申请的各方面。
术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
需要说明的是，尽管在附图中以特定顺序描述了本申请中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。上述附图仅是根据本申请示例性实施例的方法所包括的处理的示意性说明，而不是限制目的。易于理解，上述附图所示的处理并不表明或限制这些处理的时间顺序。另外，也易于理解，这些处理可以是例如在多个模块中同步或异步执行的。
此外，虽然已经参考若干具体实施方式描述了本申请的精神和原理，但是应该理解，本申请并不限于所公开的具体实施方式，对各方面的划分 也不意味着这些方面中的特征不能组合以进行受益，这种划分仅是为了表述的方便。本申请旨在涵盖所附权利要求的精神和范围内所包括的各种修改和等同布置。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到其各种变化或替换，这些都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (12)

  1. 一种读操作电路，应用于半导体存储器，其特征在于，所述半导体存储器包括DQ端口、DBI端口和存储块，所述读操作电路包括：
    DBI编码模块，连接于所述存储块，用于从所述存储块中读出读取数据，并根据所述读取数据中为低的数据的位数，确定是否翻转所述读取数据，以输出供全局总线传输的全局总线数据和供DBI信号线传输的DBI数据，所述DBI端口用于接收所述DBI数据；
    并串转换电路，通过所述全局总线连接于所述DQ端口和所述DBI编码模块之间，用于对所述全局总线数据进行并串转换，以生成所述DQ端口的输出数据；
    数据缓冲模块，通过所述全局总线连接于所述存储块；
    预充电模块，连接于预充电信号线，用于将所述全局总线的初始态设置为高。
  2. 根据权利要求1所述的读操作电路，其特征在于，所述DBI编码模块用于在所述读取数据中为低的数据的位数大于预设值的情况下，将所述读取数据的翻转数据作为所述全局总线数据输出，并将所述DBI数据置为高；以及在所述读取数据中为低的数据的位数小于等于所述预设值的情况下，将原始的读取数据作为所述全局总线数据输出，并将所述DBI数据置为低。
  3. 根据权利要求1所述的读操作电路，其特征在于，所述读取数据和所述全局总线数据均被划分为M组，所述DBI数据为M位，M位DBI数据与M组读取数据一一对应，并且M位DBI数据与M组全局总线数据一一对应，所述并串转换电路还连接于所述DBI编码模块和所述DBI端口之间，用于将M位DBI数据并串转换后输出至所述DBI端口，其中，M为大于1的整数。
  4. 根据权利要求3所述的读操作电路，其特征在于，每组读取数据为 N位，其中，N为大于1的整数，所述DBI编码模块用于在输入的一组读取数据中为低的数据的位数大于N/2的情况下，将输入的一组读取数据的翻转数据作为对应的一组全局总线数据输出，并将输入的一组读取数据对应的一位DBI数据置为高；以及在输入的一组读取数据中为低的数据的位数小于等于N/2的情况下，将输入的一组读取数据作为对应的一组全局总线数据输出，并将输入的一组读取数据对应的一位DBI数据置为低。
  5. 根据权利要求1所述的读操作电路，其特征在于，所述DBI编码模块包括：
    DBI编码单元，所述DBI编码单元的输入端连接于所述存储块，所述DBI编码单元的输出端与所述DBI信号线连接，所述DBI编码单元用于在读取数据中为低的数据的位数大于预设值的情况下，将所述DBI数据置为高；以及在所述读取数据中为低的数据的位数小于等于所述预设值的情况下，将所述DBI数据置为低；
    数据选择器，所述数据选择器的输入端连接于所述DBI编码单元，用于通过所述DBI编码单元接收所述读取数据，所述数据选择器的输入端还通过所述DBI信号线接收所述DBI数据，所述数据选择器的输出端通过所述全局总线连接于所述并串转换电路，所述数据选择器用于在所述DBI数据为高的情况下，将所述读取数据的翻转数据作为所述全局总线数据输出；以及在所述DBI数据为高的情况下，将原始的读取数据作为所述全局总线数据输出。
  6. 根据权利要求5所述的读操作电路，其特征在于，所述数据选择器包括多个数据选择单元，所述数据选择单元包括：
    第一反相器，所述第一反相器的输入端通过所述DBI信号线接收所述DBI数据；
    第二反相器，所述第二反相器的输入端连接于所述DBI编码单元，用于从所述DBI编码单元接收所述读取数据；
    第一传输门，所述第一传输门的输入端连接于所述第二反相器的输出 端，所述第一传输门的输出端与所述全局总线连接，用于输出所述全局总线数据，所述第一传输门的反控制端连接于所述第一反相器的输出端，所述第一传输门的正控制端通过所述DBI信号线接收所述DBI数据；
    第二传输门，所述第二传输门的输入端连接于所述DBI编码单元，用于从所述DBI编码单元接收所述读取数据，所述第二传输门的输出端与所述全局总线连接，用于输出所述全局总线数据，所述第二传输门的反控制端通过所述DBI信号线接收所述DBI数据，所述第二传输门的正控制端连接于所述第一反相器的输出端。
  7. 根据权利要求5所述的读操作电路，其特征在于，所述数据选择器包括多个数据选择单元，所述数据选择单元包括：
    第三反相器，所述第三反相器的输入端通过所述DBI信号线接收所述DBI数据；
    第四反相器，所述第四反相器的输入端连接于所述DBI编码单元，用于从所述DBI编码单元接收所述读取数据；
    第一逻辑与门，所述第一逻辑与门的第一输入端连接于所述DBI编码单元，用于从所述DBI编码单元接收所述读取数据，所述第一逻辑与门的第二输入端连接于所述第三反相器的输出端；
    第二逻辑与门，所述第二逻辑与门的第一输入端通过所述DBI信号线接收所述DBI数据，所述第二逻辑与门的第二输入端连接于所述第四反相器的输出端；
    逻辑或门，所述逻辑或门的两个输入端分别连接于所述第一逻辑与门的输出端和所述第二逻辑与门的输出端，所述逻辑或门的输出端与所述全局总线连接，用于输出所述全局总线数据。
  8. 根据权利要求1至7任一项所述的读操作电路，其特征在于，所述数据缓冲模块包括多个NMOS晶体管，所述NMOS晶体管的栅极连接于所述存储块，所述NMOS晶体管的漏极连接于所述全局总线；以及所述预充电模块包括多个PMOS晶体管和多个保持电路，所述PMOS晶体管的栅 极连接于所述预充电信号线，所述PMOS晶体管的漏极连接于所述全局总线，所述保持电路的输入和输出端连接于所述全局总线。
  9. 一种半导体存储器，其特征在于，包括DQ端口、DBI端口、存储块以及权利要求1至8任一项所述的读操作电路。
  10. 一种读操作方法，应用于半导体存储器，其特征在于，所述半导体存储器包括DQ端口、DBI端口和存储块，所述读操作方法包括：
    将全局总线的初始态设置为高；
    从所述存储块中读出读取数据；
    根据所述读取数据中为低的数据的位数，确定是否翻转所述读取数据，以输出供所述全局总线传输的全局总线数据和供DBI信号线传输的DBI数据；
    对所述全局总线数据进行并串转换，以生成所述DQ端口的输出数据。
  11. 根据权利要求10所述的读操作方法，其特征在于，根据所述读取数据中为低的数据的位数，确定是否翻转所述读取数据，以输出供全局总线传输的全局总线数据和供DBI信号线传输的DBI数据，包括：
    在所述读取数据中为低的数据的位数大于预设值的情况下，将所述读取数据的翻转数据作为所述全局总线数据输出，并将所述DBI数据置为高；
    在所述读取数据中为低的数据的位数小于等于所述预设值的情况下，将原始的读取数据作为所述全局总线数据输出，并将所述DBI数据置为低。
  12. 根据权利要求10所述的读操作方法，其特征在于，根据所述读取数据中为低的数据的位数，确定是否翻转所述读取数据，以输出供全局总线传输的全局总线数据和供DBI信号线传输的DBI数据，包括：
    将所述读取数据划分为M组，其中，每组读取数据为N位，M和N均为大于1的整数；
    在输入的一组读取数据中为低的数据的位数大于N/2的情况下，将输入的一组读取数据的翻转数据作为对应的一组全局总线数据输出，并将输入的一组读取数据对应的一位DBI数据置为高；
    在输入的一组读取数据中为低的数据的位数小于等于N/2的情况下，将输入的一组读取数据作为对应的一组全局总线数据输出，并将输入的一组读取数据对应的一位DBI数据置为低。
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