WO2021077779A1 - 写操作电路、半导体存储器和写操作方法 - Google Patents

写操作电路、半导体存储器和写操作方法 Download PDF

Info

Publication number
WO2021077779A1
WO2021077779A1 PCT/CN2020/097409 CN2020097409W WO2021077779A1 WO 2021077779 A1 WO2021077779 A1 WO 2021077779A1 CN 2020097409 W CN2020097409 W CN 2020097409W WO 2021077779 A1 WO2021077779 A1 WO 2021077779A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
dbi
global bus
port
input
Prior art date
Application number
PCT/CN2020/097409
Other languages
English (en)
French (fr)
Inventor
张良
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP20879032.9A priority Critical patent/EP3886100B1/en
Priority to US17/242,281 priority patent/US11803319B2/en
Publication of WO2021077779A1 publication Critical patent/WO2021077779A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/107—Serial-parallel conversion of data or prefetch

Definitions

  • This application relates to the technical field of semiconductor memory, and in particular to a write operation circuit, a semiconductor memory and a write operation method.
  • Semiconductor memory includes Static Random-Access Memory (SRAM), Dynamic Random Access Memory (DRAM), and Synchronous Dynamic Random Access Memory (SDRAM) , Read-Only Memory (ROM), flash memory, etc.
  • SRAM Static Random-Access Memory
  • DRAM Dynamic Random Access Memory
  • SDRAM Synchronous Dynamic Random Access Memory
  • ROM Read-Only Memory
  • the embodiments of the present application provide a write operation circuit, a semiconductor memory, and a write operation method to solve or alleviate one or more technical problems in the prior art.
  • an embodiment of the present application provides a write operation circuit applied to a semiconductor memory.
  • the semiconductor memory includes a DQ port, a DBI port, and a memory block.
  • the write operation circuit includes:
  • the serial-to-parallel conversion circuit is connected to the DBI port and the DQ port for serial-to-parallel conversion of the first DBI data of the DBI port to generate the second DBI data for transmission by the DBI signal line, and according to the second DBI data and the DQ port Input data to generate the input data of the data buffer module;
  • the data buffer module includes a plurality of PMOS transistors.
  • the gate of the PMOS transistor is connected to the serial-to-parallel conversion circuit to receive the input data of the data buffer module.
  • the drain of the PMOS transistor is connected to the global bus.
  • the data buffer module is used to buffer the module according to the data Input data to determine whether to flip the global bus;
  • the DBI decoding module is connected to the storage block.
  • the DBI decoding module receives the global bus data on the global bus, and receives the second DBI data through the DBI signal line, and is used to decode and decode the global bus data according to the second DBI data
  • the subsequent data is written into the storage block, and decoding includes determining whether to flip the global bus data;
  • the precharge module is connected to the precharge signal line and is used to set the initial state of the global bus to low.
  • the first DBI data when the number of bits of the high data in the external data is greater than the preset value, the first DBI data is set to high, and the input data of the DQ port is the inverted data of the external data; In the case that the number of bits of the medium-high data is less than or equal to the preset value, the first DBI data is set to low, and the input data of the DQ port is external data; and the serial-to-parallel conversion circuit is used to serialize the input data of the DQ port And convert to generate converted data, and in the case that the second DBI data is high, flip the converted data to generate the input data of the data buffer module, in the case of the second DBI data is low, convert the converted data As the input data of the data buffer module.
  • the serial-to-parallel conversion circuit is used to perform serial-to-parallel conversion on one bit of the first DBI data to generate M bits of second DBI data.
  • the global bus data is divided into M groups, and the M bits of second DBI data is combined with M groups of global bus data have a one-to-one correspondence;
  • DBI decoding module includes M DBI decoding sub-modules, DBI decoding sub-modules are connected to the storage block, each DBI decoding sub-module is used to correspond to the global bus of the corresponding group according to one bit of second DBI data The data is decoded; where M is an integer greater than 1.
  • the DBI decoding sub-module includes:
  • the first inverter the input terminal of the first inverter is connected to the DBI signal line;
  • the decoding unit the input end of the decoding unit is connected to the global bus, and the output end of the decoding unit is connected to the storage block, and is used to output the inverted data of the global bus data when the second DBI data is high; and in the second DBI data When it is low, output the original global bus data.
  • the decoding unit includes:
  • the second inverter the input terminal of the second inverter is connected to the global bus
  • a first logical AND gate two input terminals of the first logical AND gate are respectively connected to the output terminal of the first inverter and the output terminal of the second inverter;
  • the second logic AND gate, the two input terminals of the second logic AND gate are respectively connected to the DBI signal line and the global bus;
  • the two input terminals of the logic NOR gate are respectively connected to the output terminal of the first logic AND gate and the output terminal of the second logic AND gate, and the output terminal of the logic NOR gate is connected to the memory block.
  • the pre-charging module includes a plurality of NMOS transistors and a plurality of holding circuits, the gate of the NMOS transistor is connected to the pre-charging signal line, the drain of the NMOS transistor is connected to the global bus, and the input and output terminals of the holding circuit Connect to the global bus.
  • an embodiment of the present application provides a semiconductor memory including a DQ port, a DBI port, a memory block, and a write operation circuit for any of the above.
  • an embodiment of the present application provides a write operation method applied to a semiconductor memory.
  • the semiconductor memory includes a DQ port, a DBI port, and a memory block.
  • the write operation method includes:
  • the decoding includes determining whether to flip the global bus data
  • generating input data of the data buffer module according to the second DBI data and the input data of the DQ port includes:
  • the converted data is used as the input data of the data buffer module.
  • decoding the global bus data on the global bus according to the second DBI data includes:
  • the global bus data of the corresponding group is decoded.
  • the embodiment of the present application adopts the above technical solution, which can reduce the number of flips of the global bus under the Precharge pull-down architecture, thereby greatly compressing current and reducing power consumption.
  • FIG. 1 schematically shows a block diagram of a partial structure of a semiconductor memory in an implementation manner of this embodiment
  • FIG. 2 schematically shows a block diagram of a partial structure of a semiconductor memory in another implementation manner of this embodiment
  • Figure 3 schematically shows a schematic diagram of the DBI function
  • FIG. 4 schematically shows a circuit diagram (corresponding to a storage block) of a data buffer module and a precharge module in an implementation manner of this embodiment
  • FIG. 5 schematically shows a circuit diagram (corresponding to multiple storage blocks) of a data buffer module and a precharge module in an implementation manner of this embodiment
  • FIG. 6 schematically shows a block diagram of a DBI decoding module in an implementation manner of this embodiment
  • FIG. 7 schematically shows a block diagram of a DBI decoding submodule in an implementation manner of this embodiment
  • FIG. 8 schematically shows a flowchart of a write operation method in an implementation manner of this embodiment.
  • FIG. 1 schematically shows a block diagram of a part of the structure of a semiconductor memory in an implementation manner of this embodiment.
  • the semiconductor memory 20 includes a DQ port 24, a data line inversion (Data Bus Inversion, DBI) port 25, a bank 26, and a write operation circuit.
  • the write operation circuit includes a global bus (Global Bus). , DBI signal line, serial-to-parallel conversion circuit 21, data buffer module (Data Buffer) 22, DBI decoder module (Decoder) 23, and pre-charge module 27.
  • the semiconductor memory is a DRAM, such as the fourth-generation double-rate synchronous dynamic random access memory (Double Data Rate SDRAM 4, DDR4 for short).
  • the 8-bit input data DQ ⁇ 7:0> input from the DQ port 24 writes the write data D ⁇ 127:0> into the memory block 26 through the write operation circuit.
  • An Active command opens the only designated storage block 26, and the write operation can only be performed on one storage block 26. In other words, when one of the eight memory blocks 26 (ie, Bank ⁇ 7:0>) is working, the other banks are not working.
  • the number of storage blocks 26, the number of data bits of each storage block 26, and the number and number of data bits of the DQ port 24 are not limited in this embodiment.
  • DQ port 24 can also be one, used to input 8-bit input data; DQ port 24 can also be two, that is, each DQ port 24 is used to input 8-bit input data DQ ⁇ 7:0> or DQ ⁇ 15 :8>, and then input 16-bit input data DQ ⁇ 15:0>.
  • the input data DQ ⁇ 7:0> applies the above-mentioned write operation circuit to a group of memory blocks.
  • Bank ⁇ 7:0> performs a write operation;
  • the input data DQ ⁇ 15:8> performs a write operation on another group of memory blocks Bank ⁇ 15:8> through the above-mentioned another write operation circuit.
  • the eight memory blocks 26 ie Bank ⁇ 15:8>
  • the other Banks do not work.
  • the function of DBI port 25 is described below in conjunction with Figure 3.
  • the on-die termination (ODT) of the semiconductor memory 20 can absorb the current of the DQ port 24 through the ground pin to prevent the signal from being reflected on the internal circuit of the semiconductor memory 20.
  • the size of the ODT is adjusted to match the controller 10.
  • the ODT structure is a pull-down structure. When the data of the DQ port 24 is "1", the leakage current through the ODT is relatively large, which will increase power consumption.
  • the first DBI data of the DBI port 25 is set high, and the external data is flipped to obtain the input data of the DQ port; in the external data, it is When the number of bits of the high data is less than or equal to the preset value, the first DBI data is set to low, and the input data of the DQ port is the external data.
  • each bit of external data will be flipped and input into the semiconductor memory 20, and at the same time the first DBI data of the DBI port is set to high for Indicates that the input data is external data after inversion.
  • the input data DQ ⁇ 7:0> is ⁇ 00000000> and the first DBI data is equal to 0, it means that the input data DQ ⁇ 7:0> is the original external data, that is, the external data is also ⁇ 00000000>; if the input The data DQ ⁇ 7:0> is ⁇ 00000000> and the first DBI data is equal to 1, indicating that the input data DQ ⁇ 7:0> is the data after the external data is inverted, that is, the external data is ⁇ 11111111>.
  • the data being high can mean that the data is equal to "1”
  • the data being “low” can be that the data is equal to "0”.
  • Data flipping can be understood as changing from “0” to “1”, or from “1” to "0".
  • the inversion of the data line or the signal line can be understood as a high level changing to a low level, or a low level changing to a high level.
  • the semiconductor memory 20 has an array structure, and the structure of each unit may be the same, but due to different input data, the output data of each unit may be different.
  • the following takes one of the memory blocks as an example to introduce the write operation circuit of this embodiment.
  • the serial-to-parallel conversion circuit 21 is connected to the DBI port 25 and is used to perform serial-to-parallel conversion on the first DBI data of the DBI port 25 to generate second DBI data for transmission by the DBI signal line.
  • the serial-to-parallel conversion circuit 21 is connected to the DQ port 24 for generating input data of the data buffer module 22 according to the second DBI data and the input data DQ of the DQ port.
  • the serial-to-parallel conversion circuit 21 is used to perform serial-to-parallel conversion on the input data of the DQ port 24 to generate converted data, and according to the second DBI data, determine whether to flip the converted data to generate a data buffer The input data of the module.
  • the serial-to-parallel conversion circuit 21 performs serial-to-parallel conversion on the input 8-bit input data DQ ⁇ 7:0> to generate 128-bit converted data, and then determines according to the 16-bit second DBI data DBI ⁇ 0:15> Whether to flip the converted data, and then output 128-bit input data D2' ⁇ 127:0> to the data buffer module 22.
  • the 128-bit converted data is divided into 16 groups, each group of converted data is 8 bits, one second DBI data corresponds to a group of 8-bit converted data, and then a group of 8-bit input is generated Data D2'.
  • serial-to-parallel conversion circuit 21 may include two serial-to-parallel conversion modules, which are respectively used to perform serial-to-parallel conversion on the input data of the DQ port 24 and the first DBI data, which is not limited in this embodiment.
  • the precharge module 27 is connected to the precharge signal line (Precharge), and is used to set the initial state of the global bus to low.
  • the semiconductor memory 20 adopts a precharge pull-down (Low) global bus transmission structure.
  • FIG. 4 schematically shows a circuit diagram (corresponding to a storage block 26) of the data buffer module 22 in an implementation manner of this embodiment.
  • Fig. 5 schematically shows a circuit diagram (corresponding to 8 storage blocks 26) of the data buffer module 22 in an implementation of this embodiment.
  • the data buffer module 22 includes a plurality of PMOS (Positive Channel Metal Oxide Semiconductor) transistors 221, and the precharge module 27 includes a plurality of NMOS (Negative Channel Metal Oxide Semiconductor) transistors 222 and a plurality of hold (hold ) Circuit 223.
  • PMOS Physical Channel Metal Oxide Semiconductor
  • NMOS Negative Channel Metal Oxide Semiconductor
  • the gate of the PMOS transistor 221 is connected to the serial-to-parallel conversion circuit 21 to receive the input data of the data buffer module 22, and the drain of the PMOS transistor 221 is connected to the global bus, so that the data buffer module 22 will respond according to the input of the data buffer module 22 Data, determine whether to flip the global bus; the gate of the NMOS transistor 222 is connected to the precharge signal line, the drain of the NMOS transistor 222 is connected to the global bus; the input and output terminals of the holding circuit 223 are connected to the global bus, thereby forming a positive feedback circuit .
  • Precharge The function of Precharge is to set the initial state of each global bus to low.
  • the specific process is that Precharge generates a pull-down pulse (pulse, about 2ns), pulls down the corresponding global bus for a while, and the holding circuit 223 forms a positive feedback.
  • This global bus is locked at low level, but the ability of the holding circuit 223 to pull up and pull down current is relatively weak; when a certain global bus needs to change to high level, it will represent the data line corresponding to this global bus (That is, the data line connected to the gate of the corresponding PMOS transistor 221) is pulled down (also a pulse, about 2ns), so that the corresponding PMOS transistor 221 will pull up the global bus for a while (the pull-up capacity is greater than The pull-down capability of the circuit 223 is maintained), and then the global bus is locked to a high level through positive feedback to complete the data line inversion action.
  • the input data DQ ⁇ 7:0> of the DQ port 24 has more data "0", it has not been decoded at this time, so in the 128-bit global bus data D1' ⁇ 127:0>, it is " 0" has more data.
  • the semiconductor memory 20 shown in FIG. 2 in the input data DQ ⁇ 15:0>, there are many "0" data. Since it has not been decoded at this time, the 256-bit global bus data (including Among the 128-bit global bus data corresponding to DQ ⁇ 7:0> and the 128-bit global bus data corresponding to DQ ⁇ 15:8>, there are many "0" data.
  • the DBI decoding module 23 is connected to the storage block 26 and receives the second DBI data through the DBI signal line, and receives the global bus data through the global bus.
  • the DBI decoding module 23 is configured to decode the global bus data according to the second DBI data, and write the decoded data into the storage block 26.
  • the decoding includes determining whether to invert the global bus data. Among them, the decoded data is the written data, such as D ⁇ 127:0>. In other words, before the data is written into the memory block 26, more data of "0" is transmitted on the global bus.
  • the semiconductor memory when the DBI function is enabled, when the semiconductor memory is performing a write operation, when the input data just enters the semiconductor memory, the semiconductor memory will decode the input data according to the state of the DBI port . If the status of DBI is "1", all input data will be inverted (flip); if the status of DBI is "0", all input data will not be inverted, which is the original value.
  • This decoded module is located just before the input data enters the semiconductor memory, that is, before the serial-parallel conversion module. Therefore, in the related art, there are more data "1"s transmitted by the global bus inside the semiconductor memory, which will cause the IDD4W to be too large and the power consumption to be higher.
  • the first DBI data has only one bit
  • the serial-to-parallel conversion circuit 21 is used to perform serial-to-parallel conversion on one bit of the first DBI data to generate M bits of second DBI data.
  • the serial-to-parallel conversion circuit 21 can perform serial-to-parallel conversion on one bit of the data of the DBI port 25 to generate 16-bit second DBI data DBI ⁇ 15:0>.
  • the global bus data is divided into M groups, and the M-bit second DBI data corresponds to the M groups of global bus data one-to-one.
  • the DBI decoding module 23 includes M DBI decoding sub-modules 230. Each DBI decoding sub-module 230 is connected to a storage block 26. Each DBI decoding sub-module 230 is used for one bit of second DBI data, Decode the global bus data of the corresponding group; where M is an integer greater than 1.
  • the DBI decoding module 23 outputs the inverted data of the global bus data when the second DBI data is high; and outputs the original global bus data when the second DBI data is low.
  • the global bus data D1' ⁇ 127:0> is divided into 16 groups, and each group of global bus data is 8 bits.
  • the second DBI data is 16 bits, such as DBI ⁇ 15:0>.
  • each global bus transmits one bit of global bus data.
  • M is an integer greater than 1
  • each global bus transmits one bit of global bus data.
  • Global bus ⁇ 0> transmits global bus data D1' ⁇ 0>;
  • global bus ⁇ 1> transmits global bus data D1' ⁇ 1>;
  • global bus ⁇ 127> transmits global bus data D1' ⁇ 127>.
  • each DBI signal line transmits 1 bit of the second DBI data.
  • the DBI signal line ⁇ 0> transmits the second DBI data DBI ⁇ 0>, which is used to characterize the write data D ⁇ 7:0> is the data after the global bus data D1' ⁇ 7:0> is flipped;
  • DBI signal line ⁇ 1> transmits the second DBI data DBI ⁇ 1>, which is used to characterize whether the write data D ⁇ 8:15> It is the data after the global bus data D1' ⁇ 8:15> is inverted; ...;
  • the DBI signal line ⁇ 15> transmits the second DBI data DBI ⁇ 15>, which is used to characterize whether the write data D ⁇ 120:127> is global The data after bus data D1' ⁇ 120:127> is flipped.
  • the semiconductor memory 20 of this embodiment when DQ ⁇ 7:0> is input for the first time ⁇ 00000000> and the first DBI data is equal to 0; when the second time is input ⁇ 00000000> and the first DBI data is equal to 1, the corresponding every The group global bus data (8 bits) will always be ⁇ 00000000> before being written into the memory block 26, and only one bit of the second DBI data corresponding to it is equal to 1. Therefore, in this embodiment, when the global bus data is 256 bits (including 128-bit global bus data corresponding to DQ ⁇ 7:0> and 128-bit global bus data corresponding to DQ ⁇ 15:8>), if necessary If the 256-bit global bus data is flipped, only the 32-bit second DBI data will be flipped. The IDD4W current will be greatly compressed.
  • the DBI decoding sub-module 230 may include a first inverter 231 and a decoding unit 232.
  • the input terminal of the first inverter 231 is connected to the DBI signal line
  • the input terminal of the decoding unit 232 is connected to the global bus
  • the output terminal of the decoding unit 232 is connected to the storage block 26, which is used when the second DBI data is high , Output the inverted data of the global bus data; and when the second DBI data is low, output the original global bus data.
  • the decoding unit 232 includes: a second inverter 232A, a first logical AND gate 232B, a second logical AND gate 232C, and a logical NOR gate 232D.
  • the input terminal of the second inverter 232A is connected to the global bus;
  • the two input terminals of the first logical AND gate 232B are respectively connected to the output terminal of the first inverter 231 and the output terminal of the second inverter 232A;
  • the two input terminals of the second logic AND gate 232C are respectively connected to the DBI signal line and the global bus;
  • the two input terminals of the logic NOR gate 232D are respectively connected to the output terminal of the first logic AND gate 232B and the second logic AND gate 232C
  • the output terminal of the logic NOR gate 232D is connected to the storage block 26.
  • each DBI decoding sub-module 230 is the same, but because the input data is different, the output data is different.
  • FIG. 7 shows the structure of one of the DBI decoding sub-modules 230.
  • the data input to the DBI decoding sub-module is D1' ⁇ 7:0> and DBI ⁇ 0>, and the output data is D ⁇ 7:0>.
  • this embodiment does not limit the implementation circuit of the DBI decoding sub-module 230, as long as the inversion data of the global bus data can be output when the second DBI data is 1, and the global bus data is output when the second DBI data is 0. can.
  • the semiconductor memory 20 of this embodiment also includes other structures such as a sense amplifier, a precharge circuit, etc., because they are all the prior art, and this embodiment will not be repeated here.
  • FIG. 8 shows a flowchart schematically showing a write operation method in an implementation manner of this embodiment.
  • This writing operation method can be applied to the semiconductor memory 20 described above.
  • the write operation method may include:
  • Step S801 Set the initial state of the global bus to low
  • Step S802 Perform serial-to-parallel conversion on the first DBI data of the DBI port to generate second DBI data;
  • Step S803 Generate input data of the data buffer module according to the second DBI data and the input data of the DQ port;
  • Step S804 Determine whether to flip the global bus according to the input data of the data buffer module
  • Step S805 Decode the global bus data on the global bus according to the second DBI data, and the decoding includes determining whether to flip the global bus data;
  • Step S806 Write the decoded data into the storage block.
  • step S803 may include: performing serial-to-parallel conversion on the input data of the DQ port to generate converted data; in the case that the second DBI data is high, flip the converted data to generate data The input data of the buffer module; when the second DBI data is low, the converted data is used as the input data of the data buffer module.
  • step S805 may include: serial-to-parallel conversion of one bit of the first DBI data of the DBI port to generate M bits of second DBI data, where M is an integer greater than; and converting the global bus data Divide into M groups; according to one bit of second DBI data, decode the global bus data of the corresponding group.
  • the write operation circuit provided by the embodiment of the application is applied to a semiconductor memory whose global bus transmission structure is Precharge pull-down.
  • a semiconductor memory whose global bus transmission structure is Precharge pull-down.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the present application, "a plurality of” means two or more than two, unless otherwise specifically defined.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)

Abstract

本申请实施例提供一种写操作电路、半导体存储器和写操作方法，包括：串并转换电路，用于对DBI端口的第一DBI数据进行串并转换，以生成供DBI信号线传输的第二DBI数据，以及根据第二DBI数据和DQ端口的输入数据，生成数据缓冲模块的输入数据；数据缓冲模块，用于根据数据缓冲模块的输入数据，确定是否翻转全局总线；DBI解码模块，用于根据第二DBI数据，对全局总线数据进行解码，并将解码后的数据写入存储块，解码包括确定是否翻转全局总线数据；预充电模块，连接于预充电信号线，用于将全局总线的初始态设置为低。本申请实施例的技术方案可以实现在下拉架构下，减少全局总线的翻转次数，从而大幅压缩电流，降低功耗。

Description

写操作电路、半导体存储器和写操作方法
本申请要求于2019年10月25日提交中国专利局、申请号为201911021458.4、发明名称为“写操作电路、半导体存储器和写操作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体存储器技术领域，尤其涉及一种写操作电路、半导体存储器和写操作方法。
背景技术
本部分旨在为权利要求书中陈述的本申请的实施例提供背景或上下文。此处的描述不因为包括在本部分中就承认是现有技术。
半导体存储器包括静态随机存取存储器(Static Random-Access Memory，简称SRAM)、动态随机存取存储器(Dynamic Random Access Memory，简称DRAM)、同步动态随机存取内存(Synchronous Dynamic Random Access Memory，简称SDRAM)、只读存储器(Read-Only Memory，简称ROM)、闪存等。
在固态技术协会(Joint Electron Device Engineering Council，JEDEC)的DRAM协议中，对DRAM的速度、省电都有具体要求。如何使DRAM更省电的同时，亦能保证信号的完整性以及数据传输和存储的可靠性，是行业内亟待解决的问题。
发明内容
本申请实施例提供一种写操作电路、半导体存储器和写操作方法，以解决或缓解现有技术中的一项或更多项技术问题。
第一方面，本申请实施例提供一种写操作电路，应用于半导体存储器，该半导体存储器包括DQ端口、DBI端口和存储块，写操作电路包括：
串并转换电路，连接于DBI端口和DQ端口，用于对DBI端口的第一DBI数据进行串并转换，以生成供DBI信号线传输的第二DBI数据，以及根据第二DBI数据和DQ端口的输入数据，生成数据缓冲模块的输入数据；
数据缓冲模块，包括多个PMOS晶体管，PMOS晶体管的栅极连接于串并转换电路，以接收数据缓冲模块的输入数据，PMOS晶体管的漏极连接于全局总线，数据缓冲模块用于根据数据缓冲模块的输入数据，确定是否翻转全局总线；
DBI解码模块，连接于存储块，DBI解码模块接收全局总线上的全局总线数据，并通过DBI信号线接收第二DBI数据，并用于根据第二DBI数据，对全局总线数据进行解码，并将解码后的数据写入存储块，解码包括确定是否翻转全局总线数据；
预充电模块，连接于预充电信号线，用于将全局总线的初始态设置为低。
在一种实施方式中，在外部数据中为高的数据的位数大于预设值的情况下，第一DBI数据被置为高，DQ端口的输入数据为外部数据的翻转数据；在外部数据中为高的数据的位数小于等于预设值的情况下，第一DBI数据被置为低，DQ端口的输入数据为外部数据；以及串并转换电路用于对DQ端口的输入数据进行串并转换，以生成转换后数据，并在第二DBI数据为高的情况下，翻转转换后数据，以生成数据缓冲模块的输入数据，在第二DBI数据为低的情况下，将转换后数据作为数据缓冲模块的输入数据。
在一种实施方式中，串并转换电路用于对一位第一DBI数据进行串并转换，以生成M位第二DBI数据，全局总线数据被划分为M组，M位第二DBI数据与M组全局总线数据一一对应；DBI解码模块包括M个DBI解码子模块，DBI解码子模块连接于存储块，各DBI解码子模块用于根据一位第二DBI数据，对对应组的全局总线数据进行解码；其中，M为大于1的整数。
在一种实施方式中，DBI解码子模块包括：
第一反相器，第一反相器的输入端连接于DBI信号线；
解码单元，解码单元的输入端连接于全局总线，解码单元的输出端连接于存储块，用于在第二DBI数据为高的情况下，输出全局总线数据的翻转数据；以及在第二DBI数据为低的情况下，输出原始的全局总线数据。
在一种实施方式中，解码单元包括：
第二反相器，第二反相器的输入端连接于全局总线；
第一逻辑与门，第一逻辑与门的两个输入端分别连接于第一反相器的输出端和第二反相器的输出端；
第二逻辑与门，第二逻辑与门的两个输入端分别连接于DBI信号线和全局总线；
逻辑或非门，逻辑或非门的两个输入端分别连接于第一逻辑与门的输出端和第二逻辑与门的输出端，逻辑或非门的输出端连接于存储块。
在一种实施方式中，预充电模块包括多个NMOS晶体管和多个保持电路，NMOS晶体管的栅极连接于预充电信号线，NMOS晶体管的漏极连接于全局总线，保持电路的输入和输出端连接于全局总线。
第二方面，本申请实施例提供一种半导体存储器，包括DQ端口、DBI端口、存储块以及以上任一项的写操作电路。
第三方面，本申请实施例提供一种写操作方法，应用于半导体存储器，该半导体存储器包括DQ端口、DBI端口和存储块，写操作方法包括：
将全局总线的初始态设置为低；
对DBI端口的第一DBI数据进行串并转换，以生成第二DBI数据；
根据第二DBI数据和DQ端口的输入数据，生成数据缓冲模块的输入数据；
根据数据缓冲模块的输入数据，确定是否翻转全局总线；
根据第二DBI数据，对全局总线上的全局总线数据进行解码，解码包括确定是否翻转全局总线数据；
将解码后的数据写入存储块。
在一种实施方式中，根据第二DBI数据和DQ端口的输入数据，生成数据缓冲模块的输入数据，包括：
对DQ端口的输入数据进行串并转换，以生成转换后数据；
在第二DBI数据为高的情况下，翻转转换后数据，以生成数据缓冲模块的输入数据；
在第二DBI数据为低的情况下，将转换后数据作为数据缓冲模块的输入数据。
在一种实施方式中，根据第二DBI数据，对全局总线上的全局总线数据进行解码，包括：
对DBI端口的一位第一DBI数据进行串并转换，以生成M位第二DBI数据，其中，M为大于的整数；
将全局总线数据划分为M组；
根据一位第二DBI数据，对对应组的全局总线数据进行解码。
本申请实施例采用上述技术方案，可以实现在Precharge下拉架构下，减少全局总线的翻转次数，从而可以大幅压缩电流，降低功耗。
上述概述仅仅是为了说明书的目的，并不意图以任何方式进行限制。除上述描述的示意性的方面、实施方式和特征之外，通过参考附图和以下的详细描述，本申请进一步的方面、实施方式和特征将会是容易明白的。
附图说明
在附图中，除非另外规定，否则贯穿多个附图相同的附图标记表示相同或相似的部件或元素。这些附图不一定是按照比例绘制的。应该理解，这些附图仅描绘了根据本申请公开的一些实施方式，而不应将其视为是对本申请范围的限制。
图1示意性地示出了本实施例一种实施方式的半导体存储器部分结构的框图；
图2示意性地示出了本实施例另一种实施方式的半导体存储器部分结构的框图；
图3示意性地示出了DBI功能的原理图；
图4示意性地示出了本实施例一种实施方式的数据缓冲模块和预充电模块的电路图(对应于一个存储块)；
图5示意性地示出了本实施例一种实施方式的数据缓冲模块和预充电模块的电路图(对应于多个存储块)；
图6示意性地示出了本实施例一种实施方式的DBI解码模块的框图；
图7示意性地示出了本实施例一种实施方式的DBI解码子模块的框图；
图8示意性地示出了本实施例一种实施方式的写操作方法的流程图。
附图标记说明：
10：控制器；
20：半导体存储器；
21：串并转换电路；
22：数据缓冲模块；
23：DBI解码模块；
24：DQ端口；
25：DBI端口；
26：存储块；
27：预充电模块；
221：PMOS管；
222：NMOS管；
223：保持电路；
230：DBI解码子模块；
231：第一反相器；
232：解码单元；
232A：第二反相器；
232B：第一逻辑与门；
232C：第二逻辑与门；
232D：逻辑或非门。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的实施例；相反，提供这些实施例使得本申请将全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。在图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。
图1示意性地示出了本实施例一种实施方式的半导体存储器部分结构的框图。如图1所示，半导体存储器20包括DQ端口24、数据线翻转(Data Bus Inversion，DBI)端口25、存储块(Bank)26以及写操作电路，其中，写操作电路包括全局总线(Global Bus)、DBI信号线、串并转换电路21、数据缓冲模块(Data Buffer)22、DBI解码模块(Decoder)23和预充电模块27。在一种实施方式中，半导体存储器为DRAM，如第四代双倍速率同步动态随机存储器(Double Data Rate SDRAM 4，简称DDR4)。
在一个示例中，如图1所示，从DQ端口24输入的8位输入数据DQ<7:0>通过写操作电路，将写入数据D<127:0>写入存储块26。一次激活(Active)命令打开唯一指定的存储块26，写操作也只能针对一个存储块26进行。也就是说，当八个存储块26(即Bank<7:0>)中，有一个Bank工作的时候，其他Bank不工作。需要说明的是，存储块26的数量、每个存储块26的数据位数以及DQ端口24的数据位数和数量，本实施例不作限定。例如：DQ端口24也可以为一个，用作输入8位输入数据；DQ端口24也可以为两个，即每个DQ端口24用作输入8位输入数据DQ<7:0>或DQ<15:8>，进而输入16位输入数据DQ<15:0>。
在另一个示例中，如图2所示，从DQ端口24输入的16位输入数据DQ<15:0>中，输入数据DQ<7:0>通过上述的一个写操作电路对一组存储块Bank<7:0>执行写操作；输入数据DQ<15:8>通过上述的另一个写操作电路对另一组存储块Bank<15:8>执行写操作。相应地，与DQ<15:8>对应的八个存储块26(即Bank<15:8>)中，当有一个Bank工作的时候，其他Bank不工作。
下面结合图3介绍DBI端口25的作用。半导体存储器20的片上终结电阻(On-Die Termination，ODT)可以将DQ端口24的电流通过接地引脚吸收掉，防止信号在半导体存储器20的内部电路上形成反射。在半导体存储器20的工作过程中调节ODT的大小使之与控制器10匹配。在一个示例中，ODT结构为下拉结构，当DQ端口24的数据为“1”时，通过ODT的漏电流较大，这会增加功耗。因此，在外部数据中为高的数据的位数大于预设值的情况下，DBI端口25的第一DBI数据被置为高，并翻转外部数据得到DQ端口的输入数据；在外部数据中为高的数据的位数小于等于预设值的情况下，第一DBI数据被置为低，DQ端口的输入数据即为外部数据。
例如：向DQ端口24写入的外部数据中，如果“1”的数据较多，则每位外部数据都会被翻转后输入半导体存储器20，同时DBI端口的第一DBI数据置为高，用于指示输入数据为翻转后的外部数据。例如：如果输入数据DQ<7:0>为<00000000>且第一DBI数据等于0，则表示输入数据DQ<7:0>为原始的外部数据，即外部数据也为<00000000>；如果输入数据DQ<7:0>为<00000000>且第一DBI数据等于1，则表示输入数据DQ<7:0>为外部数据翻转后的数据，即外部数据为<11111111>。DQ端口24的输入数据DQ<15:8>亦是同样的道理。从而，DQ端口24的输入数据DQ<15:0>中，为“0”的数据较多，从而可以降低功耗。
其中，数据为高可以是数据等于“1”，数据为“低”可以是数据等于“0”。数据的翻转可以理解为从“0”变为“1”，或者，从“1”变为“0”。 数据线或信号线的翻转可以理解为高电平变为低电平，或低电平变为高电平。
半导体存储器20为阵列式结构，各单元结构可以相同，但因输入的数据不同，各单元输出的数据可能不同。下面以其中一个存储块为例，介绍本实施例的写操作电路。
如图1所示，串并转换电路21连接于DBI端口25，用于对DBI端口25的第一DBI数据进行串并转换，以生成供DBI信号线传输的第二DBI数据。串并转换电路21连接于DQ端口24，用于根据第二DBI数据和DQ端口的输入数据DQ，生成数据缓冲模块22的输入数据。
在一种实施方式中，串并转换电路21用于对DQ端口24的输入数据进行串并转换，以生成转换后数据，并根据第二DBI数据，确定是否翻转转换后数据，以生成数据缓冲模块的输入数据。
例如：串并转换电路21对输入的8位输入数据DQ<7:0>进行串并转换，生成128位的转换后数据，然后根据16位的第二DBI数据DBI<0:15>，确定是否翻转转换数据，进而向数据缓冲模块22输出128位的输入数据D2′<127:0>。
在一个示例中，128位的转换后数据被分为16组，每组转换后数据为8位，一位第二DBI数据对应一组8位的转换后数据，进而生成一组8位的输入数据D2′。
需要说明的是，串并转换电路21可以包括两个串并转换模块，分别用于对DQ端口24的输入数据和第一DBI数据进行串并转换，本实施例不作限定。
预充电模块27连接于预充电信号线(Precharge)，用于将全局总线的初始态设置为低。也就是说，本实施例中，半导体存储器20采用的是Precharge下拉(Low)的全局总线传输结构。
图4示意性地示出了本实施例一种实施方式的数据缓冲模块22的电路图(对应于一个存储块26)。图5示意性地示出了本实施例一种实施方式 的数据缓冲模块22的电路图(对应于8个存储块26)。
如图4和图5所示，数据缓冲模块22包括多个PMOS(Positive Channel Metal Oxide Semiconductor)晶体管221，预充电模块27包括多个NMOS(Negative Channel Metal Oxide Semiconductor)晶体管222和多个保持(hold)电路223。其中，PMOS晶体管221的栅极连接于串并转换电路21，以接收数据缓冲模块22的输入数据，PMOS晶体管221的漏极连接于全局总线，从而数据缓冲模块22将根据数据缓冲模块22的输入数据，确定是否翻转全局总线；NMOS晶体管222的栅极连接于预充电信号线，NMOS晶体管222的漏极连接于全局总线；保持电路223的输入和输出端连接于全局总线，从而形成正反馈电路。
Precharge的作用是将每根全局总线的初始态设置为低，具体过程为Precharge产生一个下拉脉冲(pulse，大约2ns左右)，将相应的某根全局总线下拉片刻，保持电路223形成正反馈并将这根全局总线锁在低电平，但是该保持电路223的上拉和下拉电流的能力比较弱；当某根全局总线需要变为高电平的时候，将代表这根全局总线对应的数据线(即对应的PMOS晶体管221的栅极上连接的数据线)拉低一下(也是一个pulse，大约2ns左右)，这样相应的PMOS晶体管221就会将这根全局总线上拉片刻(上拉能力大于保持电路223的下拉能力)，然后会通过正反馈将这根全局总线锁到高电平，完成数据线的翻转动作。
由于数据缓冲模块22的输入数据D2′<127:0>(即PMOS晶体管221的栅极连接的数据线上的数据)中，为“1”的数据较多，因此需要翻转的全局总线的数量就会较少，并且全局总线数据D1′<127:0>中，为“0”的数据较多。因此，半导体存储器的IDD4W(写入电流)将会被降低，从而可以降低半导体存储器的功耗。也就是说，如果全局总线数据中为“0”的数据较多，则可以减低IDD4W，从而降低功耗。
由于DQ端口24的输入数据DQ<7:0>中，为“0”的数据较多，由于此时还未解码，因此，128位的全局总线数据D1′<127:0>中，为“0”的数 据较多。相应地，在图2所示的半导体存储器20中，输入数据DQ<15:0>中，为“0”的数据较多，由于此时还未解码，因此，256位的全局总线数据(包括与DQ<7:0>对应的128位全局总线数据和与DQ<15:8>对应的128位全局总线数据)中，为“0”的数据较多。
进一步地，DBI解码模块23通过连接于存储块26，并通过DBI信号线接收第二DBI数据，通过全局总线接收全局总线数据。DBI解码模块23用于根据第二DBI数据，对全局总线数据进行解码，并将解码后的数据写入存储块26，该解码包括确定是否翻转全局总线数据。其中，解码后的数据即为写入数据，如D<127:0>。也就是说，在数据被写入存储块26之前，全局总线上传输的为“0”的数据较多。
而相关技术中，DBI功能被使能(enable)的情况下，当半导体存储器在执行写操作时，输入数据在刚进入半导体存储器内部时，半导体存储器即会根据DBI端口的状态对输入数据进行解码。如果DBI的状态为“1”，所有的输入数据都会取反(翻转)；如果DBI的状态为“0”，所有的输入数据不翻转，即为原先的值。这个解码的模块在输入数据刚进入半导体存储器的位置，即位于串并转换的模块之前。因此，在相关技术中，半导体存储器内部全局总线传输的数据“1”较多，会造成IDD4W过大，功耗较高。
在一种实施方式中，第一DBI数据只有一位，串并转换电路21用于对一位第一DBI数据进行串并转换，以生成M位第二DBI数据。例如：串并转换电路21可以对一位DBI端口25的数据进行串并转换，生成16位第二DBI数据DBI<15:0>。
全局总线数据被划分为M组，M位第二DBI数据与M组全局总线数据一一对应。如图6所示，DBI解码模块23包括M个DBI解码子模块230，每个DBI解码子模块230均连接于一个存储块26，各DBI解码子模块230用于根据一位第二DBI数据，对对应组的全局总线数据进行解码；其中，M为大于1的整数。
DBI解码模块23在第二DBI数据为高的情况下，输出全局总线数据的翻转数据；以及在第二DBI数据为低的情况下，输出原始的全局总线数据。
例如：全局总线数据D1′<127:0>被划分为16组，每组全局总线数据为8位，相应地，第二DBI数据为16位，如DBI<15:0>。每组全局总线数据与一位DBI数据对应。于是，当DBI<15>＝1时，从DBI解码模块23输出的解码后的数据，即向存储块26(如Bank0)写入的写入数据D<127:120>为全局总线数据D1′<127：120>的翻转数据；当DBI<15>＝0时，写入数据D<127:120>即为全局总线数据D1′<127：120>。类似地，当DBI<1>＝1时，写入数据D<15:8>为全局总线数据D1′<15:8>的翻转数据；当DBI<1>＝0时，写入数据D<15:8>即为全局总线数据D1′<15:8>。当DBI<0>＝1时，写入数据D<7:0>为全局总线数据D1′<7:0>的翻转数据；当DBI<0>＝0时，写入数据D<7:0>即为全局总线数据D1′<7:0>。
在一个示例中，全局总线为多根且被划分为M(M为大于1的整数)组，每根全局总线传输一位全局总线数据。例如：全局总线为128根，128根全局总线分为16组。全局总线<0>传输全局总线数据D1′<0>；全局总线<1>传输全局总线数据D1′<1>；……；全局总线<127>传输全局总线数据D1′<127>。
在一个示例中，DBI信号线为16根，每根DBI信号线传输1位第二DBI数据，如DBI信号线<0>传输第二DBI数据DBI<0>，用于表征写入数据D<7:0>是否为全局总线数据D1′<7:0>翻转后的数据；DBI信号线<1>传输第二DBI数据DBI<1>，用于表征写入数据D<8:15>是否为全局总线数据D1′<8:15>翻转后的数据；……；DBI信号线<15>传输第二DBI数据DBI<15>，用于表征写入数据D<120:127>是否为全局总线数据D1′<120:127>翻转后的数据。
根据本实施例的半导体存储器20，当DQ<7:0>第一次输入<00000000>且第一DBI数据等于0；第二次输入<00000000>且第一DBI数据等于1 时，对应的每组全局总线数据(8位)，在写入存储块26之前将会一直是<00000000>，只有与其对应的一位第二DBI数据等于1。因此，本实施例中，当全局总线数据为256位(包括与DQ<7:0>对应的128位全局总线数据和与DQ<15:8>对应的128位全局总线数据)时，如果需要256位全局总线数据翻转，将变成只有32位第二DBI数据在翻转，IDD4W电流将会大幅压缩。
在一种实施方式中，如图7所示，DBI解码子模块230可以包括第一反相器231和解码单元232。第一反相器231的输入端连接于DBI信号线，解码单元232的输入端连接于全局总线，解码单元232的输出端连接于存储块26，用于在第二DBI数据为高的情况下，输出全局总线数据的翻转数据；以及在第二DBI数据为低的情况下，输出原始的全局总线数据。
在一种实施方式中，解码单元232包括：第二反相器232A、第一逻辑与门232B、第二逻辑与门232C和逻辑或非门232D。其中，第二反相器232A的输入端连接于全局总线；第一逻辑与门232B的两个输入端分别连接于第一反相器231的输出端和第二反相器232A的输出端；第二逻辑与门232C的两个输入端分别连接于DBI信号线和全局总线；逻辑或非门232D的两个输入端分别连接于第一逻辑与门232B的输出端和第二逻辑与门232C的输出端，逻辑或非门232D的输出端连接于存储块26。
如图7所示，以DBI<0>、写入数据D<7:0>和全局总线数据D1′<7:0>对应的解码单元232为例，当DBI<0>＝1时，D<7>等于D1′<7>的翻转数据，……，D<1>等于D1′<1>的翻转数据，D<0>等于D1′<0>的翻转数据；当DBI<0>＝0时，D<7>等于D1′<7>，……，D<1>等于D1′<1>，D<0>等于D1′<0>。
需要说明的是，每个DBI解码子模块230的相同，但因输入的数据不同，输出的数据不同。图7示出了其中一个DBI解码子模块230的结构，输入该DBI解码子模块的数据为D1′<7:0>和DBI<0>，输出的数据为D<7:0>。另外，本实施例不对DBI解码子模块230的实现电路不作限定， 只要可以在第二DBI数据为1时，输出全局总线数据的翻转数据，在第二DBI数据为0时，输出全局总线数据即可。
本实施例的半导体存储器20在实际应用中还包括灵敏放大器、预充电电路等其他结构，因其均为现有技术本实施例在此不复赘述。
图8示出示意性地示出了本实施例一种实施方式的写操作方法的流程图。该写操作方法可以应用上述的半导体存储器20中。如图8所示，该写操作方法可以包括：
步骤S801、将全局总线的初始态设置为低；
步骤S802、对DBI端口的第一DBI数据进行串并转换，以生成第二DBI数据；
步骤S803、根据第二DBI数据和DQ端口的输入数据，生成数据缓冲模块的输入数据；
步骤S804、根据数据缓冲模块的输入数据，确定是否翻转全局总线；
步骤S805、根据第二DBI数据，对全局总线上的全局总线数据进行解码，解码包括确定是否翻转全局总线数据；
步骤S806、将解码后的数据写入存储块。
在一种实施方式中，在步骤S803中可以包括：对DQ端口的输入数据进行串并转换，以生成转换后数据；在第二DBI数据为高的情况下，翻转转换后数据，以生成数据缓冲模块的输入数据；在第二DBI数据为低的情况下，将转换后数据作为数据缓冲模块的输入数据。
在一种实施方式中，在步骤S805中可以包括：对DBI端口的一位第一DBI数据进行串并转换，以生成M位第二DBI数据，其中，M为大于的整数；将全局总线数据划分为M组；根据一位第二DBI数据，对对应组的全局总线数据进行解码。
本申请实施例提供的写操作电路，应用于全局总线传输结构为Precharge下拉的半导体存储器，通过将DBI解码模块设置在串并转换电路与存储块之间，可以实现在数据被写入存储块之前，全局总线上传输为“0” 的数据较多，从而减少内部全局总线翻转次数，可以大幅压缩电流，降低功耗。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施例或示例中。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
此外，所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。然而，本领域技术人员将意识到，可以实践本申请的技术方案而没有所述特定细节中的一个或更多，或者可以采用其它的方法、组元、材料、装置、步骤等。在其它情况下，不详细示出或描述公知结构、方法、装置、实现、材料或者操作以避免模糊本申请的各方面。
术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
需要说明的是，尽管在附图中以特定顺序描述了本申请中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。上述附图仅是根据本申请示例性实施例的方法所包括的处理的示意性说明，而不是限制目的。易于理解，上述附图所示的处理并不表明或限制这些处理的时间顺序。另外，也易于理解，这些处理可以是例如在多个模块中同步或异步执行的。
此外，虽然已经参考若干具体实施方式描述了本申请的精神和原理， 但是应该理解，本申请并不限于所公开的具体实施方式，对各方面的划分也不意味着这些方面中的特征不能组合以进行受益，这种划分仅是为了表述的方便。本申请旨在涵盖所附权利要求的精神和范围内所包括的各种修改和等同布置。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到其各种变化或替换，这些都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (10)

  1. 一种写操作电路，应用于半导体存储器，其特征在于，所述半导体存储器包括DQ端口、DBI端口和存储块，所述写操作电路包括：
    串并转换电路，连接于所述DBI端口和所述DQ端口，用于对所述DBI端口的第一DBI数据进行串并转换，以生成供DBI信号线传输的第二DBI数据，以及根据所述第二DBI数据和所述DQ端口的输入数据，生成数据缓冲模块的输入数据；
    数据缓冲模块，包括多个PMOS晶体管，所述PMOS晶体管的栅极连接于所述串并转换电路，以接收所述数据缓冲模块的输入数据，所述PMOS晶体管的漏极连接于全局总线，所述数据缓冲模块用于根据所述数据缓冲模块的输入数据，确定是否翻转所述全局总线；
    DBI解码模块，连接于所述存储块，所述DBI解码模块接收所述全局总线上的全局总线数据，并通过所述DBI信号线接收所述第二DBI数据，并用于根据所述第二DBI数据，对所述全局总线数据进行解码，并将解码后的数据写入所述存储块，所述解码包括确定是否翻转所述全局总线数据；
    预充电模块，连接于预充电信号线，用于将所述全局总线的初始态设置为低。
  2. 根据权利要求1所述的写操作电路，其特征在于，在外部数据中为高的数据的位数大于预设值的情况下，所述第一DBI数据被置为高，所述DQ端口的输入数据为所述外部数据的翻转数据；在所述外部数据中为高的数据的位数小于等于所述预设值的情况下，所述第一DBI数据被置为低，所述DQ端口的输入数据为所述外部数据；以及所述串并转换电路用于对所述DQ端口的输入数据进行串并转换，以生成转换后数据，并在所述第二DBI数据为高的情况下，翻转所述转换后数据，以生成所述数据缓冲模块的输入数据，在所述第二DBI数据为低的情况下，将所述转换后数据作为所述数据缓冲模块的输入数据。
  3. 根据权利要求1所述的写操作电路，其特征在于，所述串并转换电路用于对一位第一DBI数据进行串并转换，以生成M位第二DBI数据，所述全局总线数据被划分为M组，M位第二DBI数据与M组全局总线数据一一对应；所述DBI解码模块包括M个DBI解码子模块，所述DBI解码子模块连接于所述存储块，各所述DBI解码子模块用于根据一位第二DBI数据，对对应组的全局总线数据进行所述解码；其中，M为大于1的整数。
  4. 根据权利要求3所述的写操作电路，其特征在于，所述DBI解码子模块包括：
    第一反相器，所述第一反相器的输入端连接于所述DBI信号线；
    解码单元，所述解码单元的输入端连接于所述全局总线，所述解码单元的输出端连接于所述存储块，用于在所述第二DBI数据为高的情况下，输出所述全局总线数据的翻转数据；以及在所述第二DBI数据为低的情况下，输出原始的全局总线数据。
  5. 根据权利要求4所述的写操作电路，其特征在于，所述解码单元包括：
    第二反相器，所述第二反相器的输入端连接于所述全局总线；
    第一逻辑与门，所述第一逻辑与门的两个输入端分别连接于所述第一反相器的输出端和所述第二反相器的输出端；
    第二逻辑与门，所述第二逻辑与门的两个输入端分别连接于所述DBI信号线和所述全局总线；
    逻辑或非门，所述逻辑或非门的两个输入端分别连接于所述第一逻辑与门的输出端和所述第二逻辑与门的输出端，所述逻辑或非门的输出端连接于所述存储块。
  6. 根据权利要求1至5任一项所述的写操作电路，其特征在于，所述预充电模块包括多个NMOS晶体管和多个保持电路，所述NMOS晶体管的栅极连接于所述预充电信号线，所述NMOS晶体管的漏极连接于所述全 局总线，所述保持电路的输入和输出端连接于所述全局总线。
  7. 一种半导体存储器，其特征在于，包括DQ端口、DBI端口、存储块以及权利要求1至6任一项所述的写操作电路。
  8. 一种写操作方法，应用于半导体存储器，其特征在于，所述半导体存储器包括DQ端口、DBI端口和存储块，所述写操作方法包括：
    将全局总线的初始态设置为低；
    对所述DBI端口的第一DBI数据进行串并转换，以生成第二DBI数据；
    根据所述第二DBI数据和所述DQ端口的输入数据，生成数据缓冲模块的输入数据；
    根据所述数据缓冲模块的输入数据，确定是否翻转所述全局总线；
    根据所述第二DBI数据，对所述全局总线上的全局总线数据进行解码，所述解码包括确定是否翻转所述全局总线数据；
    将解码后的数据写入所述存储块。
  9. 根据权利要求8所述的写操作方法，其特征在于，根据所述第二DBI数据和所述DQ端口的输入数据，生成数据缓冲模块的输入数据，包括：
    对所述DQ端口的输入数据进行串并转换，以生成转换后数据；
    在所述第二DBI数据为高的情况下，翻转所述转换后数据，以生成所述数据缓冲模块的输入数据；
    在所述第二DBI数据为低的情况下，将所述转换后数据作为所述数据缓冲模块的输入数据。
  10. 根据权利要求8所述的写操作方法，其特征在于，根据所述第二DBI数据，对所述全局总线上的全局总线数据进行解码，包括：
    对DBI端口的一位第一DBI数据进行串并转换，以生成M位第二DBI数据，其中，M为大于的整数；
    将所述全局总线数据划分为M组；
    根据一位第二DBI数据，对对应组的全局总线数据进行所述解码。
PCT/CN2020/097409 2019-10-25 2020-06-22 写操作电路、半导体存储器和写操作方法 WO2021077779A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP20879032.9A EP3886100B1 (en) 2019-10-25 2020-06-22 Write operation circuit, semiconductor memory, and write operation method
US17/242,281 US11803319B2 (en) 2019-10-25 2021-04-27 Write operation circuit, semiconductor memory and write operation method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201911021458.4A CN112712832A (zh) 2019-10-25 2019-10-25 写操作电路、半导体存储器和写操作方法
CN201911021458.4 2019-10-25

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/242,281 Continuation US11803319B2 (en) 2019-10-25 2021-04-27 Write operation circuit, semiconductor memory and write operation method

Publications (1)

Publication Number Publication Date
WO2021077779A1 true WO2021077779A1 (zh) 2021-04-29

Family

ID=75541415

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/097409 WO2021077779A1 (zh) 2019-10-25 2020-06-22 写操作电路、半导体存储器和写操作方法

Country Status (4)

Country Link
US (1) US11803319B2 (zh)
EP (1) EP3886100B1 (zh)
CN (1) CN112712832A (zh)
WO (1) WO2021077779A1 (zh)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5216637A (en) * 1990-12-07 1993-06-01 Trw Inc. Hierarchical busing architecture for a very large semiconductor memory
CN1702768A (zh) * 2004-05-26 2005-11-30 恩益禧电子股份有限公司 半导体存储装置
CN104272389A (zh) * 2012-05-18 2015-01-07 美光科技公司 用于低功率多电平经编码信号的方法及设备
CN108630255A (zh) * 2017-03-17 2018-10-09 爱思开海力士有限公司 半导体存储器件、标志生成电路以及输出半导体器件中的数据的方法
CN109643563A (zh) * 2016-08-10 2019-04-16 美光科技公司 具有数据总线的半导体分层装置
CN210575117U (zh) * 2019-10-25 2020-05-19 长鑫存储技术(上海)有限公司 写操作电路和半导体存储器
CN210667805U (zh) * 2019-10-25 2020-06-02 长鑫存储技术(上海)有限公司 写操作电路和半导体存储器

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3784979B2 (ja) * 1999-02-09 2006-06-14 株式会社東芝 バス駆動回路
US6674671B1 (en) * 2002-08-14 2004-01-06 Broadcom Corp. Circuit for lines with multiple drivers
JP2007133987A (ja) * 2005-11-11 2007-05-31 Toshiba Corp 半導体記憶装置および半導体記憶装置の駆動方法
US8127204B2 (en) * 2008-08-15 2012-02-28 Micron Technology, Inc. Memory system and method using a memory device die stacked with a logic die using data encoding, and system using the memory system
US9432298B1 (en) * 2011-12-09 2016-08-30 P4tents1, LLC System, method, and computer program product for improving memory systems
KR20150038792A (ko) * 2013-09-30 2015-04-09 에스케이하이닉스 주식회사 반도체 메모리 장치 및 이의 데이터 입출력 방법
US9983925B2 (en) * 2014-04-11 2018-05-29 Micron Technology, Inc. Apparatuses and methods for fixing a logic level of an internal signal line
JP6200370B2 (ja) * 2014-04-23 2017-09-20 ルネサスエレクトロニクス株式会社 データバス駆動回路、それを備えた半導体装置及び半導体記憶装置
US9405721B2 (en) * 2014-06-06 2016-08-02 Micron Technology, Inc. Apparatuses and methods for performing a databus inversion operation
KR20160093430A (ko) * 2015-01-29 2016-08-08 에스케이하이닉스 주식회사 반도체 메모리 장치 및 이의 데이터 입출력 방법
KR102457144B1 (ko) * 2017-04-18 2022-10-20 에스케이하이닉스 주식회사 메모리 시스템 및 메모리 시스템의 동작 방법
US10621116B2 (en) * 2017-06-08 2020-04-14 Western Digital Technologies, Inc. Non-volatile storage device with adaptive data bus inversion
US10425260B2 (en) * 2017-08-07 2019-09-24 Micron Technology, Inc. Multi-level signaling in memory with wide system interface
CN108509365B (zh) * 2018-01-23 2020-08-04 东莞市爱协生智能科技有限公司 一种dbi的数据传输方法及系统
US10128842B1 (en) * 2018-03-23 2018-11-13 Micron Technology, Inc. Output impedance calibration for signaling
US10747693B2 (en) * 2018-05-10 2020-08-18 Micron Technology, Inc. Semiconductor device with a time multiplexing mechanism for size efficiency

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5216637A (en) * 1990-12-07 1993-06-01 Trw Inc. Hierarchical busing architecture for a very large semiconductor memory
CN1702768A (zh) * 2004-05-26 2005-11-30 恩益禧电子股份有限公司 半导体存储装置
CN104272389A (zh) * 2012-05-18 2015-01-07 美光科技公司 用于低功率多电平经编码信号的方法及设备
CN109643563A (zh) * 2016-08-10 2019-04-16 美光科技公司 具有数据总线的半导体分层装置
CN108630255A (zh) * 2017-03-17 2018-10-09 爱思开海力士有限公司 半导体存储器件、标志生成电路以及输出半导体器件中的数据的方法
CN210575117U (zh) * 2019-10-25 2020-05-19 长鑫存储技术(上海)有限公司 写操作电路和半导体存储器
CN210667805U (zh) * 2019-10-25 2020-06-02 长鑫存储技术(上海)有限公司 写操作电路和半导体存储器

Also Published As

Publication number Publication date
EP3886100B1 (en) 2024-01-17
EP3886100A1 (en) 2021-09-29
US20210247927A1 (en) 2021-08-12
US11803319B2 (en) 2023-10-31
EP3886100A4 (en) 2022-04-13
CN112712832A (zh) 2021-04-27

Similar Documents

Publication Publication Date Title
WO2021077777A1 (zh) 读操作电路、半导体存储器和读操作方法
CN210575117U (zh) 写操作电路和半导体存储器
WO2021077778A1 (zh) 读操作电路、半导体存储器和读操作方法
US11816351B2 (en) Write operation circuit, semiconductor memory, and write operation method
CN210667805U (zh) 写操作电路和半导体存储器
WO2021077783A1 (zh) 写操作电路、半导体存储器和写操作方法
WO2021077773A1 (zh) 写操作电路、半导体存储器和写操作方法
WO2021077779A1 (zh) 写操作电路、半导体存储器和写操作方法
CN211125037U (zh) 写操作电路和半导体存储器
CN210667807U (zh) 读操作电路和半导体存储器
WO2021077774A1 (zh) 写操作电路、半导体存储器和写操作方法
WO2021077776A1 (zh) 读操作电路、半导体存储器和读操作方法
WO2021077775A1 (zh) 读操作电路、半导体存储器和读操作方法
WO2021077780A1 (zh) 读操作电路、半导体存储器和读操作方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20879032

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2020879032

Country of ref document: EP

Effective date: 20210623

NENP Non-entry into the national phase

Ref country code: DE