WO2021077776A1 - 读操作电路、半导体存储器和读操作方法 - Google Patents

读操作电路、半导体存储器和读操作方法 Download PDF

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WO2021077776A1
WO2021077776A1 PCT/CN2020/097399 CN2020097399W WO2021077776A1 WO 2021077776 A1 WO2021077776 A1 WO 2021077776A1 CN 2020097399 W CN2020097399 W CN 2020097399W WO 2021077776 A1 WO2021077776 A1 WO 2021077776A1
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Prior art keywords
data
global bus
read
output
bits
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PCT/CN2020/097399
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English (en)
French (fr)
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张良
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长鑫存储技术有限公司
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Priority to EP20879580.7A priority Critical patent/EP3926633A4/en
Priority to US17/240,922 priority patent/US11928067B2/en
Publication of WO2021077776A1 publication Critical patent/WO2021077776A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G06F13/4077—Precharging or discharging
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/107—Serial-parallel conversion of data or prefetch

Definitions

  • This application relates to the technical field of semiconductor memory, and in particular to a read operation circuit, a semiconductor memory and a read operation method.
  • Semiconductor memory includes Static Random-Access Memory (SRAM), Dynamic Random Access Memory (DRAM), and Synchronous Dynamic Random Access Memory (SDRAM) , Read-Only Memory (ROM), flash memory, etc.
  • SRAM Static Random-Access Memory
  • DRAM Dynamic Random Access Memory
  • SDRAM Synchronous Dynamic Random Access Memory
  • ROM Read-Only Memory
  • the embodiments of the present application provide a read operation circuit, a semiconductor memory, and a read operation method to solve or alleviate one or more technical problems in the prior art.
  • an embodiment of the present application provides a read operation circuit, which is applied to a semiconductor memory.
  • the semiconductor memory includes a DQ port and a memory block, and the read operation circuit includes:
  • the data judgment module connected to the storage block, is used to read the read data from the storage block, and determine whether to flip the read data according to the number of bits of the low data in the read data to output the global data for global bus transmission Bus data and inversion identification data for the inversion identification signal line transmission;
  • the data receiving module is connected to the global bus and the flip identification signal line, and is used to determine whether to flip the global bus data according to the flip identification data, so as to output the buffered data;
  • Parallel-serial conversion circuit connected between the data receiving module and the DQ port, used for parallel-serial conversion of the buffered data to generate the output data of the DQ port;
  • the data buffer module is connected to the storage block through the global bus;
  • the precharge module is connected to the precharge signal line and is used to set the initial state of the global bus to high.
  • the data judging module is used to output the inversion data of the read data as global bus data when the number of bits of the low data in the read data is greater than the preset value, and to invert the identification data Set to high; and when the number of bits of the low data in the read data is less than or equal to the preset value, output the original read data as global bus data, and set the flip identification data to low.
  • the read data and the global bus data are both divided into M groups
  • the flip identification data is M bits
  • the M bit flip identification data corresponds to the M sets of read data
  • the M bit flip identification data corresponds to M groups of global bus data have a one-to-one correspondence, where M is an integer greater than 1.
  • each set of read data is N bits, where N is an integer greater than 1, and the data judgment module is used to determine the number of bits of the data that is low in the input set of read data greater than N/2 In the case of inputting a set of read data inversion data as a corresponding set of global bus data output, and set the one-bit inversion identification data corresponding to the input set of read data to high; and in the input one When the number of bits of the low data in the group read data is less than or equal to N/2, the input group of read data is output as a corresponding group of global bus data, and the input group of read data corresponds to The one-bit flip flag data is set low.
  • the data judgment module includes:
  • Data judging unit the input end of the data judging unit is connected to the storage block, the output end of the data judging unit is connected to the inversion identification signal line, the data judging unit is used to read the data whose number of bits is greater than the preset value In this case, set the flip identification data to high; and set the flip identification data to low when the number of bits of the low data in the read data is less than or equal to the preset value;
  • Data selector the input end of the data selector is connected to the data judgment unit, and is used to receive the read data through the data judgment unit, the input end of the data selector also receives the inversion identification data through the inversion identification signal line, and the output end of the data selector Connected to the global bus, the data selector is used to output the flipped data of the read data as global bus data when the flipped identification data is high; and when the flipped identification data is low, use the original read data as Global bus data output.
  • the data selector includes a plurality of data selection units, and the data selection unit includes:
  • the first inverter the input terminal of the first inverter receives the inversion identification data through the inversion identification signal line;
  • the second inverter the input terminal of the second inverter is connected to the data judgment unit, and is used to receive read data from the data judgment unit;
  • the first transmission gate the input terminal of the first transmission gate is connected to the output terminal of the second inverter, the output terminal of the first transmission gate is connected to the global bus for outputting global bus data, and the anti-control terminal of the first transmission gate Connected to the output terminal of the first inverter, the positive control terminal of the first transmission gate receives the inversion identification data through the inversion identification signal line;
  • the second transmission gate The input end of the second transmission gate is connected to the data judgment unit and is used to receive read data from the data judgment unit.
  • the output end of the second transmission gate is connected to the global bus and is used to output global bus data.
  • the inverse control terminal of the transmission gate receives the inversion identification data through the inversion identification signal line, and the positive control terminal of the second transmission gate is connected to the output terminal of the first inverter.
  • the data receiving module is configured to output the inversion data of the global bus data as buffer data when the inversion identification data is high; and in the case in which the inversion identification data is low, to output the original global bus The data is output as cached data.
  • the data receiving module includes a plurality of data receiving units, and the data receiving unit includes:
  • the third inverter the input terminal of the third inverter receives the inversion identification data through the inversion identification signal line;
  • the fourth inverter the input terminal of the fourth inverter receives global bus data through the global bus;
  • the third transmission gate the input terminal of the third transmission gate is connected to the output terminal of the fourth inverter, and the output terminal of the third transmission gate is connected to the parallel-serial conversion circuit for outputting buffered data to the parallel-serial conversion circuit.
  • the inverse control terminal of the transmission gate is connected to the output terminal of the third inverter, and the positive control terminal of the third transmission gate receives the inversion identification data through the inversion identification signal line;
  • the fourth transmission gate receives global bus data through the global bus.
  • the output terminal of the fourth transmission gate is connected to the parallel-serial conversion circuit for outputting buffered data to the parallel-serial conversion circuit.
  • the anti-control terminal receives the inversion identification data through the inversion identification signal line, and the positive control terminal of the fourth transmission gate is connected to the output terminal of the third inverter.
  • the data buffer module includes a plurality of NMOS transistors, the gate of the NMOS transistor is connected to the memory block, and the drain of the NMOS transistor is connected to the global bus; and the precharge module includes a plurality of PMOS transistors and a plurality of holding circuits , The gate of the PMOS transistor is connected to the precharge signal line, the drain of the PMOS transistor is connected to the global bus, and the input and output terminals of the holding circuit are connected to the global bus.
  • an embodiment of the present application provides a semiconductor memory including a DQ port, a memory block, and a read operation circuit of any one of the above.
  • an embodiment of the present application provides a read operation method, which is applied to a semiconductor memory.
  • the semiconductor memory includes a DQ port and a memory block.
  • the read operation method includes:
  • the number of bits of the low data in the read data determine whether to invert the read data, so as to output the global bus data for global bus transmission and the inversion identification data for the inversion identification signal line transmission;
  • the flip identification data determine whether to flip the global bus data to output the cache data
  • Parallel-serial conversion is performed on the buffered data to generate the output data of the DQ port.
  • the read data it is determined whether to flip the read data, so as to output the global bus data for global bus transmission and the flip identification data for the flip identification signal line transmission, including :
  • the original read data is output as global bus data, and the inversion identification data is set low.
  • the read data it is determined whether to flip the read data, so as to output the global bus data for global bus transmission and the flip identification data for the flip identification signal line transmission, including :
  • the inverted data of the input set of read data is output as the corresponding set of global bus data, and the input one Set the one-bit flip identification data corresponding to the group read data to high;
  • the input set of read data is output as the corresponding set of global bus data, and the input set of read data is output. Fetch the corresponding bit of the data and set the flag data to low.
  • the embodiment of the application adopts the above-mentioned technical solution to realize that more data is transmitted as “1” on the global bus of the Precharge High (pull-up) architecture, thereby reducing the number of internal global bus inversions, greatly compressing current, and reducing power consumption.
  • FIG. 1 schematically shows a block diagram of a partial structure of a semiconductor memory in an implementation manner of this embodiment
  • FIG. 2 schematically shows a block diagram of a partial structure of a semiconductor memory in another implementation manner of this embodiment
  • FIG. 3 schematically shows a circuit diagram (corresponding to a storage block) of a data buffer module and a precharge module in an implementation manner of this embodiment
  • FIG. 4 schematically shows a circuit diagram (corresponding to multiple storage blocks) of a data buffer module and a precharge module in an implementation manner of this embodiment
  • FIG. 5 schematically shows a block diagram of a data judgment module in an implementation manner of this embodiment
  • FIG. 6 schematically shows a block diagram of a data selection unit in an implementation manner of this embodiment
  • FIG. 7 schematically shows a block diagram of a data receiving module in an implementation manner of this embodiment
  • FIG. 8 schematically records a block diagram of a data receiving unit in an implementation manner of this embodiment
  • FIG. 9 schematically shows a flowchart of a read operation method in an implementation manner of this embodiment.
  • FIG. 1 schematically shows a block diagram of a part of the structure of a semiconductor memory in an implementation manner of this embodiment.
  • the semiconductor memory 20 includes a DQ port 24, a bank 26, and a read operation circuit.
  • the read operation circuit includes a global bus (Global Bus), a flag signal line, a data judgment module 23, a data buffer module (Data Buffer) 22, a data receiving module 25, and a parallel-to-serial conversion circuit 21.
  • the semiconductor memory 20 is a DRAM, such as a fourth-generation double-rate synchronous dynamic random access memory (Double Data Rate SDRAM 4, DDR4 for short).
  • an Active command opens the only designated storage block 26, and the read operation can only be performed on one storage block 26.
  • the read operation circuit Through the read operation circuit, the read data D ⁇ 127:0> in the memory block 26 outputs 8-bit output data DQ ⁇ 7:0> through the DQ port 24.
  • the number of storage blocks 26, the number of data bits of each storage block 26, and the number and number of data bits of the DQ port 24 are not limited in this embodiment. For example, there may be one DQ port 24, which is used to output 16-bit output data; there may also be two DQ ports 24, that is, each DQ port 24 is used to output 8-bit output data.
  • the output data DQ ⁇ 7:0> is obtained by performing a read operation on a group of memory blocks Bank ⁇ 7:0> through the above-mentioned read operation circuit; the output data DQ ⁇ 15:8> is obtained through the above-mentioned read operation.
  • the other read operation circuit is obtained by performing a read operation on another group of memory blocks Bank ⁇ 15:8>.
  • the eight memory blocks 26 ie Bank ⁇ 15:8>
  • DQ ⁇ 15:8> when one Bank is working, the other Banks do not work.
  • the semiconductor memory 20 has an array structure, and the structure of each unit may be the same, but due to different input data, the output data of each unit may be different.
  • the following takes one of the memory blocks as an example to introduce the read operation circuit of this embodiment.
  • the data judgment module 23 is connected to the storage block 26 and is used to read the read data from the storage block 26, such as D ⁇ 127:0>, and determine whether to flip the read according to the number of bits in the read data that is low Data to output global bus data for global bus transmission and Flag data for Flag signal line transmission. Among them, data is high can be data equal to "1", data is “low” can be data equal to "0". Data flipping can be understood as changing from “0” to "1", or from "1" to "0". The inversion of the data line or the signal line can be understood as a high level changing to a low level, or a low level changing to a high level.
  • the data judgment module 23 is configured to output the inverted data of the read data as global bus data and output the flag data when the number of bits of the low data in the read data is greater than the preset value. Set to high; and when the number of bits of the low data in the read data is less than or equal to the preset value, output the original read data as global bus data, and set the Flag data to low.
  • the multi-bit read data is not grouped, that is, the Flag data can be one bit. In one example, multiple bits of read data can be grouped.
  • the read data and global bus data are divided into M groups, the Flag data is M bits, the M-bit Flag data corresponds to the M groups of read data, and the M-bit Flag data corresponds to M groups.
  • Group global bus data corresponds to one-to-one, where M is an integer greater than 1.
  • each set of read data may be N bits, where N is an integer greater than 1, and the data judgment module 23 is used for the case where the number of bits of the input data that is low in the input set of read data is greater than N/2
  • the flip data of the input set of read data is output as the corresponding set of global bus data, and the one bit of Flag data corresponding to the input set of read data is set high; and the set of input reads
  • the input set of read data is output as a corresponding set of global bus data, and the input set of read data corresponds to a flag The data is set low.
  • the read data D ⁇ 127:0> is divided into 16 groups, each group of read data is 8 bits, and each group of read data corresponds to one bit of Flag data.
  • the Flag data is 16 bits, such as Flag ⁇ 15:0>.
  • the global bus data D1' ⁇ 127:0> will also be divided into 16 groups accordingly. Each bit of Flag data corresponds to a group of global bus data.
  • the data D1' ⁇ 120:127> is D ⁇ 127:120>.
  • the global bus data D1' ⁇ 127:120> output from the data judgment module 23 is the flip data of the read data D ⁇ 127:120> of the memory block 26 (such as Bank0);
  • the global bus data D1' ⁇ 15:8> output from the data judgment module 23 is the flip data of the read data D ⁇ 15:8> of the memory block 26 (such as Bank0) ;
  • each global bus transmits one bit of global bus data.
  • M is an integer greater than 1
  • each global bus transmits one bit of global bus data.
  • Global bus ⁇ 0> transmits global bus data D1' ⁇ 0>;
  • global bus ⁇ 1> transmits global bus data D1' ⁇ 1>;
  • global bus ⁇ 127> transmits global bus data D1' ⁇ 127>.
  • Flag signal line ⁇ 0> transmits Flag data Flag ⁇ 0>, and is connected to global bus data D1' ⁇ 7:0> Correspondingly, it represents whether D1' ⁇ 7:0> is the flipped data;
  • Flag signal line ⁇ 1> transmits Flag data Flag ⁇ 1>, and corresponds to the global bus data D1' ⁇ 15:8>, which represents D1' ⁇ 15 :8>Whether it is the flipped data;
  • Flag signal line ⁇ 15> transmits Flag data Flag ⁇ 15>, and corresponds to the global bus data D1' ⁇ 127:120>, indicating whether D1' ⁇ 127:120> It is the data after flipping.
  • the 256-bit global bus data (including the 128-bit global bus data corresponding to DQ ⁇ 7:0> and the 128-bit global bus data corresponding to DQ ⁇ 15:8> In the data), there are many data with "1".
  • the data buffer module 22 is connected to the storage block 26 through the global bus, and the precharge module 27 is connected to the precharge signal line (Precharge) for setting the initial state of the global bus to high. That is to say, in this embodiment, the semiconductor memory 20 adopts the global bus transmission structure of Precharge pull-up.
  • FIG. 3 schematically shows a circuit diagram (corresponding to a storage block 26) of the data buffer module 22 and the precharge module 27 in an implementation of this embodiment.
  • Fig. 4 schematically shows a circuit diagram of the data buffer module 22 and the precharge module 27 (corresponding to 8 storage blocks 26) in an implementation of this embodiment.
  • the data buffer module 22 includes a plurality of NMOS (Negative Channel Metal Oxide Semiconductor) transistors 222
  • the precharge module 27 includes a plurality of PMOS (Positive Channel Metal Oxide Semiconductor) transistors 221 and a plurality of holding ( hold) Circuit 223.
  • the gate of the PMOS transistor 221 is connected to the precharge signal line, the drain of the PMOS transistor 221 is connected to the global bus; the gate of the NMOS transistor 222 is connected to the memory block 26, and the drain of the NMOS transistor 222 is connected to the global bus (Global Bus);
  • the input and output terminals of the holding circuit 223 are connected to the global bus, thereby forming a positive feedback circuit.
  • Precharge is to set the initial state of each global bus to high.
  • the specific process is that Precharge generates a pull-up pulse (pulse, about 2ns), pulls the corresponding global bus for a while, and the holding circuit 223 forms a positive feedback And lock the global bus at high level, but the ability of the holding circuit 223 to pull up and pull down the current is relatively weak; when a global bus needs to be turned to low level, it will represent the corresponding global bus
  • the data line (that is, the data line connected to the gate of the corresponding NMOS transistor 222) is pulled high (also a pulse, about 2ns), so that the corresponding NMOS transistor 222 will pull down the global bus for a while (the pull-down capability is greater than The pull-up capability of the circuit 223 is maintained), and then the global bus is locked to a low level through positive feedback, and the data line is flipped. Since there are more data "1" in the global bus data D1' ⁇ 127:0>, fewer flipping actions are required. Therefore
  • the data judgment module 23 includes a data judgment unit 231 and a data selector 232.
  • the input end of the data judgment unit 231 is connected to the storage block 26 through a local bus, and the output end of the data judgment unit 231 is connected to the Flag signal line and connected to the input end of the data selector 232.
  • the data judging unit 231 is configured to set the Flag data to high when the number of bits of the low data in the read data is greater than the preset value; and the number of bits of the low data in the read data is less than or equal to the preset value In the case of the value, the Flag data is set to low.
  • the data judging unit 231 may include multiple data judging subunits, and each data judging subunit is used to process a set of read data, and then output one bit of Flag data.
  • each data judging subunit is used to process a set of read data, and then output one bit of Flag data.
  • the input end of the data selector 232 is connected to the data judging unit 231 for receiving the read data through the data judging unit 231, the input end of the data selector 232 also receives Flag data through the Flag signal line, and the output end of the data selector 232 is connected with Global bus connection.
  • the data selector 232 is used for outputting the flipped data of the read data as global bus data when the Flag data is high; and for outputting the original read data as global bus data when the Flag data is high.
  • the data selector 232 includes a plurality of data selection units 232', and each data selection unit 232' is used to process one bit of Flag data and a set of read data.
  • each data selection unit 232' is used to process one bit of Flag data and a set of read data.
  • Fig. 6 shows an implementation of the data selection unit 232'.
  • the data selection unit 232' includes a first inverter 232A, a second inverter 232B, a first transmission gate 232C, and a second transmission gate 232D.
  • the input terminal of the first inverter 232A receives Flag data through the Flag signal line; the input terminal of the second inverter 232B is connected to the data judging unit 231 for receiving the read data from the data judging unit 231; the first transmission gate 232C
  • the input terminal of the first transmission gate 232C is connected to the output terminal of the second inverter 232B, the output terminal of the first transmission gate 232C is connected to the global bus for outputting global bus data, and the anti-control terminal of the first transmission gate 232C (top in Figure 6
  • the control terminal is connected to the output terminal of the first inverter 232A, the positive control terminal of the first transmission gate 232C (the lower control terminal in FIG.
  • the data judging unit 231 is used to receive the read data from the data judging unit 231, the output terminal of the second transmission gate 232D is connected to the global bus for outputting global bus data, and the anti-control terminal of the second transmission gate 232D passes the Flag signal
  • the line receives Flag data, and the positive control terminal of the second transmission gate 232D is connected to the output terminal of the first inverter 232A.
  • a set of second inverter 232B, first transmission gate 232C, and second transmission gate 232D are used to process one bit of read data and output one bit of corresponding global bus data.
  • the second inverter 232A, the first transmission gate 232C, and the second transmission gate 232D should also have 8 groups, and then output the 8-bit global Bus data D1' ⁇ 7:0>.
  • the read operation circuit in this embodiment also includes a data receiving module 25, which is connected to the global bus and the Flag signal respectively, and is used to determine whether to flip the global bus data according to the Flag data.
  • Output buffered data For example: when the Flag data is high, the flip data of the global bus data is output as the buffer data; and when the Flag data is low, the original global bus data is output as the buffer data.
  • the cache data is restored to the read data in the storage block 26. Furthermore, the data and functions of the external ports of the semiconductor memory 20, such as the DQ port 24 and the DBI port (not shown in the figure), will not be changed.
  • the data receiving module 25 may include a plurality of data receiving units 250, and each data receiving unit 250 is used to process one bit of Flag data and a group of global bus data.
  • each data receiving unit 250 is used to process one bit of Flag data and a group of global bus data.
  • FIG. 8 shows an implementation manner of the data receiving unit 250.
  • the data receiving unit 250 includes a third inverter 251, a fourth inverter 252, a third transmission gate 253, and a fourth transmission gate 254.
  • the input terminal of the third inverter 251 receives Flag data through the Flag signal line; the input terminal of the fourth inverter 252 receives global bus data through the global bus; the input terminal of the third transmission gate 253 is connected to the fourth inverter 252
  • the output terminal of the third transmission gate 253 is connected to the parallel-serial conversion circuit 21 for outputting buffered data to the parallel-serial conversion circuit 21, and the inverse control terminal of the third transmission gate 253 (the upper control terminal in FIG.
  • the positive control terminal of the third transmission gate 253 receives Flag data through the Flag signal line; the input terminal of the fourth transmission gate 254 receives global bus data through the global bus, and the fourth transmission gate 254
  • the output terminal of is connected to the parallel-serial conversion circuit 21 for outputting buffered data to the parallel-serial conversion circuit 21.
  • the anti-control terminal (the upper control terminal in FIG. 8) of the fourth transmission gate 254 receives Flag data through the Flag signal line.
  • the positive control terminal (the lower control terminal in FIG. 8) of the four transmission gate 254 is connected to the output terminal of the third inverter 251.
  • a set of fourth inverter 252, third transmission gate 253, and fourth transmission gate 254 are used to process one bit of global bus data and output one bit of corresponding buffer data.
  • the fourth inverter 252, the third transmission gate 253, and the fourth transmission gate 254 should also have 8 groups, and then output 8-bit Cache data D2' ⁇ 7:0>.
  • the read operation circuit of this embodiment further includes a parallel-to-serial conversion circuit 21.
  • the parallel-to-serial conversion circuit 21 is connected to the data receiving module 25 and is used to perform parallel-to-serial conversion on the buffered data to generate the output data of the DQ port 24 and transmit it to the DQ port 24 through a data bus.
  • the parallel-to-serial conversion circuit 21 performs parallel-to-serial conversion on the 128-bit buffer data D2' ⁇ 127:0> corresponding to Bank 0, and then generates 8-bit output data DQ ⁇ 7:0>.
  • the global bus data is 256 bits If you need to flip the 256-bit global bus data, only the 32-bit Flag data will be flipped, and the IDD4R current will be greatly compressed.
  • the semiconductor memory 20 of this embodiment also includes other structures such as a sense amplifier, a precharge circuit, etc., because they are all the prior art, and this embodiment will not be repeated here.
  • FIG. 9 shows a flowchart schematically showing a read operation method in an implementation manner of this embodiment.
  • the read operation method can be applied to the semiconductor memory 20 described above.
  • the read operation method may include:
  • Step S901 Set the initial state of the global bus to high
  • Step S902 Read data from the storage block
  • Step S903 Determine whether to flip the read data according to the number of bits of the low data in the read data, so as to output the global bus data for global bus transmission and the flip identification data for the flip identification signal line transmission;
  • Step S904 Determine whether to invert the global bus data according to the inversion identification data, so as to output the buffered data;
  • Step S905 Parallel-serial conversion is performed on the buffered data to generate output data of the DQ port.
  • step S903 may include: in the case where the number of bits of the low data in the read data is greater than the preset value, output the inverted data of the read data as the global bus data, and output the Flag The data is set to high; when the number of bits of the low data in the read data is less than or equal to the preset value, the original read data is output as global bus data, and the Flag data is set to low.
  • step S903 may include: dividing the read data into M groups, where each group of read data is N bits, and M and N are both integers greater than 1; When the number of bits of the low data in the data is greater than N/2, the inversion data of the input set of read data is output as the corresponding set of global bus data, and the input set of read data corresponds to One-bit inversion identification data is set to high; when the number of bits of the inputted set of read data that is low is less than or equal to N/2, the inputted set of read data is regarded as the corresponding set of global bus data Output, and set the one-bit flip identification data corresponding to a set of read data input to low.
  • the read operation circuit provided by the embodiment of the present application is applied to a semiconductor memory whose global bus transmission structure is Precharge pull-up.
  • the read data is flipped through the data judgment module, which can realize that more data is transmitted as "1" on the global bus. Thereby reducing the number of internal global bus flips, the current can be greatly compressed, and the power consumption can be reduced.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the present application, "a plurality of” means two or more than two, unless otherwise specifically defined.

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Abstract

本申请实施例提供一种读操作电路、半导体存储器和读操作方法，读操作电路包括：数据判断模块，从存储块中读出读取数据，并根据读取数据中为低的数据的位数，确定是否翻转读取数据，以输出供全局总线传输的全局总线数据和供翻转标识信号线传输的翻转标识数据；数据接收模块，根据翻转标识数据，确定是否翻转全局总线数据，以输出缓存数据；并串转换电路，对缓存数据进行并串转换，以生成DQ端口的输出数据；预充电模块，将全局总线的初始态设置为高。本申请实施例的技术方案可以实现在上拉架构的全局总线上传输"1"的数据较多，从而可以减少内部全局总线翻转次数，大幅压缩电流，降低功耗。

Description

读操作电路、半导体存储器和读操作方法
本申请要求于2019年10月25日提交中国专利局、申请号为201911021472.4、发明名称为“读操作电路、半导体存储器和读操作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体存储器技术领域，尤其涉及一种读操作电路、半导体存储器和读操作方法。
背景技术
本部分旨在为权利要求书中陈述的本申请的实施例提供背景或上下文。此处的描述不因为包括在本部分中就承认是现有技术。
半导体存储器包括静态随机存取存储器(Static Random-Access Memory，简称SRAM)、动态随机存取存储器(Dynamic Random Access Memory，简称DRAM)、同步动态随机存取内存(Synchronous Dynamic Random Access Memory，简称SDRAM)、只读存储器(Read-Only Memory，简称ROM)、闪存等。
在固态技术协会(Joint Electron Device Engineering Council，JEDEC)的DRAM协议中，对DRAM的速度、省电都有具体要求。如何使DRAM更省电的同时，亦能保证信号的完整性以及数据传输和存储的可靠性，是行业内亟待解决的问题。
发明内容
本申请实施例提供一种读操作电路、半导体存储器和读操作方法，以解决或缓解现有技术中的一项或更多项技术问题。
第一方面，本申请实施例提供一种读操作电路，应用于半导体存储器，半导体存储器包括DQ端口和存储块，读操作电路包括：
数据判断模块，连接于存储块，用于从存储块中读出读取数据，并根据读取数据中为低的数据的位数，确定是否翻转读取数据，以输出供全局总线传输的全局总线数 据和供翻转标识信号线传输的翻转标识数据；
数据接收模块，与全局总线和翻转标识信号线连接，用于根据翻转标识数据，确定是否翻转全局总线数据，以输出缓存数据；
并串转换电路，连接于数据接收模块和DQ端口之间，用于对缓存数据进行并串转换，以生成DQ端口的输出数据；
数据缓冲模块，通过全局总线连接于存储块；
预充电模块，连接于预充电信号线，用于将全局总线的初始态设置为高。
在一种实施方式中，数据判断模块用于在读取数据中为低的数据的位数大于预设值的情况下，将读取数据的翻转数据作为全局总线数据输出，并将翻转标识数据置为高；以及在读取数据中为低的数据的位数小于等于预设值的情况下，将原始的读取数据作为全局总线数据输出，并将翻转标识数据置为低。
在一种实施方式中，读取数据和全局总线数据均被划分为M组，翻转标识数据为M位，M位翻转标识数据与M组读取数据一一对应，并且M位翻转标识数据与M组全局总线数据一一对应，其中，M为大于1的整数。
在一种实施方式中，每组读取数据为N位，其中，N为大于1的整数，数据判断模块用于在输入的一组读取数据中为低的数据的位数大于N/2的情况下，将输入的一组读取数据的翻转数据作为对应的一组全局总线数据输出，并将输入的一组读取数据对应的一位翻转标识数据置为高；以及在输入的一组读取数据中为低的数据的位数小于等于N/2的情况下，将输入的一组读取数据作为对应的一组全局总线数据输出，并将输入的一组读取数据对应的一位翻转标识数据置为低。
在一种实施方式中，数据判断模块包括：
数据判断单元，数据判断单元的输入端连接于存储块，数据判断单元的输出端与翻转标识信号线连接，数据判断单元用于在读取数据中为低的数据的位数大于预设值的情况下，将翻转标识数据置为高；以及在读取数据中为低的数据的位数小于等于预设值的情况下，将翻转标识数据置为低；
数据选择器，数据选择器的输入端连接于数据判断单元，用于通过数据判断单元接收读取数据，数据选择器的输入端还通过翻转标识信号线接收翻转标识数据，数据 选择器的输出端与全局总线连接，数据选择器用于在翻转标识数据为高的情况下，将读取数据的翻转数据作为全局总线数据输出；以及在翻转标识数据为低的情况下，将原始的读取数据作为全局总线数据输出。
在一种实施方式中，数据选择器包括多个数据选择单元，数据选择单元包括：
第一反相器，第一反相器的输入端通过翻转标识信号线接收翻转标识数据；
第二反相器，第二反相器的输入端连接于数据判断单元，用于从数据判断单元接收读取数据；
第一传输门，第一传输门的输入端连接于第二反相器的输出端，第一传输门的输出端与全局总线连接，用于输出全局总线数据，第一传输门的反控制端连接于第一反相器的输出端，第一传输门的正控制端通过翻转标识信号线接收翻转标识数据；
第二传输门，第二传输门的输入端连接于数据判断单元，用于从数据判断单元接收读取数据，第二传输门的输出端与全局总线连接，用于输出全局总线数据，第二传输门的反控制端通过翻转标识信号线接收翻转标识数据，第二传输门的正控制端连接于第一反相器的输出端。
在一种实施方式中，数据接收模块用于在翻转标识数据为高的情况下，将全局总线数据的翻转数据作为缓存数据输出；以及在翻转标识数据为低的情况下，将原始的全局总线数据作为缓存数据输出。
在一种实施方式中，数据接收模块包括多个数据接收单元，数据接收单元包括：
第三反相器，第三反相器的输入端通过翻转标识信号线接收翻转标识数据；
第四反相器，第四反相器的输入端通过全局总线接收全局总线数据；
第三传输门，第三传输门的输入端连接于第四反相器的输出端，第三传输门的输出端与并串转换电路连接，用于向并串转换电路输出缓存数据，第三传输门的反控制端连接于第三反相器的输出端，第三传输门的正控制端通过翻转标识信号线接收翻转标识数据；
第四传输门，第四传输门的输入端通过全局总线接收全局总线数据，第四传输门的输出端与并串转换电路连接，用于向并串转换电路输出缓存数据，第四传输门的反控制端通过翻转标识信号线接收翻转标识数据，第四传输门的正控制端连接于第三反 相器的输出端。
在一种实施方式中，数据缓冲模块包括多个NMOS晶体管，NMOS晶体管的栅极连接于存储块，NMOS晶体管的漏极连接于全局总线；以及预充电模块包括多个PMOS晶体管和多个保持电路，PMOS晶体管的栅极连接于预充电信号线，PMOS晶体管的漏极连接于全局总线，保持电路的输入和输出端连接于全局总线。
第二方面，本申请实施例提供一种半导体存储器，包括DQ端口、存储块以及以上任一项的读操作电路。
第三方面，本申请实施例提供一种读操作方法，应用于半导体存储器，半导体存储器包括DQ端口和存储块，读操作方法包括：
将全局总线的初始态设置为高；
从存储块中读出读取数据；
根据读取数据中为低的数据的位数，确定是否翻转读取数据，以输出供全局总线传输的全局总线数据和供翻转标识信号线传输的翻转标识数据；
根据翻转标识数据，确定是否翻转全局总线数据，以输出缓存数据；
对缓存数据进行并串转换，以生成DQ端口的输出数据。
在一种实施方式中，根据读取数据中为低的数据的位数，确定是否翻转读取数据，以输出供全局总线传输的全局总线数据和供翻转标识信号线传输的翻转标识数据，包括：
在读取数据中为低的数据的位数大于预设值的情况下，将读取数据的翻转数据作为全局总线数据输出，并将翻转标识数据置为高；
在读取数据中为低的数据的位数小于等于预设值的情况下，将原始的读取数据作为全局总线数据输出，并将翻转标识数据置为低。
在一种实施方式中，根据读取数据中为低的数据的位数，确定是否翻转读取数据，以输出供全局总线传输的全局总线数据和供翻转标识信号线传输的翻转标识数据，包括：
将读取数据划分为M组，其中，每组读取数据为N位，M和N均为大于1的整数；
在输入的一组读取数据中为低的数据的位数大于N/2的情况下，将输入的一组读取数据的翻转数据作为对应的一组全局总线数据输出，并将输入的一组读取数据对应的一位翻转标识数据置为高；
在输入的一组读取数据中为低的数据的位数小于等于N/2的情况下，将输入的一组读取数据作为对应的一组全局总线数据输出，并将输入的一组读取数据对应的一位翻转标识数据置为低。
本申请实施例采用上述技术方案，可以实现在Precharge High(上拉)架构的全局总线上传输为“1”的数据较多，从而可以减少内部全局总线翻转次数，大幅压缩电流，降低功耗。
上述概述仅仅是为了说明书的目的，并不意图以任何方式进行限制。除上述描述的示意性的方面、实施方式和特征之外，通过参考附图和以下的详细描述，本申请进一步的方面、实施方式和特征将会是容易明白的。
附图说明
在附图中，除非另外规定，否则贯穿多个附图相同的附图标记表示相同或相似的部件或元素。这些附图不一定是按照比例绘制的。应该理解，这些附图仅描绘了根据本申请公开的一些实施方式，而不应将其视为是对本申请范围的限制。
图1示意性地示出了本实施例一种实施方式的半导体存储器部分结构的框图；
图2示意性地示出了本实施例另一种实施方式的半导体存储器部分结构的框图；
图3示意性地示出了本实施例一种实施方式的数据缓冲模块和预充电模块的电路图(对应于一个存储块)；
图4示意性地示出了本实施例一种实施方式的数据缓冲模块和预充电模块的电路图(对应于多个存储块)；
图5示意性地示出了本实施例一种实施方式的数据判断模块的框图；
图6示意性地示出了本实施例一种实施方式的数据选择单元的框图；
图7示意性地示出了本实施例一种实施方式的数据接收模块的框图
图8示意性的实录了本实施例一种实施方式的数据接收单元的框图；
图9示意性地示出了本实施例一种实施方式的读操作方法的流程图。
附图标记说明：
20：半导体存储器；
21：并串转换电路；
22：数据缓冲模块；
23：数据判断模块；
24：DQ端口；
25：数据接收模块；
26：存储块；
27：预充电模块；
221：PMOS管；
222：NMOS管；
223：保持电路；
231：数据判断单元；
232：数据选择器；
232′：数据选择单元；
232A：第一反相器；
232B：第二反相器；
232C：第一传输门；
232D：第二传输门；
250：数据接收单元；
251：第三反相器；
252：第四反相器；
253：第三传输门；
254：第四传输门。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的实施例；相反，提供这些实施例使得本申请将全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。在图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。
图1示意性地示出了本实施例一种实施方式的半导体存储器部分结构的框图。如图1所示，半导体存储器20包括DQ端口24、存储块(Bank)26以及读操作电路。其中，读操作电路包括全局总线(Global Bus)、翻转标识(Flag)信号线、数据判断模块23、数据缓冲模块(Data Buffer)22、数据接收模块25以及并串转换电路21。在一种实施方式中，半导体存储器20为DRAM，如第四代双倍速率同步动态随机存储器(Double Data Rate SDRAM 4，简称DDR4)。
在一个示例中，如图1所示，一次激活(Active)命令打开唯一指定的存储块26，读操作也只能针对一个存储块26进行。也就是说，当八个存储块26(即Bank<7:0>)中有一个Bank工作的时候，其他Bank不工作。通过读操作电路，存储块26中的读取数据D<127:0>通过DQ端口24输出8位输出数据DQ<7:0>。需要说明的是，存储块26的数量、每个存储块26的数据位数以及DQ端口24的数据位数和数量，本实施例不作限定。例如：DQ端口24也可以为一个，用作输出16位输出数据；DQ端口24也可以为两个，即每个DQ端口24用作输出8位输出数据。
例如，如图2所示，输出数据DQ<7:0>通过上述的一个读操作电路对一组存储块Bank<7:0>执行读操作而得到；输出数据DQ<15:8>通过上述的另一个读操作电路对另一组存储块Bank<15:8>执行读操作而得到。相应地，与DQ<15:8>对应的八个存储块26(即Bank<15:8>)中，当有一个Bank工作的时候，其他Bank不工作。
半导体存储器20为阵列式结构，各单元结构可以相同，但因输入的数据不同，各单元输出的数据可能不同。下面以其中一个存储块为例，介绍本实施例的读操作电路。
数据判断模块23连接于存储块26，用于从存储块26中读出读取数据，如D<127:0>，并根据读取数据中为低的数据的位数，确定是否翻转读取数据，以输出供全局总线传输的全局总线数据和供Flag信号线传输的Flag数据。其中，数据为高可以是数据等于 “1”，数据为“低”可以是数据等于“0”。数据的翻转可以理解为从“0”变为“1”，或者，从“1”变为“0”。数据线或信号线的翻转可以理解为高电平变为低电平，或低电平变为高电平。
在一种实施方式中，数据判断模块23用于在读取数据中为低的数据的位数大于预设值的情况下，将读取数据的翻转数据作为全局总线数据输出，并将Flag数据置为高；以及在读取数据中为低的数据的位数小于等于预设值的情况下，将原始的读取数据作为全局总线数据输出，并将Flag数据置为低。
在一个示例中，多位读取数据没有被分组，即Flag数据可以为一位。在一个示例中，多位读取数据可以被分组。例如：在一种实施方式中，读取数据和全局总线数据均被划分为M组，Flag数据为M位，M位Flag数据与M组读取数据一一对应，并且M位Flag数据与M组全局总线数据一一对应，其中，M为大于1的整数。
进一步地，每组读取数据可以为N位，其中，N为大于1的整数，数据判断模块23用于在输入的一组读取数据中为低的数据的位数大于N/2的情况下，将输入的一组读取数据的翻转数据作为对应的一组全局总线数据输出，并将输入的一组读取数据对应的一位Flag数据置为高；以及在输入的一组读取数据中为低的数据的位数小于等于N/2的情况下，将输入的一组读取数据作为对应的一组全局总线数据输出，并将输入的一组读取数据对应的一位Flag数据置为低。
例如：读取数据D<127:0>被划分为16组，每组读取数据为8位，每组读取数据与一位Flag数据对应。相应地，Flag数据为16位，如Flag<15:0>。全局总线数据D1′<127:0>相应也会被划分为16组。每一位Flag数据与一组全局总线数据对应。对于一组读取数据D<127:120>，如果D<127:120>中等于“0”的位数大于4位，则对应的Flag<15>＝1，输出的一组全局总线数据D1′<120:127>等于D<127:120>的翻转数据；如果读取数据中等于“0”的位数小于等于4位，则对应的Flag<15>＝0，输出的一组全局总线数据D1′<120:127>即为D<127:120>。
于是，当Flag<15>＝1时，从数据判断模块23输出的全局总线数据D1′<127：120>为存储块26(如Bank0)的读取数据D<127:120>的翻转数据；当Flag<15>＝0时，从数据判断模块23输出的全局总线数据D1′<127：120>即为存储块26(如Bank0)的读 取数据D<127:120>，即读取数据D1′<127:120>＝D<127:120>。类似地，当Flag<1>＝1时，从数据判断模块23输出的全局总线数据D1′<15:8>为存储块26(如Bank0)的读取数据D<15:8>的翻转数据；当Flag<1>＝0时，从数据判断模块23输出的全局总线数据D1′<15:8>即为存储块26(如Bank0)的读取数据D<15:8>，即全局总线数据D1′<15:8>＝D<15:8>。当Flag<0>＝1时，从数据判断模块23输出的全局总线数据D1′<7:0>为存储块26(如Bank0)的读取数据D<7:0>的翻转数据；当Flag<0>＝0时，从数据判断模块23输出的全局总线数据D1′<7：0>即为存储块26(如Bank0)的读取数据D<7:0>，即全局总线数据D1′<7:0>＝D<7:0>。
在一个示例中，全局总线为多根且被划分为M(M为大于1的整数)组，每根全局总线传输一位全局总线数据。例如：全局总线为128根，128根全局总线分为16组。全局总线<0>传输全局总线数据D1′<0>；全局总线<1>传输全局总线数据D1′<1>；……；全局总线<127>传输全局总线数据D1′<127>。
在一个示例中，Flag信号线为16根，每根Flag信号线传输1位Flag数据，如Flag信号线<0>传输Flag数据Flag<0>，并且与全局总线数据D1′<7:0>对应，表征D1′<7:0>是否为翻转后的数据；Flag信号线<1>传输Flag数据Flag<1>，并且与全局总线数据D1′<15:8>对应，表征D1′<15:8>是否为翻转后的数据；……；Flag信号线<15>传输Flag数据Flag<15>，并且与全局总线数据D1′<127:120>对应，表征D1′<127:120>是否为翻转后的数据。
从而，在全局总线上传输的全局总线数据D1′<127:0>中，为“1”的数据较多。相应地，在图2所示的半导体存储器20中，256位的全局总线数据(包括与DQ<7:0>对应的128位全局总线数据和与DQ<15:8>对应的128位全局总线数据)中，为“1”的数据较多。
数据缓冲模块22通过全局总线连接于存储块26，预充电模块27连接于预充电信号线(Precharge)，用于将全局总线的初始态设置为高。也就是说，本实施例中，半导体存储器20采用的是Precharge上拉的全局总线传输结构。
图3示意性地示出了本实施例一种实施方式的数据缓冲模块22和预充电模块27的电路图(对应于一个存储块26)。图4示意性地示出了本实施例一种实施方式的数据 缓冲模块22和预充电模块27的电路图(对应于8个存储块26)。
如图3和图4所示，数据缓冲模块22包括多个NMOS(Negative Channel Metal Oxide Semiconductor)晶体管222，预充电模块27包括多个PMOS(Positive Channel Metal Oxide Semiconductor)晶体管221、和多个保持(hold)电路223。其中，PMOS晶体管221的栅极连接于预充电信号线，PMOS晶体管221的漏极连接于全局总线；NMOS晶体管222的栅极连接于存储块26，NMOS晶体管222的漏极连接于全局总线(Global Bus)；保持电路223的输入和输出端连接于全局总线，从而形成正反馈电路。
Precharge的作用是将每根全局总线的初始态设置为高，具体过程为Precharge产生一个上拉脉冲(pulse，大约2ns左右)，将相应的某根全局总线上拉片刻，保持电路223形成正反馈并将这根全局总线锁在高电平，但是该保持电路223的上拉和下拉电流的能力比较弱；当某根全局总线需要变为低电平的时候，将代表这根全局总线对应的数据线(即对应的NMOS晶体管222的栅极上连接的数据线)拉高一下(也是一个pulse，大约2ns左右)，这样相应的NMOS晶体管222就会将这根全局总线下拉片刻(下拉能力大于保持电路223的上拉能力)，然后会通过正反馈将这根全局总线锁到低电平，完成数据线的翻转动作。由于全局总线数据D1′<127:0>中，为“1”的数据较多，因此需要的翻转动作就会较少。因此，半导体存储器的IDD4R(读出电流)将会被降低，从而可以降低半导体存储器的功耗。
在一种实施方式中，如图5所示，数据判断模块23包括数据判断单元231和数据选择器232。
数据判断单元231的输入端通过局部总线(local Bus)连接于存储块26，数据判断单元231的输出端与Flag信号线连接，并与数据选择器232的输入端连接。数据判断单元231用于在读取数据中为低的数据的位数大于预设值的情况下，将Flag数据置为高；以及在读取数据中为低的数据的位数小于等于预设值的情况下，将Flag数据置为低。
在一个示例中，数据判断单元231可以包括多个数据判断子单元，每个数据判断子单元用于处理一组读取数据，进而输出一位Flag数据。例如：数据选择单元子单元可以有16个，分别对应于16组读取数据，进而输出16位Flag数据，其中，每组读取 数据可以有8位。
数据选择器232的输入端连接于数据判断单元231，用于通过数据判断单元231接收读取数据，数据选择器232的输入端还通过Flag信号线接收Flag数据，数据选择器232的输出端与全局总线连接。数据选择器232用于在Flag数据为高的情况下，将读取数据的翻转数据作为全局总线数据输出；以及在Flag数据为高的情况下，将原始的读取数据作为全局总线数据输出。
在一种实施方式中，数据选择器232包括多个数据选择单元232′，每个数据选择单元232′用于处理一位Flag数据和一组读取数据。例如：数据选择单元232′可以有16个，分别对应于16组读取数据和一位Flag数据，每组读取数据可以有8位。
图6示出了数据选择单元232′的一种实现方式。如图6所示，数据选择单元232′包括第一反相器232A、第二反相器232B、第一传输门232C和第二传输门232D。
第一反相器232A的输入端通过Flag信号线接收Flag数据；第二反相器232B的输入端连接于数据判断单元231，用于从数据判断单元231接收读取数据；第一传输门232C的输入端连接于第二反相器232B的输出端，第一传输门232C的输出端与全局总线连接，用于输出全局总线数据，第一传输门232C的反控制端(图6中的上方控制端)连接于第一反相器232A的输出端，第一传输门232C的正控制端(图6中的下方控制端)通过Flag信号线接收Flag数据；第二传输门232D的输入端连接于数据判断单元231，用于从数据判断单元231接收读取数据，第二传输门232D的输出端与全局总线连接，用于输出全局总线数据，第二传输门232D的反控制端通过Flag信号线接收Flag数据，第二传输门232D的正控制端连接于第一反相器232A的输出端。
以Flag<0>和读取数据D<7:0>为例，如图6所示，当Flag＝1时，全局总线数据D1′<7:0>为读取数据D<7:0>的翻转数据；当Flag＝0时，全局总线数据D1′<7:0>即为读取数据D<7:0>。
需要说明的是，一组第二反相器232B、第一传输门232C和第二传输门232D用于处理一位读取数据，输出一位对应的全局总线数据。也就说说，对应于8位的读取数据D<7:0>，第二反相器232A、第一传输门232C和第二传输门232D也应当有8组，进而输出8位的全局总线数据D1′<7:0>。
如图1、图2和图7所示，本实施例中的读操作电路还包括数据接收模块25，分别与全局总线和Flag信号连接，用于根据Flag数据，确定是否翻转全局总线数据，以输出缓存数据。例如：在Flag数据为高的情况下，将全局总线数据的翻转数据作为缓存数据输出；以及在Flag数据为低的情况下，将原始的全局总线数据作为缓存数据输出。
由此，缓存数据恢复为存储块26中的读取数据。进而，半导体存储器20的外部端口，如DQ端口24以及DBI端口(图中未示出)的数据和功能都不会被改变。
在一种实施方式中，数据接收模块25可以包括多个数据接收单元250，每个数据接收单元250用于处理一位Flag数据和一组全局总线数据。例如：数据接收单元250可以有16个，分别对应于16组全局总线数据和一位Flag数据。图8示出了数据接收单元250的一种实现方式。
如图8所示，数据接收单元250包括第三反相器251、第四反相器252、第三传输门253和第四传输门254。
第三反相器251的输入端通过Flag信号线接收Flag数据；第四反相器252的输入端通过全局总线接收全局总线数据；第三传输门253的输入端连接于第四反相器252的输出端，第三传输门253的输出端与并串转换电路21连接，用于向并串转换电路21输出缓存数据，第三传输门253的反控制端(图8中的上方控制端)连接于第三反相251器的输出端，第三传输门253的正控制端通过Flag信号线接收Flag数据；第四传输门254的输入端通过全局总线接收全局总线数据，第四传输门254的输出端与并串转换电路21连接，用于向并串转换电路21输出缓存数据，第四传输门254的反控制端(图8中的上方控制端)通过Flag信号线接收Flag数据，第四传输门254的正控制端(图8中的下方控制端)连接于第三反相器251的输出端。
以Flag<0>和全局总线数据D1′<7:0>为例，如图8所示，当Flag＝1时，缓存数据D2′<7:0>为全局总线数据D1′<7:0>的翻转数据；当Flag＝0时，缓存数据D2′<7:0>即为全局总线数据D1′<7:0>，即D2′<7:0>＝D1′<7:0>。
需要说明的是，一组第四反相器252、第三传输门253和第四传输门254用于处理一位全局总线数据，输出一位对应的缓存数据。也就说说，对应于8位的全局总线数 据D1′<7:0>，第四反相器252、第三传输门253和第四传输门254也应当有8组，进而输出8位的缓存数据D2′<7:0>。
如图1和图2所示，本实施例的读操作电路还包括并串转换电路21。并串转换电路21连接于数据接收模块25，用于对缓存数据进行并串转换，以生成DQ端口24的输出数据，并通过数据总线(data bus)传输给DQ端口24。例如：并串转换电路21对Bank0对应的128位的缓存数据D2′<127:0>进行并串转换，进而生成8位的输出数据DQ<7:0>。
根据本实施例的半导体存储器20，在从半导体存储器20读出数据(DQ<7:0>＝<00000000>；DQ<15:8>＝<00000000>)的过程中，全局总线数据为256位，如果需要256位全局总线数据翻转，将变成只有32位Flag数据在翻转，IDD4R电流将会大幅压缩。
本实施例的半导体存储器20在实际应用中还包括灵敏放大器、预充电电路等其他结构，因其均为现有技术本实施例在此不复赘述。
图9示出示意性地示出了本实施例一种实施方式的读操作方法的流程图。该读操作方法可以应用上述的半导体存储器20中。如图9所示，该读操作方法可以包括：
步骤S901、将全局总线的初始态设置为高；
步骤S902、从存储块中读出读取数据；
步骤S903、根据读取数据中为低的数据的位数，确定是否翻转读取数据，以输出供全局总线传输的全局总线数据和供翻转标识信号线传输的翻转标识数据；
步骤S904、根据翻转标识数据，确定是否翻转全局总线数据，以输出缓存数据；
步骤S905、对缓存数据进行并串转换，以生成DQ端口的输出数据。
在一种实施方式中，在步骤S903中可以包括：在读取数据中为低的数据的位数大于预设值的情况下，将读取数据的翻转数据作为全局总线数据输出，并将Flag数据置为高；在读取数据中为低的数据的位数小于等于预设值的情况下，将原始的读取数据作为全局总线数据输出，并将Flag数据置为低。
在一种实施方式中，在步骤S903中可以包括：将读取数据划分为M组，其中，每组读取数据为N位，M和N均为大于1的整数；在输入的一组读取数据中为低的数 据的位数大于N/2的情况下，将输入的一组读取数据的翻转数据作为对应的一组全局总线数据输出，并将输入的一组读取数据对应的一位翻转标识数据置为高；在输入的一组读取数据中为低的数据的位数小于等于N/2的情况下，将输入的一组读取数据作为对应的一组全局总线数据输出，并将输入的一组读取数据对应的一位翻转标识数据置为低。
本申请实施例提供的读操作电路，应用于全局总线传输结构为Precharge上拉的半导体存储器，通过数据判断模块对读取数据进行翻转，可以实现全局总线上传输为“1”的数据较多，从而减少内部全局总线翻转次数，可以大幅压缩电流，降低功耗。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施例或示例中。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
此外，所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。然而，本领域技术人员将意识到，可以实践本申请的技术方案而没有所述特定细节中的一个或更多，或者可以采用其它的方法、组元、材料、装置、步骤等。在其它情况下，不详细示出或描述公知结构、方法、装置、实现、材料或者操作以避免模糊本申请的各方面。
术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
需要说明的是，尽管在附图中以特定顺序描述了本申请中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。上述附图仅是根据本申 请示例性实施例的方法所包括的处理的示意性说明，而不是限制目的。易于理解，上述附图所示的处理并不表明或限制这些处理的时间顺序。另外，也易于理解，这些处理可以是例如在多个模块中同步或异步执行的。
此外，虽然已经参考若干具体实施方式描述了本申请的精神和原理，但是应该理解，本申请并不限于所公开的具体实施方式，对各方面的划分也不意味着这些方面中的特征不能组合以进行受益，这种划分仅是为了表述的方便。本申请旨在涵盖所附权利要求的精神和范围内所包括的各种修改和等同布置。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到其各种变化或替换，这些都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

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  1. 一种读操作电路，应用于半导体存储器，其特征在于，所述半导体存储器包括DQ端口和存储块，所述读操作电路包括：
    数据判断模块，连接于所述存储块，用于从所述存储块中读出读取数据，并根据所述读取数据中为低的数据的位数，确定是否翻转所述读取数据，以输出供全局总线传输的全局总线数据和供翻转标识信号线传输的翻转标识数据；
    数据接收模块，与所述全局总线和所述翻转标识信号线连接，用于根据所述翻转标识数据，确定是否翻转所述全局总线数据，以输出缓存数据；
    并串转换电路，连接于所述数据接收模块和所述DQ端口之间，用于对所述缓存数据进行并串转换，以生成所述DQ端口的输出数据；
    数据缓冲模块，通过所述全局总线连接于所述存储块；
    预充电模块，连接于预充电信号线，用于将所述全局总线的初始态设置为高。
  2. 根据权利要求1所述的读操作电路，其特征在于，所述数据判断模块用于在所述读取数据中为低的数据的位数大于预设值的情况下，将所述读取数据的翻转数据作为所述全局总线数据输出，并将所述翻转标识数据置为高；以及在所述读取数据中为低的数据的位数小于等于所述预设值的情况下，将原始的读取数据作为所述全局总线数据输出，并将所述翻转标识数据置为低。
  3. 根据权利要求1所述的读操作电路，其特征在于，所述读取数据和所述全局总线数据均被划分为M组，所述翻转标识数据为M位，M位翻转标识数据与M组读取数据一一对应，并且M位翻转标识数据与M组全局总线数据一一对应，其中，M为大于1的整数。
  4. 根据权利要求3所述的读操作电路，其特征在于，每组读取数据为N位，其中，N为大于1的整数，所述数据判断模块用于在输入的一组读取数据中为低的数据的位数大于N/2的情况下，将输入的一组读取数据的翻转数据作为对应的一组全局总线数据输出，并将输入的一组读取数据对应的一位翻转标识数据置为高；以及在输入的一组读取数据中为低的数据的位数小于等于N/2的情况下，将输入的一组读取数据作为 对应的一组全局总线数据输出，并将输入的一组读取数据对应的一位翻转标识数据置为低。
  5. 根据权利要求1所述的读操作电路，其特征在于，所述数据判断模块包括：
    数据判断单元，所述数据判断单元的输入端连接于所述存储块，所述数据判断单元的输出端与所述翻转标识信号线连接，所述数据判断单元用于在读取数据中为低的数据的位数大于预设值的情况下，将所述翻转标识数据置为高；以及在所述读取数据中为低的数据的位数小于等于所述预设值的情况下，将所述翻转标识数据置为低；
    数据选择器，所述数据选择器的输入端连接于所述数据判断单元，用于通过所述数据判断单元接收所述读取数据，所述数据选择器的输入端还通过所述翻转标识信号线接收所述翻转标识数据，所述数据选择器的输出端与所述全局总线连接，所述数据选择器用于在所述翻转标识数据为高的情况下，将所述读取数据的翻转数据作为所述全局总线数据输出；以及在所述翻转标识数据为低的情况下，将原始的读取数据作为所述全局总线数据输出。
  6. 根据权利要求5所述的读操作电路，其特征在于，所述数据选择器包括多个数据选择单元，所述数据选择单元包括：
    第一反相器，所述第一反相器的输入端通过所述翻转标识信号线接收所述翻转标识数据；
    第二反相器，所述第二反相器的输入端连接于所述数据判断单元，用于从所述数据判断单元接收所述读取数据；
    第一传输门，所述第一传输门的输入端连接于所述第二反相器的输出端，所述第一传输门的输出端与所述全局总线连接，用于输出所述全局总线数据，所述第一传输门的反控制端连接于所述第一反相器的输出端，所述第一传输门的正控制端通过所述翻转标识信号线接收所述翻转标识数据；
    第二传输门，所述第二传输门的输入端连接于所述数据判断单元，用于从所述数据判断单元接收所述读取数据，所述第二传输门的输出端与所述全局总线连接，用于输出所述全局总线数据，所述第二传输门的反控制端通过所述翻转标识信号线接收所述翻转标识数据，所述第二传输门的正控制端连接于所述第一反相器的输出端。
  7. 根据权利要求1所述的读操作电路，其特征在于，所述数据接收模块用于在所述翻转标识数据为高的情况下，将所述全局总线数据的翻转数据作为所述缓存数据输出；以及在所述翻转标识数据为低的情况下，将原始的全局总线数据作为所述缓存数据输出。
  8. 根据权利要求1所述的读操作电路，其特征在于，所述数据接收模块包括多个数据接收单元，所述数据接收单元包括：
    第三反相器，所述第三反相器的输入端通过所述翻转标识信号线接收所述翻转标识数据；
    第四反相器，所述第四反相器的输入端通过所述全局总线接收所述全局总线数据；
    第三传输门，所述第三传输门的输入端连接于所述第四反相器的输出端，所述第三传输门的输出端与所述并串转换电路连接，用于向所述并串转换电路输出所述缓存数据，所述第三传输门的反控制端连接于所述第三反相器的输出端，所述第三传输门的正控制端通过所述翻转标识信号线接收所述翻转标识数据；
    第四传输门，所述第四传输门的输入端通过所述全局总线接收所述全局总线数据，所述第四传输门的输出端与所述并串转换电路连接，用于向所述并串转换电路输出所述缓存数据，所述第四传输门的反控制端通过所述翻转标识信号线接收所述翻转标识数据，所述第四传输门的正控制端连接于所述第三反相器的输出端。
  9. 根据权利要求1至8任一项所述的读操作电路，其特征在于，所述数据缓冲模块包括多个NMOS晶体管，所述NMOS晶体管的栅极连接于所述存储块，所述NMOS晶体管的漏极连接于所述全局总线；以及所述预充电模块包括多个PMOS晶体管和多个保持电路，所述PMOS晶体管的栅极连接于所述预充电信号线，所述PMOS晶体管的漏极连接于所述全局总线，所述保持电路的输入和输出端连接于所述全局总线。
  10. 一种半导体存储器，其特征在于，包括DQ端口、存储块以及权利要求1至9任一项所述的读操作电路。
  11. 一种读操作方法，应用于半导体存储器，其特征在于，所述半导体存储器包括DQ端口和存储块，所述读操作方法包括：
    将全局总线的初始态设置为高；
    从所述存储块中读出读取数据；
    根据所述读取数据中为低的数据的位数，确定是否翻转所述读取数据，以输出供所述全局总线传输的全局总线数据和供翻转标识信号线传输的翻转标识数据；
    根据所述翻转标识数据，确定是否翻转所述全局总线数据，以输出缓存数据；
    对所述缓存数据进行并串转换，以生成所述DQ端口的输出数据。
  12. 根据权利要求11所述的读操作方法，其特征在于，根据所述读取数据中为低的数据的位数，确定是否翻转所述读取数据，以输出供全局总线传输的全局总线数据和供翻转标识信号线传输的翻转标识数据，包括：
    在所述读取数据中为低的数据的位数大于预设值的情况下，将所述读取数据的翻转数据作为所述全局总线数据输出，并将所述翻转标识数据置为高；
    在所述读取数据中为低的数据的位数小于等于所述预设值的情况下，将原始的读取数据作为所述全局总线数据输出，并将所述翻转标识数据置为低。
  13. 根据权利要求11所述的读操作方法，其特征在于，根据所述读取数据中为低的数据的位数，确定是否翻转所述读取数据，以输出供全局总线传输的全局总线数据和供翻转标识信号线传输的翻转标识数据，包括：
    将所述读取数据划分为M组，其中，每组读取数据为N位，M和N均为大于1的整数；
    在输入的一组读取数据中为低的数据的位数大于N/2的情况下，将输入的一组读取数据的翻转数据作为对应的一组全局总线数据输出，并将输入的一组读取数据对应的一位翻转标识数据置为高；
    在输入的一组读取数据中为低的数据的位数小于等于N/2的情况下，将输入的一组读取数据作为对应的一组全局总线数据输出，并将输入的一组读取数据对应的一位翻转标识数据置为低。
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