WO2021072812A1 - Dispositif de transistor à effet de champ à jonction à enrichissement à base de gan latéral et son procédé de préparation - Google Patents

Dispositif de transistor à effet de champ à jonction à enrichissement à base de gan latéral et son procédé de préparation Download PDF

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WO2021072812A1
WO2021072812A1 PCT/CN2019/114216 CN2019114216W WO2021072812A1 WO 2021072812 A1 WO2021072812 A1 WO 2021072812A1 CN 2019114216 W CN2019114216 W CN 2019114216W WO 2021072812 A1 WO2021072812 A1 WO 2021072812A1
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gan
channel layer
layer
effect transistor
junction field
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PCT/CN2019/114216
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English (en)
Chinese (zh)
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郭慧
陈敦军
张�荣
郑有炓
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南京大学
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Publication of WO2021072812A1 publication Critical patent/WO2021072812A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
    • H01L29/66901—Unipolar field-effect transistors with a PN junction gate, i.e. JFET with a PN homojunction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate

Definitions

  • the invention relates to an enhanced junction field effect transistor (JFET), in particular to a lateral GaN-based enhanced junction field effect transistor.
  • JFET junction field effect transistor
  • GaN-based field effect transistors have the advantages of high operating frequency, low on-resistance, high power density, and high breakdown voltage, so they have broad application prospects.
  • AlGaN/GaN Heterojunction High Electron Mobility Transistor (HEMT) has developed rapidly due to the relatively easy growth process to achieve, while GaN-based junction field effect transistor (JFET) requires the use of re-growth or ion implantation process to achieve pn junction. The process is more complicated, so its development is relatively lagging behind.
  • JFET devices have the characteristics of high input impedance, low noise, high limit frequency, low power consumption, and strong anti-radiation ability. They have important applications in the field of variable resistors and power amplifiers. JFET is generally a depletion type device, and the gate can only work normally by applying a reverse voltage. For power electronics applications, power semiconductor devices are often required to be enhanced devices, otherwise it will increase the design difficulty of the drive circuit and increase The off-state loss of high-power semiconductor devices.
  • the purpose of the present invention is to provide a lateral GaN-based enhancement mode junction field effect transistor device, which realizes an enhancement mode GaN-based junction field effect transistor.
  • a lateral GaN-based enhancement mode junction field effect transistor device includes:
  • n-GaN channel layer grown on a semi-insulating GaN layer, where a plurality of parallel channels are arranged in the n-GaN channel layer, reaching as deep as the semi-insulating GaN layer;
  • It also includes strip-shaped p-GaN filled in the channel of the n-GaN channel layer, and the p-GaN and the n-GaN channel layer form multiple sandwich p-n junctions;
  • the source electrode and the drain electrode are respectively arranged at both ends of the top surface of the n-GaN channel layer;
  • the gate electrode covers the top surface of the p-GaN and is connected at one end to form a gate electrode with an interdigital structure.
  • the substrate layer is a sapphire substrate, a Si substrate or a SiC substrate.
  • the height of the semi-insulating GaN layer is 2-5 ⁇ m.
  • the channel width of the n-GaN channel layer is 300-500 nm.
  • the channel thickness of n-GaN is 50-200nm, the channel length is 15-30 ⁇ m, and the silicon doping concentration is 1*10 18 cm -3 ;
  • the surface of p-GaN and n- The surface of the GaN channel layer is flush or slightly higher than the surface of the n-GaN channel layer, the width of p-GaN is 50-100nm, the length is the same as the channel length of the n-GaN channel layer, and the doping concentration is 1*10 18 -1*10 19 cm-3, control the width of the channel so that the channel is in a depleted state under zero bias. That is, the device is in enhanced mode.
  • Slightly higher than the surface of the n-GaN channel layer means that the height difference is within 50 nm.
  • the source electrode and the drain electrode are Ti/Al/Ni/Au multilayer metal with a thickness of 30/150/50/150 nm
  • the gate electrode is Ni/Au multilayer metal with a thickness of 50/100 nm.
  • the invention also discloses a method for preparing the above-mentioned lateral GaN-based enhancement type junction field effect transistor device, the steps of which include:
  • MOCVD method deposits a semi-insulating GaN layer and an n-GaN channel layer on the surface of the substrate;
  • the method for growing semi-insulating GaN in step (1) Trimethylgallium and NH 3 are used as Ga source and N source respectively, the carrier gas is H 2 or N 2 , the growth temperature is 1000-1100° C., and the growth time is 2 -5h, the growth method of the n-GaN channel layer: temperature 950-1050°C, silicon doping concentration 1*10 18 cm -3 , growth time 15-20min;
  • the channel depth is to the semi-insulating GaN layer and over-etched by 50-100 nm to ensure that the n-GaN is completely removed;
  • step (4) an electron beam evaporation method is used to fabricate Ti/Al/Ni/Au30/150/50/150nm multilayer metal on both ends of the top surface of the n-GaN channel layer as the source and drain electrodes.
  • the Ni/Au 50/100nm gate metal electrode with interdigital structure was fabricated on the top surface of GaN, and it was placed in a rapid thermal annealing furnace at 850°C for 30s.
  • the invention also discloses another preparation method of the above-mentioned lateral GaN-based enhancement type junction field effect transistor device, the steps of which include:
  • MOCVD method deposits a semi-insulating GaN layer and an n-GaN channel layer on the surface of the substrate;
  • the method for growing semi-insulating GaN in step (1) Trimethylgallium and NH 3 are used as Ga source and N source respectively, the carrier gas is H 2 or N 2 , the growth temperature is 1000-1100° C., and the growth time is 2 -5h, the growth method of the n-GaN channel layer: temperature 950-1050°C, silicon doping concentration 1*10 18 cm -3 , growth time 15-20min;
  • step (2) the energy of ion implantation is 100-120KeV, the implantation dose is 1*10 18 cm -3 -1*10 19 cm -3 , annealing is performed at 800-1200 degrees for 30s-60s;
  • step (3) an electron beam evaporation method is used to fabricate Ti/Al/Ni/Au30/150/50/150nm multilayer metal on both ends of the top surface of the n-GaN channel layer as source and drain electrodes.
  • the Ni/Au 50/100nm gate metal electrode with interdigital structure was fabricated on the top surface of GaN, and it was placed in a rapid thermal annealing furnace at 850°C for 30s.
  • a multi-piece vertical interdigital structure p-GaN is obtained on an n-GaN substrate by groove + epitaxial re-growth or ion implantation, and a plurality of thin pn junction lateral n-type channels are formed with the n-GaN substrate, and then through
  • the control of the channel thickness and the p-type and n-type doping concentration makes the n-type channel in a fully depleted state of the built-in electric field of the pn junction under zero bias, that is, the device is in the off state, and a forward bias is required to Make the channel in a conductive state, that is, the device has a positive threshold voltage.
  • the multi-channel ensures the large current output of the device.
  • the invention realizes an enhanced GaN-based junction field effect transistor.
  • the traditional junction field effect transistors are all depletion type, and they are in the on state under zero bias, which will increase the off-state loss of the power semiconductor device, and it is not safe to use.
  • the enhanced device of the present invention not only does not have these problems, but can also simplify the driving circuit.
  • the multi-channel ensures that the GaN-based junction field effect transistor has a large output current.
  • Fig. 1 is a schematic diagram of the structure of the n-GaN epitaxial wafer obtained in step (1) of Example 1.
  • FIG. 2 is a schematic diagram of the structure of the n-GaN epitaxial wafer obtained in step (2) of Example 1.
  • Fig. 3 is a schematic structural diagram of a lateral GaN-based enhancement mode device obtained in step (3) of Example 1.
  • FIG. 4 is a schematic diagram of the structure of the lateral GaN-based enhancement mode device obtained in step (4) of Example 1.
  • FIG. 5 is a schematic diagram of the lateral GaN-based enhancement mode device in FIG. 3 with dimensions in various directions marked.
  • a method for manufacturing a lateral GaN-based enhancement mode junction field effect transistor device the steps include:
  • MOCVD method deposits a semi-insulating GaN layer 2 and an n-GaN channel layer 3 on the surface of the sapphire substrate 1, as shown in Figure 1.
  • the growth method of semi-insulating GaN Trimethylgallium and NH 3 are used as Ga sources respectively With N source, the carrier gas is H 2 or N 2 , the growth temperature is 1000-1100°C, and the growth time is 3-5h.
  • the growth method of the n-GaN channel layer temperature 950-1050°C, silicon doping concentration 1*10 18 cm -3 , growth time 15-20min;
  • p-GaN strip structure is about n higher -
  • the surface of the GaN channel layer is 10-50nm, forming multiple sandwich pn junctions, as shown in Figure 3;
  • Ti/Al/Ni/Au30/150/50/150nm multilayer metal is fabricated on both ends of the top surface of the n-GaN channel layer by electron beam evaporation method, and annealed at 850 degrees for 30s in a rapid thermal annealing furnace ,
  • the source alloy electrode 6 and the drain alloy electrode 7 are formed, and an interdigitated Ni/Au 50/100nm gate metal electrode 8 is fabricated on the top surface of the p-GaN to obtain the lateral GaN-based enhancement mode junction field shown in Figure 4 Effect tube device.
  • the method for preparing a lateral GaN-based enhancement mode junction field effect transistor device has basically the same steps as in Embodiment 1. The difference is that the p-GaN strip structure is substantially flush with the surface of the n-GaN channel layer.
  • a method for preparing a lateral GaN-based enhancement type junction field effect transistor device the steps of which include:
  • MOCVD method deposits semi-insulating GaN layer and n-GaN channel layer on the surface of SiC substrate.
  • the growth method of semi-insulating GaN Trimethylgallium and NH 3 are used as Ga source and N source respectively, and the carrier gas is H 2 Or N 2 , the growth temperature is 1000-1100°C, and the growth time is 3-5h.
  • the growth method of the n-GaN channel layer temperature 950-1050°C, silicon doping concentration 1*10 18 cm -3 , growth time 15-20min;
  • Ti/Al/Ni/Au30/150/50/150nm multilayer metal is fabricated on both ends of the top surface of the n-GaN channel layer by electron beam evaporation method, and annealed at 850 degrees for 30s in a rapid thermal annealing furnace , Forming source and drain alloy electrodes, and fabricating an interdigitated Ni/Au 50/100nm gate metal on the top surface of the p-GaN.
  • a sapphire substrate layer A sapphire substrate layer
  • An n-GaN channel layer grown on a semi-insulating GaN layer has a thickness (ie, the channel width of n-GaN) of 300 nm, and a plurality of parallel grooves are provided in the n-GaN channel layer to a depth of half Insulating GaN layer, the channel thickness of n-GaN is 50 nm, and the channel length is 15 ⁇ m.
  • the n-GaN silicon doping concentration is 1*10 18 cm -3 ;
  • It also includes p-GaN filled in the groove of the n-GaN channel layer.
  • the p-GaN and the n-GaN channel layer form multiple sandwich pn junctions.
  • the surface of the p-GaN is slightly higher than the n-GaN channel.
  • the layer surface is 10nm; the width of p-GaN is 50nm, the length is 15 ⁇ m, and the doping concentration of p-GaN is 1*10 19 cm -3 ;
  • the source electrode and the drain electrode are respectively arranged at both ends of the top surface of the n-GaN channel layer; the source electrode and the drain electrode are Ti/Al/Ni/Au multilayer metal with a thickness of 30/150/50/150nm;
  • the gate electrode of the interdigital structure covers the top surface of the p-GaN.
  • the gate electrode is a Ni/Au multilayer metal with a thickness of 50/100nm.
  • An n-GaN channel layer grown on a semi-insulating GaN layer has a thickness (that is, the width of the n-GaN channel) of 500 nm, and a plurality of parallel grooves are provided in the n-GaN channel layer to a depth of half Insulating GaN layer, the channel thickness of n-GaN is 200 nm, and the channel length is 30 ⁇ m.
  • the n-GaN silicon doping concentration is 1*10 18 cm -3 ;
  • It also includes p-GaN filled in the groove of the n-GaN channel layer.
  • the p-GaN and the n-GaN channel layer form multiple sandwich pn junctions; the width of p-GaN is 100 nm and the length is 30 ⁇ m.
  • the p-GaN and n-GaN channel layer surfaces are flush, and the doping concentration of p-GaN is 1*10 18 cm -3 ;
  • the source electrode and the drain electrode are respectively arranged at both ends of the top surface of the n-GaN channel layer; the source electrode and the drain electrode are Ti/Al/Ni/Au multilayer metal with a thickness of 30/150/50/150nm;
  • the gate electrode of the interdigital structure covers the top surface of the p-GaN.
  • the gate electrode is a Ni/Au multilayer metal with a thickness of 50/100nm.
  • An n-GaN channel layer grown on a semi-insulating GaN layer has a thickness (that is, the width of the n-GaN channel) of 400 nm, and a plurality of parallel grooves are provided in the n-GaN channel layer to a depth of half Insulating GaN layer, the channel thickness of n-GaN is 100 nm, and the channel length is 25 ⁇ m.
  • the n-GaN silicon doping concentration is 1*10 18 cm -3 ;
  • It also includes p-GaN filled in the groove of the n-GaN channel layer.
  • the p-GaN and the n-GaN channel layer form multiple sandwich pn junctions.
  • the surface of the p-GaN is slightly higher than the n-GaN channel.
  • the layer surface is 50nm; the width of p-GaN is 80nm, the length is 25 ⁇ m, and the doping concentration of p-GaN is 1*10 19 cm -3 ;
  • the source electrode and the drain electrode are respectively arranged at both ends of the top surface of the n-GaN channel layer; the source electrode and the drain electrode are Ti/Al/Ni/Au multilayer metal with a thickness of 30/150/50/150nm;
  • the gate electrode of the interdigital structure covers the top surface of the p-GaN.
  • the gate electrode is a Ni/Au multilayer metal with a thickness of 50/100nm.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

L'invention concerne un dispositif de transistor à effet de champ à jonction à enrichissement à base de GaN latéral et son procédé de préparation. Selon le dispositif, au moyen d'un rainurage et d'une re-croissance épitaxiale ou d'une implantation ionique, de multiples structures de bande verticale p-GaN sont obtenues sur un substrat n-GaN, et forment de multiples canaux du type n latéraux de jonction p-n mince avec le substrat n-GaN ; puis, au moyen d'une commande de l'épaisseur de canal et des concentrations de dopage du type p et du type n, les canaux du type n sont dans l'état complètement appauvri du champ électrique intrinsèque d'une jonction p-n sous polarisation nulle, c'est-à-dire que le dispositif est dans un état bloqué, et une polarisation directe doit être appliquée pour mettre les canaux dans un état passant, c'est-à-dire que le dispositif a une tension de seuil positive. De plus, les multiples canaux assurent une sortie à fort courant du dispositif.
PCT/CN2019/114216 2019-10-16 2019-10-30 Dispositif de transistor à effet de champ à jonction à enrichissement à base de gan latéral et son procédé de préparation WO2021072812A1 (fr)

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CN201910981564.0 2019-10-16
CN201910981564.0A CN110690273B (zh) 2019-10-16 2019-10-16 横向GaN基增强型结型场效应管器件及其制备方法

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Cited By (1)

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Publication number Priority date Publication date Assignee Title
CN115732563A (zh) * 2022-11-29 2023-03-03 西安电子科技大学 一种热电优化的鳍式氧化镓mosfet结构及制作方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111524973A (zh) * 2020-05-06 2020-08-11 南京冠鼎光电科技有限公司 叉指状p-GaN栅结构HEMT型紫外探测器及其制备方法
CN111599856B (zh) * 2020-05-27 2022-06-21 南京大学 双沟道增强型准垂直结构GaN基JFET及其制备方法

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EP0167810A1 (fr) * 1984-06-08 1986-01-15 Eaton Corporation JFET de puissance comportant plusieurs pincements latéraux
US5118632A (en) * 1989-10-20 1992-06-02 Harris Corporation Dual layer surface gate JFET having enhanced gate-channel breakdown voltage
FR2818013A1 (fr) * 2000-12-13 2002-06-14 St Microelectronics Sa Transistor a effet de champ a jonction destine a former un limiteur de courant
JP2004349327A (ja) * 2003-05-20 2004-12-09 Sumitomo Electric Ind Ltd 横型トランジスタおよび直流交流変換装置
CN108054215A (zh) * 2017-12-21 2018-05-18 深圳市晶特智造科技有限公司 结型场效应晶体管及其制作方法
US20180219106A1 (en) * 2017-01-30 2018-08-02 QROMIS, Inc. Lateral gallium nitride jfet with controlled doping profile

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EP0167810A1 (fr) * 1984-06-08 1986-01-15 Eaton Corporation JFET de puissance comportant plusieurs pincements latéraux
US5118632A (en) * 1989-10-20 1992-06-02 Harris Corporation Dual layer surface gate JFET having enhanced gate-channel breakdown voltage
FR2818013A1 (fr) * 2000-12-13 2002-06-14 St Microelectronics Sa Transistor a effet de champ a jonction destine a former un limiteur de courant
JP2004349327A (ja) * 2003-05-20 2004-12-09 Sumitomo Electric Ind Ltd 横型トランジスタおよび直流交流変換装置
US20180219106A1 (en) * 2017-01-30 2018-08-02 QROMIS, Inc. Lateral gallium nitride jfet with controlled doping profile
CN108054215A (zh) * 2017-12-21 2018-05-18 深圳市晶特智造科技有限公司 结型场效应晶体管及其制作方法

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* Cited by examiner, † Cited by third party
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CN115732563A (zh) * 2022-11-29 2023-03-03 西安电子科技大学 一种热电优化的鳍式氧化镓mosfet结构及制作方法

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