WO2021068551A1 - 数据的存储比较方法、存储比较电路装置及半导体存储器 - Google Patents

数据的存储比较方法、存储比较电路装置及半导体存储器 Download PDF

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WO2021068551A1
WO2021068551A1 PCT/CN2020/097334 CN2020097334W WO2021068551A1 WO 2021068551 A1 WO2021068551 A1 WO 2021068551A1 CN 2020097334 W CN2020097334 W CN 2020097334W WO 2021068551 A1 WO2021068551 A1 WO 2021068551A1
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input
output
terminal
data
gate
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PCT/CN2020/097334
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English (en)
French (fr)
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张良
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长鑫存储技术有限公司
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Priority to EP20875151.1A priority Critical patent/EP4044435A4/en
Priority to US17/178,250 priority patent/US11632100B2/en
Publication of WO2021068551A1 publication Critical patent/WO2021068551A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H03K19/215—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using field-effect transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors

Definitions

  • the present invention relates to the technical field of semiconductor integrated circuits, in particular to a data storage comparison method, a storage comparison circuit device and a semiconductor memory.
  • common memory comparators include latches and XOR gates.
  • the latch is a level-triggered storage unit, and the data storage action (state transition) depends on the level of the input clock (or enable) signal.
  • the output will change with the data input.
  • One of the two input terminals in the XOR gate is used to input the first data, and the other input terminal is connected with the output terminal of the latch.
  • the second data can be input into the latch, and the second data is delayed by the latch to obtain delayed data.
  • the delayed data is input to the other input terminal of the XOR gate.
  • the output signal is obtained.
  • the internal structure of the latch and the XOR gate is complicated and the area is too large. When such circuit units are used too much, the chip area will be too large and the chip cost will be affected.
  • the present invention provides a data storage and comparison method, a storage comparison circuit device and a semiconductor memory to overcome or alleviate one or more problems in the background art, and at least provide a beneficial choice.
  • a storage comparison circuit device in a first aspect, includes a latch and a comparator.
  • the latch is used to latch input first input data and output the first input data.
  • One output data and second output data, the first output data is the same as the first input data, and the second output data is different from the first input data, wherein the first output data and the first input data are different.
  • the second output data are respectively input to the comparator;
  • the comparator is configured to receive second input data, the first output data, and the second output data, and output a comparison result.
  • the latch includes a transmission gate, an inverter, and a tri-state gate;
  • the input terminal of the transmission gate is used to input the first input data
  • the output terminal of the transmission gate is connected to the input terminal of the inverter
  • the output terminal of the inverter is connected to the tri-state gate
  • the input terminal of the three-state gate and the output terminal of the three-state gate are connected to the output terminal of the transmission gate
  • the transmission gate further includes a transmission gate control terminal
  • the three-state gate further includes a three-state gate control terminal
  • the transmission gate control terminal and the three-state gate control terminal are used to receive control signals, and the control signals are used to control the transmission gate to be turned on and the three-state gate to close, so that the output terminal of the transmission gate outputs The first output data, and the output terminal of the inverter outputs the second output data; or the transmission gate is controlled to close and the tri-state gate is turned on, so that the output terminal of the inverter outputs The second output data.
  • the comparator includes a first input terminal, a second input terminal, and a third input terminal.
  • the first input terminal is used for receiving the second input data
  • the second input terminal is used for When receiving the first output data
  • the third input terminal is used to receive the second output data
  • the output terminal of the comparator is used to output the comparison result.
  • the transmission gate control terminal includes a first control terminal and a second control terminal
  • the tri-state gate control terminal includes a third control terminal and a fourth control terminal.
  • the third control terminal is connected to the gate of the PMOS tube, and the second control terminal and the fourth control terminal are both connected to the gate of the NMOS tube;
  • the transmission gate is controlled to be turned on; when the third control terminal inputs a high level, and the fourth control terminal When a low level is input to the terminal, the three-state gate is in a high-impedance state;
  • the transmission gate is controlled to close; when the third control terminal inputs a low level, and the fourth control terminal When a high level is input, the three-state gate is turned on.
  • the comparator includes a first transistor and a second transistor connected in series, and a third transistor and a fourth transistor connected in parallel;
  • the gate of the first transistor and the gate of the second transistor are connected to a first connection point, the source of the third transistor and the source of the fourth transistor are connected to a second connection point, and The first connection point and the second connection point are connected to the first input terminal;
  • the source of the first transistor and the gate of the third transistor are connected to the third input terminal, and the third input terminal is connected to the output terminal of the inverter;
  • the source of the second transistor and the gate of the fourth transistor are connected to the second input terminal, and the second input terminal is connected to the input terminal of the inverter;
  • the drain of the first transistor and the drain of the second transistor are connected to a third connection point
  • the drain of the third transistor and the drain of the fourth transistor are connected to a fourth connection point
  • the third connection point and the fourth connection point are connected to the output terminal of the comparator.
  • a semiconductor memory including the storage comparison circuit device according to any one of the above embodiments.
  • a data storage comparison method is provided, which is applied to the storage comparison circuit device according to any one of the above embodiments, and the storage comparison method includes:
  • the transmission gate in the latch When the transmission gate in the latch is controlled to be turned on according to the control signal, and the three-state gate in the latch is closed, the first input data is input to the transmission gate to output the first output data, And input the first output data to the inverter in the latch to output the second output data; or
  • the second input data, the first output data, and the second output data are input to a comparator to output a comparison result.
  • the inputting the second input data, the first output data, and the second output data into a comparator to output a comparison result includes:
  • the output comparison result is a logic signal 1;
  • the output comparison result is a logic signal 0.
  • the present invention adopts the above technical solution and has the following advantages: the unit structure of the latch and the comparator used in this application can simplify the device data in the latch and the comparator, reduce the chip area, and at the same time, reduce the amount of calculation and increase the data The efficiency of comparison.
  • FIG. 1 is a schematic structural diagram of a storage comparison circuit device provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of the internal structure of a latch and a comparator provided by an embodiment of the present application
  • Fig. 3 is a data storage comparison method provided by an embodiment of the present application.
  • the transmission gate 110 the input terminal 111 of the transmission gate, the output terminal 115 of the transmission gate, the transmission gate control terminal 112, the first control terminal 113, and the second control terminal 114;
  • An inverter 120 an input terminal 121 of the inverter, and an output terminal 122 of the inverter;
  • the first transistor 210, the second transistor 220, the third transistor 230, and the fourth transistor 240 are The first transistor 210, the second transistor 220, the third transistor 230, and the fourth transistor 240.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features.
  • “plurality” means two or more than two, unless otherwise specifically defined.
  • the terms “installed”, “connected”, “connected”, “fixed” and other terms should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. , Or integrated; it can be a mechanical connection, it can be an electrical connection, it can also be communication; it can be directly connected, or indirectly connected through an intermediate medium, it can be the internal communication of two components or the interaction relationship between two components .
  • installed can be a fixed connection or a detachable connection. , Or integrated; it can be a mechanical connection, it can be an electrical connection, it can also be communication; it can be directly connected, or indirectly connected through an intermediate medium, it can be the internal communication of two components or the interaction relationship between two components .
  • the "on" or “under” of the first feature of the second feature may include direct contact between the first and second features, or may include the first and second features. Not in direct contact but through other features between them.
  • “above”, “above” and “above” the second feature of the first feature include the first feature being directly above and obliquely above the second feature, or it simply means that the level of the first feature is higher than that of the second feature.
  • the “below”, “below” and “below” the first feature of the second feature include the first feature directly below and obliquely below the second feature, or it simply means that the level of the first feature is smaller than the second feature.
  • a storage comparison circuit device is provided.
  • the storage comparison circuit device 1 includes a latch 10 and a comparator 20, and the latch 10 is used for the first input of the input.
  • the data is latched, and the first output data and the second output data are output.
  • the first output data is the same as the first input data, and the second output data is different from the first input data.
  • the first output data and the second output data They are respectively input to the comparator; the comparator 20 is used to receive the second input data, the first output data, and the second output data, and output the comparison result.
  • a latch is a memory cell circuit sensitive to the pulse level, which can change its state under the action of a specific input pulse level.
  • Latching means temporarily storing the signal to maintain a certain level state.
  • the main function of the latch is to cache.
  • the comparator compares two or more data items to determine whether they are equal, or to determine the size relationship and arrangement order between them.
  • a circuit or device that can realize this comparison function is called a comparator.
  • the comparator is a circuit that compares an analog voltage signal with a reference voltage.
  • the latch 10 includes a transmission gate 110, an inverter 120 and a tri-state gate 130.
  • the internal connection relationship of the latch 10 includes: the input terminal 111 of the transmission gate is used to input the first input data D1, the output terminal 115 of the transmission gate is connected to the input terminal 121 of the inverter, and the output terminal 122 of the inverter is connected to The input terminal 131 of the tri-state gate and the output terminal 132 of the tri-state gate are connected to the output terminal 115 of the transmission gate.
  • the transmission gate 110 further includes a transmission gate control terminal 112, and the tri-state gate 130 also includes a tri-state gate control terminal. 133.
  • the transmission gate control terminal 112 and the tri-state gate control terminal 133 are used to receive control signals.
  • the control signals are used to control the transmission gate 110 to be turned on and the tri-state gate 130 to close, so that the output terminal 115 of the transmission gate outputs the first output data Q , And the output terminal 122 of the inverter outputs the second output data QF; or the transmission gate 110 is controlled to close and the tri-state gate 130 is turned on, so that the output terminal 122 of the inverter outputs the second output data QF.
  • the comparator 20 includes a first input terminal 201, a second input terminal 202, and a third input terminal 203.
  • the first input terminal 201 is used to receive the second input data D0
  • the second input terminal 202 is used to receive the first output data Q.
  • the third input terminal 203 is used to receive the second output data QF
  • the output terminal 204 of the comparator is used to output the comparison result.
  • the first input data D1 input to the transmission gate 110 may be a logic signal 1
  • the obtained first output data Q is a logic signal 1.
  • the second output data QF obtained is a logic signal 0.
  • the first input terminal 201 of the comparator 20 receives the second input data D0
  • the second input data D0 may be a logic signal 0 or a logic signal 1.
  • the first output data Q that is a logic signal 1 is input to the second input terminal 202 of the comparator 20, and the second output data QF that is a logic signal 0 is input to the third input terminal 203 of the comparator 20.
  • the comparison result output by the output terminal 204 of the comparator is a logic signal 0. Since the first output data Q can represent the same data information as the first input data D1, and the second output data QF can represent data information different from the first input data D1, the result of this comparison indicates that it is the first of the logic signal 1. An input data D1 is different from the second input data D0 which is a logic signal 0, and the output comparison result is 0.
  • the comparison result output by the output terminal 204 of the comparator is a logic signal 1. Since the first output data Q can represent the same data information as the first input data D1, and the second output data QF can represent data information different from the first input data D1, the result of this comparison indicates that it is the first of the logic signal 1.
  • An input data D1 is the same as the second input data D0 which is a logic signal 1, and the output comparison result is 1.
  • the control signal controls the transmission gate 110 to close and the tri-state gate 130 is turned on
  • the first input data D1 input to the transmission gate 110 cannot enter the transmission gate no matter what changes.
  • the tri-state gate 130 is turned on.
  • the second output data QF is input to the tri-state gate 120, and the first output data Q is output from the tri-state gate 120, thereby forming a latch for the first input data D1 input before the transmission gate 110 is closed.
  • the comparison result output from the comparator 120 please refer to the foregoing process, which will not be repeated here.
  • the unit structure of the latch adopted in this embodiment can simplify the device data in the latch, reduce the chip area, and reduce the amount of calculation at the same time, ensuring the latching effect of the input data.
  • the transmission gate control terminal 112 includes a first control terminal 113 and a second control terminal 114
  • the tri-state gate control terminal 133 includes a third control terminal 134 and a fourth control terminal 135,
  • the first control terminal 113 and the third control terminal 134 are both connected to the gate of the PMOS tube
  • the second control terminal 114 and the fourth control terminal 135 are both connected to the gate of the NMOS tube.
  • the control transmission gate 110 When the first control terminal 113 inputs a high level and the second control terminal 114 inputs a low level, the control transmission gate 110 is closed; when the third control terminal 134 inputs a low level and the fourth control terminal 135 inputs a high level, The tri-state gate 130 is turned on.
  • the NMOS is turned on at a high level and turned off at a low level, and can be used to control the conduction with the ground.
  • PMOS is a low-level gate conduction, high-level disconnection, which can be used to control the conduction with the power supply.
  • the control signal controls the on and off of the transmission gate 110 and the tri-state gate 130 to achieve the latching of the first input data D1.
  • the comparator 20 includes a first transistor 210 and a second transistor 220 connected in series, and a third transistor 230 and a fourth transistor 240 connected in parallel.
  • the gate of the first transistor 210 and the gate of the second transistor 220 are connected to the first connection point A
  • the source of the third transistor 230 and the source of the fourth transistor 240 are connected to the second connection point B
  • the first connection Point A and the second connection point B are connected to the first input terminal 201
  • the source of the first transistor 210 and the gate of the third transistor 230 are connected to the third input terminal 203
  • the third input terminal 203 is connected to the inverter
  • the output terminal 122; the source of the second transistor 220 and the gate of the fourth transistor 240 are connected to the second input terminal 202, and the second input terminal 202 is connected to the input terminal 121 of the inverter
  • the drain of the first transistor 210 and The drain of the second transistor 220 is connected to the third connection point C
  • the unit structure of the comparator adopted in this embodiment can simplify the device data in the comparator, reduce the chip area, and reduce the amount of calculation at the same time, ensuring the comparison effect of the first input data D1 and the second input data D0.
  • a semiconductor memory including the storage comparison circuit device as in any one of the above embodiments.
  • a data storage comparison method is provided, which is applied to the storage comparison circuit device in Embodiment 1.
  • the storage comparison method includes:
  • Step S10 When the transmission gate in the latch is controlled to be turned on according to the control signal, and the three-state gate in the latch is closed, the first input data is input to the transmission gate to output the first output data, and Input the first output data to the inverter in the latch to output the second output data; or
  • Step S20 When the transmission gate is controlled to close according to the control signal and the three-state gate is turned on, input the second output data to the three-state gate to output the first output data;
  • Step S30 Input the second input data, the first output data, and the second output data into the comparator to output the comparison result.
  • step S30 includes:
  • the output comparison result is a logic signal 1;
  • the output comparison result is a logic signal 0.
  • the present invention adopts the above technical solution and has the following advantages: the unit structure of the latch and the comparator used in this application can simplify the device data in the latch and the comparator, reduce the chip area, and at the same time, reduce the amount of calculation and increase the data The efficiency of comparison.

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Abstract

本申请公开了数据的存储比较方法、存储比较电路装置及半导体存储器。存储比较电路装置包括锁存器和比较器，锁存器用于对输入的第一输入数据进行锁存，并输出第一输出数据和第二输出数据，第一输出数据与第一输入数据相同，第二输出数据与第一输入数据相异，其中第一输出数据和第二输出数据分别输入到比较器；比较器用于接收第二输入数据、第一输出数据以及第二输出数据，并输出比较结果。采用的锁存器和比较器的单元结构，能够简化锁存器和比较器中的器件数据，缩小芯片面积，同时，减少计算量，提高数据比较的效率。

Description

数据的存储比较方法、存储比较电路装置及半导体存储器
本申请要求于2019年10月8日提交中国专利局、申请号为201910949145.9、发明名称为“数据的存储比较方法、存储比较电路装置及半导体存储器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体集成电路技术领域，具体涉及一种数据的存储比较方法、存储比较电路装置以及半导体存储器。
背景技术
目前，常见的存储比较器中包括锁存器和同或门。锁存器(latch)是由电平触发的存储单元，且数据存储的动作(状态转换)取决于输入时钟(或者使能)信号的电平值，其中当锁存器处于使能状态时，输出才会随着数据输入发生变化。同或门中两个输入端中的一个输入端用于输入第一数据，另一个输入端与锁存器的输出端连接。可以将第二数据输入至锁存器中，第二数据经过锁存器的延时得到延时数据。延时数据输入至同或门的所述另一个输入端。最后，第一数据和延时数据经过同或门的比较之后，得到输出信号。然而，现有的存储比较器中，锁存器和同或门的内部结构复杂，面积过大。当这样的电路单元使用过多时，会造成芯片面积过大，影响芯片成本。
在背景技术中公开的上述信息仅用于加强对本发明的背景的理解，因此其可能包含没有形成为本领域普通技术人员所知晓的现有技术的信息。
发明内容
本发明提供一种数据的存储比较方法、存储比较电路装置以及半导体存储器，以克服或缓解背景技术中存在的一个或者更多个问题，至少提供一种有益的选择。
在第一方面，提供了一种存储比较电路装置，所述存储比较电路装置包括锁存器和比较器，所述锁存器，用于对输入的第一输入数据进行锁存，并输出第一输出数据和第二输出数据，所述第一输出数据与所述第一输入数据相同，而所述第二输出数据与所述第一输入数据相异，其中所述第一输出数据和所述第二输出数据分别输入到所述比较器；
所述比较器，用于接收第二输入数据、所述第一输出数据以及所述第二输出数据，并输出比较结果。
在一种实施方式中，所述锁存器包括传输门、反相器以及三态门；
所述传输门的输入端用于输入所述第一输入数据，所述传输门的输出端连接至所述反相器的输入端，所述反相器的输出端连接至所述三态门的输入端，以及所述三态门的输出端连接至所述传输门的输出端，其中，所述传输门还包括传输门控制端，且所述三态门还包括三态门控制端，所述传输门控制端和所述三态门控制端用于接收控制信号，所述控制信号用于控制所述传输门导通且所述三态门关闭，使得所述传输门的输出端输出所述第一输出数据，且所述反相器的输出端输出所述第二输出数据；或者控制所述传输门关闭且所述三态门导通，使得所述反相器的输出端输出所述第二输出数据。
在一种实施方式中，所述比较器包括第一输入端、第二输入端以及第三输入端，所述第一输入端用于接收所述第二输入数据，所述第二输入端用于接收所述第一输出数据，所述第三输入端用于接收所述第二输出数据，以及所述比较器的输出端用于输出所述比较结果。
在一种实施方式中，所述传输门控制端包括第一控制端和第二控制端，所述三态门控制端包括第三控制端和第四控制端，所述第一控制端和所述第三控制端均连接至PMOS管的栅极，以及所述第二控制端和第四控制端均连接至NMOS管的栅极；
当所述第一控制端输入低电平，且所述第二控制端输入高电平时，控制所述传输门导通；当所述第三控制端输入高电平，且所述第四控制端输入低电平时，所述三态门为高阻态；
当所述第一控制端输入高电平，且所述第二控制端输入低电平时，控制所述传输门关闭；当所述第三控制端输入低电平，且所述第四控制端输入高电平时，所述三态门导通。
在一种实施方式中，所述比较器包括串联的第一晶体管和第二晶体管，以及并联的第三晶体管和第四晶体管；
所述第一晶体管的栅极与所述第二晶体管的栅极相连于第一连接点，所述第三晶体管的源极与所述第四晶体管的源极相连于第二连接点，以及所述第一连接点和所述第二连接点连接至所述第一输入端；
所述第一晶体管的源极与所述第三晶体管的栅极相连至所述第三输入端，所述第三输入端连接至所述反相器的输出端；
所述第二晶体管的源极与所述第四晶体管的栅极相连至所述第二输入端，所述第二输入端连接至所述反相器的输入端；
所述第一晶体管的漏极和所述第二晶体管的漏极相连于第三连接点，所述第三晶体管的漏极和所述第四晶体管的漏极相连于第四连接点，以及所述第三连接点和所述第四连接点连接至所述比较器的输出端。
在第二方面，提供了一种半导体存储器，包括如上述实施方式中任一项所述的存储比较电路装置。
在第三方面，提供了一种数据的存储比较方法，应用于上述实施方式中任一项所述的存储比较电路装置，所述存储比较方法包括：
在根据控制信号控制锁存器中的传输门导通，且所述锁存器中的三态门关闭的情况下，将第一输入数据输入至所述传输门，以输出第一输出数据，以及将所述第一输出数据输入至所述锁存器中的反相器，以输出第二输出数据；或
在根据所述控制信号控制所述传输门关闭，且所述三态门导通的情况下，将所述第二输出数据输入至所述三态门，以输出所述第一输出数据；以及
将第二输入数据、所述第一输出数据以及所述第二输出数据输入至比较器中，以输出比较结果。
在一种实施方式中，所述将第二输入数据、所述第一输出数据以及 所述第二输出数据输入至比较器中，以输出比较结果，包括：
在所述第二输入数据与所述第一输出数据相同的情况下，输出的比较结果为逻辑信号1；或
在所述第二输入数据与所述第二输出数据相同的情况下，输出的比较结果为逻辑信号0。
本发明采用上述技术方案，具有如下优点：本申请采用的锁存器和比较器的单元结构，能够简化锁存器和比较器中的器件数据，缩小芯片面积，同时，减少计算量，提高数据比较的效率。
上述概述仅仅是为了说明书的目的，并不意图以任何方式进行限制。除上述描述的示意性的方面、实施方式和特征之外，通过参考附图和以下的详细描述，本发明进一步的方面、实施方式和特征将会是容易明白的。
附图说明
在附图中，除非另外规定，否则贯穿多个附图相同的附图标记表示相同或相似的部件或元素。这些附图不一定是按照比例绘制的。应该理解，这些附图仅描绘了根据本发明公开的一些实施方式，而不应将其视为是对本发明范围的限制。附图用于更好地理解本方案，不构成对本申请的限定。其中：
图1是本申请实施例提供的一种存储比较电路装置的结构示意图；
图2是本申请实施例提供的一种锁存器和比较器的内部结构示意图；
图3是本申请实施例提供的一种数据的存储比较方法。
附图说明：
锁存器10；
传输门110、传输门的输入端111、传输门的输出端115、传输门控制端112、第一控制端113、第二控制端114；
反相器120、反相器的输入端121、反相器的输出端122；
三态门130、三态门的输入端131、三态门的输出端132、三态门控制端133、第三控制端134、第四控制端135；
比较器20；
第一输入端201、第二输入端202、第三输入端203、比较器的输出端204；
第一晶体管210、第二晶体管220、第三晶体管230、第四晶体管240。
具体实施方式
在下文中，仅简单地描述了某些示例性实施例。正如本领域技术人员可认识到的那样，在不脱离本发明的精神或范围的情况下，可通过各种不同方式修改所描述的实施例。因此，附图和描述被认为本质上是示例性的而非限制性的。
在本发明的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”、“轴向”、“径向”、“周向”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本发明的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本发明中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”、“固定”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，也可以是电连接，还可以是通信；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的 连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。
在本发明中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本发明提供了各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
实施例一
在一种具体实施方式中，提供了一种存储比较电路装置，如图1所示，存储比较电路装置1包括锁存器10和比较器20，锁存器10用于对输入的第一输入数据进行锁存，输出第一输出数据和第二输出数据，第一输出数据与第一输入数据相同，而第二输出数据与第一输入数据相异，其中第一输出数据和第二输出数据分别输入到比较器；比较器20用于接收第二输入数据、第一输出数据以及第二输出数据，并输出比较结果。锁存器(Latch)是一种对脉冲电平敏感的存储单元电路，其可以在特定输入脉冲电平作用下改变状态。锁存，就是把信号暂存以维持某种电平状态。锁存器的最主要作用是缓存。比较器对两个或多个数据项进行比较，以确定它们是否相等，或确定它们之间的大小关系及排列顺序。能够实现这种比较功能的电路或装置称为比较器。比较器是 将一个模拟电压信号与一个基准电压相比较的电路。
在一种实施方式中，如图2所示，锁存器10包括传输门110、反相器120以及三态门130。锁存器10的内部连接关系包括：传输门的输入端111用于输入第一输入数据D1，传输门的输出端115连接至反相器的输入端121，反相器的输出端122连接至三态门的输入端131，以及三态门的输出端132连接至传输门的输出端115，其中，传输门110还包括传输门控制端112，且三态门130还包括三态门控制端133，传输门控制端112和三态门控制端133用于接收控制信号，控制信号用于控制传输门110导通且三态门130关闭，使得传输门的输出端115输出第一输出数据Q，且反相器的输出端122输出第二输出数据QF；或者控制传输门110关闭且三态门130导通，使得反相器的输出端122输出第二输出数据QF。
比较器20包括第一输入端201、第二输入端202以及第三输入端203，第一输入端201用于接收第二输入数据D0，第二输入端202用于接收第一输出数据Q，第三输入端203用于接收第二输出数据QF，以及比较器的输出端204用于输出比较结果。
在一种示例中，当控制信号控制传输门110导通，三态门130为高阻态的情况下，输入传输门110的第一输入数据D1可以为逻辑信号1，第一输入数据D1经过传输门110之后，得到的第一输出数据Q为逻辑信号1。第一输出数据Q经过反相器120之后，得到的第二输出数据QF为逻辑信号0。需要指出的是，第一输出数据Q能够表示与第一输入数据D1相同的数据信息，而第二输出数据QF能够表示与第一输入数据D1相异的数据信息。比较器20的第一输入端201接收第二输入数据D0，第二输入数据D0可以为逻辑信号0或者逻辑信号1。为逻辑信号1的第一输出数据Q输入至比较器20的第二输入端202，为逻辑信号0的第二输出数据QF输入至比较器20的第三输入端203。
当第二输入数据D0为逻辑信号0，第一输出数据Q为逻辑信号1，以及第二输出数据QF为逻辑信号0时，比较器的输出端204输出的比较结果为逻辑信号0。由于第一输出数据Q能够表示与第一输入数据 D1相同的数据信息，而第二输出数据QF能够表示与第一输入数据D1相异的数据信息，所以此比较结果表明为逻辑信号1的第一输入数据D1与为逻辑信号0的第二输入数据D0相异，输出比较结果为0。
当第二输入数据D0为逻辑信号1，第一输出数据Q为逻辑信号1，第二输出数据QF为逻辑信号0时，比较器的输出端204输出的比较结果为逻辑信号1。由于第一输出数据Q能够表示与第一输入数据D1相同的数据信息，而第二输出数据QF能够表示与第一输入数据D1相异的数据信息，所以此比较结果表明为逻辑信号1的第一输入数据D1与为逻辑信号1的第二输入数据D0相同，输出比较结果为1。
当控制信号控制传输门110关闭，且三态门130导通的情况下，输入传输门110的第一输入数据D1无论如何变化，都无法进入传输门，此时，三态门130导通，使得第二输出数据QF输入至三态门120，从三态门120输出第一输出数据Q，从而对在传输门110关闭之前输入的第一输入数据D1形成锁存。此时，从比较器120输出的比较结果请参考前述过程，在此不再赘述。本实施方式采用的锁存器的单元结构，能够简化锁存器中的器件数据，缩小芯片面积，同时，减少计算量，保证了对输入数据的锁存效果。
一种实施方式中，在锁存器10中，传输门控制端112包括第一控制端113和第二控制端114，三态门控制端133包括第三控制端134和第四控制端135，第一控制端113和第三控制端134均接入PMOS管的栅极，以及第二控制端114和第四控制端135均接入NMOS管的栅极。当第一控制端113输入低电平，且第二控制端114输入高电平时，控制传输门110导通；当第三控制端134输入高电平，第四控制端135输入低电平时，三态门130为高阻态。当第一控制端113输入高电平，且第二控制端114输入低电平时，控制传输门110关闭；当第三控制端134输入低电平，且第四控制端135输入高电平时，三态门130导通。
在一种示例中，NMOS是栅极高电平导通、低电平断开，可用来控制与地之间的导通。PMOS是栅极低电平导通、高电平断开，可用来控制与电源之间的导通。根据前述原理，控制信号对传输门110和三态门 130的导通和关闭进行控制，达到对第一输入数据D1的锁存。
在一种实施方式中，比较器20包括串联的第一晶体管210和第二晶体管220，以及并联的第三晶体管230和第四晶体管240。第一晶体管210的栅极与第二晶体管220的栅极相连于第一连接点A，第三晶体管230的源极和第四晶体管240的源极相连于第二连接点B，以及第一连接点A和第二连接点B连接至第一输入端201；第一晶体管210的源极与第三晶体管230的栅极相连至第三输入端203，第三输入端203连接至反相器的输出端122；第二晶体管220的源极与第四晶体管240的栅极相连至第二输入端202，第二输入端202连接至反相器的输入端121；第一晶体管210的漏极和第二晶体管220的漏极相连于第三连接点C，第三晶体管230的漏极和第四晶体管240的漏极相连于第四连接点D，第三连接点C和第四连接点D连接至比较器的输出端204。
本实施方式采用的比较器的单元结构，能够简化比较器中的器件数据，缩小芯片面积，同时，减少计算量，保证了对第一输入数据D1和第二输入数据D0的比较效果。
实施例二
在另一种具体实施方式中，提供了一种半导体存储器，包括如上述实施方式中任一项的存储比较电路装置。
实施例三
在一种具体实施方式中，如图3所示，提供了一种数据的存储比较方法，应用于实施例一中的存储比较电路装置，所述存储比较方法包括：
步骤S10：在根据控制信号控制锁存器中的传输门导通，且锁存器中的三态门关闭的情况下，将第一输入数据输入至传输门，以输出第一输出数据，以及将第一输出数据输入至锁存器中的反相器，以输出第二输出数据；或
步骤S20：在根据控制信号控制传输门关闭，且三态门导通的情况下，将第二输出数据输入至三态门，以输出第一输出数据；以及
步骤S30：将第二输入数据、第一输出数据以及第二输出数据输入 至比较器中，以输出比较结果。
在一种实施方式中，步骤S30，包括：
在第二输入数据与第一输出数据相同的情况下，输出的比较结果为逻辑信号1；或
在第二输入数据与第二输出数据相同的情况下，输出的比较结果为逻辑信号0。
本发明采用上述技术方案，具有如下优点：本申请采用的锁存器和比较器的单元结构，能够简化锁存器和比较器中的器件数据，缩小芯片面积，同时，减少计算量，提高数据比较的效率。
上述具体实施方式，并不构成对本申请保护范围的限制。本领域技术人员应该明白的是，根据设计要求和其他因素，可以进行各种修改、组合、子组合和替代。任何在本申请的精神和原则之内所作的修改、等同替换和改进等，均应包含在本申请保护范围之内。

Claims (8)

  1. 一种存储比较电路装置，所述存储比较电路装置包括锁存器和比较器，其特征在于，
    所述锁存器，用于对输入的第一输入数据进行锁存，并输出第一输出数据和第二输出数据，所述第一输出数据与所述第一输入数据相同，而所述第二输出数据与所述第一输入数据相异，其中所述第一输出数据和所述第二输出数据分别输入到所述比较器；
    所述比较器，用于接收第二输入数据、所述第一输出数据以及所述第二输出数据，并输出比较结果。
  2. 根据权利要求1所述的存储比较电路装置，其特征在于，所述锁存器包括传输门、反相器以及三态门；
    所述传输门的输入端用于输入所述第一输入数据，所述传输门的输出端连接至所述反相器的输入端，所述反相器的输出端连接至所述三态门的输入端，以及所述三态门的输出端连接至所述传输门的输出端，其中，所述传输门还包括传输门控制端，且所述三态门还包括三态门控制端，所述传输门控制端和所述三态门控制端用于接收控制信号，所述控制信号用于控制所述传输门导通且所述三态门关闭，使得所述传输门的输出端输出所述第一输出数据，且所述反相器的输出端输出所述第二输出数据；或者控制所述传输门关闭且所述三态门导通，使得所述反相器的输出端输出所述第二输出数据。
  3. 根据权利要求2所述的存储比较电路装置，其特征在于，所述比较器包括第一输入端、第二输入端以及第三输入端，所述第一输入端用于接收所述第二输入数据，所述第二输入端用于接收所述第一输出数据，所述第三输入端用于接收所述第二输出数据，以及所述比较器的输出端用于输出所述比较结果。
  4. 根据权利要求2或3所述的存储比较电路装置，其特征在于，所述传输门控制端包括第一控制端和第二控制端，所述三态门控制端包括第三控制端和第四控制端，所述第一控制端和所述第三控制端均连接至PMOS 管的栅极，以及所述第二控制端和第四控制端均连接至NMOS管的栅极；
    当所述第一控制端输入低电平，且所述第二控制端输入高电平时，控制所述传输门导通；当所述第三控制端输入高电平，且所述第四控制端输入低电平时，所述三态门为高阻态；
    当所述第一控制端输入高电平，且所述第二控制端输入低电平时，控制所述传输门关闭；当所述第三控制端输入低电平，且所述第四控制端输入高电平时，所述三态门导通。
  5. 根据权利要求3所述的存储比较电路装置，其特征在于，所述比较器包括串联的第一晶体管和第二晶体管，以及并联的第三晶体管和第四晶体管；
    所述第一晶体管的栅极与所述第二晶体管的栅极相连于第一连接点，所述第三晶体管的源极与所述第四晶体管的源极相连于第二连接点，以及所述第一连接点和所述第二连接点连接至所述第一输入端；
    所述第一晶体管的源极与所述第三晶体管的栅极相连至所述第三输入端，所述第三输入端连接至所述反相器的输出端；
    所述第二晶体管的源极与所述第四晶体管的栅极相连至所述第二输入端，所述第二输入端连接至所述反相器的输入端；
    所述第一晶体管的漏极和所述第二晶体管的漏极相连于第三连接点，所述第三晶体管的漏极和所述第四晶体管的漏极相连于第四连接点，以及所述第三连接点和所述第四连接点连接至所述比较器的输出端。
  6. 一种半导体存储器，包括如权利要求1至5中任一项所述的存储比较电路装置。
  7. 一种数据的存储比较方法，其特征在于，应用于权利要求1至5中任一项所述的存储比较电路装置，所述存储比较方法包括：
    在根据控制信号控制锁存器中的传输门导通，且所述锁存器中的三态门关闭的情况下，将第一输入数据输入至所述传输门，以输出第一输出数据，以及将所述第一输出数据输入至所述锁存器中的反相器，以输出第二输出数据；或
    在根据所述控制信号控制所述传输门关闭，且所述三态门导通的情况 下，将所述第二输出数据输入至所述三态门，以输出所述第一输出数据；以及
    将第二输入数据、所述第一输出数据以及所述第二输出数据输入至比较器中，以输出比较结果。
  8. 根据权利要求7所述的存储比较方法，其特征在于，所述将第二输入数据、所述第一输出数据以及所述第二输出数据输入至比较器中，以输出比较结果，包括：
    在所述第二输入数据与所述第一输出数据相同的情况下，输出的比较结果为逻辑信号1；或
    在所述第二输入数据与所述第二输出数据相同的情况下，输出的比较结果为逻辑信号0。
PCT/CN2020/097334 2019-10-08 2020-06-22 数据的存储比较方法、存储比较电路装置及半导体存储器 WO2021068551A1 (zh)

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