WO2021068461A1 - 一种可控硅门极与阳极短接的低正向钳位电压开关二极管 - Google Patents

一种可控硅门极与阳极短接的低正向钳位电压开关二极管 Download PDF

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WO2021068461A1
WO2021068461A1 PCT/CN2020/081887 CN2020081887W WO2021068461A1 WO 2021068461 A1 WO2021068461 A1 WO 2021068461A1 CN 2020081887 W CN2020081887 W CN 2020081887W WO 2021068461 A1 WO2021068461 A1 WO 2021068461A1
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type
heavily doped
anode
gate
thyristor
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PCT/CN2020/081887
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English (en)
French (fr)
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赵德益
苏海伟
吕海凤
王允
赵志方
叶毓明
冯星星
李亚文
吴青青
张利明
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上海维安半导体有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/87—Thyristor diodes, e.g. Shockley diodes, break-over diodes

Definitions

  • the invention belongs to the technical field of semiconductors, and in particular relates to a low forward clamping voltage switching diode in which a thyristor gate and an anode are short-connected.
  • TVS transient voltage suppressor
  • Switching diodes are a type of semiconductor diodes, which are specially designed and manufactured for "on” (forward conduction) and “off” (reverse cutoff) on the circuit. Switching diodes have the characteristics of fast switching speed, small size, long life, high reliability, and low capacitance. They are widely used in switching circuits, detection circuits, high-frequency and pulse rectifier circuits and automatic control circuits of electronic equipment. Among them, one form of high-frequency application is to use with TVS diodes. By using the series and parallel connection of switching diodes and TVS diodes, the port capacitance is reduced from the large capacitance of the TVS diode to the low capacitance close to the switching diode, thereby reducing the capacitance of TVS products. So as to adapt to the application of high-speed ports. Switching diodes can be integrated with TVS diodes through packaging, or integrated on the same chip through chip process design.
  • TVS Low-capacitance TVS products including TVS diodes and switching diodes (D1 and D2) are shown in Figure 1.
  • TVS is used for potential control and is in a breakdown state during operation. The breakdown voltage is adjusted to adapt to different application scenarios. Generally, breakdown The voltage is greater than 1.2 times the working voltage.
  • FIG. 2 shows the schematic diagram of the circuit diagram of the switching diode D1 and the general cross-sectional structure of the commonly used low-capacitance TVS.
  • the switching diode In order to reduce the capacitance of the switching diode, high-resistance epitaxial materials are usually used to make the switching diode, or the switching diode is made in a low-concentration well to widen the depletion region of the switching diode to achieve the purpose of reducing capacitance, and at the same time bring negative
  • the effect is that the forward on-state dynamic resistance of the switching diode increases, which affects the protection effect of the TVS device.
  • the purpose of the present invention is to provide a low forward clamping voltage switching diode in which the thyristor gate and the anode are short-circuited.
  • Another object of the present invention is to provide a method for obtaining a low forward clamping voltage by using a silicon controlled rectifier structure to solve the problems in the prior art.
  • the present invention proposes a low forward clamping voltage switching diode with a thyristor gate and anode shorted, including a substrate material or an epitaxial layer of substrate material, N-type well, P-type well, and N-type heavily doped And P-type heavily doped semiconductor body, by designing the size and spacing of N-type well, P-type well, N-type doping and P-type doping to form a thyristor structure, in which the thyristor structure is connected by metal The gate and anode are shorted to form a switching diode.
  • the principle of the invention is: when the switching diode has excellent capacitance capability, its forward conduction current capability is enhanced, dynamic resistance is reduced, and low forward clamping voltage is obtained. When applied in series and parallel with TVS diodes, low capacitance and Protection device with low forward clamping voltage.
  • the thyristor includes two gate electrodes, both of which are short-circuited with the anode.
  • the substrate material is a P-type substrate or an N-type substrate
  • the substrate material epitaxial layer is a P epitaxial layer formed on the substrate material or an N epitaxial layer formed on the substrate material.
  • the structure is fabricated in a P-type substrate, an N-type substrate, a P epitaxy formed on the substrate material, or an N epitaxy formed on the substrate material.
  • the resistivity of the P-type substrate, the N-type substrate, the P epitaxial layer formed on the substrate material, and the N outer layer formed on the substrate material are all greater than or equal to 1 ⁇ cm.
  • an ohmic contact with the metal is formed by N-type heavy doping and P-type heavy doping.
  • an ohmic contact is formed with the metal through the N-well and the P-well.
  • the present invention also provides a method for obtaining a low forward clamping voltage by using a silicon controlled rectifier structure, which includes the following steps:
  • the gate-to-cathode current is used to provide a trigger current from the anode to the cathode to form a positive feedback, which enables the SCR structure to be turned on in advance, reduces the opening voltage of the SCR structure, and obtains a low positive clamping voltage.
  • the gate-to-cathode current is used to provide the trigger current from the anode to the cathode, including the first gate-to-cathode current to provide the trigger current from the anode to the cathode, and the second participating charge is used.
  • Transport accelerate the positive feedback of anode to cathode current.
  • the thyristor structure is fabricated in an N-well and a P-well whose combined concentration can be adjusted within a certain range, wherein the spacing, concentration, and junction depth between the N-well and the P-well can be adjusted to the anode to The voltage and trigger current of the cathode.
  • the implantation dose of the junction formed by the N-well and the P-well is 1E13 to 1E15, and the junction temperature is 1050°C to 1200°C.
  • step A the path from the gate to the cathode of the thyristor structure is made to have the "switching" characteristics and low capacitance characteristics of a switching diode
  • step B the path from the anode to the cathode of the thyristor structure is made
  • the path has the "off" state characteristics and low capacitance characteristics of the switching diode, and the turn-on voltage range through the "on" state characteristics includes the use of adjusting junction density matching and size spacing.
  • the switch diode of the invention has excellent capacitance capability, its forward conduction current capability is enhanced, dynamic resistance is reduced, and a low forward clamping voltage is obtained.
  • a protection device with low capacitance and low forward clamping voltage is obtained.
  • FIG. 1 Commonly used low-capacitance TVS circuit structure diagram
  • FIG. 2 A schematic diagram of the D1 circuit graphic symbol and general cross-sectional structure in the commonly used low-capacitance TVS;
  • Fig. 3 is a schematic diagram of the circuit graphic symbols and general cross-sectional structure of the thyristor structure
  • Figure 4 Schematic diagram and IV curve diagram of the electrical connection of the thyristor gate and anode short-circuit structure
  • Figure 5 uses a low-capacitance TVS circuit structure diagram of a low forward clamping voltage switching diode with a thyristor gate and anode short-circuit structure;
  • Fig. 6 is a schematic cross-sectional view of a switching diode with a short-circuit structure of the thyristor gate and anode;
  • Figure 7 is a schematic diagram of the cross-section and electrical connection of a switching diode with a short-circuit structure of the thyristor gate and anode;
  • Fig. 8 is a schematic diagram of the cross-section and electrical connection of a switching diode with a short-circuit structure of SCR gates and anodes of multiple groups of interposing fingers;
  • Fig. 9 is a schematic cross-sectional view of a switching diode with a gate electrode G2 having a short-circuited structure between the thyristor gate electrode and the anode;
  • Fig. 10 is a cross-section and electrical connection diagram of a switching diode with a gate electrode G2 of a thyristor gate and anode short-circuit structure;
  • Fig. 11 is a schematic diagram of the cross-section and electrical connection of a switching diode with a short-circuit structure of the thyristor gate electrode G2 and the anode electrode with multiple sets of interposing fingers.
  • Nwell N-type well
  • Pwell P-type well
  • G1 The first gate
  • G2 The second gate
  • A-anode; K-cathode K-cathode
  • the gate electrode G and the anode A of the SCR SCR shown in FIG. 3 are short-circuited through metal connection to form a switching diode.
  • the method for obtaining a low forward clamping voltage by using the SCR structure of the present invention includes the following steps:
  • the gate-to-cathode current is used to provide a trigger current from the anode to the cathode to form a positive feedback, which enables the SCR structure to be turned on in advance, reduces the opening voltage of the SCR structure, and obtains a low positive clamping voltage.
  • the characteristic curve is shown in Figure 4.
  • the diode forward conduction characteristic is as Diode V F
  • the curve shows that it has a lower turn-on voltage and a larger forward conduction resistance.
  • the characteristics of the thyristor path are as shown in the SCR snapback curve.
  • the thyristor When connecting in parallel, by optimizing process design parameters, such as Nsub thickness and resistivity, Pwell concentration and diffusion depth, the thyristor can be triggered to conduct after the diode is turned on, forming a characteristic curve as shown by the solid line in the first quadrant , To obtain low on-resistance; in the fourth quadrant, there are two current paths from the cathode to the anode and the gate short-circuit point, the diode reverse breakdown path from the cathode to the gate path and the thyristor reverse strike from the cathode to the anode The breakdown voltage of the two paths is relatively high, and the breakdown voltage from the cathode to the gate level is slightly lower, which bears the main current.
  • process design parameters such as Nsub thickness and resistivity, Pwell concentration and diffusion depth
  • Fig. 6 is the cross-sectional schematic diagram of the switching diode of the SCR gate and anode short connection structure
  • Fig. 7 is the cross-section and electrical connection schematic diagram of the SCR gate and anode short connection structure switching diode:
  • a low forward clamping voltage switching diode with a thyristor gate and anode short-circuited is integrated on a silicon chip to form a semiconductor body, including:
  • the silicon substrate material can be any one of the four types of P epitaxial layer Pepi, P type substrate Psub, N epitaxial layer Nepi, and N type substrate Nsub.
  • the silicon controlled structure is fabricated on the P type substrate. Take Psub as an example, the resistivity of the substrate material is greater than or equal to 1 ⁇ cm.
  • N-type well Nwell P-type heavily doped P+ region in N-type well Nwell;
  • the N-type heavily doped N+ and P-type heavily doped P+ regions in the P-well Pwell wherein the lead-out end of the P-type heavily doped P+ region in the N-type well Nwell is anode A, and the P-type well
  • the N-type heavily doped N+ in the Pwell is the cathode K and the P-type heavily doped P+ is the gate G, as shown in Figure 6;
  • the gate G and anode A of the thyristor SCR shown in Figure 7 are short-circuited to form a switching diode to be used in a TVS circuit, connected between Pin1 and Pin2, as the transient high voltage of Pin1 to Pin2
  • the discharge path, the switching diode is identified as SCR-D1 in Figure 5.
  • D2 and TVS serve as a discharge path from Pin2's transient high voltage to Pin1.
  • While the switching diode SCR-D1 has excellent capacitance capability, its forward conduction current capability is enhanced, dynamic resistance is reduced, and low forward clamping voltage is obtained. When applied in series and parallel with TVS diodes, low capacitance and low positive are obtained. Protection device for clamping voltage.
  • the N-type well Nwell and the P-type well Pwell whose concentration can be adjusted within a certain range are fabricated through the thyristor structure. Among them, the spacing, concentration and junction depth of the N-type well Nwell and the P-type well Pwell can be adjusted to adjust the anode A to The voltage and trigger current of the cathode K.
  • the implantation dose of the junction between the N-type well Nwell and the P-type well Pwell is between 1E13 and 1E15, and the junction temperature is 1050°C to 1200°C.
  • step A the path from the gate of the thyristor structure to the cathode K has the "switching" characteristics and low capacitance characteristics of a switching diode
  • step B the path from the anode A to the cathode K of the thyristor structure has a switch
  • concentrations of N-type heavily doped N+ and P-type heavily doped P+ are designed to form ohmic contact with metal, or the concentrations of N-well Nwell and P-well Pwell are designed to form ohmic contact with metal.
  • a low forward clamping voltage switching diode with a short-circuit structure of the thyristor gate and anode A is prepared.
  • the diode is an integrated switching diode, including a substrate material, an epitaxial layer, an N-well Nwell,
  • the semiconductor body composed of P-well Pwell, N-type heavily doped N+ and P-type heavily doped P+ can be constructed by appropriately designing the positions of N-well Nwell, P-well Pwell, N-type heavily doped N+ and P-type heavily doped P+.
  • the gate and anode A of the thyristor structure are short-circuited through a metal connection to form a switching diode.
  • the path from the gate to the cathode K of the thyristor structure has the "switching" characteristics and low capacitance characteristics of a switching diode, and can be used as a switching diode.
  • the path from the anode A to the cathode K of the thyristor structure has the "off" state characteristics and low capacitance characteristics of the switching diode.
  • the gate and anode A of the thyristor structure are short-circuited through a metal connection. Based on the compatibility of the switching diode, the current from the gate to the cathode K provides the trigger current for the switching diode from the anode A to the cathode K, and the trigger forms a positive feedback , The thyristor structure is turned on in advance, that is, the turn-on voltage of the thyristor structure is reduced. Since the current efficiency per unit area of the two paths is different, the current path from anode A to cathode K becomes the main current path.
  • the switching diode While the switching diode has excellent capacitance capability, its forward current capability is enhanced, dynamic resistance is reduced, and a low forward clamping voltage is obtained. When used in series and parallel with TVS diodes, a protection device with low capacitance and low forward clamping voltage is obtained.
  • the structure is fabricated in N-well Nwell and P-well Pwell.
  • concentration of N-well Nwell and P-well Pwell are designed in combination with different layout sizes and can be adjusted within a certain range to obtain suitable capacitance value, turn-on voltage and on-resistance;
  • FIG. 8 it is a schematic diagram of the cross-section and electrical connection of a switching diode with a short-circuit structure of the thyristor gate and the anode of multiple sets of interposing fingers:
  • a switching diode with multiple groups of interdigitated silicon controlled gate and anode short-circuit structure switching diodes which integrates the following structures on a silicon chip to form a semiconductor body, including:
  • the silicon substrate material can be any one of the four types of P epitaxial layer Pepi, P type substrate Psub, N epitaxial layer Nepi, and N type substrate Nsub.
  • the silicon controlled structure is fabricated on the P type substrate. Take Psub as an example, the resistivity of the substrate material is greater than or equal to 1 ⁇ cm.
  • the gate G and the anode A of the thyristor SCR are short-circuited through the metal connection line through the metal connection, as the PIN1 end of the switch tube, each The N-type heavily doped N+ in the P-type well Pwell is connected by metal and serves as the PIN2 terminal.
  • FIG. 9 is a cross-sectional schematic diagram of a thyristor gate and anode short-connected structure switching diode with gate G2 and Figure 10 can be used with gate G2.
  • the cross-section and electrical connection diagram of the switching diode of the short-circuit structure of the thyristor gate and anode are shown as follows:
  • the silicon substrate material can be any one of the four types of P epitaxial layer Pepi, P type substrate Psub, N epitaxial layer Nepi, and N type substrate Nsub.
  • the silicon controlled structure is fabricated on the P type substrate. Take Psub as an example, the resistivity of the substrate material is greater than or equal to 1 ⁇ cm.
  • the miscellaneous P+ area is anode A;
  • the P-type well Pwell the N-type heavily doped N+ and P-type heavily doped P+ regions in the P-type well Pwell, the N-type heavily doped N+ region is the cathode K of the thyristor switching diode, and the P-type heavily doped
  • the P+ area is a gate electrode G1, which constitutes the main silicon chip structure of the thyristor switch diode.
  • gates one and two G1 and G2 and anode A are short-circuited by metal as the PIN1 end of the switching diode; the cathode K leading end is the PIN1 end.
  • step C the current from the gate to the cathode K is used to provide the trigger current from the anode A to the cathode K, including the current from the first gate G1 to the cathode K to provide the trigger current from the anode A to the cathode K, and the second gate G2 is used. Participate in charge transport and accelerate the positive feedback of anode A to cathode K current.
  • a kind of multi-group insert finger double-gate thyristor gate and anode short-circuit structure switching diode as shown in Figure 11, the cross-section of the multi-group insert finger thyristor gate and anode short-circuit structure switch diode with gate G2 And electrical connection diagram as shown:
  • a multi-group interposing finger double-gate thyristor gate and anode short-circuit structure switching diode which integrates the following structure on a silicon chip to form a semiconductor body, including:
  • the silicon substrate material can be any one of the four types of P epitaxial layer Pepi, P type substrate Psub, N epitaxial layer Nepi, and N type substrate Nsub.
  • the silicon controlled structure is fabricated on the P type substrate. Take Psub as an example, the resistivity of the substrate material is greater than or equal to 1 ⁇ cm.
  • a second P-type well Pwell a first N-type heavily doped N+, a P-type heavily doped P+, and a second N-type heavily doped N+ region in the P-type well Pwell;
  • the third N-type well Nwell, and the internal structure of the N-type well Nwell is the same as that of the first and second N-type wells Nwell; wherein,
  • the lead-out end of the P-type heavily doped P+ region in each N-type well Nwell is anode A, and the lead-out end of the N-type heavily doped N+ region in each N-type well Nwell is the gate electrode Gi; the N-type in each P-type well Pwell The heavily doped N+ is the cathode K and the P-type heavily doped P+ is the gate G.
  • the multiple gate electrodes Gi and anode A of the thyristor SCR are short-circuited through the metal connection line through the metal connection, as the PIN1 end of the switch tube;
  • the N-type heavily doped N+ in each P-type well Pwell serves as the cathode of the diode and is connected by metal, and the lead-out terminal is the PIN2 terminal.
  • the concentration of N-type heavily doped N+ and P-type heavily doped P+ forming anode A, cathode K, and gate G can be adjusted within a certain range in combination with the design of different layout sizes to obtain suitable capacitance values and turn-on voltages.
  • N-type heavily doped N+ and P-type heavily doped P+ can form a good ohmic contact with metal; when to obtain a larger resistance, you can use N-type heavily doped N+ and P-type with appropriate doping concentration P+ is heavily doped, or the ohmic contact formed by the N-type well Nwell and the P-type well Pwell and the metal is used.

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Abstract

本发明提出了一种可控硅门极与阳极短接的低正向钳位电压开关二极管，包括由衬底材料或衬底材料外延层、N型阱、P型阱、N型重掺杂和P型重掺杂构成的半导体主体，通过适当设计N型阱、P型阱、N型掺杂和P型掺杂的尺寸和间距构成可控硅结构，通过金属连接将可控硅结构的门极和阳极短接形成开关二极管。利用门极到阴极的电流为阳极到阴极提供触发电流，形成正反馈，提前使可控硅结构开启，降低可控硅结构的开启电压，获得低正向钳位电压，本发明通过金属连接将控硅结构的门极和阳极短接形成开关二极管，获得低正向钳位电压。

Description

一种可控硅门极与阳极短接的低正向钳位电压开关二极管 技术领域
本发明属于半导体技术领域，特别涉及一种可控硅门极与阳极短接的低正向钳位电压开关二极管。
背景技术
随着工艺尺寸的缩小，片上集成电路的防护等级越来越弱，而电压和电流的瞬态干扰无时不在，随时会给设备带来致命损害，对瞬态电压抑制器(TVS)的需求和依赖随之增加。应用在数据接口电路中的TVS，电容是至关重要的参数，电容太大会衰减传输信号，因此低电容的保护器件需求日益紧迫。
开关二极管是半导体二极管的一种，是为在电路上进行“开”(正向导通)、“关”(反向截止)而特殊设计制造的一类二极管。开关二极管具有开关速度快、体积小、寿命长、可靠性高、低电容等特点，广泛应用于电子设备的开关电路、检波电路、高频和脉冲整流电路及自动控制电路中。其中，高频应用的一种形式是与TVS二极管搭配使用，通过使用开关二极管与TVS二极管的串并联，端口电容从TVS二极管的大电容降低至接近开关二极管的低电容，降低TVS产品的电容，从而可适应高速端口的应用。开关二极管可通过封装与TVS二极管集成，也可通过芯片工艺设计集成到同一个芯片上。
包括TVS二极管和开关二极管(D1和D2)的低电容TVS产品如附图1，TVS用于电位的控制，工作时处于击穿状态，通过调节击穿电压以适应不同的应用场景，一般击穿电压大于工作电压的1.2倍。与TVS串并联后，由于开关二极管的击穿电压为几十伏至上百伏，远高于TVS二极管，电荷泄放时无法从击穿方向泄放，而是通过正向导通方向至TVS二极管反向击穿的路径泄放掉，如附图1，开关二极管两端Pin2-Pin1施加正向电压时，电流通过D2正向和TVS击穿方向，泄放到Pin1(一般为GND)；开关二极管两端Pin2-Pin1施加负向电压时，电流通过D1正向泄放。虽然增加了电流路径，但是由于其优良的电容性能，被广泛应用。
普遍使用的低电容TVS中开关二极管D1电路图形符号和一般剖面结构示意图如图2所示。
TVS产品方面的参数与两类二极管的关系：
击穿电压——TVS二极管决定；
电容——开关二极管决定；
钳位电压、动态电阻——TVS二极管和开关二极管共同决定；
因此，通过缩小开关二极管的面积可以获得低电容，但瞬态电荷泄放能力也与开关二极管的面积成正比，在获得较低电容的同时，瞬态电荷泄放能力也会降低，且动态电阻增大。
为了降低开关二极管的电容，通常用高阻外延材料制作开关二极管，或将开关二极管制作在低浓度的阱里，将开关二极管的耗尽区增宽，达到降低电容的目的，同时带来的负面影响是开关二极管的正向开态动态电阻增大，影响了TVS器件的保护效果。
可控硅结构的电路图形符号和一般剖面结构示意图如图3所示。
因此，鉴于上述方案于实际制作及实施使用上的缺失之处，而加以修正、改良，同时本着求好的精神及理念，并由专业的知识、经验的辅助，以及在多方巧思、试验后，方创设出本发明。
发明内容
为克服现有技术缺陷，本发明目的在于：提供一种可控硅门极与阳极短接的低正向钳位电压开关二极管。
本发明的再一目的在于：提供一种利用可控硅结构获得低正向钳位电压的方法，以解决现有技术中的问题。
本发明提出了一种可控硅门极与阳极短接的低正向钳位电压开关二极管，包括由衬底材料或衬底材料外延层、N型阱、P型阱、N型重掺杂和P型重掺杂构成的半导体主体，通过设计N型阱、P型阱、N型掺杂和P型掺杂的尺寸和间距构成可控硅结构，其中，通过金属连接将可控硅结构的门极和阳极短接形成开关二极管。
本发明原理是：当开关二极管具有优良电容能力的同时，其正向导通电流能力得到增强，动态电阻得到降低，获得低正向钳位电压，在与TVS二极管串并联应用时，获得低电容和低正向钳位电压的保护器件。
优选地，所述可控硅包括两个门极，均与阳极短接。
优选地，所述衬底材料为P型衬底或N型衬底，衬底材料外延层为在衬底材料上形成的P外延层或在衬底材料上形成的N外延层，可控硅结构制作在P型衬底、N型衬底内、在衬底材料上形成的P外延内或在衬底材料上形成的N外延内。
优选地，所述P型衬底、N型衬底、在衬底材料上形成的P外延层及在衬底材料上形成的N外层，其电阻率均大于等于1Ω·cm。
优选地，通过N型重掺杂和P型重掺杂与金属形成欧姆接触。
优选地，通过N阱与P阱与金属形成欧姆接触。
本发明还提供一种利用可控硅结构获得低正向钳位电压的方法，包括如下步骤：
A：使可控硅结构的门极到阴极的路径具有开关二极管的“开关”特性和低电容特性；
B：使可控硅结构的阳极到阴极的路径具有开关二极管的“关”态特性和低电容特性并通过“开”态特性的开启电压范围；
C：利用门极到阴极的电流为阳极到阴极提供触发电流，形成正反馈，提前使可控硅结构开启，降低可控硅结构的开启电压，获得低正向钳位电压。
作为一种优选的实施方式，步骤C中利用门极到阴极的电流为阳极到阴极提供触发电流，包括第一门极到阴极的电流为阳极到阴极提供触发电流，还包括利用第二参与电荷输运，加速阳极到阴极电流的正反馈。
作为一种优选的实施方式，所述可控硅结构制作在结合浓度可在一定范围内调节的N阱和P阱内，其中，N阱和P阱间距、浓度及结深以能够调节阳极至阴极的电压和触发电流。
作为一种优选的实施方式，所述N阱和P阱形成结的注入剂量在1E13至1E15，推结温度1050℃至1200℃。
作为一种优选的实施方式，步骤A中使可控硅结构的门极到阴极的路径具有开关二极管的“开关”特性和低电容特性，和步骤B中使可控硅结构的阳极到阴极的路径具有开关二极管的“关”态特性和低电容特性并通过“开”态特性的开启电压范围，均包括采用调节结浓度搭配以及尺寸间距。
本发明开关二极管在具有优良电容能力的同时，其正向导通电流能力得到增强，动态电阻得到降低，获得低正向钳位电压。在与TVS二极管串并联应用时，获得低电容和低正向钳位电压的保护器件。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1普遍使用的低电容TVS电路结构图；
图2普遍使用的低电容TVS中D1电路图形符号和一般剖面结构示意图；
图3可控硅结构的电路图形符号和一般剖面结构示意图；
图4可控硅门极与阳极短接结构的电连接示意图和IV曲线图；
图5使用了可控硅门极与阳极短接结构的低正向钳位电压开关二极管的低电容TVS电路结构图；
图6可控硅门极与阳极短接结构开关二极管的剖面示意图；
图7可控硅门极与阳极短接结构开关二极管的剖面及电连接示意图；
图8多组插指的可控硅门极与阳极短接结构开关二极管的剖面及电连接示意图；
图9带门极G2的可控硅门极与阳极短接结构开关二极管的剖面示意图；
图10带门极G2的可控硅门极与阳极短接结构开关二极管的剖面及电连接示意图；
图11多组插指的带门极G2的可控硅门极与阳极短接结构开关二极管的剖面及电连接示意图。
图中标号说明：
Nsub——N型衬底；Psub——P型衬底；
Nepi——N外延层；Pepi——P外延层；
Nwell——N型阱；Pwell——P型阱；
P+——P型重掺杂；N+——N型重掺杂；
G——门极；
G1——第一门极；G2——第二门极；
A——阳极；K——阴极。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
实施例1
如图3和4所示，
通过金属连接将如图3所示可控硅SCR的门极G和阳极A短接形成开关二极管，本发明利用该可控硅结构获得低正向钳位电压的方法，包括如下步骤：
A：使可控硅结构的门极到阴极的路径具有开关二极管的“开关”特性和低电容特性；
B：使可控硅结构的阳极到阴极的路径具有开关二极管的“关”态特性和低电容特性并通过“开”态特性的开启电压范围；
C：利用门极到阴极的电流为阳极到阴极提供触发电流，形成正反馈，提前使可控硅结构开启，降低可控硅结构的开启电压，获得低正向钳位电压。
特性曲线如图4所示第一象限内，从阳极和门级短接点到阴极，结构内有两个电流通路，二极管正向导通通路和可控硅通路，二极管正向导通特性如Diode V F曲线所示，其具有较低的开启电压和较大的正向导通电阻，可控硅通路特性如SCR snapback曲线所示，其具有较高的开启电压和较小的导通电阻，两个路径并联时，通过优化工艺设计参数，如Nsub厚度和电阻率、Pwell浓度和扩散深度，使得在二极管正向导通后即可触发可控硅导通，形成如第一象限实线所示的特性曲线，获得低导通电阻；第四象限，从阴极到阳极和门级短路点有两个电流路径，从阴极到门级路径的二极管反向击穿路径和阴极到阳极的可控硅反向击穿路径，两个路径击穿电压都比较高，其中阴极到门级击穿电压略低，承担主要电流。
如图6可控硅门极与阳极短接结构开关二极管的剖面示意图和图7可控硅门极与阳极短接结构开关二极管的剖面及电连接示意图所示：
一种可控硅门极与阳极短接的低正向钳位电压开关二极管，在硅片上集成下述结构，构成了半导体主体，包括：
硅衬底材料，可以是P外延层Pepi、P型衬底Psub、N外延层Nepi、N型衬底Nsub四种中的任意一种，本实施例以可控硅结构制作在P型衬底Psub上为例，其衬底材料的电阻率均大于等于1Ω·cm。
在硅衬底材料上依序设置：
N型阱Nwell、N型阱Nwell内的P型重掺杂P+区；
P型阱Pwell、P型阱Pwell内的N型重掺杂N+和P型重掺杂P+区，其中，N型阱Nwell内的P型重掺杂P+区引出端为阳极A，P型阱Pwell内的N型重掺杂N+为阴极K和P型重掺杂P+为门极G，如图6所示；
通过金属连接将可控硅SCR的门极G和阳极A短接形成开关二极管,如图7所示。
如图5所示，将图7所示可控硅SCR的门极G和阳极A短接形成开关二极管应用于TVS电路中，连接在Pin1与Pin2之间，作为Pin1瞬态高电压到Pin2的泄放路径，该开关二极管如图5中标识SCR-D1。D2和TVS作为Pin2瞬态高电压到Pin1的泄放路径。
该开关二极管SCR-D1具有优良电容能力的同时，其正向导通电流能力得到增强，动态电阻得到降低，获得低正向钳位电压，在与TVS二极管串并联应用时，获得低电容和低正向钳位电压的保护器件。
通过可控硅结构制作再结合浓度可在一定范围内调节的N型阱Nwell和P型阱Pwell内，其中，N型阱Nwell和P型阱Pwell间距、浓度及结深以能够调节阳极A至阴极K的电压和触发电流。
N型阱Nwell和P型阱Pwell形成结的注入剂量在1E13至1E15，推结温度1050℃至1200℃。
其中，步骤A中使可控硅结构的门极到阴极K的路径具有开关二极管的“开关”特性和低电容特性，和步骤B中使可控硅结构的阳极A到阴极K的路径具有开关二极管的“关”态特性和低电容特性并通过“开”态特性的开启电压范围，均包括采用调节结浓度搭配以及尺寸间距。
N型重掺杂N+和P型重掺杂P+的浓度设计在能够与金属形成欧姆接触，或者N阱Nwell与P阱Pwell的浓度设计在能够与金属形成欧姆接触。
基于上述方法，制备成的利用可控硅门极与阳极A短接结构的低正向钳位电压开关二极管，该二极管为集成型开关二极管，包括由衬底材料、外延层、N阱Nwell、P阱Pwell、N型重掺杂N+和P型重掺杂P+构成的半导体主体，通过适当设计N阱Nwell、P阱Pwell、N型重掺杂N+和P型重掺杂P+的位置构成可控硅结构，通过金属连接将控硅结构的门极和阳极A短接形成开关二极管。通过适当的结浓度搭配和尺寸间距设计，可控硅结构的门极到阴极K的路径具有开关二极管的“开关”特性和低电容特性，可作为开关二极管。可控硅结构的阳极A到阴极K的路径具有开关二极管的“关”态特性和低电容特性，通过控制“开”态特性的开启电压范围，也可作为开关二极管。
通过金属连接将可控硅结构的门极和阳极A短接，在兼容了开关二极管的基础上，门极到阴极K的电流为阳极A到阴极K的开关二极管提供触发电流，触发形成正反馈，提前使可控硅结构开启，即降低了可控硅结构开启电压。由于两条路径的单位面积电流效率不同，阳极A到阴极K的电流路径变成了主要电流路径。
并联的两个开关二极管在具有优良电容能力的同时，其正向导通电流能力得到增强，动态电阻得到降低，获得低正向钳位电压。
开关二极管在具有优良电容能力的同时，其正向导通电流能力得到增强，动态电阻得到降低，获得低正向钳位电压。在与TVS二极管串并联应用时，获得低电容和低正向钳位电压的保护器件。
结构制作在N型阱Nwell和P阱Pwell内，N型阱Nwell和P型阱Pwell浓度结合不同版图尺寸设计，可以在一定范围内调节，以获得合适的电容值和开启电压及导通电阻；为获得良好特性，需要设计适当的结浓度，并搭配设计合适的 尺寸间距，包括，N型阱Nwell和P型阱Pwell间距、浓度及结深，可调节阳极A至阴极K的击穿电压和触发电流。
实施例2
如图8所示，为多组插指的可控硅门极与阳极短接结构开关二极管的剖面及电连接示意图：
一种多组插指的可控硅门极与阳极短接结构开关二极管，在硅片上集成下述结构，构成的半导体主体，包括：
硅衬底材料，可以是P外延层Pepi、P型衬底Psub、N外延层Nepi、N型衬底Nsub四种中的任意一种，本实施例以可控硅结构制作在P型衬底Psub上为例做说明，其衬底材料的电阻率均大于等于1Ω·cm。
在硅衬底材料上依序设置：
第一N型阱Nwell、该N型阱Nwell内的P型重掺杂P+区；
第一P型阱Pwell、该P型阱Pwell内的N型重掺杂N+、P型重掺杂P+和N型重掺杂N+区；
第二N型阱Nwell、该N型阱Nwell内的P型重掺杂P+区；
第二P型阱Pwell、该P型阱Pwell内的N型重掺杂N+、P型重掺杂P+和N型重掺杂N+区；
第三N型阱Nwell、该N型阱Nwell内的P型重掺杂P+区；其中，N型阱Nwell内的P型重掺杂P+区引出端为阳极A，P型阱Pwell内的N型重掺杂N+为阴极K和P型重掺杂P+为门极G，通过金属连接将可控硅SCR的门极G和阳极A经金属连接线短接，作为开关管的PIN1端，各P型阱Pwell内的N型重掺杂N+经金属连接，作为PIN2端。
实施例3
为双门极的可控硅门极与阳极短接结构开关二极管，如图9带门极G2的可控硅门极与阳极短接结构开关二极管的剖面示意图和图10带门极G2的可控硅门极与阳极短接结构开关二极管的剖面及电连接示意图所示：
一种双门极的可控硅门极与阳极短接结构开关二极管，在硅片上集成下述结构，构成的半导体主体，包括：
硅衬底材料，可以是P外延层Pepi、P型衬底Psub、N外延层Nepi、N型衬底Nsub四种中的任意一种，本实施例以可控硅结构制作在P型衬底Psub上为例做说明，其衬底材料的电阻率均大于等于1Ω·cm。
在硅衬底材料上依序设置：
N型阱Nwell、该N型阱Nwell内的N型重掺杂N+和P型重掺杂P+区，该N型重掺杂N+为可控硅开关二极管的门极二G2，P型重掺杂P+区为阳极A；
P型阱Pwell、该P型阱Pwell内的N型重掺杂N+和P型重掺杂P+区，该N型重掺杂N+区为可控硅开关二极管的阴极K，P型重掺杂P+区为门极一G1，构成可控硅开关二极管的主体硅片结构。
如图10所示，门极一、二G1、G2和阳极A经金属短接，作为该开关二极管的PIN1端；阴极K引出端为PIN1端。
与实施例1步骤不同的是：
步骤C中利用门极到阴极K的电流为阳极A到阴极K提供触发电流，包括第一门极G1到阴极K的电流为阳极A到阴极K提供触发电流，还包括利用第二门极G2参与电荷输运，加速阳极A到阴极K电流的正反馈。
实施例4
一种多组插指的双门极可控硅门极与阳极短接结构开关二极管，如图11多组插指的带门极G2的可控硅门极与阳极短接结构开关二极管的剖面及电连接示意图所示：
一种多组插指的双门极可控硅门极与阳极短接结构开关二极管，在硅片上集成下述结构，构成的半导体主体，包括：
硅衬底材料，可以是P外延层Pepi、P型衬底Psub、N外延层Nepi、N型衬底Nsub四种中的任意一种，本实施例以可控硅结构制作在P型衬底Psub上为例做说明，其衬底材料的电阻率均大于等于1Ω·cm。
在硅衬底材料上依序设置：
第一N型阱Nwell、该N型阱Nwell内的第一P型重掺杂P+区、N型重掺杂N+、第二P型重掺杂P+区；
第一P型阱Pwell、该P型阱Pwell内的第一N型重掺杂N+、P型重掺杂P+和第二N型重掺杂N+区；
第二N型阱Nwell、该N型阱Nwell内的第一P型重掺杂P+区、N型重掺杂N+、第二P型重掺杂P+区；
第二P型阱Pwell、该P型阱Pwell内的第一N型重掺杂N+、P型重掺杂P+和第二N型重掺杂N+区；
第三N型阱Nwell、该N型阱Nwell内结构与第一和第二N型阱Nwell相同；其中，
各N型阱Nwell内的P型重掺杂P+区引出端为阳极A，各N型阱Nwell内的N型重掺杂N+区引出端为门极Gi；各P型阱Pwell内的N型重掺杂N+为阴极K 和P型重掺杂P+为门极G，通过金属连接将可控硅SCR的多个门极Gi和阳极A经金属连接线短接，作为开关管的PIN1端；各P型阱Pwell内的N型重掺杂N+作为二极管的阴极经金属连接，引出端为PIN2端。
形成阳极A、阴极K、门极G的N型重掺杂N+和P型重掺杂P+的浓度，结合不同版图尺寸设计，可以在一定范围内调节，以获得合适的电容值和开启电压及导通电阻；N型重掺杂N+和P型重掺杂P+可以与金属形成良好的欧姆接触；当为获得较大电阻时，可以使用适当掺杂浓度的N型重掺杂N+和P型重掺杂P+，或使用N型阱Nwell和P型阱Pwell与金属形成的欧姆接触。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (14)

  1. 一种可控硅门极与阳极短接的低正向钳位电压开关二极管，包括由衬底材料或衬底材料外延层、N型阱、P型阱、N型重掺杂和P型重掺杂构成的半导体主体，通过设计N型阱、P型阱、N型掺杂和P型掺杂的尺寸和间距构成可控硅结构，其特征在于，通过金属连接将可控硅结构的门极和阳极短接形成开关二极管。
  2. 根据权利要求1所述的可控硅门极与阳极短接的低正向钳位电压开关二极管，其特征在于，所述可控硅包括两个门极，均与阳极短接。
  3. 根据权利要求1或2所述的可控硅门极与阳极短接的低正向钳位电压开关二极管，其特征在于，所述衬底材料为P型衬底或N型衬底，衬底材料外延层为在衬底材料上形成的P外延层或在衬底材料上形成的N外延层，可控硅结构制作在P型衬底、N型衬底内、在衬底材料上形成的P外延内或在衬底材料上形成的N外延内。
  4. 根据权利要求3所述的可控硅门极与阳极短接的低正向钳位电压开关二极管，其特征在于，所述P型衬底、N型衬底、在衬底材料上形成的P外延层及在衬底材料上形成的N外层，其电阻率均大于等于1Ω·cm。
  5. 根据权利要求3所述的可控硅门极与阳极短接的低正向钳位电压开关二极管，其特征在于，通过N型重掺杂和P型重掺杂与金属形成欧姆接触。
  6. 根据权利要求3所述的可控硅门极与阳极短接的低正向钳位电压开关二极管，其特征在于，通过N阱与P阱与金属形成欧姆接触。
  7. 根据权利要求3所述的可控硅门极与阳极短接的低正向钳位电压开关二极管，其特征在于，所述N型阱和P型阱形成结的注入剂量在1E13至1E15，推结温度1050℃至1200℃。
  8. 根据权利要求1所述的可控硅门极与阳极短接的低正向钳位电压开关二极管，其特征在于，与TVS管串并联构成保护电路，获得低电容和低正向钳位电压的保护器件，从阳极和门级短接点到阴极，结构内有两个电流通路，二极管正向导通通路和可控硅通路，其中，所述的二极管正向导通具有较低的开启电压和较大的正向导通电阻，可控硅通路具有较高的开启电压和较小的导通电阻，两个路径并联时，通过工艺参数设计，使得在二极管正向导通后即可触发可控硅导通，获得低导通电阻；从阴极到阳极和门级短路点有两个电流路径，从阴极到门级路径的二极管反向击穿路径和阴极到阳极的可控硅反向击穿路径，两个路径击穿电压都比较高，其中阴极到门级击穿电压略低，承担主要电流。
  9. 一种利用根据权利要求1至8任一项所述的二极管获得低正向钳位电压的 方法，其特征在于，包括如下步骤：
    A：使可控硅结构的门极到阴极的路径具有开关二极管的“开关”特性和低电容特性；
    B：使可控硅结构的阳极到阴极的路径具有开关二极管的“关”态特性和低电容特性并通过“开”态特性的开启电压范围；
    C：利用门极到阴极的电流为阳极到阴极提供触发电流，形成正反馈，提前使可控硅结构开启，降低可控硅结构的开启电压，获得低正向钳位电压。
  10. 一种利用根据权利要求2至8任一项所述的二极管获得低正向钳位电压的方法，其特征在于，包括如下步骤：
    A：使可控硅结构的门极到阴极的路径具有开关二极管的“开关”特性和低电容特性；
    B：使可控硅结构的阳极到阴极的路径具有开关二极管的“关”态特性和低电容特性并通过“开”态特性的开启电压范围；
    C：步骤C中利用门极到阴极K的电流为阳极A到阴极K提供触发电流，包括第一门极G1到阴极K的电流为阳极A到阴极K提供触发电流，还包括利用第二门极G2参与电荷输运，加速阳极A到阴极K电流的正反馈。
  11. 根据权利要求1、3至8任一项所述的二极管的所述的二极管的制备，其特征在于，可控硅结构制作在P型衬底上，其衬底材料的电阻率均大于等于1Ω·cm，包括下述步骤：
    在P型衬底上依序设置：
    N型阱Nwell、N型阱Nwell内的P型重掺杂P+区；
    P型阱Pwell、P型阱Pwell内的N型重掺杂N+和P型重掺杂P+区，其中，N型阱Nwell内的P型重掺杂P+区引出端为阳极A，P型阱Pwell内的N型重掺杂N+为阴极K和P型重掺杂P+为门极G；
    通过金属连接将可控硅SCR的门极G和阳极A短接形成开关二极管；
    该开关二极管应用于TVS电路中，连接在Pin1与Pin2之间，作为Pin1瞬态高电压到Pin2的泄放路径，二极管D2和TVS作为Pin2瞬态高电压到Pin1的泄放路径；
    该开关二极管与TVS二极管串并联应用时，获得低电容和低正向钳位电压的保护器件。
  12. 根据权利要求1、3至8任一项所述的二极管的所述的二极管的制备，其特征在于，在硅片上集成下述结构，构成的半导体主体，构成一种多组插指的可控硅门极与阳极短接结构开关二极管，包括下述制备步骤：
    可控硅结构制作在P型衬底上，其硅衬底材料的电阻率均大于等于1Ω·cm，在硅衬底材料上依序设置：
    第一N型阱Nwell、该N型阱Nwell内的P型重掺杂P+区；
    第一P型阱Pwell、该P型阱Pwell内的N型重掺杂N+、P型重掺杂P+和N型重掺杂N+区；
    第二N型阱Nwell、该N型阱Nwell内的P型重掺杂P+区；
    第二P型阱Pwell、该P型阱Pwell内的N型重掺杂N+、P型重掺杂P+和N型重掺杂N+区；
    第三N型阱Nwell、该N型阱Nwell内的P型重掺杂P+区；其中，
    N型阱Nwell内的P型重掺杂P+区引出端为阳极A，P型阱Pwell内的N型重掺杂N+为阴极K和P型重掺杂P+为门极G，通过金属连接将可控硅结构的门极G和阳极A经金属连接线短接形成所述的二极管；
    将该开关二极管应用于TVS电路中，将该可控硅SCR的门极G和阳极A经金属连接线短接作为开关管的PIN1端，各P型阱Pwell内的N型重掺杂N+经金属连接，作为PIN2端。
  13. 根据权利要求2至8任一项所述的二极管的所述的二极管的制备，其特征在于，在硅片上集成下述结构，构成半导体主体，制备成双门极的可控硅门极与阳极短接结构开关二极管，包括下述步骤：
    可控硅结构制作在P型衬底Psub上，其衬底材料的电阻率均大于等于1Ω·cm，在硅衬底材料上依序设置：
    N型阱Nwell、该N型阱Nwell内的N型重掺杂N+和P型重掺杂P+区，该N型重掺杂N+为可控硅开关二极管的门极二G2，P型重掺杂P+区为阳极A；
    P型阱Pwell、该P型阱Pwell内的N型重掺杂N+和P型重掺杂P+区，该N型重掺杂N+区为可控硅开关二极管的阴极K，P型重掺杂P+区为门极一G1，构成可控硅开关二极管的主体硅片结构；
    该开关二极管应用于TVS电路中，门极一、二G1、G2和阳极A经金属短接，作为该开关二极管的PIN1端；阴极K引出端为PIN1端。
  14. 根据权利要求2至8任一项所述的二极管的所述的二极管的制备，其特征在于，在硅片上集成下述结构，构成的半导体主体，制备一种多组插指的双门极可控硅门极与阳极短接结构开关二极管，包括下述步骤：
    可控硅结构制作在P型衬底Psub上，其衬底材料的电阻率均大于等于1Ω·cm，在硅衬底材料上依序设置：
    第一N型阱Nwell、该N型阱Nwell内的第一P型重掺杂P+区、N型重掺杂 N+、第二P型重掺杂P+区；
    第一P型阱Pwell、该P型阱Pwell内的第一N型重掺杂N+、P型重掺杂P+和第二N型重掺杂N+区；
    第二N型阱Nwell、该N型阱Nwell内的第一P型重掺杂P+区、N型重掺杂N+、第二P型重掺杂P+区；
    第二P型阱Pwell、该P型阱Pwell内的第一N型重掺杂N+、P型重掺杂P+和第二N型重掺杂N+区；
    第三N型阱Nwell、该N型阱Nwell内结构与第一和第二N型阱Nwell相同；其中，
    各N型阱Nwell内的P型重掺杂P+区引出端为阳极A，各N型阱Nwell内的N型重掺杂N+区引出端为门极Gi；各P型阱Pwell内的N型重掺杂N+为阴极K和P型重掺杂P+为门极G，通过金属连接将可控硅SCR的多个门极Gi和阳极A经金属连接线短接，作为开关管的PIN1端；各P型阱Pwell内的N型重掺杂N+作为二极管的阴极经金属连接，引出端为PIN2端。
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