WO2021063048A1 - 微发光二极管芯片及显示面板 - Google Patents

微发光二极管芯片及显示面板 Download PDF

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Publication number
WO2021063048A1
WO2021063048A1 PCT/CN2020/098626 CN2020098626W WO2021063048A1 WO 2021063048 A1 WO2021063048 A1 WO 2021063048A1 CN 2020098626 W CN2020098626 W CN 2020098626W WO 2021063048 A1 WO2021063048 A1 WO 2021063048A1
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layer
semiconductor layer
type semiconductor
light emitting
emitting diode
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PCT/CN2020/098626
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English (en)
French (fr)
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郭恩卿
王程功
盖翠丽
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成都辰显光电有限公司
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Priority to KR1020227005750A priority Critical patent/KR20220031127A/ko
Publication of WO2021063048A1 publication Critical patent/WO2021063048A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/405—Reflective materials

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a micro light emitting diode chip and a display panel.
  • a micro light-emitting diode ( ⁇ LED) display panel is a display panel that integrates micro light-emitting diode chips with a size below one hundred microns on a substrate as display pixels to achieve image display. Each pixel can be individually displayed. Driven to light up, the micro-LED display panel is a self-luminous display panel.
  • the existing micro light emitting diode chip Due to the large sidewall area of the existing micro light emitting diode chip, there is a problem of optical crosstalk caused by light emitted from the sidewall, and the problem of optical crosstalk may lead to poor display effects of the display panel. Therefore, the existing micro light emitting diode chip has the problem of poor display effect caused by light crosstalk.
  • the embodiments of the present disclosure provide a micro-light-emitting diode chip and a display panel to solve the problem of poor display effect of the existing micro-light-emitting diode.
  • a micro light emitting diode chip including a first type semiconductor layer; a light emitting layer; a second type semiconductor layer; a first type electrode layer, the first type electrode layer is located in the first type On the sidewall on one side of the semiconductor layer and in ohmic contact with the first type semiconductor layer; a second type electrode layer; and an insulating passivation layer, the insulating passivation layer covering part of the sidewall of the first type semiconductor layer , The sidewall and bottom surface of the first type electrode layer, the sidewall of the light-emitting layer, the sidewall and part of the bottom surface of the second type semiconductor layer, the second type electrode layer covers the insulating passivation layer A part of the bottom surface of the second type semiconductor layer exposed from the insulating passivation layer is in ohmic contact with the second type electrode layer, wherein the first type semiconductor layer, the light emitting layer, and the second type The semiconductor layers are stacked in sequence.
  • the micro light emitting diode chip provided by the embodiments of the present disclosure has the following advantages:
  • the micro light emitting diode chip provided by the embodiment of the present disclosure covers the first type electrode layer on the sidewall of the first type semiconductor layer and the second type electrode layer on the insulating passivation layer, thereby making the first type electrode layer Together with the second type electrode layer, it covers all the sidewalls of the micro light emitting diode chip, reducing or avoiding the possibility of light from the sidewalls, thereby avoiding the problem of light crosstalk; at the same time, the first type electrode layer and the second type electrode layer The light-emitting surface is not blocked, and the display effect of the micro light-emitting diode chip is improved; further, the first type electrode layer and the second type electrode layer have reflective properties, so that the light directed to the sidewall can be reflected, which can further reduce or avoid In addition, the top surfaces of the first type electrode layer and the second type electrode layer are exposed in the same direction, which facilitates alignment and connection with the driving substrate during batch transfer, which solves the problem of high transfer difficulty.
  • an embodiment of the present disclosure also provides a display panel including the above-mentioned micro light emitting diode chip.
  • the display panel provided by the embodiments of the present disclosure includes the above-mentioned micro-light-emitting diode chip, and therefore also has the same advantages as those of the above-mentioned micro-light-emitting diode chip, which will not be repeated here.
  • FIG. 1 is a first structural diagram of a micro light-emitting diode chip provided in the first embodiment of the present disclosure
  • Figure 2 is a top view of Figure 1;
  • FIG. 3 is a second structural diagram of the micro light emitting diode chip provided in the first embodiment of the disclosure.
  • the micro light emitting diode chip provided in the first embodiment of the present disclosure includes a first type semiconductor layer 10, a light emitting layer 30, a second type semiconductor layer 20, a first type electrode layer 40, and a second type electrode layer 50 and an insulating passivation layer 60, wherein the first type semiconductor layer 10, the light emitting layer 30, and the second type semiconductor layer 20 are stacked in sequence; the first type electrode layer 40 is located on the sidewall of the first type semiconductor layer 10 And is in ohmic contact with the first type semiconductor layer 10; the insulating passivation layer 60 covers part of the sidewalls of the first type semiconductor layer 10, the sidewalls and bottom surfaces of the first type electrode layer 40, the sidewalls of the light emitting layer 30, and the second type The sidewalls and part of the bottom surface of the semiconductor layer 20; the second type electrode layer 50 covers the insulating passivation layer 60, and a part of the bottom surface of the second type semiconductor layer 20 exposed from the insulating passivation layer 60 is in ohmic contact with the second type
  • the first type semiconductor layer 10, the light emitting layer 30, and the second type semiconductor layer 20 are stacked from top to bottom.
  • the light emitting layer 30 is formed on the bottom surface of the first type semiconductor layer 10
  • the second type semiconductor layer 20 is formed on the bottom surface of the light emitting layer 30.
  • the first type electrode layer 40 is formed on the sidewall of the first type semiconductor layer 10, and the first type electrode layer 40 forms an ohmic contact with the first type semiconductor layer 10.
  • a step surface 11 may be provided on the sidewall of the first type semiconductor layer 10. As shown in FIG. 3, when the first type electrode layer 40 is formed on the first type semiconductor layer 10, it covers the step surface 11, thereby increasing The coverage area is enlarged, and the performance of the ohmic contact is further improved. At the same time, the arrangement of the step surface 11 facilitates the formation of the second type electrode layer 50 and reduces the processing difficulty of the second type electrode layer 50.
  • an insulating passivation layer 60 covers the first type electrode layer 40, the first type semiconductor layer 10, the light emitting layer 30, and the second type semiconductor layer 20.
  • the second type electrode layer 50 is formed on the insulating passivation layer 60.
  • the insulating passivation layer 60 in this embodiment has high transparency to visible light, and the insulating passivation layer 60 can be specifically set as a transparent glue layer.
  • the second type electrode layer 50 is formed on the bottom surface and sidewalls of the insulating passivation layer 60, and a part of the bottom surface of the second type semiconductor layer 20 is exposed from the insulating passivation layer 60.
  • the second-type electrode layer 50 is connected to the above exposed part to form an ohmic contact.
  • the second type electrode layer 50 may be provided with an extension in the horizontal direction for supporting the insulating passivation layer 60, the first type electrode layer 40, the first type semiconductor layer 10, the light emitting layer 30, and the second type semiconductor layer.
  • the sidewall of the second type electrode layer 50 may be perpendicular to the horizontal direction, and the sidewall of the second type electrode layer 50 is flush with the outermost end of the first type electrode layer 40 in the horizontal direction.
  • the first type electrode layer 40 is covered on the sidewall of the first type semiconductor layer 10
  • the second type electrode layer 50 is covered on the insulating passivation layer.
  • the first type electrode layer 40 and the second type electrode layer 50 jointly cover all the sidewalls of the micro light emitting diode chip, which reduces or avoids the possibility of light emission from the sidewalls, thereby avoiding the problem of light crosstalk.
  • the first type electrode layer 40 and the second type electrode layer 50 do not block the light-emitting surface, which improves the display effect of the micro light emitting diode chip; in the micro light emitting diode chip provided in the first embodiment, the first type electrode layer 40 and The top surface of the second type electrode layer 50 is exposed in the same direction, which facilitates alignment and connection with the driving substrate during batch transfer, which solves the problem of high transfer difficulty.
  • the cross-sectional shape of the first-type semiconductor layer 10, the light-emitting layer 30, and the second-type semiconductor layer 20 is an inverted trapezoid with a plane perpendicular to the light-emitting surface as a cross-section.
  • the cross-sections of the first type semiconductor layer 10, the light-emitting layer 30, and the second type semiconductor layer 20 refer to the cross-section of the laminated structure composed of the first type semiconductor layer 10, the light-emitting layer 30, and the second type semiconductor layer 20. In this embodiment, as shown in FIG.
  • the surface (top surface) of the first type semiconductor layer 10 away from the light emitting layer 30 is the light-emitting surface, and a plane perpendicular to the top surface of the first type semiconductor layer 10 is taken as the cross section.
  • the cross-sectional shape of the laminated structure composed of the first type semiconductor layer 10, the light-emitting layer 30, and the second type semiconductor layer 20 is an inverted trapezoid.
  • the length of the bottom side of the inverted trapezoid on the side of the light-emitting surface is greater than that far away from the light-emitting surface.
  • the length of the bottom side and the inverted trapezoidal structure are convenient for the manufacture of micro light emitting diode chips.
  • the first type electrode layer 40 and the second type electrode layer 50 are metal electrode layers.
  • the first type electrode layer 40 and the second type electrode layer 50 cover the micro
  • the first type electrode layer 40 and the second type electrode layer 50 are set as metal electrode layers, which can be specifically silver, aluminum, etc.
  • the reflectivity of the metal is relatively high, which further increases
  • the reflectivity of the first type electrode layer 40 and the second type electrode layer 50 enables the light directed to the sidewalls to be reflected, which can further reduce or avoid light from the sidewalls.
  • the range of the bottom angle of the inverted trapezoid is 50° to 85°.
  • the bottom angle of the inverted trapezoid can take any value in the range of 50° to 85°.
  • the laminated structure of the first type semiconductor layer 10, the light emitting layer 30, and the second type semiconductor layer 20 The cross-sectional shape of the isosceles trapezoid, and the bottom angle of the isosceles trapezoid can be set to 60°, which is convenient for the manufacture of the micro light emitting diode chip.
  • the shape of the first type semiconductor layer 10, the light emitting layer 30, and the second type semiconductor layer 20 is a truncated truncated cone or a truncated pyramid. It should be noted that the shapes of the first type semiconductor layer 10, the light emitting layer 30, and the second type semiconductor layer 20 refer to the shape of the laminated structure composed of the first type semiconductor layer 10, the light emitting layer 30, and the second type semiconductor layer 20 As shown in FIG. 2, the laminated structure formed by the first type semiconductor layer 10, the light emitting layer 30, and the second type semiconductor layer 20 may be a pyramid frustum, specifically a quadrangular frustum.
  • the first type electrode layer 40 extends horizontally to the side away from the first type semiconductor layer 10 to form the first extension 41; the second type electrode layer 50 is moving away from the first type electrode layer.
  • the other side of 40 extends horizontally to form a second extension 51.
  • the first type electrode layer 40 covers one side of the sidewall of the first type semiconductor layer 10, and the first type electrode layer 40 faces outwards away from the first type semiconductor layer 10.
  • the top surface of the first extension 41 is a flat surface. Specifically, when the first extension 41 is formed, it can be thickened by an electroplating process, and a chemical mechanical polishing process can be used to The first extension 41 is flattened.
  • the top surface of the first protrusion 41 may be flush with the top surface of the first type semiconductor layer 10 or may be higher than the top surface of the first type semiconductor layer 10.
  • the arrangement of the first protrusion 41 not only facilitates the subsequent formation of the insulating passivation layer 60 and the second type electrode layer 50, but also facilitates the alignment and connection with the driving substrate during the subsequent batch transfer.
  • the insulating passivation layer 60 covers the first type electrode layer 40
  • the second type electrode layer 50 covers the insulating passivation layer 60, taking the orientation shown in FIG. 1 as
  • the second type electrode layer 50 covers the insulating passivation layer 60 and extends to both sides.
  • the second type electrode layer 50 extends horizontally to form a second protrusion Portion 51, and the top surface of the second extension portion 51 is a flat surface.
  • thickening may be performed through an electroplating process, and the second extension 51 may be planarized through a chemical mechanical polishing process.
  • the top surface of the second protrusion 51 may be flush with the top surface of the first type semiconductor layer 10 or may be higher than the top surface of the first type semiconductor layer 10.
  • the arrangement of the second protrusion 51 facilitates alignment and connection with the driving substrate during subsequent batch transfer.
  • the top surface of the first extension 41 is flush with the top surface of the second extension 51 in the horizontal direction.
  • the first type electrode layer 40 forms a first extension 41
  • the second type electrode layer 50 forms a second extension 51.
  • the top surface of the first extension 41 and The top surface of the second extension 51 is flush, that is, the exposed part of the first type electrode layer 40 is flush with the exposed part of the second type electrode layer 50. This arrangement further improves the alignment when connecting with the driving substrate. Accuracy.
  • the top surface of the first protrusion 41 is flush with the top surface of the first type semiconductor layer 10 in the horizontal direction.
  • the top surface of the first extension 41 is flush with the top surface of the second extension 51.
  • the top surface of the first extension 41 and the second extension are arranged flush with each other to facilitate the fabrication of the micro light emitting diode chip.
  • the top surface of the first protrusion 41 is higher than the top surface of the first type semiconductor layer 10 in the horizontal direction.
  • the top surface of the first extension 41 is flush with the top surface of the second extension 51.
  • the top surface of the first extension 41 and the second extension The arrangement of the top surface of 51 slightly higher than the top surface of the first type semiconductor layer 10 further ensures that light can be reflected and avoids the problem of optical crosstalk.
  • the top surface of the first type semiconductor layer 10 is configured as a rough surface.
  • the top surface of the first type semiconductor layer 10 is set as a rough surface.
  • the reflection cone The light outside the cone’s central axis is parallel to the interface normal
  • the rough surface can provide more With the oriented reflection cone, light in certain directions that could not escape can also escape the LED chip, so the rough surface is conducive to the light extraction of the micro light-emitting diode chip.
  • the display panel provided in the second embodiment of the present disclosure includes the micro-light-emitting diode chip provided in the first embodiment.
  • the micro-light-emitting diode chip provided in the first embodiment.
  • the display panel provided in this embodiment can be applied to any display device with a display function including a micro light emitting diode chip, such as a mobile phone, a tablet computer, a smart watch, an e-book, a navigator, a TV, a digital camera, and the like.
  • a micro light emitting diode chip such as a mobile phone, a tablet computer, a smart watch, an e-book, a navigator, a TV, a digital camera, and the like.
  • the display panel provided in this embodiment also has the same advantages as the micro light-emitting diode chip provided in the first embodiment, which will not be repeated here.

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Abstract

本公开提供一种微发光二极管芯片及显示面板，其中，本公开提供的微发光二极管芯片包括第一类型半导体层、发光层、第二类型半导体层、第一类型电极层、第二类型电极层和绝缘钝化层，第一类型半导体层、发光层、第二类型半导体层依次层叠设置；第一类型电极层位于第一类型半导体层一侧的侧壁上并与第一类型半导体层欧姆接触；绝缘钝化层覆盖第一类型半导体层的部分侧壁、第一类型电极层的侧壁和底面、发光层的侧壁、第二类型半导体层的侧壁和部分底面；第二类型电极层覆盖绝缘钝化层，第二类型电极层从绝缘钝化层露出的部分底面与第二类型电极层欧姆接触。

Description

微发光二极管芯片及显示面板 技术领域
本公开涉及显示技术领域，尤其涉及一种微发光二极管芯片及显示面板。
背景技术
微发光二极管(micro light-emitting diode,μLED)显示面板是一种以在一个基板上集成尺寸在百微米级别以下的微发光二极管芯片作为显示像素实现图像显示的显示面板，其中每一个像素可单独驱动点亮，微发光二极管显示面板是一种自发光显示面板。
由于现有的微发光二极管芯片的侧壁面积较大，存在侧壁出光造成的光串扰问题，光串扰问题会导致显示面板的显示效果较差。因此现有的微发光二极管芯片存在光串扰导致的显示效果差的问题。
发明内容
本公开实施例提供一种微发光二极管芯片及显示面板，用以解决现有的微发光二极管显示效果差的问题。
为了实现上述目的，本公开实施例提供如下技术方案：
一方面，本公开实施例提供一种微发光二极管芯片，包括第一类型半导体层；发光层；第二类型半导体层；第一类型电极层，所述第一类型电极层位于所述第一类型半导体层一侧的侧壁上并与所述第一类型半导体层欧姆接触；第二类型电极层；和绝缘钝化层，所述绝缘钝化层覆盖所述第一类型半导体层的部分侧壁、所述第一类型电极层的侧壁和底面、所述发光层的侧壁、所述第二类型半导体层的侧壁和部分底面，所述第二类型电极层覆盖所述绝缘钝化层，所述第二类型半导体层从所述绝缘钝化层露出的部分底面与所述 第二类型电极层欧姆接触，其中，所述第一类型半导体层、所述发光层、所述第二类型半导体层依次层叠设置。
与相关技术相比，本公开的实施例提供的微发光二极管芯片具有如下优点：
本公开实施例提供的微发光二极管芯片通过将第一类型电极层覆盖在第一类型半导体层的侧壁上，将第二类型电极层覆盖在绝缘钝化层上，从而使第一类型电极层和第二类型电极层共同覆盖了微发光二极管芯片的全部侧壁，降低或避免了侧壁出光的可能性，进而避免了光串扰的问题；同时，第一类型电极层和第二类型电极层不遮挡出光面，提高了微发光二极管芯片的显示效果；进一步地，第一类型电极层和第二类型电极层具有反射性能，使得射向侧壁的光线能够被反射，可以进一步地降低或避免了侧壁出光的可能性；此外，第一类型电极层与第二类型电极层的顶面露出在同一方向上，便于批量转移时与驱动基板对准和连接，解决了转移难度大的问题。
另一方面，本公开实施例还提供了一种显示面板，包括上述微发光二极管芯片。
本公开实施例提供的显示面板包括上述微发光二极管芯片，因此也具有与上述微发光二极管芯片的优点相同的优点，在此不再赘述。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对本公开实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一部分实施例。
图1为本公开实施例一提供的微发光二极管芯片的结构示意图一；
图2为图1的俯视图；
图3为本公开实施例一提供的微发光二极管芯片的结构示意图二。
具体实施方式
为了使本公开实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。
实施例一
请参阅图1-图3，本公开实施例一提供的微发光二极管芯片包括第一类型半导体层10、发光层30、第二类型半导体层20、第一类型电极层40、第二类型电极层50和绝缘钝化层60，其中，第一类型半导体层10、发光层30、第二类型半导体层20依次层叠设置；第一类型电极层40位于第一类型半导体层10一侧的侧壁上并与第一类型半导体层10欧姆接触；绝缘钝化层60覆盖第一类型半导体层10的部分侧壁、第一类型电极层40的侧壁和底面、发光层30的侧壁、第二类型半导体层20的侧壁和部分底面；第二类型电极层50覆盖绝缘钝化层60，第二类型半导体层20从绝缘钝化层60露出的部分底面与第二类型电极层50欧姆接触。
在本实施例中，如图1所示，第一类型半导体层10、发光层30、第二类型半导体层20自上而下层叠设置，需要说明的是，第一类型半导体层10的顶面为出光面，具体地，发光层30形成在第一类型半导体层10的底面，第二类型半导体层20形成在发光层30的底面。第一类型电极层40形成在第一类型半导体层10的侧壁上，且第一类型电极层40与第一类型半导体层10形成欧姆接触。
进一步地，第一类型半导体层10的侧壁上可以设置台阶面11，如图3所示，第一类型电极层40形成在第一类型半导体层10上时，覆盖上述台阶面11，从而增大了覆盖面积，进一步提高了欧姆接触的性能，同时台阶面11的设置便于第二类型电极层50的形成，降低了第二类型电极层50的加工难度。
在上述实施方式的基础上，如图1所示，绝缘钝化层60覆盖第一类型电 极层40、第一类型半导体层10、发光层30以及第二类型半导体层20，第二类型电极层50形成在绝缘钝化层60上，本实施例中的绝缘钝化层60对可见光具有较高的透明度，绝缘钝化层60具体可以设置为透明胶层。以图1所示的方位为例进行描述，第二类型电极层50形成在绝缘钝化层60的底面和侧壁上，第二类型半导体层20的部分底面从绝缘钝化层60露出，第二类型电极层50与上述露出部分连接，形成欧姆接触。
具体地，第二类型电极层50在水平方向上可以设置有延伸部，用于支撑绝缘钝化层60、第一类型电极层40、第一类型半导体层10、发光层30、第二类型半导体层20的侧壁部分，以降低加工难度。优选地，第二类型电极层50的侧壁可以与水平方向垂直，第二类型电极层50的侧壁在水平方向上与第一类型电极层40的最外端平齐。
综上所述，本公开实施例一提供的微发光二极管芯片中，通过将第一类型电极层40覆盖在第一类型半导体层10的侧壁上，将第二类型电极层50覆盖在绝缘钝化层60上，从而使第一类型电极层40和第二类型电极层50共同覆盖了微发光二极管芯片的全部侧壁，降低或避免了侧壁出光的可能性，进而避免了光串扰的问题；同时，第一类型电极层40和第二类型电极层50不遮挡出光面，提高了微发光二极管芯片的显示效果；本实施例一提供的微发光二极管芯片中，第一类型电极层40与第二类型电极层50的顶面露出在同一方向上，便于批量转移时与驱动基板对准和连接，解决了转移难度大的问题。
进一步地，在一种可能的实现方式中，以垂直于出光面的平面为截面，第一类型半导体层10、发光层30、第二类型半导体层20的截面形状为倒梯形。需要说明的是，第一类型半导体层10、发光层30、第二类型半导体层20的截面指的是第一类型半导体层10、发光层30、第二类型半导体层20构成的层叠结构的截面，本实施例中，如图1所示，第一类型半导体层10的远离发光层30的一面(顶面)为出光面，以垂直于第一类型半导体层10的顶 面的平面为截面，上述第一类型半导体层10、发光层30、第二类型半导体层20构成的层叠结构的截面形状为倒梯形，本实施例中倒梯形的位于出光面一侧的底边长度大于远离出光面的底边的长度，倒梯形的结构设置便于微发光二极管芯片的制作。
在一种可能的实现方式中，第一类型电极层40和第二类型电极层50为金属电极层，在上述实施方式的基础上，第一类型电极层40和第二类型电极层50覆盖微发光二极管的侧壁，本实施例中，将第一类型电极层40和第二类型电极层50设置为金属电极层，具体可以为银、铝等，金属的反射率较高，进一步增大了第一类型电极层40和第二类型电极层50的反射率，使得射向侧壁的光线能够被反射，可以进一步地降低或避免了侧壁出光。
在上述实施方式的基础上，倒梯形的底角的范围为50°～85°。具体地，本实施例中，倒梯形的底角可以在50°～85°范围内取任意值，优选地，第一类型半导体层10、发光层30、第二类型半导体层20构成的层叠结构的截面形状为等腰梯形，该等腰梯形的底角可以设置为60°，这样的设置便于微发光二极管芯片的制作。
在一种可能的实现方式中，第一类型半导体层10、发光层30、第二类型半导体层20的形状为圆台或棱台。需要说明的是，第一类型半导体层10、发光层30、第二类型半导体层20的形状指的是第一类型半导体层10、发光层30、第二类型半导体层20构成的层叠结构的形状，如图2所示，第一类型半导体层10、发光层30、第二类型半导体层20构成的层叠结构可以为棱台，具体可以为四棱台。
在一种可能的实现方式中，第一类型电极层40向远离第一类型半导体层10的一侧水平延伸形成第一伸出部41；第二类型电极层50在向远离第一类型电极层40的另一侧水平延伸形成第二伸出部51。以图1所示的方位为例进行描述，第一类型电极层40覆盖第一类型半导体层10的侧壁的一侧，第一类型电极层40朝远离第一类型半导体层10的方向向外延伸，形成第一伸 出部41，第一伸出部41的顶面为平坦面，具体地，在形成第一伸出部41时可以通过电镀工艺进行加厚，以及通过化学机械抛光工艺对第一伸出部41进行平坦化处理。第一伸出部41的顶面可以与第一类型半导体层10的顶面平齐，也可以高于第一类型半导体层10的顶面。第一伸出部41的设置不仅有利于后续绝缘钝化层60、第二类型电极层50的形成，而且便于后续批量转移时与驱动基板对准和连接。
当第一类型电极层40形成第一伸出部41后，绝缘钝化层60覆盖第一类型电极层40，第二类型电极层50覆盖绝缘钝化层60，以图1所示的方位为例进行描述，第二类型电极层50覆盖绝缘钝化层60并向两侧延伸，在背离上述第一伸出部41的一侧，第二类型电极层50沿向水平延伸形成第二伸出部51，且第二伸出部51的顶面为平坦面。具体地，在形成第二类型电极层50时可以通过电镀工艺进行加厚，以及通过化学机械抛光工艺对第二伸出部51进行平坦化处理。第二伸出部51的顶面可以与第一类型半导体层10的顶面平齐，也可以高于第一类型半导体层10的顶面。第二伸出部51的设置有利于后续批量转移时与驱动基板对准和连接。
在一种可能的实现方式中，第一伸出部41的顶面在水平方向上与第二伸出部51的顶面平齐。在上述实施方式的基础上，第一类型电极层40形成第一伸出部41，第二类型电极层50形成第二伸出部51，本实施例中第一伸出部41的顶面与第二伸出部51的顶面平齐，即第一类型电极层40露出的部分与第二类型电极层50露出的部分相平齐，这样的设置进一步提高了与驱动基板连接时的对准精度。
在一种可能的实现方式中，第一伸出部41的顶面在水平方向上与第一类型半导体层10的顶面平齐。在上述实施方式的基础上，第一伸出部41的顶面与第二伸出部51的顶面平齐，本实施例中，第一伸出部41的顶面、第二伸出部51的顶面、第一类型半导体层10的顶面相平齐的设置便于微发光二极管芯片的制作。
在另一种可能的实现方式中，第一伸出部41的顶面在水平方向上高于第一类型半导体层10的顶面。在上述实施方式的基础上，第一伸出部41的顶面与第二伸出部51的顶面平齐，本实施例中，第一伸出部41的顶面和第二伸出部51的顶面略高于第一类型半导体层10的顶面的设置进一步保证了光线能够被反射，避免了光串扰问题。
在一种可能的实现方式中，第一类型半导体层10的顶面设置为粗糙表面。本实施例中将第一类型半导体层10的顶面设置为粗糙表面，具体地，由于光从光密介质射向光疏介质时存在全反射现象，如果界面是光滑平整的，那么反射锥(锥体中心轴与界面法线平行)之外的光线会逐渐被LED芯片内的材料所吸收而无法逃逸出去，只有入射方向在反射锥之内的光线能部分逃逸；而粗糙表面能提供多个取向的反射锥，原本无法逃逸的某些方向的光线也能逃逸出LED芯片，因此粗糙表面有利于微发光二级管芯片的光提取。
实施例二
本公开实施例二提供的显示面板包括上述实施例一中提供的微发光二极管芯片，其中，微发光二极管芯片的结构、功能及实现可参照上述实施例中的具体描述，此处不再赘述。
本实施例提供的显示面板可以应用于手机、平板电脑、智能手表、电子书、导航仪、电视、数码相机等任意包括微发光二极管芯片的、具有显示功能的显示装置中。本实施例提供的显示面板也具有与实施一所提供的微发光二极管芯片相同的优点，在此不再赘述。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。

Claims (15)

  1. 一种微发光二极管芯片，包括：
    第一类型半导体层；
    发光层；
    第二类型半导体层；
    第一类型电极层，所述第一类型电极层位于所述第一类型半导体层一侧的侧壁上并与所述第一类型半导体层欧姆接触；
    第二类型电极层；和
    绝缘钝化层，所述绝缘钝化层覆盖所述第一类型半导体层的部分侧壁、所述第一类型电极层的侧壁和底面、所述发光层的侧壁、所述第二类型半导体层的侧壁和部分底面，所述第二类型电极层覆盖所述绝缘钝化层，所述第二类型半导体层从所述绝缘钝化层露出的部分底面与所述第二类型电极层欧姆接触，
    其中，所述第一类型半导体层、所述发光层、所述第二类型半导体层依次层叠设置。
  2. 根据权利要求1所述的微发光二极管芯片，其中，所述第一类型半导体层的侧壁上设置台阶面，所述第一类型电极层形成在所述第一类型半导体层上时，覆盖所述台阶面。
  3. 根据权利要求2所述的微发光二极管芯片，其中，所述第二类型电极层在水平方向上设置有延伸部，用于支撑所述绝缘钝化层、所述第一类型电极层、所述第一类型半导体层、所述发光层、所述第二类型半导体层的侧壁部分。
  4. 根据权利要求1所述的微发光二极管芯片，其中，以垂直于出光面的平面为截面，所述第一类型半导体层、所述发光层、所述第二类型半导体层的截面形状为倒梯形。
  5. 根据权利要求4所述的微发光二极管芯片，其中，所述倒梯形的底角 在50°～85°范围内。
  6. 根据权利要求4所述的微发光二极管芯片，其中，所述第一类型半导体层、所述发光层、所述第二类型半导体层的截面形状为等腰梯形，所述等腰梯形的底角为60°。
  7. 根据权利要求1所述的微发光二极管芯片，其中，所述第一类型电极层和所述第二类型电极层为金属电极层。
  8. 根据权利要求7所述的微发光二极管芯片，其中，所述第一类型电极层和所述第二类型电极层均为银和铝中的任一个或两者的合金。
  9. 根据权利要求1所述的微发光二极管芯片，其中，所述第一类型半导体层、所述发光层、所述第二类型半导体层的形状为圆台或棱台。
  10. 根据权利要求1所述的微发光二极管芯片，其中，所述第一类型电极层向远离所述第一类型半导体层的一侧水平延伸形成第一伸出部；所述第二类型电极层在向远离所述第一类型电极层的另一侧水平延伸形成第二伸出部。
  11. 根据权利要求10所述的微发光二极管芯片，其中，所述第一伸出部的顶面在水平方向上与所述第二伸出部的顶面平齐。
  12. 根据权利要求11所述的微发光二极管芯片，其中，所述第一伸出部的顶面在水平方向上与所述第一类型半导体层的顶面平齐。
  13. 根据权利要求11所述的微发光二极管芯片，其中，所述第一伸出部的顶面在水平方向上高于所述第一类型半导体层的顶面。
  14. 根据权利要求1或11所述的微发光二极管芯片，其中，所述第一类型半导体层的顶面设置为粗糙表面。
  15. 一种显示面板，包括权利要求1-14任一项所述的微发光二极管芯片。
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