WO2021057275A1 - 一种双向esd保护器件及电子装置 - Google Patents

一种双向esd保护器件及电子装置 Download PDF

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WO2021057275A1
WO2021057275A1 PCT/CN2020/107324 CN2020107324W WO2021057275A1 WO 2021057275 A1 WO2021057275 A1 WO 2021057275A1 CN 2020107324 W CN2020107324 W CN 2020107324W WO 2021057275 A1 WO2021057275 A1 WO 2021057275A1
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region
well region
well
implantation
bidirectional
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PCT/CN2020/107324
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French (fr)
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梁旦业
汪广羊
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无锡华润上华科技有限公司
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Priority to US17/639,076 priority Critical patent/US20220302104A1/en
Publication of WO2021057275A1 publication Critical patent/WO2021057275A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions

Definitions

  • the present invention relates to the field of semiconductor technology, in particular to a bidirectional ESD protection device and an electronic device.
  • ESD protection design becomes more and more challenging and difficult in nanometer CMOS technology.
  • ESD discharge modes There are four common ESD discharge modes, namely: 1. PS mode: positive ESD pulse appears on the IO port (for example, the input terminal), IO port discharges to the ground; 2. NS mode: negative ESD pulse appears on the IO port, ground to IO port discharge; 3. ND mode: negative ESD pulse appears on IO port, VDD discharges to IO port; 4. PD mode: positive ESD pulse appears on IO port, IO port discharges to VDD.
  • the ESD current direction of the above-mentioned discharge mode is schematically shown in FIG. 1. It can be seen from Figure 1 that for devices that can provide unidirectional protection, at least four devices are required to meet the complete ESD protection design requirements; and for devices that can provide bidirectional protection, at least two devices are required.
  • SCR Silicon Controlled Rectifier
  • ESD Electro-Static Discharge
  • a bidirectional ESD protection device and an electronic device are provided.
  • a bidirectional ESD protection device includes a bidirectional SCR device formed on a semiconductor substrate, and the bidirectional ESD protection device includes: a first well region having a first conductivity type formed in the semiconductor substrate And the second well region;
  • the two well regions are located on the same straight line, and the second conductivity type is opposite to the first conductivity type;
  • first implanted regions and not less than two second implanted regions are formed in the first well region, and not less than two fourth implanted regions and not less than two fourth implanted regions are formed in the second well region Not less than two fifth implanted regions, the first implanted region and the fourth implanted region have the first conductivity type, the second implanted region and the fifth implanted region have the second conductivity type, the The first injection regions are arranged at intervals along the length direction of the first well region, the second injection regions are arranged at intervals along the length direction of the first well region, and the fourth injection regions are arranged along the length of the second well region.
  • the fifth injection regions are arranged at intervals along the length direction of the second well region, the first injection regions and the second injection regions are in the length direction of the first well region, and the fourth The implantation region and the fifth implantation region are respectively located on different straight lines in the length direction of the second well region and are offset from each other by a certain distance;
  • a third implantation region formed at the junction of the first well region and the third well region, and at the junction of the second well region and the third well region, the third implantation region having a first A conductivity type, the third implanted region extends along the length direction of the first well region;
  • the first implantation region, the second implantation region, the third implantation region, the fourth implantation region, the fifth implantation region and the first well region, the second well region and the third well region constitute a bidirectional SCR device
  • the first implantation region and the second implantation region in the first well region are used as the first pole of the bidirectional SCR device
  • the fourth implantation region and the fifth implantation region in the second well region are used as the first pole of the bidirectional SCR device.
  • the first pole and the second pole are the anode and the cathode of the bidirectional SCR device, respectively.
  • An electronic device includes the above-mentioned bidirectional ESD protection device and an electronic component connected with the ESD protection device.
  • FIG. 1 shows a schematic diagram of the discharge current of an ESD protection device
  • FIG. 2A shows a schematic cross-sectional view and equivalent circuit diagram of a unidirectional SCR device in the conventional technology
  • FIG. 2B shows a schematic cross-sectional view and an equivalent circuit diagram of the first bidirectional SCR device in the conventional technology
  • 3A shows a schematic cross-sectional view and equivalent circuit diagram of a second bidirectional SCR device in the conventional technology
  • FIG. 3B shows a schematic top view of the bidirectional SCR device shown in FIG. 3A;
  • FIG. 4A shows a schematic cross-sectional view and equivalent circuit diagram of a third type of bidirectional SCR device in the conventional technology
  • FIG. 4B shows a schematic top view of the bidirectional SCR device shown in FIG. 4A;
  • 5A shows a schematic cross-sectional view and equivalent circuit diagram of a fourth bidirectional SCR device in the conventional technology
  • FIG. 5B shows a schematic top view of the bidirectional SCR device shown in FIG. 5A;
  • Fig. 6A shows a schematic top view of a bidirectional ESD protection device in an embodiment of the present application
  • FIG. 6B shows a schematic cross-sectional view and equivalent circuit diagram of the bidirectional ESD protection device shown in FIG. 6A;
  • 6C shows a schematic top view of a bidirectional ESD protection device in another embodiment of the present application.
  • FIG. 7 shows diagrams of TLP test results of the bidirectional ESD protection device shown in FIG. 5A, FIG. 6A, and FIG. 6C;
  • FIG. 8 shows a schematic diagram of an electronic device in an embodiment of the present application.
  • FIG. 2A is a schematic cross-sectional view and equivalent circuit diagram of a unidirectional SCR device in the conventional technology
  • FIG. 2B is a schematic cross-sectional view and equivalent circuit diagram of the first bidirectional SCR device in the conventional technology.
  • the unidirectional SCR device 200A is formed on a P-type semiconductor substrate P-sub, including an N-type buried layer BN formed on the P-type semiconductor substrate, and an N-well located on the N-type buried layer BN.
  • NW N-type buried layer BN
  • PW P well
  • P+ implantation area and N+ implantation area are formed in the N well
  • P+ implantation area and N+ implantation area are formed in the P well.
  • the P+ injection area and N+ injection area in the N well are used as the anode of the unidirectional SCR device 200A, and are connected to the anode terminal; the P+ injection area and the N+ injection area in the P well are used as the cathode of the unidirectional SCR device 200A, and The cathode terminal is connected.
  • the P+ implantation area and N+ implantation area in the N well, the P+ implantation area and the N+ implantation area in the P well, and the N well and the P well together constitute the unidirectional SCR device 200A.
  • the bidirectional SCR device 200B is formed on a P-type semiconductor substrate P-sub, and includes an N-type buried layer BN formed on the P-type semiconductor substrate, and a first P-type layer located on the N-type buried layer BN.
  • the well (PW1), the second P well (PW2), the N well (NW) located between the first P well and the second P well, the P+ implantation region and the N+ implantation region are formed in the first P well (PW1), And forming a P+ implantation region and an N+ implantation region in the second P well (PW2).
  • the P+ injection area and N+ injection area in the first P well (PW1) are used as anodes and are connected to the anode terminal
  • the P+ injection area and N+ injection area in the second P well (PW2) are used as the cathode, which is connected to the cathode terminal.
  • Connection, or the P+ injection area and N+ injection area in the second P well (PW2) are used as anodes and connected to the anode terminal
  • the P+ injection area and N+ injection area in the first P well (PW1) are used as the cathode, and the cathode Extremely connected.
  • the bidirectional SCR device 200B When the bidirectional SCR device 200B is turned on on one side, the working principle is the same as that of the unidirectional SCR200A. As shown in Figure 2B, the bidirectional SCR device 200B has a symmetrical structure. When a positive ESD pulse appears at terminal 1, Q3 and Q2 form an SCR loop to discharge ESD current; similarly, when a positive ESD pulse appears at terminal 2, Q1 , Q3 turns on and discharges ESD current.
  • FIG. 3A is a schematic cross-sectional view and equivalent circuit diagram of the second bidirectional SCR device in the conventional technology
  • FIG. 3B is a schematic top view of the bidirectional SCR device shown in FIG. 3A.
  • the bidirectional SCR device 300 shown in FIG. 3A and FIG. 3B is improved on the basis of the SCR device shown in FIG. 2B, and a P-type implantation region is added at the junction of the first P-well, the second P-well and the N-well, so
  • the triggering of the SCR device 300 is achieved by the NW/P+ junction breakdown, which reduces the trigger voltage, but the sustain voltage is still low. If the power supply voltage is greater than the sustain voltage, the power supply can provide energy to maintain the latch, and the latch is maintained until the power consumption is consumed. However, after the ESD pulse, the normally-off state of the ESD protection device cannot be restored, resulting in failure.
  • FIG. 4A is a schematic cross-sectional view and equivalent circuit diagram of a third type of bidirectional SCR device in the conventional technology
  • FIG. 4B is a schematic top view of the bidirectional SCR device shown in FIG. 4A.
  • the bidirectional SCR device 400 shown in FIGS. 4A and 4B is improved on the basis of the SCR device shown in FIGS. 3A and 3B.
  • the N+ strip implantation regions in the first P well and the second P well are implanted by N+ and P+ islands. Alternate zone structure replacement. Since the N+ strip is replaced by the alternate P+ and N+ island structure, and the potentials connected to N+ and P+ are the same, there is carrier movement like PN junction, and the number of electrons emitted by the N+ structure for NPN conduction Decrease, the injection efficiency of the emission junction decreases, and the injection efficiency of the emission junction decreases, the NPN is more difficult to turn on, and a larger energy ESD pulse trigger is required.
  • the latch is a positive feedback formed by the mutual promotion of conduction between NPN and PNP, the NPN is more difficult to trigger, so the latch is more difficult to form. That is, the bidirectional SCR device 400 shown in FIGS. 4A and 4B reduces the injection efficiency of the NPN emitter junction to make it more difficult to enter the latched state after triggering, thereby increasing the sustaining voltage. However, it is found through testing that the SCR device ESD of this structure Robustness (characterization of current capability) is low.
  • FIG. 5A is a schematic cross-sectional view and equivalent circuit diagram of a fourth type of bidirectional SCR device in the conventional technology
  • FIG. 5B is a schematic top view of the bidirectional SCR device shown in FIG. 5A.
  • the bidirectional SCR device 500 shown in FIGS. 5A and 5B is improved on the basis of the SCR device shown in FIGS. 4A and 4B.
  • the P+ injection region in the first P well and the second P well is removed, and the anode and cathode positions are directly
  • the alternate structure of N+ and P+ island implantation regions is used instead.
  • the sustain voltage is higher, it also has the problem of lower ESD robustness.
  • the present application provides a bidirectional ESD protection device that can increase the sustain voltage and improve the ESD robustness.
  • a bidirectional ESD protection device is provided, and the bidirectional ESD protection device includes:
  • the two well regions are located on the same straight line, and the second conductivity type is opposite to the first conductivity type;
  • first implanted regions and not less than two second implanted regions are formed in the first well region, and not less than two fourth implanted regions and not less than two fourth implanted regions are formed in the second well region Not less than two fifth implanted regions, the first implanted region and the fourth implanted region have the first conductivity type, the second implanted region and the fifth implanted region have the second conductivity type, the The first injection regions are arranged at intervals along the length direction of the first well region, the second injection regions are arranged at intervals along the length direction of the first well region, and the fourth injection regions are arranged along the length of the second well region.
  • the fifth injection regions are arranged at intervals along the length direction of the second well region, the first injection regions and the second injection regions are in the length direction of the first well region, and the fourth The implantation region and the fifth implantation region are respectively located on different straight lines in the length direction of the second well region and are offset from each other by a certain distance;
  • a third implantation region formed at the junction of the first well region and the third well region, and at the junction of the second well region and the third well region, the third implantation region having a first A conductivity type, the third implanted region extends along the length direction of the first well region;
  • the first implantation region, the second implantation region, the third implantation region, the fourth implantation region, the fifth implantation region and the first well region, the second well region and the third well region constitute a bidirectional SCR device
  • the first implantation region and the second implantation region in the first well region are used as the first pole of the bidirectional SCR device
  • the fourth implantation region and the fifth implantation region in the second well region are used as the first pole of the bidirectional SCR device.
  • the first pole and the second pole are the anode and the cathode of the bidirectional SCR device, respectively.
  • FIG. 6A shows a schematic top view of a bidirectional ESD protection device in an embodiment of the present application
  • FIG. 6B shows a schematic cross-sectional view and an equivalent circuit diagram of the bidirectional ESD protection device shown in FIG. 6A.
  • a bidirectional ESD protection device 600A is provided.
  • the bidirectional ESD protection device 600A includes a bidirectional SCR device formed on a semiconductor substrate 601.
  • the semiconductor substrate 601 may be at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III/V compound semiconductor materials, and It can be a multilayer structure including the above-mentioned semiconductor materials, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon germanium-on-insulator (SiGeOI), and silicon on insulator Germanium (GeOI) and so on.
  • the constituent material of the semiconductor substrate is single crystal silicon.
  • the semiconductor substrate 601 has a first conductivity type, and the first conductivity type is, for example, a P-type, that is, the semiconductor substrate 601 is a P-type semiconductor substrate. It should be understood that, in other embodiments, the semiconductor substrate 601 has the second conductivity type, and the second conductivity type is, for example, N-type.
  • the semiconductor substrate 601 may also be an N-type semiconductor substrate.
  • the bidirectional SCR device in the bidirectional ESD protection device 600A includes a buried layer 602 formed on a semiconductor substrate 601, a first well region 603, a second well region 604, a third well region 605, and a second well region 604.
  • the buried layer 602 and the third well region 605 have the second conductivity type, such as N-type;
  • the semiconductor substrate 601, the first well region 603, and the second well region 604 have the first conductivity type, such as P-type, and the second conductivity type.
  • the second conductivity type is opposite to the first conductivity type.
  • the buried layer 602 is formed between the semiconductor substrate 601 and the first well region 603, the second well region 604, and the third well region 605 to isolate the well region above the buried layer 602 from the semiconductor substrate 601 below the buried layer 602 .
  • the buried layer 602 includes a deep N buried layer.
  • the buried layer 602 may be formed by diffusion.
  • the first well region 603 and the second well region 604 are formed on the buried layer 602.
  • the first well region 603 and the second well region 604 may be formed by implanting dopant ions of the first conductivity type into the semiconductor substrate 601.
  • the implantation concentration and implantation depth of the dopant ions in the first well region 603 and the second well region 604 can be determined according to design requirements, and are not specifically limited here.
  • the third well region 605 is located between the first well region 603 and the second well region 604 and is located on the same straight line as the first well region 603 and the second well region 604.
  • the third well region 605 may be formed by implanting dopant ions of the second conductivity type into the semiconductor substrate 601.
  • the implantation concentration and implantation depth of the doped ions in the third well region 605 can be determined according to design requirements, which are not specifically limited here.
  • the first implanted region 606 and the second implanted region 607 are formed in the first well region 603 to serve as the first pole of the bidirectional SCR device, and the fourth implanted region 609 and the fifth implanted region 610 are formed in the second well region 604, Used as the second pole of the bidirectional SCR device, the first pole and the second pole are the anode and the cathode of the bidirectional SCR device, respectively.
  • no less than two first implant regions 606 and no less than two second implant regions 607 are formed in the first well region 603.
  • the first implanted region 606 has a first conductivity type, for example, P-type
  • the second implanted region 607 has a second conductivity type, for example, N-type.
  • the first injection regions 606 are arranged at intervals along the length direction of the first well region 603, and the second injection regions 607 are arranged at intervals along the length direction of the first well region 603; There are less than two fourth injection regions 609 and no less than two fifth injection regions 610.
  • the fourth implanted region 609 has a first conductivity type, for example, P-type, and the fifth implanted region 610 has a second conductivity type, for example, N-type.
  • the fourth injection regions 609 are arranged at intervals along the length direction of the second well region 604, and the fifth injection regions 610 are arranged at intervals along the length direction of the second well region 604.
  • the first injection area 606, the second injection area 607, the fourth injection area 609, and the fifth injection area 610 are no longer strip injection areas, but island injection areas arranged at intervals.
  • the first implanted region 606 and the second implanted region 607 are located at different lengths in the length direction of the first well region 603, and the fourth implanted region 609 and the fifth implanted region 610 are respectively located in different directions along the length of the second well region 604.
  • the first injection area 606 and the second injection area 607 are offset from each other in the width direction of the first well area 603 and are not on the same straight line; the fourth injection area 609 and the fifth injection area 610 are The width directions of the second well regions 604 are staggered from each other and are not on the same straight line. That is, the island-shaped P+ implantation region and the N+ implantation region in the SCR device of this embodiment are not on the same straight line, but are staggered by a certain distance from each other, thereby increasing its ESD robustness.
  • the third implantation region 608 is respectively formed at the junction of the first well region 603 and the third well region 605, and the junction of the second well region 604 and the third well region 605, the third implantation region 608 has the first conductivity type, For example, it is P type.
  • the third implanted region 608 extends along the length of the first well region 603/the second well region 604, and its length is the same as the length of the first well region 603/the second well region 604, that is, the third implanted region 608 is Strip injection zone or strip injection zone.
  • the third implantation region 608 is formed in the first well region 603 and the second well region 604 respectively, and the third implantation region 608 is adjacent to the third well region 605.
  • the third implantation region 608 is formed in the third well region 605, and one third implantation region 608 is adjacent to the first well region 603, and the other third implantation region 608 is adjacent to the second well region 604.
  • the third implant region 608 crosses the first well region 603 and the third well region 605, and crosses the second well region 604 and the third well region 605, respectively (as shown in FIG. 6B).
  • the first implanted region 606, the fourth implanted region 609, and the third implanted region 608 are P+ implanted regions formed by implanting P-type ions into the semiconductor substrate 601.
  • the first implanted region 606, the fourth implanted region 606, and the fourth implanted region 608 are P+ implanted regions formed by implanting P-type ions into the semiconductor substrate 601.
  • the doping concentration of P-type ions in the implantation region 609 and the third implantation region 608 is higher than that in the first well region 603 and the second well region 604, and in the first implant region 606, the fourth implant region 609 and the third implant region 608
  • the implantation depth of P-type ions is smaller than the depth of the first well region and the second well region.
  • the second implantation region 607 and the fifth implantation region 610 are N+ implantation regions formed by implanting N-type ions into the semiconductor substrate 601.
  • the doping concentration of N-type ions in the second implantation region 607 and the fifth implantation region 610 is higher than The third well region, and the implantation depth of N-type ions in the second implantation region 607 and the fifth implantation region 610 is smaller than the depth of the third well region.
  • the length direction of the first well region 603 and the second well region 604 refers to the direction perpendicular to the paper in the cross-sectional view shown in FIG. 6B or the longitudinal direction in FIGS. 6A and 6C.
  • the width direction of the region 603 and the second well region 604 refers to the lateral direction in FIGS. 6A and 6C.
  • third injection regions 608 between the third injection region 608 and the first injection region 606, and between the third injection region 608 and the second injection region 608.
  • An isolation structure can be formed between the regions 607, between the third injection region 608 and the fourth injection region 609, and between the third injection region 608 and the fifth injection region 610, so that the third injection regions 608 can be separated
  • the three-injection area 608 and the first injection area 606 or the second injection area 607 or the fourth injection area 609 or the fifth injection area 610 are isolated from each other.
  • FIG. 6C shows a schematic top view of another bidirectional ESD protection device according to an embodiment of the present invention.
  • the main difference between the bidirectional ESD protection device 600B shown in FIG. 6C and the bidirectional ESD protection device 600A shown in FIGS. 6A and 6B is that: in the bidirectional ESD protection device 600A shown in FIGS.
  • the second implanted region 607 is closer to the third well region 605, and the fourth implanted region 609 is closer to the third well region 605 than the fifth implanted region 610.
  • the second implanted region 607 is closer to the third well region 605 than the first implanted region 606, and the fifth implanted region 610 is closer to the third well region 605 than the fourth implanted region 609.
  • FIG. 7 shows diagrams of TLP test results of the bidirectional ESD protection device shown in FIG. 5A, FIG. 6A, and FIG. 6C.
  • curves 1, 2, and 3 respectively represent the TLP test results of the bidirectional ESD protection device shown in FIG. 5A, FIG. 6A, and FIG. 6C.
  • the overcurrent capability of the bidirectional ESD protection device shown in Fig. 6A and Fig. 6C is much increased (that is, the ESD robustness is increased).
  • the holding voltage of the bidirectional ESD protection device shown in FIG. 6B is higher, and the overcurrent capability of the bidirectional ESD protection device shown in FIG. 6B is stronger.
  • the bidirectional ESD protection device shown in FIG. 6A has a higher trigger voltage because of the effective basis of the NPN (NW/PW/N+) structure of the SCR path. As the base increases, the NPN is more difficult to trigger, so there is a higher Vt1 (Vt1 is the trigger voltage), and because the gain of the NPN itself is reduced, the SCR path needs higher energy to maintain the positive feedback of mutual promotion, so Vh (Vh is the sustain voltage) increases.
  • the reason for the higher It2 (current) of the bidirectional ESD protection device shown in FIG. 6A is that the contact of N+ and P+ in the bidirectional ESD protection device shown in FIG.
  • the bidirectional ESD protection device shown in FIG. 6A causes a depletion region, and the conductive area of P+ and N+ is smaller.
  • N+ and P+ are separated, and the conductive areas of N+ and P+ are larger, and the current concentration is not as high as the bidirectional ESD protection device shown in FIG. 5A, so the current capability is stronger.
  • the P+ ground at the cathode end of the bidirectional ESD protection device shown in FIG. 6C is farther away from the floating P+ on the right side. Because of the well resistance, the potential of the floating P+ on the right side of the bidirectional ESD protection device shown in FIG. 6C is higher.
  • the first implantation region and the second implantation region serving as the first pole are provided as a plurality of first implantation regions and a plurality of first implantation regions arranged and spaced along the length direction of the first well region.
  • the first well region is arranged in the length direction of the second implantation region and spaced apart, and the first implantation region and the second implantation region are located on different straight lines and are staggered from each other by a certain distance, and the first implantation region and the second implantation region are in the first
  • the width direction of the well region is staggered from each other, and the fourth and fifth implantation regions serving as the second pole are arranged as a plurality of fourth implantation regions arranged and spaced along the length direction of the second well region and a plurality of fourth implantation regions arranged along the length of the second well region.
  • the fifth implantation region is arranged in the longitudinal direction of the two well regions and arranged at intervals, and the fourth implantation region and the fifth implantation region are located on different straight lines and are offset from each other by a certain distance, and the fourth implantation region and the fifth implantation region are in the second well
  • the regions are staggered in the width direction, wherein the first pole and the second pole are the anode and the cathode of the bidirectional SCR device, respectively.
  • the bidirectional ESD protection device includes a bidirectional SCR device formed on a semiconductor substrate
  • the bidirectional ESD protection device includes: a first well region and a second well having a first conductivity type formed in the semiconductor substrate Region; a third well region of the second conductivity type formed in the semiconductor substrate, the third well region being located between the first well region and the second well region and with the first well region And the second well region are located on the same straight line, the second conductivity type is opposite to the first conductivity type; no less than two first injection regions and no less than two second implant regions are formed in the first well region Implantation region, the first implantation region has a first conductivity type, the second implantation region has a second conductivity type, the first implantation regions are arranged at intervals along the length direction of the first well region, and the second The implanted regions are arranged at intervals along the length of
  • the first implanted regions and the second implanted regions are located on different straight lines and are offset from each other by a certain distance; no less than Two fourth injection zones and no less than two fifth injection zones.
  • the fourth implantation region has the first conductivity type, for example, P-type
  • the fifth implantation region has the second conductivity type, for example, N-type.
  • the fourth implantation regions are arranged at intervals along the length direction of the second well region
  • the fifth implantation regions are arranged at intervals along the length direction of the second well region.
  • the fifth implantation region and the first, second, and third well regions constitute a bidirectional SCR device, and the first implantation region and the second implantation region in the first well region serve as the bidirectional SCR device.
  • the first pole of the SCR device, the fourth implanted region and the fifth implanted region in the second well region are used as the second pole of the bidirectional SCR device, and the first pole and the second pole are respectively bidirectional SCR devices Anode and cathode.
  • the electronic component can be any electronic component such as a discrete device or an integrated circuit.
  • the electronic device of this embodiment can be any electronic product or equipment such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a TV, a VCD, a DVD, a navigator, a camera, a camcorder, a voice recorder, an MP3, an MP4, a PSP, etc. , It can also be any intermediate product that includes the semiconductor device.
  • the electronic device includes a mobile phone. As shown in FIG. 8, a display part 802 included in a housing 801, an operation button 803, an external connection port 804, a speaker 805, and a microphone 806 are provided on the outside of the mobile phone 800. Wait.
  • the included ESD protection device can increase the sustaining voltage while increasing the ESD robustness and the current discharge capability, a better ESD protection effect can be achieved. Therefore, the electronic device also has similar advantages.

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Abstract

一种双向ESD保护器件及电子装置，该双向ESD保护器件包括：形成在半导体衬底(601)中的第一阱区(603)、第二阱区(604)和第三阱区(605)；在第一阱区(603)中形成的不少于两个第一注入区(606)和不少于两个第二注入区(607)，在第二阱区(604)中形成的不少于两个第四注入区(609)和不少于两个第五注入区(610)，第一注入区(606)和第二注入区(607)分别沿第一阱区(603)的长度方向间隔排列，第四注入区(609)和第五注入区(610)分别沿第二阱区(604)的长度方向间隔排列，第一注入区(606)和第二注入区(607)在第一阱区(603)的长度方向上，以及第四注入区(609)和第五注入区(610)在第二阱区(604)的长度方向上分别位于不同的直线上且彼此错开一定距离；形成在第一阱区(603)和第三阱区(605)的交界处以及第二阱区(604)和第三阱区(605)的交界处的第三注入区(608)。

Description

一种双向ESD保护器件及电子装置
相关申请的交叉引用
本申请要求于2019年09月26日提交中国专利局、申请号为2019109167099、发明名称为“一种双向ESD保护器件及电子装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体技术领域，具体而言涉及一种双向ESD保护器件及电子装置。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成示例性技术。
随着CMOS工艺连续按比例缩小，由静电放电(ESD)导致的IC芯片失效已经成为一个重大的可靠性问题，尤其是对于具有超薄栅极氧化层和薄介电层的小型器件而言呈现出更严重的ESD破坏趋势。ESD防护设计在纳米级的CMOS技术中变得越来越具有挑战性和难度。ESD放电常见有四种模式，分别为：1、PS模式：正ESD脉冲出现在IO口(例如输入端)，IO口对地放电；2、NS模式：负ESD脉冲出现在IO口，地对IO口放电；3、ND模式：负ESD脉冲出现在IO口，VDD对IO口放电；4、PD模式：正ESD脉冲出现在IO口，IO口对VDD放电。上述放电模式的ESD电流方向示意如图1所示。由图1可知，对于能够提供单向保护的器件，要满足完整的ESD防护设计需求，至少需要四个器件；而对于能够提供双向则最少需两个器件就可实现。
SCR(Silicon Controlled Rectifier，硅控整流器)作为一种常用的 ESD(Electro-Static Discharge)防护器件，广泛用于各种ESD防护设计之中。然而，传统的ESD器件只能提供单向的保护，要设计完整保护方案需要大量的器件来实现，且占用过多的layout面积。因此能够提供多向保护的新器件越来越受到关注。通过改进SCR结构，使其能够提供双向保护是一个发展方向，但其传统双向结构因为靠P阱和N阱的结击穿触发，导致触发电压过高，触发之后，又因为SCR路径中的闩锁结构进入深度正反馈，导致其维持电压过低，这样ESD设计窗口过大，需要调整才能用来做防护。
因此，有必要对SCR构成的双向ESD保护器件进行改进，以使其具有相对较高维持电压的同时，ESD鲁棒性对比之前的结构大大提高。
发明内容
根据本申请的各种实施例，提供一种双向ESD保护器件及电子装置。
一种双向ESD保护器件，该双向ESD保护器件包括形成在半导体衬底上的双向SCR器件，该双向ESD保护器件包括：形成在所述半导体衬底中的具有第一导电类型的第一阱区和第二阱区；
形成在所述半导体衬底中的具有第二导电类型的第三阱区，所述第三阱区位于所述第一阱区和第二阱区之间且与所述第一阱区和第二阱区位于同一直线上，所述第二导电类型与所述第一导电类型相反；
在所述第一阱区中形成的不少于两个第一注入区和不少于两个第二注入区，在所述第二阱区中形成的不少于两个第四注入区和不少于两个第五注入区，所述第一注入区和所述第四注入区具有第一导电类型，所述第二注入区和所述第五注入区具有第二导电类型，所述第一注入区沿所述第一阱区的长度方向间隔排列，所述第二注入区沿所述第一阱区的长度方向间隔排列，所述第四注入区沿所述第二阱区的长度方向间隔排列，所述第五注入区沿所述第二阱区的长度方向间隔排列，所述第一注入区和所述第二注入区在第一阱区的长度方向上，以及第四注入区和第五注入区在第二阱区的长度方向上分别位于不同的直线上且彼此错开一定距离；以及
形成在所述第一阱区和所述第三阱区的交界处，以及所述第二阱区和所述第三阱区的交界处的第三注入区，所述第三注入区具有第一导电类型，所述第三注入区沿所述第一阱区的长度方向延伸；
其中，所述第一注入区、第二注入区、第三注入区、第四注入区、第五注入区以及所述第一阱区、第二阱区和第三阱区构成双向SCR器件，所述第一阱区中的所述第一注入区和第二注入区用作所述双向SCR器件的第一极，所述第二阱区中的所述第四注入区和第五注入区用作所述双向SCR器件的第二极，第一极和第二极分别为所述双向SCR器件的阳极和阴极。
一种电子装置，其包括如上所述的双向ESD保护器件以及与所述ESD保护器件相连接的电子组件。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例或示例性技术中的技术方案，下面将对实施例或示例性技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。图1示出ESD防护器件放电电流示意图；
图2A示出传统技术中一种单向SCR器件的示意性剖视图及等效电路图；
图2B示出传统技术中第一种双向SCR器件的示意性剖面图及等效电路图；
图3A示出传统技术中第二种双向SCR器件的示意性剖视图及等效电路图；
图3B示出图3A所示双向SCR器件的示意性俯视图；
图4A示出传统技术中第三种双向SCR器件的示意性剖视图及等效电路图；
图4B示出图4A所示双向SCR器件的示意性俯视图；
图5A示出传统技术中第四种双向SCR器件的示意性剖视图及等效电路图；
图5B示出图5A所示双向SCR器件的示意性俯视图；
图6A示出本申请一实施例中双向ESD保护器件的示意性俯视图；
图6B示出图6A所示双向ESD保护器件示意性剖视图及等效电路图；
图6C示出本申请另一实施例中的双向ESD保护器件的示意性俯视图；
图7示出图5A、图6A和图6C所示的双向ESD保护器件的TLP测试结果图示；
图8示出本申请一实施例中的电子装置的示意图。
具体实施方式
在下文的描述中，给出了大量具体的细节以便提供对本申请更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本申请可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本申请发生混淆，对于本领域公知的一些技术特征未进行描述。
为了彻底理解本申请，将在下列的描述中提出详细的结构及步骤，以便阐释本申请提出的技术方案。本申请的较佳实施例详细描述如下，然而除了这些详细描述外，本申请还可以具有其他实施方式。
图2A为传统技术中一种单向SCR器件的示意性剖视图及等效电路图；图2B为传统技术中第一种双向SCR器件的示意性剖面图及等效电路图。
如图2A所示，单向SCR器件200A形成在P型半导体衬底P-sub上，包括形成在P型半导体衬底上的N型埋层BN，位于N型埋层BN之上的N阱(NW)和P阱(PW)，在N阱中形成P+注入区和N+注入区，以及在P阱中形成P+注入区和N+注入区。其中，N阱中的P+注入区和N+注入区用作单向SCR器件200A的阳极，与阳极端连接；P阱中的P+注入区和N+注入区用作单向SCR器件200A的阴极，与阴极端连接。N阱中的P+注入区和N+注入区、P阱中的P+注入区和N+注入区以及N阱和P阱共同构成单向SCR器件200A，当施加在 阳极端的ESD脉冲将N阱和P阱形成的结击穿时，SCR回路导通，形成ESD电流释放路径。
如图2B所示，双向SCR器件200B形成在P型半导体衬底P-sub上，包括形成在P型半导体衬底上的N型埋层BN，位于N型埋层BN之上的第一P阱(PW1)、第二P阱(PW2)，位于第一P阱和第二P阱之间的N阱(NW)，在第一P阱(PW1)中形成P+注入区和N+注入区，以及在第二P阱(PW2)中形成P+注入区和N+注入区。其中，第一P阱(PW1)中的P+注入区和N+注入区用作阳极，与阳极端连接，第二P阱(PW2)中的P+注入区和N+注入区用作阴极，与阴极端连接，或者第二P阱(PW2)中的P+注入区和N+注入区用作阳极，与阳极端连接，第一P阱(PW1)中的P+注入区和N+注入区用作阴极，与阴极端连接。第一P阱(PW1)中的P+注入区和N+注入区、第二P阱(PW2)中的P+注入区和N+注入区以及N阱、第一P阱(PW1)和第二P阱(PW2)共同构成双向SCR器件200B。双向SCR器件200B单边导通时工作原理与单向SCR200A相同。如图2B所示，双向SCR器件200B是一个对称结构，当正ESD脉冲出现在端点1时，Q3、Q2组成SCR回路泄放ESD电流；同理，当正ESD脉冲出现在端点2时，Q1、Q3导通泄放ESD电流。这种双向SCR器件虽然可以实现双向保护，但是由于这种双向SCR器件是通过阱击穿触发，触发电压较大，当ESD脉冲低于该触发电压时，该ESD脉冲将无法实现泄放，可能造成ESD防护失效，导致器件损坏，因此，需要对SCR器件进行改进，以降低其触发电压。图3A为传统技术中第二种双向SCR器件的示意性剖视图及等效电路图；图3B为出图3A所示双向SCR器件的示意性俯视图。
如图3A和图3B所示的双向SCR器件300，在图2B所示SCR器件的基础进行改进，在第一P阱、第二P阱与N阱的交界处增加了P型注入区，这样SCR器件300的触发通过NW/P+的结击穿实现，使得触发电压降低，但是维持电压仍然较低，若电源电压大于维持电压，电源可以提供维持闩锁的能量，闩锁维持直到电源能量耗尽，这样ESD脉冲过后不能恢复ESD保护器件的常关状态，导致失效。
图4A为传统技术中第三种双向SCR器件的示意性剖视图及等效电路图；图4B示出图4A所示双向SCR器件的示意性俯视图。
图4A和图4B所示的双向SCR器件400，在图3A和图3B所示SCR器件的基础上进行改进，第一P阱和第二P阱中的N+条注入区使用N+、P+岛注入区交替结构替代，由于N+条由P+、N+岛交替的结构替代，而N+、P+所接电位相同，所以存在像PN结那样的载流子移动，N+结构发出的用于NPN导电的电子数量减少，发射结注入效率降低，而发射结注入效率降低，NPN就越难导通，需要更大能量的ESD脉冲触发。由于闩锁是NPN、PNP相互促进导通形成的正反馈，NPN更难触发所以闩锁更难形成。即，图4A和图4B所示的双向SCR器件400通过降低NPN发射结注入效率，使其触发之后更难进入闩锁状态，从而提高了维持电压，但是通过测试发现这种结构的SCR器件ESD鲁棒性(电流能力的表征)较低。
图5A为传统技术中第四种双向SCR器件的示意性剖视图及等效电路图；图5B示出图5A所示双向SCR器件的示意性俯视图。
图5A和图5B所示双向SCR器件500，在图4A和图4B所示SCR器件的基础上进行改进，其去掉了第一P阱和第二P阱中的P+注入区，阴阳极位置直接用N+、P+岛注入区交替结构代替，虽然维持电压较高，但是其同样存在ESD鲁棒性较低的问题。
因此，基于前述传统技术中ESD器件的结构的不足，本申请提供了一种既可增加维持电压又可提高ESD鲁棒性的双向ESD保护器件。
在其中一个实施例中，提供一种双向ESD保护器件，该双向ESD保护器件包括：
形成在所述半导体衬底中的具有第一导电类型的第一阱区和第二阱区；
形成在所述半导体衬底中的具有第二导电类型的第三阱区，所述第三阱区位于所述第一阱区和第二阱区之间且与所述第一阱区和第二阱区位于同一直线上，所述第二导电类型与所述第一导电类型相反；
在所述第一阱区中形成的不少于两个第一注入区和不少于两个第二注入 区，在所述第二阱区中形成的不少于两个第四注入区和不少于两个第五注入区，所述第一注入区和所述第四注入区具有第一导电类型，所述第二注入区和所述第五注入区具有第二导电类型，所述第一注入区沿所述第一阱区的长度方向间隔排列，所述第二注入区沿所述第一阱区的长度方向间隔排列，所述第四注入区沿所述第二阱区的长度方向间隔排列，所述第五注入区沿所述第二阱区的长度方向间隔排列，所述第一注入区和所述第二注入区在第一阱区的长度方向上，以及第四注入区和第五注入区在第二阱区的长度方向上分别位于不同的直线上且彼此错开一定距离；以及
形成在所述第一阱区和所述第三阱区的交界处，以及所述第二阱区和所述第三阱区的交界处的第三注入区，所述第三注入区具有第一导电类型，所述第三注入区沿所述第一阱区的长度方向延伸；
其中，所述第一注入区、第二注入区、第三注入区、第四注入区、第五注入区以及所述第一阱区、第二阱区和第三阱区构成双向SCR器件，所述第一阱区中的所述第一注入区和第二注入区用作所述双向SCR器件的第一极，所述第二阱区中的所述第四注入区和第五注入区用作所述双向SCR器件的第二极，第一极和第二极分别为所述双向SCR器件的阳极和阴极。
图6A示出本申请一实施例中的双向ESD保护器件的示意性俯视图；图6B示出图6A所示的双向ESD保护器件示意性剖视图及等效电路图。
如图6A和图6B所示，在其中一个实施例中，提供一种双向ESD保护器件600A，该双向ESD保护器件600A包括形成在半导体衬底601之上的双向SCR器件。
在其中一个实施例中，半导体衬底601可以是以下所提到的材料中的至少一种：Si、Ge、SiGe、SiC、SiGeC、InAs、GaAs、InP或者其它III/V化合物半导体材料，还可以是包括上述半导体材料构成的多层结构、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。作为示例，在本实施例中，半导体衬底的构成材料选用单晶硅。
在其中一个实施例中，半导体衬底601具有第一导电类型，所述第一导电类型例如为P型，即半导体衬底601为P型半导体衬底。应该理解的是，在其它实施例中，半导体衬底601具有第二导电类型，第二导电类型例如为N型，半导体衬底601也可以为N型半导体衬底。
在其中一个实施例中，双向ESD保护器件600A中的双向SCR器件包括形成在半导体衬底601之上的埋层602、第一阱区603、第二阱区604、第三阱区605、第一注入区606、第二注入区607、第三注入区608、第四注入区609和第五注入区610。其中，埋层602和第三阱区605具有第二导电类型，例如为N型；半导体衬底601、第一阱区603和第二阱区604具有第一导电类型，例如为P型，第二导电类型与第一导电类型相反。
埋层602形成在半导体衬底601与第一阱区603、第二阱区604、第三阱区605之间，用于隔离埋层602上方的阱区与埋层602下方的半导体衬底601。
在其中一个实施例中，埋层602包括深N埋层。
在其中一个实施例中，埋层602可以通过扩散形成。
第一阱区603和第二阱区604形成在埋层602之上。第一阱区603和第二阱区604可以通过向半导体衬底601中注入第一导电类型的掺杂离子形成。第一阱区603和第二阱区604掺杂离子的注入浓度和注入深度可以根据设计要求进行确定，在此不做具体限定。
第三阱区605位于第一阱区603和第二阱区604之间，且与第一阱区603和第二阱区604位于同一直线上。第三阱区605可以通过向半导体衬底601中注入第二导电类型的掺杂离子形成。第三阱区605掺杂离子的注入浓度和注入深度可以根据设计要求进行确定，在此不做具体限定。
第一注入区606和第二注入区607形成在第一阱区603中，用作双向SCR器件的第一极，第四注入区609和第五注入区610形成在第二阱区604中，用作双向SCR器件的第二极，第一极和第二极分别为双向SCR器件的阳极和阴极。在本实施例中，在第一阱区603中形成有不少于两个第一注入区606和不少于两个第二注入区607。第一注入区606具有第一导电类型，例如为P 型，第二注入区607具有第二导电类型，例如为N型。所述第一注入区606沿第一阱区603的长度方向间隔排列，所述第二注入区607沿所述第一阱区603的长度方向间隔排列；在第二阱区604中形成有不少于两个第四注入区609和不少于两个第五注入区610。第四注入区609具有第一导电类型，例如为P型，第五注入区610具有第二导电类型，例如为N型。所述第四注入区609沿所述第二阱区604的长度方向间隔排列，所述第五注入区610沿所述第二阱区604的长度方向间隔排列。即在本实施例中，第一注入区606、第二注入区607、第四注入区609和第五注入区610不再是条状注入区，而是间隔布置的岛状注入区。并且，第一注入区606和第二注入区607在第一阱区603的长度方向上，以及第四注入区609和第五注入区610在第二阱区604的长度方向上分别位于不同的直线上且彼此错开一定距离；第一注入区606和第二注入区607在第一阱区603的宽度方向上彼此错开，不处于同一直线上；第四注入区609和第五注入区610在第二阱区604的宽度方向上彼此错开，不处于同一直线上。即本实施例的SCR器件中岛状的P+注入区和N+注入区不处于同一直线上，而是彼此错开一定距离，从而增加其ESD鲁棒性。
第三注入区608分别形成在第一阱区603和第三阱区605的交界处，以及第二阱区604和第三阱区605的交界处，第三注入区608具有第一导电类型，例如为P型。所述第三注入区608沿第一阱区603/第二阱区604的长度方向延伸，其长度与第一阱区603/第二阱区604的长度相同，也即第三注入区608为条状注入区或带状注入区。
在其中一个实施例中，第三注入区608分别形成在第一阱区603和第二阱区604中，并且第三注入区608紧邻所述第三阱区605。
在其中一个实施例中，第三注入区608均形成在第三阱区605中，并且一个第三注入区608紧邻所述第一阱区603，另一个第三注入区608紧邻第二阱区604。
在其中一个实施例中，第三注入区608分别横跨第一阱区603和第三阱区605以及横跨第二阱区604和第三阱区605(如图6B所示)。
在其中一个实施例中，第一注入区606、第四注入区609和第三注入区608为通过在半导体衬底601中注入P型离子形成的P+注入区，第一注入区606、第四注入区609和第三注入区608中P型离子的掺杂浓度高于第一阱区603和第二阱区604，并且第一注入区606、第四注入区609和第三注入区608中P型离子的注入深度小于第一阱区和第二阱区的深度。第二注入区607和第五注入区610为通过在半导体衬底601中注入N型离子形成的N+注入区，第二注入区607和第五注入区610中N型离子的掺杂浓度高于第三阱区，并且第二注入区607和第五注入区610中N型离子的注入深度小于第三阱区的深度。
需要说明的是，在本文中，第一阱区603和第二阱区604的长度方向指的是图6B所示剖视图中垂直纸面的方向或图6A、图6C中的纵向，第一阱区603和第二阱区604的宽度方向指的是图6A、图6C中的横向。
此外，还需要说明的是，虽然图中未示，但是在相邻的第三注入区608之间、第三注入区608与第一注入区606之间、第三注入区608与第二注入区607之间、第三注入区608与第四注入区609之间、第三注入区608与第五注入区610之间均可以形成隔离结构，以使第三注入区608彼此之间、第三注入区608与第一注入区606或第二注入区607或第四注入区609或第五注入区610之间彼此隔离。
图6C示出根据本发明实施例的另一种双向ESD保护器件的示意性俯视图。图6C所示的双向ESD保护器件600B与图6A和图6B所示的双向ESD保护器件600A主要区别在于：在图6A和图6B所示的双向ESD保护器件600A中，第一注入区606比第二注入区607更靠近第三阱区605，第四注入区609比第五注入区610更靠近第三阱区605，而在图6C所示的双向ESD保护器件600B中，第二注入区607比第一注入区606更靠近第三阱区605，第五注入区610比第四注入区609更靠近第三阱区605。
图7示出图5A、图6A和图6C所示的双向ESD保护器件的TLP测试结果图示。在图7中，曲线1、2、3分别表示图5A、图6A和图6C所示的双向ESD 保护器件的TLP测试结果。根据图7可知，与图5A所示的双向ESD保护器件相比，图6A和图6C所示的双向ESD保护器件的过电流能力都增加很多(即ESD鲁棒性增加)，其中图6A所示的双向ESD保护器件的维持电压更高，图6B所示的双向ESD保护器件的过电流能力更强。这是因为：首先，与图5A所示的双向ESD保护器件相比，图6A所示的双向ESD保护器件有较高触发电压是因为SCR路径的NPN(NW/PW/N+)结构的有效基区(base)增大，NPN更难触发，所以有较高的Vt1(Vt1为触发电压)，并且由于本身NPN的增益降低，导致SCR路径需要更高的能量来维持相互促进的正反馈，所以Vh(Vh为维持电压)增大。而图6A所示的双向ESD保护器件的It2(电流)较高的原因是因为图5A所示的双向ESD保护器件中N+、P+接触导致产生耗尽区，P+、N+的导电面积更小，图6A所示的双向ESD保护器件中N+、P+分开，N+，P+的导电面积更大，电流集中程度没有图5A所示的双向ESD保护器件那么高，所以电流能力更强。其次，图6C所示的双向ESD保护器件阴极端的P+地，距离右边的浮空P+更远，因为阱电阻的存在，所以图6C所示的双向ESD保护器件的右边浮空P+的电势更高，NPN的发射结压降更高，导致图6C所示的双向ESD保护器件的NPN更容易触发，所以图6C所示的双向ESD保护器件比图6A所示的双向ESD保护器件触发电压低。而更容易触发就不需要更高的能量来维持正反馈，Vh低，因此图6C所示的双向ESD保护器件的电流能力强。ESD释放的是能量，V和It2之间有一个平衡(trade off，Power＝Voltage X current)。假设两个器件都能承受相同的ESD能量，图6A所示的双向ESD保护器件在触发后电压都比图6C所示的双向ESD保护器件强，所以It2会较小。
根据本实施例的ESD保护器件，由于将用作第一极的第一注入区和第二注入区设置为多个沿第一阱区长度方向排列且间隔布置的第一注入区和多个沿第一阱区长度方向排列且间隔布置的第二注入区，并且第一注入区和第二注入区位于不同的直线上并彼此错开一定距离，且第一注入区和第二注入区在第一阱区的宽度方向上彼此错开，将用作第二极的第四注入区和第五注入 区设置为多个沿第二阱区长度方向排列且间隔布置的第四注入区和多个沿第二阱区长度方向排列且间隔布置的第五注入区，并且第四注入区和第五注入区位于不同的直线上并彼此错开一定距离，且第四注入区和第五注入区在第二阱区的宽度方向上彼此错开，其中，第一极和第二极分别为双向SCR器件的阳极和阴极。从而使得双向ESD保护器件在具有相对较高维持电压的同时，ESD鲁棒性对比之前的结构大大提高，可以提高一倍以上的ESD鲁棒性。
本发明的另一个方面还提供一种电子装置，包括用于IC芯片的双向ESD保护器件以及与所述双向ESD保护器件相连的电子组件。其中，该双向ESD保护器件包括形成在半导体衬底之上的双向SCR器件，该双向ESD保护器件包括：形成在所述半导体衬底中的具有第一导电类型的第一阱区和第二阱区；形成在所述半导体衬底中的具有第二导电类型的第三阱区，所述第三阱区位于所述第一阱区和第二阱区之间且与所述第一阱区和第二阱区位于同一直线上，所述第二导电类型与所述第一导电类型相反；在第一阱区中形成的不少于两个第一注入区和不少于两个第二注入区，所述第一注入区具有第一导电类型，所述第二注入区具有第二导电类型，所述第一注入区沿所述第一阱区的长度方向间隔排列，所述第二注入区沿所述第一阱区的长度方向间隔排列，所述第一注入区和所述第二注入区位于不同的直线上且彼此错开一定距离；在第二阱区中形成有不少于两个第四注入区和不少于两个第五注入区。第四注入区具有第一导电类型，例如为P型，第五注入区具有第二导电类型，例如为N型。所述第四注入区沿所述第二阱区的长度方向间隔排列，所述第五注入区沿所述第二阱区的长度方向间隔排列。形成在所述第一阱区和所述第三阱区的交界处以及所述第二阱区和所述第三阱区的交界处的第三注入区，所述第三注入区具有第一导电类型，所述第三注入区沿所述第一阱区/第二阱区的长度方向延伸；其中，所述第一注入区、第二注入区、第三注入区、第四注入区、第五注入区以及所述第一阱区、第二阱区和第三阱区构成双向SCR器件，所述第一阱区中的所述第一注入区和第二注入区用作所述双向SCR器件的第一极，所述第二阱区中的所述第四注入区和第五注入区用作所述双向 SCR器件的第二极，第一极和第二极分别为双向SCR器件的阳极和阴极。
其中，该电子组件，可以为分立器件、集成电路等任何电子组件。
本实施例的电子装置，可以是手机、平板电脑、笔记本电脑、上网本、游戏机、电视机、VCD、DVD、导航仪、照相机、摄像机、录音笔、MP3、MP4、PSP等任何电子产品或设备，也可为任何包括该半导体器件的中间产品。
在其中一个实施例中，所述电子装置包括手机，如图8所示，手机800的外部设置有包括在外壳801中的显示部分802、操作按钮803、外部连接端口804、扬声器805、话筒806等。
本发明实施例的电子装置，由于所包含的ESD保护器件可以在增加维持电压同时增大ESD鲁棒性，增加了电流泄放能力，因此可以实现更好的ESD防护效果。因此该电子装置同样具有类似的优点。
本发明已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本发明限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本发明并不局限于上述实施例，根据本发明的教导还可以做出更多种的变型和修改，这些变型和修改均落在本发明所要求保护的范围以内。本发明的保护范围由附属的权利要求书及其等效范围所界定。

Claims (15)

  1. 一种双向ESD保护器件，该双向ESD保护器件包括形成在半导体衬底上的双向SCR器件，该双向ESD保护器件包括：
    形成在所述半导体衬底中的具有第一导电类型的第一阱区和第二阱区；
    形成在所述半导体衬底中的具有第二导电类型的第三阱区，所述第三阱区位于所述第一阱区和第二阱区之间且与所述第一阱区和第二阱区位于同一直线上，所述第二导电类型与所述第一导电类型相反；
    在所述第一阱区中形成的不少于两个第一注入区和不少于两个第二注入区，在所述第二阱区中形成的不少于两个第四注入区和不少于两个第五注入区，所述第一注入区和所述第四注入区具有第一导电类型，所述第二注入区和所述第五注入区具有第二导电类型，所述第一注入区沿所述第一阱区的长度方向间隔排列，所述第二注入区沿所述第一阱区的长度方向间隔排列，所述第四注入区沿所述第二阱区的长度方向间隔排列，所述第五注入区沿所述第二阱区的长度方向间隔排列，所述第一注入区和所述第二注入区在第一阱区的长度方向上，以及第四注入区和第五注入区在第二阱区的长度方向上分别位于不同的直线上且彼此错开一定距离；以及
    形成在所述第一阱区和所述第三阱区的交界处，以及所述第二阱区和所述第三阱区的交界处的第三注入区，所述第三注入区具有第一导电类型，所述第三注入区沿所述第一阱区的长度方向延伸；
    其中，所述第一注入区、第二注入区、第三注入区、第四注入区、第五注入区以及所述第一阱区、第二阱区和第三阱区构成双向SCR器件，所述第一阱区中的所述第一注入区和第二注入区用作所述双向SCR器件的第一极，所述第二阱区中的所述第四注入区和第五注入区用作所述双向SCR器件的第二极，第一极和第二极分别为所述双向SCR器件的阳极和阴极。
  2. 根据权利要求1所述的双向ESD保护器件，其中所述第一注入区与所述第二注入区相比更靠近所述第三阱区，所述第四注入区与所述第五注入区相比更靠近所述第三阱区。
  3. 根据权利要求1所述的双向ESD保护器件，其中所述第二注入区与所述第一注入区相比更靠近所述第三阱区，所述第五注入区与所述第四注入区相比更靠近所述第三阱区。
  4. 根据权利要求1所述的双向ESD保护器件，其中所述第三注入区分别形成在所述第一阱区和所述第二阱区中，并且所述第三注入区紧邻所述第三阱区。
  5. 根据权利要求1所述的双向ESD保护器件，其中所述第三注入区均形成在所述第三阱区中，并且一个所述第三注入区紧邻所述第一阱区，另一个所述第三注入区紧邻第二阱区。
  6. 根据权利要求1所述的双向ESD保护器件，其中所述第三注入区分别横跨所述第一阱区和第三阱区以及横跨所述第二阱区和第三阱区。
  7. 根据权利要求1-6中的任一项所述的双向ESD保护器件，其中所述第一注入区和所述第二注入区在所述第一阱区的宽度方向上彼此错开，不处于同一直线上；所述第四注入区和所述第五注入区在所述第二阱区的宽度方向上彼此错开，不处于同一直线上。
  8. 根据权利要求1所述的双向ESD保护器件，其中双向ESD保护器件还包括：形成在所述半导体衬底与所述第一阱区和第二阱区之间的埋层，所述埋层具有第二导电类型。
  9. 根据权利要求1所述的双向ESD保护器件，其中所述第一导电类型为P型，所述第二导电类型为N型。
  10. 根据权利要求1所述的双向ESD保护器件，其中所述第一导电类型为N型，所述第二导电类型为P型。
  11. 根据权利要求8所述的双向ESD保护器件，其中所述埋层包括深N埋层。
  12. 根据权利要求1所述的双向ESD保护器件，其中相邻的第三注入区之间，以及第三注入区与第一注入区之间、第三注入区与第二注入区之间、第三注入区之间与第四注入区之间、第三注入区与第五注入区之间均形成有 隔离结构。
  13. 一种电子装置，包括如权利要求1-12的任意一项所述的双向ESD保护器件以及与所述双向ESD保护器件相连的电子组件。
  14. 根据权利要求13所述的双向ESD保护器件，其中所述电子装置包括手机、平板电脑、笔记本电脑、上网本、游戏机、电视机、VCD、DVD、导航仪、照相机、摄像机、录音笔、MP3、MP4、PSP。
  15. 根据权利要求13所述的双向ESD保护器件，其中所述电子组件包括分立器件、集成电路。
PCT/CN2020/107324 2019-09-26 2020-08-06 一种双向esd保护器件及电子装置 WO2021057275A1 (zh)

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