WO2021057055A1 - 集成封装结构 - Google Patents

集成封装结构 Download PDF

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Publication number
WO2021057055A1
WO2021057055A1 PCT/CN2020/092034 CN2020092034W WO2021057055A1 WO 2021057055 A1 WO2021057055 A1 WO 2021057055A1 CN 2020092034 W CN2020092034 W CN 2020092034W WO 2021057055 A1 WO2021057055 A1 WO 2021057055A1
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Prior art keywords
module
main substrate
shielding layer
package structure
integrated package
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PCT/CN2020/092034
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English (en)
French (fr)
Inventor
林耀剑
史海涛
陈雪晴
陈建
周莎莎
刘硕
Original Assignee
江苏长电科技股份有限公司
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Application filed by 江苏长电科技股份有限公司 filed Critical 江苏长电科技股份有限公司
Priority to US17/613,057 priority Critical patent/US20220223541A1/en
Publication of WO2021057055A1 publication Critical patent/WO2021057055A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Definitions

  • the present invention relates to the field of packaging technology, in particular to an integrated packaging structure.
  • the heterogeneous integrated package structure needs to be further high-density, miniaturization, and multi-dimensional.
  • high-height large-size packaged devices in the package structure one is a large-value inductance device, QFN, LGA or BGA, etc., and there are also cavity components such as filters that are more sensitive to stress; in addition, it includes various types
  • the module components of the chip are generally larger in area and volume, so the integrated packaging structure needs to be reasonably arranged to meet the needs of various devices and improve the overall integration.
  • the purpose of the present invention is to provide an integrated packaging structure to solve the current integrated packaging structure's need for further high-density, miniaturization, multi-dimensional, and multi-demand arrangement design.
  • an embodiment of the present invention provides an integrated package structure, which includes a main substrate, a first module, a second module, a cavity element, and a large-sized device.
  • the first surface of the main substrate and the second surface of the main substrate, the first module and the second module are stacked, the stacked first module and the second module and the cavity element,
  • the large-size devices are arranged horizontally on the first surface of the main substrate and are electrically connected to the main substrate respectively.
  • the integrated packaging structure further includes covering the first surface of the main substrate and encapsulating the first module, the second module, the cavity element, and the A plastic encapsulation layer of a large-size device, the encapsulation layer includes a first surface of the encapsulation layer away from the main substrate and a second surface of the encapsulation layer close to the main substrate.
  • the first surface of the encapsulation layer is provided with a cavity facing the At least a part of the opening groove extending from the element is positioned directly opposite to the cavity element.
  • the opening grooves are inverted trapezoidal opening grooves, and the inverted trapezoidal opening grooves are symmetrically distributed along the central axis of the cavity element.
  • the opening groove is a stepped opening groove located at the convex corner of the plastic encapsulation layer.
  • the integrated package structure further includes a first shielding layer and a second shielding layer, the first shielding layer covers the first module, and the second shielding layer covers the The first module, the second module, the cavity element, the large-size device, and the main substrate; the first shielding layer and the second shielding layer are made of different materials, or the first shielding layer A shielding layer and the second shielding layer have different structures, or the first shielding layer and the second shielding layer have different materials and structures.
  • the integrated package structure further includes a hollow interposer board, the interposer board is stacked between the first module and the main substrate and connects the first module to the main substrate.
  • a module is electrically connected to the main substrate, and the second module is located in the hollow part of the adapter board.
  • one end of the adapter plate is electrically connected to the first shielding layer, and the other end is electrically connected to the ground terminal of the main substrate.
  • the transfer board is an organic substrate-type transfer board, an encapsulation-type transfer board, or a heterogeneous laminated-type transfer board for stacking and rewiring.
  • the integrated package structure further includes a third module set on the second surface of the main substrate, at least a part of the third module is positioned directly opposite to the second module .
  • the second module is an SOC chip
  • the third module is a storage module
  • the integrated package structure further includes a third shielding layer covering the SOC chip and covering The fourth shielding layer of the storage module.
  • the main substrate is an organic substrate, or a homogenous or heterogeneous laminate using a film-coated or glue-coated wafer and board-level stacking and rewiring.
  • the present invention has the beneficial effects that: on the main substrate of the integrated packaging structure, the module components are stacked and then horizontally arranged with large-size devices, cavity components, etc., and the overall arrangement is reasonable to integrate
  • the packaging structure is further miniaturized and denser and can meet the packaging requirements of various packaged devices.
  • FIG. 1 is a schematic diagram of an integrated package structure in Embodiment 1 of the present invention.
  • FIG. 2 is a schematic diagram of the structure of the first module and the first shielding layer in Embodiment 1 of the present invention
  • FIG. 3 is a schematic diagram of the structure of the second module and the third shielding layer in Embodiment 1 of the present invention.
  • FIG. 4 is a schematic diagram of the structure of the hollow cavity element in the first embodiment of the present invention.
  • FIG. 5 is a schematic diagram of the structure of a large-sized device in Embodiment 1 of the present invention.
  • FIG. 6 is a schematic diagram of the structure of the adapter board in Embodiment 1 of the present invention.
  • FIG. 7 is a schematic diagram of an integrated package structure in Embodiment 2 of the present invention.
  • Embodiment 8 is a schematic diagram of the integrated package structure in Embodiment 3 of the present invention.
  • FIG. 9 is a schematic diagram of the structure of the third module and the fourth shielding layer in Embodiment 3 of the present invention.
  • FIG. 10 is a schematic diagram of an integrated package structure in Embodiment 4 of the present invention.
  • the device can be oriented in other ways (rotated by 90 degrees or other orientations), and the space-related descriptors used herein are explained accordingly.
  • the side of the substrate close to the chip is the front side of the substrate, and the side far away from the chip is the reverse side of the substrate; the direction of the plane of the substrate is the horizontal direction, and the thickness direction of the substrate is the vertical direction.
  • Direction or vertical direction is the case where the side of the substrate close to the chip is the front side of the substrate, and the side far away from the chip.
  • an embodiment of the present invention provides an integrated package structure, which includes a main substrate 2, a first module 11, a second module 12, a cavity element 14, and a large-size device 15.
  • the main substrate 2 includes a first surface 21 of a main substrate and a second surface 22 of the main substrate that are disposed oppositely.
  • the first module 11 and the second module 12 are stacked, and the stacked first module 11 and The second module 12, the cavity element 14 and the large-size device 15 are arranged horizontally on the first surface 21 of the main substrate and are electrically connected to the main substrate 2 respectively.
  • the main substrate 2 includes a first surface 21 of the main substrate and a second surface 22 of the main substrate opposite to each other.
  • the first surface 21 of the main substrate is mainly used for arranging various package components, and the second surface of the main substrate is opposite to the second surface.
  • the surface 22 is mainly used to connect the PCB board and other devices under the integrated packaging structure; on the first surface 21 of the main substrate, the first module 11 and the second module 12 are stacked and arranged to form a stacked module combination, cavity element 14 and the large-size device 15 and the stack module combination are arranged horizontally, and the cavity element 14 and the large-size device 15 and the stack module combination are electrically connected to the main substrate 2; thus, by stacking at least once, To reduce the area and space occupied by two or more modules in the integrated package structure, and at the same time arrange the high-height large-size components 15 and the stress-sensitive cavity components 14 horizontally with the stacked modules. Reasonably reduce the overall height of the packaged components inside the integrated package structure, making the overall space of the integrated package structure more compact and the internal structure more integrated.
  • the stacking form of the first module 11 and the second module 12 is not limited, and the first module 11 may be provided on the first surface 21 of the main substrate, and the second module 12 may be stacked on the first module 11 It is also possible that the second module 12 is provided on the first surface 21 of the main substrate, and the first module 11 is stacked above the second module 12.
  • the horizontal arrangement of the cavity element 14 and the large-size device 15 combined with the stacked module is not limited.
  • the cavity element 14 and the large-size device 15 can be horizontally arranged on both sides of the stacked module combination or at the same time. Distributed on one side of the stacking module assembly.
  • the large-size device 15 may be one or more of large-value inductance devices, QFN, LGA, or BGA and other high-height large-size packaged devices, and the details are not limited; the cavity element 14 may be a filter, etc. Package the device.
  • the integrated packaging structure further includes covering the first surface 21 of the main substrate and encapsulating the first module 11, the second module 12, the cavity element 14, and the large-size device 15 of the encapsulation layer 4, the encapsulation layer 4 includes a first surface 41 of the encapsulation layer away from the main substrate 2 and a second surface 42 of the encapsulation layer close to the main substrate 2.
  • the first surface 41 of the encapsulation layer is provided with At least part of the position of the opening groove 6 extending toward the cavity element 14 is directly opposite to the cavity element 14.
  • the opening groove 6 is an inverted trapezoidal opening groove 6, and the inverted trapezoidal opening groove 6 is symmetrically distributed along the central axis of the cavity element 14.
  • the plastic encapsulation layer 4 covers the first surface 21 of the main substrate, and simultaneously encapsulates all the packaging components on the first surface 21 of the main substrate, including the first module 11, the second module 12, the cavity element 14, and Large-size device 15; the upper surface of the plastic encapsulation layer 4 away from the main substrate 2 is the first surface 41 of the plastic encapsulation layer, and the lower surface close to the main substrate 2 is the second surface 42 of the plastic encapsulation layer.
  • the cavity of the cavity element 14 is generally set upward.
  • the first surface 41 of the plastic encapsulation layer corresponds to the position of the cavity element 14
  • the opening groove 6 is opened, and at least part of the opening groove 6 is directly above the cavity element 14, so that the plastic encapsulation layer 4 above the cavity element 14 is hollowed out, thereby reducing the impact of the plastic encapsulation layer 4 on the cavity element due to thermal expansion and contraction.
  • the stress of the hollow cavity 14 prevents the cavity element 14 from being damaged by undesirable stress.
  • the opening groove 6 is completely located above the cavity element 14 and corresponds to the position of the cavity, that is, the opening groove 6 is symmetrically distributed along the central axis of the cavity element 14, so that the cavity element 14 can be evenly lowered.
  • the stress relief effect is the best; at the same time, the shape of the opening groove 6 is an inverted trapezoid. After the plastic sealing layer 4 is formed, the inverted trapezoidal opening groove 6 makes the demolding process quick and convenient.
  • the shape of the opening groove 6 is not limited, as long as it is set to facilitate the demolding operation.
  • the opening groove 6 may also be formed by laser grooving after the molding layer 4 is formed.
  • the opening grooves 6 can also be arranged in the form of a porous array.
  • the opening groove 6 is a stepped opening groove 6 located at the convex corner of the plastic encapsulation layer 4.
  • the height of the stepped surface of the stepped opening groove 6 is not limited, and the stepped opening groove 6 can be located in the cavity element 14
  • the height of the step surface is higher than the height of the primary packaging surface of the cavity element 14
  • the step-shaped opening groove 6 can also be provided on the outside of the cavity element 14 in a way of avoiding, so that the height of the step surface is lower than that of the cavity element 14 The height of the package surface in 14.
  • the integrated package structure further includes a first shielding layer 81 and a second shielding layer 82, the first shielding layer 81 covers the first module 11, and the second shielding layer 82 covers the first The module 11, the second module 12, the cavity element 14, the large-size device 15, and the main substrate 2; the first shielding layer 81 and the second shielding layer 82 are made of different materials , Or the first shielding layer 81 and the second shielding layer 82 have different structures, or the first shielding layer 81 and the second shielding layer 82 have different materials and structures.
  • the integrated package structure further includes a hollow interposer board 16, which is stacked between the first module 11 and the main substrate 2 and connects the first module 11 is electrically connected to the main substrate 2, and the second module 12 is located in the hollow part of the adapter board 16.
  • a first shielding layer 81 is provided on the periphery of the first module 11, and the first shielding layer 81 covers the first module 11 to prevent interference; the entire periphery of the integrated packaging structure is provided with a second shielding layer 82.
  • the second shielding layer 82 covers all the packaged components on the main substrate 2.
  • the second shielding layer 82 is electrically connected to the ground terminal of the main substrate 2 to achieve electromagnetic shielding and protection for the packaged devices on the main substrate 2.
  • the structure of the shielding layer is not limited, it can be a single layer of metal, multiple layers of metal, conductive glue or metal cover, etc.; the materials of the two shielding layers are also not limited, and they can be aluminum, copper, chromium One or more combinations of, tin, gold, silver, nickel or stainless steel.
  • the structure type and material type of the first shielding layer 81 and the second shielding layer 82 are not limited. They can be of different materials, they can be of different structures, or the materials and structures of the two are different, in order to achieve the best EMI shielding effect and best cost.
  • the integrated package structure further includes an adapter plate 16, which is a hollow structure; the first module 11 and the adapter plate 16 are stacked on the main substrate 2, and the second module 12 is disposed on the adapter plate.
  • the hollow structure adapter plate 16 can not only nest the second module 12 and support the first module 11, but also electrically connect the first module 11 and the main substrate 2 to be arranged on the first module of the main substrate as a whole.
  • One surface 21 makes the package structure compact and complete electrical functions.
  • the form of the adapter plate 16 is not limited, and it can be a frame-shaped adapter plate, a U-shaped adapter plate or an I-shaped adapter plate; when the adapter plate 16 is an I-shaped adapter plate, the number is not limited, and it can be It is two or more.
  • one end of the transfer 16 board is electrically connected to the first shielding layer 81 and the other end is electrically connected to the ground terminal of the main substrate 2.
  • the transfer board 16 can also become a component of the EMI shielding protection function structure; when the transfer board 16 is stacked with the first module 11 and the first module 11 is electrically connected to the main substrate 2, the transfer The board 16 can be electrically connected to the first shielding layer 81, and the adapter plate 16 can be electrically connected to the ground terminal on the main substrate 2; thus, the first shielding layer 81 can be electrically connected to the ground terminal on the main substrate 2 Therefore, the first shielding layer 81 can effectively perform EMI electromagnetic shielding on the first module 11 to achieve a protection function.
  • the transfer board 16 is an organic substrate-type transfer board, an encapsulation-type transfer board, or a heterogeneous laminated-type transfer board for stacking and rewiring.
  • the type of the adapter plate 16 is not limited, and it may be one of the above three types.
  • the encapsulation material used in the encapsulation adapter plate can be epoxy resin or phenolic resin-based composite materials containing fillers.
  • the type may be one or more or a combination of the above three types.
  • the three-dimensional transfer structure in the transfer board can be designed according to actual conditions, and can be I-shaped or T-shaped; the transfer board can be designed to have only electrical switching wiring, or embedded devices.
  • the integrated package structure further includes a third module 13 provided on the second surface 22 of the main substrate, and at least a part of the third module 13 is positioned directly opposite to the second module 12.
  • the second module 12 is an SOC chip
  • the third module 13 is a storage module
  • the integrated package structure further includes a third shielding layer 83 covering the SOC chip and covering the storage module The fourth shielding layer 84 of the group.
  • the second surface 22 of the main substrate is further provided with a third module 13, and the position of the third module 13 at least partially corresponds to the position of the second module 12, so that a plurality of packaged chips can be Arranged on both sides of the main substrate 2 is not limited to one side, and the area and size of the integrated package structure can be further reduced.
  • the second module 12 and the third module 13 are the SOC chip 12 and the storage module 13 respectively.
  • the SOC chip stacked on the first surface 21 of the main substrate is further covered with a third shielding layer 83, and the memory module provided on the second surface 22 of the main substrate is also covered with a fourth shielding layer 84.
  • the first shielding layer 81, the second shielding layer 82, the third shielding layer 83 and the first module, the main module, the SOC chip and the storage module are covered.
  • the material and structure of the four shielding layer 84 are not limited, and can be specifically selected according to the application of multiple frequencies and actual conditions, so as to use the same or different materials or structures or various combinations to achieve the best EMI effect of the integrated package structure as a whole And cost.
  • the arrangement position of the SOC chip 12 and the storage module 13 can also be adjusted according to the dimensions of the two, the actual size of the space inside the integrated package structure, the specific process, and the best cost.
  • the arrangement positions of the first module 11 and the storage module 13 can also be adjusted according to factors such as their own size, the actual space inside the integrated packaging structure, the specific process, and the best cost.
  • the second surface 22 of the main substrate may also be provided with a connecting portion 9 for connecting the lower PCB board.
  • the connecting portion 9 may be a solder ball 9A or an adapter board 9B to electrically connect the main substrate 2 and the PCB board;
  • the connecting portions 9 may be horizontally arranged on both sides of the third module 13 to support the main substrate 2 and all the package components on the main substrate 2.
  • the second surface 22 of the main substrate can also be provided with a plastic encapsulation layer on the second surface of the main substrate, and this plastic encapsulation layer can at least encapsulate all sides of the third module 13 and all sides of the connecting portion 9.
  • the main substrate 2 is an organic substrate, or a homogenous or heterogeneous laminate that uses a film or glue-coated wafer and board-level stacking and rewiring.
  • the type of the main substrate 2 is not limited, and it can be an organic substrate.
  • the organic substrate is formed by laminating multiple copper layers and resin, and then through drilling, electroless copper plating, copper electroplating, etching and other processing to obtain the required Circuit pattern;
  • the main substrate 2 can also be a homogeneous or heterogeneous laminate.
  • the homogeneous or heterogeneous laminate is composed of homogenous or heterogeneous organic dielectric materials and metal lines, which can be realized by rewiring the lines layer by layer Circuit graphics.
  • the main substrate 2 includes a first surface 21 of the main substrate and a second surface 22 of the main substrate disposed oppositely.
  • the frame-shaped adapter plate 16 is nested with the second module 12 and then stacked and arranged with the first module 11.
  • the cavity element 14 and the large-size device 15 are arranged horizontally on the stacked first module 11 and the second module. Group 12 on both sides.
  • the first shielding layer 81 covers the first module 11, and the second shielding layer 82 covers the main substrate 2 and all the package components on the main substrate 2. At the same time, the second shielding layer 82 is electrically connected to the ground terminal of the main substrate 2. The shielding layer 81 is also electrically connected to the ground terminal on the main substrate 2 through the adapter plate 16.
  • the plastic encapsulation layer 4 covers the first surface 21 of the main substrate and encapsulates all the packaging components on the first surface 21 of the main substrate.
  • the first surface 41 of the plastic encapsulation layer is formed with an opening groove 6 at least partially facing the cavity element 14.
  • the large-size device 15 is a large-value inductance device
  • the cavity element 14 is a filter element
  • the second module 12 is an SOC chip
  • the first module 11 is provided with two or more packaging elements.
  • the integrated package structure in this embodiment is different from Embodiment 1.
  • the opening groove 6 is a stepped opening groove, and the stepped opening groove 6 is located at two convex corners of the plastic encapsulation layer 4, namely two
  • the step-shaped opening groove 6 can be formed by cutting two convex corners of the plastic encapsulation layer 4.
  • the upper surface of the cavity element 14 is the primary packaging surface
  • the stepped opening groove 6 provided near the cavity element 14 is located above the primary packaging surface
  • the height of the step surface is higher than the height of the upper surface of the cavity element 14 to reduce
  • the plastic molding compound above the surface of the primary encapsulation of the cavity element 14 reduces the stress effect of the plastic encapsulation layer on the cavity element 14 under the force of thermal expansion and contraction.
  • a stepped opening groove 6 is also provided near the large-sized device 15.
  • the stepped opening groove 6 is located outside the large-sized device 15, and the height of the stepped surface is lower than the height of the upper surface of the large-sized device 15, thereby reducing the large size.
  • the plastic packaging material on the outside of the device 15 reduces the effect of stress.
  • the integrated package structure in this embodiment is different from Embodiment 1.
  • the second surface 22 of the main substrate is also provided with a third module corresponding to at least a part of the position of the second module 12 13.
  • Connecting parts 9 for connecting the lower PCB board are arranged horizontally on both sides of the third module 13.
  • the first surface 41 of the plastic encapsulation layer is not provided with an opening groove 6.
  • the connecting portion 9 is a solder ball 9A
  • the third module 13 is a memory chip.
  • the second surface 22 of the main substrate can also be provided with a plastic encapsulation layer (not shown in the figure) on the second surface of the main substrate, and this plastic encapsulation layer can at least encapsulate all sides of the third module 13 and all sides of the connecting portion 9.
  • the integrated package structure in this embodiment is different from the embodiment 3 in that the connecting portion 9 is an adapter board 9B.
  • the main substrate 2 includes a first surface 21 of the main substrate and a second surface 22 of the main substrate disposed oppositely.
  • the first module 11 and the second module 12 are stacked and then combined with the empty
  • the cavity elements 14 and the large-size devices 15 are horizontally arranged on the first surface 21 of the main substrate. Therefore, through reasonable stacking and horizontal arrangement, the overall space of the integrated package structure can be made more compact and the internal structure more integrated.

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Abstract

本发明涉及的一种集成封装结构，所述集成封装结构包括主基板、第一模组、第二模组、空腔元件及大尺寸器件，所述主基板包括相对设置的主基板第一表面与主基板第二表面，所述第一模组与所述第二模组堆叠，堆叠后的所述第一模组及所述第二模组与所述空腔元件、所述大尺寸器件水平排布于所述主基板第一表面且分别与所述主基板电性连接。通过上述设置，可解决目前集成封装结构需要进一步高密度、小型化、多维化、多需求排布设计的需求。

Description

集成封装结构
本申请要求了申请日为2019年09月25日，申请号为201910909470.2，发明名称为“集成封装结构”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及封装技术领域，尤其涉及一种集成封装结构。
背景技术
随着半导体技术的发展，尤其5G通信时代的到来，不但对电子器件的需求越来越微型化、轻薄化，且对异质集成不同元件的需求越来越大，因此半导体异质集成封装逐渐成为封装的趋势。
为满足多频率和多带宽的应用，异质集成封装结构需要进一步高密度、小型化、多维化。封装结构中存在高度较高的大尺寸封装器件，一种是大数值电感器件、QFN、LGA或BGA等等，同时还会存在对应力较为敏感的滤波器等空腔元件；此外，包含各类芯片的模组组件一般面积与体积也较大，因而集成封装结构需要进行合理排布，以满足各种器件需求并提高整体集成度。
发明内容
本发明的目的在于提供一种集成封装结构，以解决目前集成封装结构需要进一步高密度、小型化、多维化、多需求排布设计的需求。
为了实现上述发明目的之一，本发明一实施方式提供一种集成封装结构，包括主基板、第一模组、第二模组、空腔元件及大尺寸器件，所述主基板包括相对设置的主基板第一表面与主基板第二表面，所述第一模组与所述第二模组堆叠，堆叠后的所述第一模组及所述第二模组与所述空腔元件、所述大尺寸器件水平排布于所述主基板第一表面且分别与所述主基板电性连接。
作为本发明一实施方式的进一步改进，所述集成封装结构还包括覆盖所述主基板第一表面且包封所述第一模组、所述第二模组、所述空腔元件及所述大尺寸器件的塑封层，所述塑封层包括远离所述主基板的塑封层第一表面及靠近所述主基板的塑封层第二表面，所述塑封层第一表面开设有朝向所述空腔元件延伸的开口槽，至少部分所述开口槽的位置正对所述空腔元件。
作为本发明一实施方式的进一步改进，所述开口槽为倒梯形开口槽，且所述倒梯形开口槽沿着所述空腔元件的中轴线对称分布。
作为本发明一实施方式的进一步改进，所述开口槽为位于所述塑封层凸角的台阶形开口槽。
作为本发明一实施方式的进一步改进，所述集成封装结构还包括第一屏蔽层与第二屏蔽层，所述第一屏蔽层覆盖所述第一模组，所述第二屏蔽层覆盖所述第一模组、所述第二模组、所述空 腔元件、所述大尺寸器件以及所述主基板；所述第一屏蔽层与所述第二屏蔽层的材料不同，或所述第一屏蔽层与所述第二屏蔽层的结构不同，或所述第一屏蔽层与所述第二屏蔽层的材料和结构均不同。
作为本发明一实施方式的进一步改进，所述集成封装结构还包括中空的转接板，所述转接板堆叠于所述第一模组与所述主基板两者之间且将所述第一模组与所述主基板电性连接，所述第二模组位于所述转接板的中空部分。
作为本发明一实施方式的进一步改进，所述转接板的一端与所述第一屏蔽层电性连接而另一端与所述主基板的接地端电性连接。
作为本发明一实施方式的进一步改进，所述转接板为有机基板类转接板或包封类转接板或堆叠重布线的异质叠层类转接板。
作为本发明一实施方式的进一步改进，所述集成封装结构还包括设于所述主基板第二表面的第三模组，至少部分所述第三模组的位置正对所述第二模组。
作为本发明一实施方式的进一步改进，所述第二模组为SOC芯片，所述第三模组为存储模组，所述集成封装结构还包括覆盖所述SOC芯片的第三屏蔽层及覆盖所述存储模组的第四屏蔽层。
作为本发明一实施方式的进一步改进，所述主基板为有机基板，或者为采用贴膜或涂胶的晶圆与板级堆叠重布线的同质或异质叠层。
与现有技术相比，本发明的有益效果在于：在集成封装结构的主基板上，将模组组件堆叠后再与大尺寸器件、空腔元件等进行水平排布，整体合理布局以将集成封装结构进一步小型化、密集化并可满足各类封装器件的封装需求。
附图说明
图1是本发明实施例1中集成封装结构的示意图；
图2是本发明实施例1中第一模组与第一屏蔽层的结构示意图；
图3是本发明实施例1中第二模组与第三屏蔽层的结构示意图；
图4是本发明实施例1中空腔元件的结构示意图；
图5是本发明实施例1中大尺寸器件的结构示意图；
图6是本发明实施例1中转接板的结构示意图；
图7是本发明实施例2中集成封装结构的示意图；
图8是本发明实施例3中集成封装结构的示意图；
图9是本发明实施例3中第三模组与第四屏蔽层的结构示意图；
图10是本发明实施例4中集成封装结构的示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合本申请具体实施方式及相应的附图对本申请技术方案进行清楚、完整地描述。显然，所描述的实施方式仅是本申请一部分实施方式，而不是全部的实施方式。基于本申请中的实施方式，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施方式，都属于本申请保护的范围。
下面详细描述本发明的实施方式，实施方式的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本发明，而不能理解为对本发明的限制。
设备可以以其他方式被定向(旋转90度或其他朝向)，并相应地解释本文使用的与空间相关的描述语。如在本发明中，为方便描述，在封装结构中，基板靠近芯片的一侧为基板正面，远离芯片的一侧为基板反面；基板所处平面的方向为水平方向，基板厚度方向为竖直方向或垂直方向。
如图1至图6所示，本发明一实施例提供了一种集成封装结构，包括主基板2、第一模组11、第二模组12、空腔元件14及大尺寸器件15，所述主基板2包括相对设置的主基板第一表面21与主基板第二表面22，所述第一模组11与所述第二模组12堆叠，堆叠后的所述第一模组11及所述第二模组12与所述空腔元件14、所述大尺寸器件15水平排布于所述主基板第一表面21且分别与所述主基板2电性连接。
具体的，集成封装结构中，主基板2包括主基板第一表面21及相对设置的主基板第二表面22，主基板第一表面21主要用于设置各类封装元件，相对的主基板第二表面22主要用于连接集成封装结构下方的PCB板等器件；在主基板第一表面21上，第一模组11与第二模组12堆叠排布，以形成堆叠模组组合，空腔元件14及大尺寸器件15与这个堆叠模组组合呈水平排布，且空腔元件14及大尺寸器件15与这个堆叠模组组合分别与主基板2电性连接；由此，通过至少一次堆叠，来减少集成封装结构中的两个或多个模组占用面积和空间，同时将高度较高的大尺寸器件15及对应力敏感的空腔元件14与堆叠后的模组组合水平排布，可合理降低集成封装结构内部封装元件组合后的整体高度，使得集成封装结构整体空间更为紧凑、内部结构更加集成化。
可选的，第一模组11与第二模组12堆叠的形式不限，可以是第一模组11设于主基板第一表面21，第二模组12堆叠于第一模组11上方；也可以是第二模组12设于主基板第一表面21，第一模组11堆叠于第二模组12上方。同时，空腔元件14及大尺寸器件15与堆叠模组组合的水平排布形式不限，空腔元件14及大尺寸器件15可以分别水平排布于堆叠模组组合的两侧或同时水平排布于堆叠模组组合的一侧。
可选的，大尺寸器件15可以是大数值电感器件、QFN、LGA或BGA等高度较高的大尺寸封装 器件中的一种或多种，具体不限；空腔元件14可以是滤波器等封装器件。
进一步的，所述集成封装结构还包括覆盖所述主基板第一表面21且包封所述第一模组11、所述第二模组12、所述空腔元件14及所述大尺寸器件15的塑封层4，所述塑封层4包括远离所述主基板2的塑封层第一表面41及靠近所述主基板2的塑封层第二表面42，所述塑封层第一表面41开设有朝向所述空腔元件14延伸的开口槽6，至少部分所述开口槽6的位置正对所述空腔元件14。
进一步的，所述开口槽6为倒梯形开口槽6，且所述倒梯形开口槽6沿着所述空腔元件14的中轴线对称分布。
具体的，塑封层4覆盖设于主基板第一表面21，同时将主基板第一表面21的所有封装元件全部包封，包括第一模组11、第二模组12、空腔元件14及大尺寸器件15；塑封层4远离主基板2的上表面为塑封层第一表面41，而贴近主基板2的下表面为塑封层第二表面42。
空腔元件14的空腔一般朝上设置，为了防止热胀冷缩作用下塑封层4对空腔元件14产生较大的应力破坏，在塑封层第一表面41对应空腔元件14的位置处开设有开口槽6，且至少部分开口槽6在空腔元件14的正上方，使得空腔元件14上方的塑封层4被挖空，从而减少热胀冷缩作用下塑封层4对空腔元件14中空腔的应力作用，避免空腔元件14受到不良应力破坏。
本实施例中，开口槽6完全位于空腔元件14的上方，并与空腔位置对应，即开口槽6沿着空腔元件14的中轴线对称分布，由此，可均匀降低空腔元件14受到的应力作用，应力缓解效果最佳；同时开口槽6形状为倒梯形，塑封层4塑封形成后，倒梯形的开口槽6使得脱模工艺快速方便。
可选的，开口槽6形状不限，只要设置成方便脱模操作即可，开口槽6也可以是塑封层4形成之后通过激光开槽形成。或者，开口槽6也可设置为多孔阵列形式。
进一步的，所述开口槽6为位于所述塑封层4凸角的台阶形开口槽6。
具体的，也可在塑封层4的凸角进行切割，以形成台阶形状的开口槽6；其中，台阶形开口槽6的台阶面高度不限，台阶形开口槽6可位于空腔元件14的上方，使得台阶面高度高于空腔元件14中一次封装表面的高度；也可将台阶形开口槽6以避让的形式设于空腔元件14的外侧，使得台阶面的高度低于空腔元件14中一次封装表面的高度。
进一步的，所述集成封装结构还包括第一屏蔽层81与第二屏蔽层82，所述第一屏蔽层81覆盖所述第一模组11，所述第二屏蔽层82覆盖所述第一模组11、所述第二模组12、所述空腔元件14、所述大尺寸器件15以及所述主基板2；所述第一屏蔽层81与所述第二屏蔽层82的材料不同，或所述第一屏蔽层81与所述第二屏蔽层82的结构不同，或所述第一屏蔽层81与所述 第二屏蔽层82的材料和结构均不同。
进一步的，所述集成封装结构还包括中空的转接板16，所述转接板16堆叠于所述第一模组11与所述主基板2两者之间且将所述第一模组11与所述主基板2电性连接，所述第二模组12位于所述转接板16的中空部分。
具体的，第一模组11的外围设有第一屏蔽层81，第一屏蔽层81覆盖第一模组11以防止其受到干扰；集成封装结构整体的外围设有第二屏蔽层82，第二屏蔽层82覆盖主基板2上的所有封装元件。同时，第二屏蔽层82与主基板2的接地端电性连接，以实现对主基板2上的封装器件的电磁屏蔽与保护作用。按照具体的多种频率应用，屏蔽层的结构不限，可以是单层金属、多层金属层、导电胶或者金属罩子等；两个屏蔽层的材料也不限，可以是铝、铜、铬、锡、金、银、镍或不锈钢的一种或多种组合。第一屏蔽层81与第二屏蔽层82两者的结构类型与材料类型不限，可以是两者材料不同，可以是两者结构不同，或者两者的材料和结构均不同，以达到最佳的EMI屏蔽效果和最佳成本。
如图7所示，集成封装结构还包括转接板16，转接板16为中空结构；第一模组11与转接板16堆叠于主基板2上，第二模组12设于转接板16的中空部分的位置，即在主基板第一表面21上，转接板16嵌套第二模组12，且第一模组11堆叠于这个嵌套结构上；同时，转接板16设有导电结构，可将第一模组11与主基板2两者电性连接。
由此，中空结构的转接板16不仅可以嵌套第二模组12、支撑第一模组11，还可以将第一模组11与主基板2电性连接，整体排布于主基板第一表面21，使得封装结构集成紧凑、电气功能完整。
可选的，转接板16形式不限，可以是框形转接板、U型转接板或I型转接板；当转接板16为I型转接板时，数量不限，可以是两个或多个。
进一步的，所述转接16板的一端与所述第一屏蔽层81电性连接而另一端与所述主基板2的接地端电性连接。
具体的，转接板16还可以成为EMI屏蔽保护功能结构中的组成部分；当转接板16与第一模组11堆叠且将第一模组11与主基板2电性连接时，转接板16可与第一屏蔽层81电性连接，同时转接板16与主基板2上的接地端电性连接；由此，第一屏蔽层81可与主基板2上的接地端电性连接，从而第一屏蔽层81可有效地对第一模组11进行EMI电磁屏蔽，以实现保护功能。
进一步的，所述转接板16为有机基板类转接板或包封类转接板或堆叠重布线的异质叠层类转接板。
具体的，转接板16的类型不限，可以是上述三种类型中的一种。其中，包封类转接板采用 的包封材料可以是环氧树脂或酚醛树脂基等含填料的复合材料。
可选的，转接板16的数量为两个或多个时，其类型可以是上述三种类型中的一种或多种或多种的组合。
可选的，转接板中的三维转接结构可以依据实际情况设计，可为工型或T型；转接板可以设计为仅有电学转接布线,也可以内埋器件。
进一步的，所述集成封装结构还包括设于所述主基板第二表面22的第三模组13，至少部分所述第三模组13的位置正对所述第二模组12。
进一步的，所述第二模组12为SOC芯片，所述第三模组13为存储模组，所述集成封装结构还包括覆盖所述SOC芯片的第三屏蔽层83及覆盖所述存储模组的第四屏蔽层84。
如图8至图9所示，主基板第二表面22还设置有第三模组13，第三模组13的位置与第二模组12位置至少部分对应，由此，多个封装芯片可排布于主基板2的两侧，不仅仅限于一侧，集成封装结构的面积和尺寸可进一步缩小。
本发明实施例中，第二模组12与第三模组13分别为SOC芯片12与存储模组13。其中，堆叠于主基板第一表面21的SOC芯片上还覆盖有第三屏蔽层83，设于主基板第二表面22的存储模组上还覆盖有第四屏蔽层84。
为满足集成封装结构多频率、多带宽的应用，第一模组、主模组、SOC芯片与存储模组上覆盖的第一屏蔽层81、第二屏蔽层82、第三屏蔽层83与第四屏蔽层84的材料和结构不限，可根据多频率的应用及实际情况进行具体选择，以采用相同或不同的材料或结构或各种组合形式，来达到集成封装结构整体的最佳EMI效果和成本。
此外，SOC芯片12与存储模组13的排布位置也可以根据两者自身尺寸、集成封装结构内部的实际空间大小、具体工艺以及成本最佳等因素进行对调调整。同样的，第一模组11与存储模组13的排布位置也可以根据两者自身尺寸、集成封装结构内部的实际空间大小、具体工艺以及成本最佳等因素进行对调调整。
可选的，主基板第二表面22还可设有用于连接下方PCB板的连接部9，连接部9可以是锡球9A或转接板9B，以将主基板2与PCB板电性连接；连接部9可以水平排布于第三模组13的两侧，以支撑主基板2及主基板2上方的所有封装元件。同时，主基板第二表面22还可设置主基板第二表面塑封层，且这个塑封层至少可包封第三模组13的所有侧面以及连接部9的所有侧面。
进一步的，所述主基板2为有机基板，或者为采用贴膜或涂胶的晶圆与板级堆叠重布线的同质或异质叠层。
具体的，主基板2的类型不限，可以是有机基板，有机基板由多层铜层和树脂压合而成，然后通过钻孔、化学镀铜、电镀铜、蚀刻等加工可得到所需的电路图形；主基板2也可以是同质或异质叠层，同质或异质叠层由同质或异质的有机介电材料和金属线路构成，可一层层地重布线线路来实现电路图形。
为方便理解，以下对示例进行具体描述：
实施例1
如图1至图6所示，本实施例中的集成封装结构中，主基板2包括主基板第一表面21及相对设置的主基板第二表面22。
框形的转接板16嵌套第二模组12后与第一模组11堆叠排布，空腔元件14及大尺寸器件15水平排布于堆叠后的第一模组11与第二模组12两侧。
第一屏蔽层81覆盖第一模组11，第二屏蔽层82覆盖主基板2及主基板2上的所有封装元件；同时第二屏蔽层82与主基板2的接地端电性连接，第一屏蔽层81通过转接板16也与主基板2上的接地端电性连接。
塑封层4覆盖主基板第一表面21且包封主基板第一表面21上的所有封装元件。塑封层第一表面41形成有至少部分位置正对空腔元件14的开口槽6。
其中，大尺寸器件15为大数值电感器件，空腔元件14为滤波器元件，第二模组12为SOC芯片，第一模组11内设有两个或多个封装元件。
实施例2
如图7所示，本实施例中的集成封装结构与实施例1不同的是，开口槽6为台阶形开口槽，且台阶形开口槽6位于塑封层4的两个凸角，即两个台阶形开口槽6可由塑封层4的两个凸角切割形成。
其中，空腔元件14的上表面为一次封装表面，靠近空腔元件14设置的台阶形开口槽6位于一次封装表面的上方，台阶面的高度高于空腔元件14上表面的高度，以减少空腔元件14中一次封装表面上方的塑封料，降低塑封层在热胀冷缩作用力下对空腔元件14的应力影响。
此外，靠近大尺寸器件15位置也设置有台阶形开口槽6，台阶形开口槽6位于大尺寸器件15的外侧，且台阶面的高度低于大尺寸器件15上表面的高度，从而减少大尺寸器件15外侧的塑封料，降低应力作用的影响。
实施例3
如图8至图9所示，本实施例中的集成封装结构与实施例1不同的是，主基板第二表面22还设置有与第二模组12位置至少部分位置对应的第三模组13，第三模组13的两侧水平排布有 用于连接下方PCB板的连接部9。同时，塑封层第一表面41未设开口槽6。
其中，连接部9为锡球9A，第三模组13为存储芯片。
同时，主基板第二表面22还可设置主基板第二表面塑封层(图中未示出)，且这个塑封层至少可包封第三模组13的所有侧面以及连接部9的所有侧面。
实施例4
如图10所示，本实施例中的集成封装结构与实施例3不同的是，连接部9为转接板9B。
综上，本发明提供的集成封装结构中，主基板2包括主基板第一表面21及相对设置的主基板第二表面22，将第一模组11与第二模组12堆叠后再与空腔元件14及大尺寸器件15水平排布于主基板第一表面21，由此，通过合理的堆叠与水平排布，可使得集成封装结构整体空间更为紧凑、内部结构更加集成化。
应当理解，虽然本说明书按照实施方式加以描述，但并非每个实施方式仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施方式中的技术方案也可以经适当组合，形成本领域技术人员可以理解的其他实施方式。
上文所列出的一系列的详细说明仅仅是针对本发明的可行性实施方式的具体说明，并非用以限制本发明的保护范围，凡未脱离本发明技艺精神所作的等效实施方式或变更均应包含在本发明的保护范围之内。

Claims (11)

  1. 一种集成封装结构，包括主基板、第一模组、第二模组、空腔元件及大尺寸器件，所述主基板包括相对设置的主基板第一表面与主基板第二表面，其特征在于，所述第一模组与所述第二模组堆叠，堆叠后的所述第一模组及所述第二模组与所述空腔元件、所述大尺寸器件水平排布于所述主基板第一表面且分别与所述主基板电性连接。
  2. 根据权利要求1所述的集成封装结构，其特征在于，所述集成封装结构还包括覆盖所述主基板第一表面且包封所述第一模组、所述第二模组、所述空腔元件及所述大尺寸器件的塑封层，所述塑封层包括远离所述主基板的塑封层第一表面及靠近所述主基板的塑封层第二表面，所述塑封层第一表面开设有朝向所述空腔元件延伸的开口槽，至少部分所述开口槽的位置正对所述空腔元件。
  3. 根据权利要求2所述的集成封装结构，其特征在于，所述开口槽为倒梯形开口槽，且所述倒梯形开口槽沿着所述空腔元件的中轴线对称分布。
  4. 根据权利要求2所述的集成封装结构，其特征在于，所述开口槽为位于所述塑封层凸角的台阶形开口槽。
  5. 根据权利要求1所述的集成封装结构，其特征在于，所述集成封装结构还包括第一屏蔽层与第二屏蔽层，所述第一屏蔽层覆盖所述第一模组，所述第二屏蔽层覆盖所述第一模组、所述第二模组、所述空腔元件、所述大尺寸器件以及所述主基板；
    所述第一屏蔽层与所述第二屏蔽层的材料不同，或所述第一屏蔽层与所述第二屏蔽层的结构不同，或所述第一屏蔽层与所述第二屏蔽层的材料和结构均不同。
  6. 根据权利要求5所述的集成封装结构，其特征在于，所述集成封装结构还包括中空的转接板，所述转接板堆叠于所述第一模组与所述主基板两者之间且将所述第一模组与所述主基板电性连接，所述第二模组位于所述转接板的中空部分。
  7. 根据权利要求6所述的集成封装结构，其特征在于，所述转接板的一端与所述第一屏蔽层电性连接而另一端与所述主基板的接地端电性连接。
  8. 根据权利要求6所述的集成封装结构，其特征在于，所述转接板为有机基板类转接板或包封类转接板或堆叠重布线的异质叠层类转接板。
  9. 根据权利要求1所述的集成封装结构，其特征在于，所述集成封装结构还包括设于所述主基板第二表面的第三模组，至少部分所述第三模组的位置正对所述第二模组。
  10. 根据权利要求9所述的集成封装结构，其特征在于，所述第二模组为SOC芯片，所述第三模组为存储模组，所述集成封装结构还包括覆盖所述SOC芯片的第三屏蔽层及覆盖所述存储模 组的第四屏蔽层。
  11. 根据权利要求1所述的集成封装结构，其特征在于，所述主基板为有机基板，或者为采用贴膜或涂胶的晶圆与板级堆叠重布线的同质或异质叠层。
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