WO2021042916A1 - 一种半导体器件的制作方法和半导体器件 - Google Patents

一种半导体器件的制作方法和半导体器件 Download PDF

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WO2021042916A1
WO2021042916A1 PCT/CN2020/105703 CN2020105703W WO2021042916A1 WO 2021042916 A1 WO2021042916 A1 WO 2021042916A1 CN 2020105703 W CN2020105703 W CN 2020105703W WO 2021042916 A1 WO2021042916 A1 WO 2021042916A1
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ion implantation
drain
region
source
lightly doped
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PCT/CN2020/105703
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French (fr)
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梁旦业
汪广羊
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无锡华润上华科技有限公司
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
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    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
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    • H01L21/2654—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
    • H01L21/26546—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds of electrically active species
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
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    • H01L29/0843—Source or drain regions of field-effect devices
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66522—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with an active layer made of a group 13/15 material
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • This application relates to the field of semiconductor manufacturing, in particular to a method for manufacturing a semiconductor device and a semiconductor device.
  • GGNMOS Gate Grounded NMOS
  • FIG. 1A A typical GGNMOS device is shown in FIG. 1A. It includes a semiconductor substrate 100. A P well 101 and an N well 102 are formed in the semiconductor substrate 100, wherein the GGNMOS device is formed In the P-well 101, a gate structure 103 is formed on the semiconductor substrate 100, a source 104 and a drain 105 are also formed in the semiconductor substrate 100 on both sides of the gate structure 103, wherein the gate structure 103 and the source
  • the electrode 104 and the lead-out end 106 of the substrate together constitute the anode of the GGNMOS device, the drain 105 is drawn separately as a cathode, and an isolation structure 107 is provided between the lead-out end 106 of the substrate and the source 104 and the drain 105 respectively.
  • the diode composed of the drain 105 and the P-well 101 in the substrate is reverse biased.
  • the diode will undergo an avalanche breakdown, and the generated avalanche current will flow through the P-well 101. Since the P-well has resistance, a voltage drop is generated; when the generated voltage drop exceeds the turn-on voltage of the diode between the source 104 and the P-well 101, the diode will be forward biased. In this way, the parasitic NPN of the NMOS tube is turned on to discharge the ESD current until the surge disappears, thereby achieving the effect of electrostatic protection.
  • ESD Electro-Static Discharge, electrostatic discharge
  • GGNMOS is in BCD
  • the (Bi-polar CMOS DMOS) process is taped out.
  • it will not particularly increase the level of injection that is beneficial to improve the ESD protection capability.
  • a typical method for forming the above-mentioned GGNMOS device includes: providing a P-type semiconductor substrate; forming a P-type well region on the semiconductor substrate, forming a gate structure above the P-type well region; performing N-type source and drain Ion implantation to form the source and drain in the semiconductor substrate on both sides of the gate structure; forming a through hole on the semiconductor substrate, and the through hole is used to fill a conductive material to connect the source and drain to the The gate structure is electrically led out; ESD ion implantation is performed to form a P-type ion implantation region under the source and drain, so as to reduce the breakdown voltage between the NMOS drain and the P-type well region.
  • the PN junction under the drain contact hole is first broken down, and the electrostatic discharge current will be discharged from the PN junction interface. Therefore, the drain of the NMOS device will not be caused by the electrostatic tip. The phenomenon of discharge is damaged by static electricity.
  • the source and drain ion implantation including oblique ion implantation is adopted.
  • the formed source and drain have a relatively vertical morphology under the gate structure to increase the conductivity.
  • the area makes the current path at the bottom of the source and drain (shown as P2 in Figure 1B) larger and larger than the current path on the surface of the source and drain (shown as P1 in Figure 1B), making the electrostatic discharge Current is more likely to concentrate on the surface, and the unit area overcurrent protection capability is lower.
  • a method for manufacturing a semiconductor device includes:
  • a source-drain ion implantation process is performed to form a source region and a drain region in the semiconductor substrate on both sides of the gate, wherein the lightly doped source region, the source pocket ion implantation region and the The source region collectively constitutes a source electrode with a slanted topography under the gate structure, and the lightly doped drain region, the drain pocket ion implantation region and the drain region together constitute the gate electrode
  • the drain has a sloped topography under the structure.
  • FIG. 1A is a schematic diagram of the structure of an exemplary GGNMOS device
  • FIG. 1B is a partial enlarged schematic diagram of the GGNMOS device corresponding to FIG. 1A;
  • 2A-2E are schematic diagrams of the semiconductor device formed during the manufacturing process of the semiconductor device in an embodiment of the application;
  • FIG. 3 is a flowchart of a method of manufacturing a semiconductor device in an embodiment.
  • this application provides a method for manufacturing a semiconductor device and a semiconductor device, including:
  • pocket ion implantation to respectively form a source pocket ion implantation region and a drain pocket ion implantation region at the bottom of the lightly doped source region and the lightly doped drain region;
  • Source and drain ion implantation is performed to form a source region and a drain region in the semiconductor substrate on both sides of the gate, wherein the lightly doped source region, the source pocket ion implantation region and the The source region collectively constitutes a source electrode with a slanted topography under the gate structure, and the lightly doped drain region, the drain pocket ion implantation region and the drain region are collectively formed in the gate structure
  • the drain has a slanted topography underneath.
  • FIGS. 2A-2E are structural schematic diagrams of the semiconductor device formed during the manufacturing process of the semiconductor device in an embodiment
  • FIG. 3 is a flowchart of a manufacturing method of a semiconductor device in an embodiment of the application.
  • step S1 is performed: a semiconductor substrate is provided, and a gate structure is formed on the semiconductor substrate.
  • a semiconductor substrate 200 is provided, and a gate structure is formed on the semiconductor substrate 200.
  • the gate structure includes a gate dielectric layer 201 and a gate material layer 202.
  • the semiconductor substrate 200 may be at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs or other III/V compound semiconductors, It also includes multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon germanium-on-insulator (SiGeOI), and insulators On germanium (GeOI) and so on.
  • SOI silicon-on-insulator
  • SSOI silicon-on-insulator
  • SiGeOI silicon-germanium-on-insulator
  • SiGeOI silicon germanium-on-insulator
  • SiOI silicon germanium-on-insulator
  • the semiconductor device is a GGNMOS device
  • the semiconductor substrate 200 is a P-type semiconductor substrate.
  • the P-type semiconductor substrate is a substrate with a P-type well region formed by an ion implantation or diffusion process.
  • the P-type semiconductor substrate is a doped layer formed on the semiconductor substrate by processes such as ion doping and vapor phase epitaxy.
  • the P-type semiconductor substrate is a P-type doped ion trap formed in the Si substrate by a diffusion process, and the doping concentration is 1 ⁇ 10 14 /cm 3 -2 ⁇ 10 14 /cm 3 .
  • the step of forming a gate structure on the semiconductor substrate 200 includes: performing a thermal oxidation process to form a thermal oxide layer on the surface of the semiconductor substrate; performing a chemical vapor deposition process on the surface of the semiconductor substrate 200 A polysilicon material layer is formed; a patterning process is performed on the thermal oxide layer and the polysilicon material layer to form the gate dielectric layer 201 and the gate material layer 202.
  • an N-type doped ion trap, an isolation structure, and other structures known to those skilled in the art are also formed in the semiconductor substrate 200, which will not be repeated here.
  • step S2 perform a lightly doped source-drain ion implantation process to form a lightly doped source region and a lightly doped drain region in the semiconductor substrate on both sides of the gate structure.
  • a lightly doped source region 204 and a lightly doped drain region 203 are respectively formed in the semiconductor substrate 200 on both sides of the gate structure.
  • the lightly doped source region 204 and the lightly doped drain region 203 suppress the hot electron effect on the one hand, and provide a diffusion buffer layer for subsequent high-concentration doping of the source and drain regions on the other hand.
  • the step of performing the lightly doped source-drain ion implantation process includes: forming a patterned mask on the semiconductor substrate 200 to expose the region where the source region and the drain region are to be formed; Lightly doped source and drain ion implantation is performed to form a lightly doped source ion implantation region 204 in the region where the source region is to be formed in the semiconductor substrate 200, and the semiconductor substrate 200 is to be formed as the drain region.
  • a lightly doped drain ion implantation region 203 is formed in the region of the region.
  • the process of forming the patterned mask includes coating to form a photoresist layer, and performing a photolithography process to form the patterned mask. The foregoing process is a process well known to those skilled in the art, and will not be repeated here.
  • the semiconductor substrate 200 is a P-type semiconductor substrate, and the lightly doped source/drain ion implantation process is an N-type doping process.
  • the ions implanted by the lightly doped source-drain ion implantation process are P ions
  • the implant energy range is 45KeV-60KeV
  • the implant dose range is 1*10 13 cm -3 -2*10 13 cm -3 .
  • the lightly doped source-drain ion implantation process is a P ion implantation process
  • the implantation energy is 50 KeV
  • the implantation dose is 1.5*E13cm -3 .
  • step S3 perform pocket ion implantation to form a source pocket ion implantation region and a drain pocket ion implantation region at the bottom of the lightly doped source region and the lightly doped drain region, respectively .
  • the source region pocket type (pocket or halo) is formed in the semiconductor substrate 200, which is located below the lightly doped source region 204 and is close to the gate structure.
  • the semiconductor substrate 200 is a P-type semiconductor substrate, and the lightly doped source/drain ion implantation process is an N-type doping process.
  • the source pocket ion implantation region 210 and the drain pocket ion implantation region 205 are formed before the source and drain regions are formed.
  • the local doping concentration of the semiconductor substrate 200 can be changed after the source region and the drain region are subsequently formed, so as to avoid the problem of semiconductor devices. The size reduction brings the source region and the drain region through and the device loses its gate control.
  • the step of performing the pocket ion implantation process includes: forming a patterned mask on the semiconductor substrate 200 to expose the region where the source region and the drain region are to be formed; and performing the pocket region Ion implantation is performed to form a source pocket ion implantation region 210 in the region where the source region is to be formed in the semiconductor substrate 200, and a drain pocket ion implantation region 205 is formed in the region where the drain region is to be formed.
  • the process of forming the patterned mask includes coating to form a photoresist layer, and performing a photolithography process to form the patterned mask. The above process is a process well known to those skilled in the art, and will not be repeated here.
  • the lightly doped ion implantation process in step S2 and the pocket ion implantation process in step S3 both perform ion implantation into the source region and the drain region.
  • the same mask or the same mask can be used.
  • a patterned mask saves process steps while saving masks.
  • the pocket ion implantation process is an oblique ion implantation process
  • the pocket ion implantation process is a B ion implantation process
  • the implant energy range is 45KeV-60KeV
  • the implant dose range is 3*10 12 cm -3 -5*10 12 cm -3 .
  • the pocket ion implantation process is a B ion implantation process
  • the inclination angle of the ion implantation is 45°
  • the implantation energy is 50 KeV
  • the implantation dose is 4*10 12 cm -3 .
  • step S4 perform source-drain ion implantation to form a source region and a drain region in the semiconductor substrate on both sides of the gate.
  • spacers are formed on both sides of the gate structure before the source and drain are formed.
  • spacers 206 are formed on both sides of the gate structure.
  • the spacer 206 prevents subsequent heavily doped source and drain ions from being implanted into the channel region under the gate structure, and suppresses the hot electron effect.
  • the spacer 206 may be a dielectric material such as silicon nitride, silicon oxide, or silicon oxynitride.
  • the step of forming the spacer 206 includes: first, forming a silicon nitride layer on the semiconductor substrate 200, and then forming a patterned mask layer on the silicon nitride layer ; Then, using the patterned mask layer as a mask, the silicon nitride layer is etched to expose the semiconductor substrate and the gate structure to obtain the spacer 206 as shown in FIG. 2D.
  • a source-drain ion implantation process is performed to form a source region and a drain region.
  • the source region 208 and the drain region 207 are formed after the source-drain ion implantation process is performed.
  • the lightly doped source region 204, the source pocket ion implantation region 210 and the source region 208 formed in the semiconductor substrate 200 jointly constitute the source electrode, and the lightly doped drain region 203, the drain pocket ion implantation region 205 and the drain region 207
  • the drain is formed together, because the source pocket ion implantation region 210 and the drain pocket ion implantation region 205 are respectively located at the bottom of the lightly doped source region 204 and the lightly doped drain region 203 in the semiconductor substrate on the side close to the gate structure , Preventing the lateral expansion of the source region and the drain region formed by the vertical ion implantation, so that the source electrode and the drain electrode formed finally have a slanted topography under the gate structure. As shown in FIG.
  • the drain 209 has a slanted morphology under the gate structure.
  • the current path at the bottom of the drain 209 (shown as P2 in FIG. 2E) is small, and the bottom of the drain 209
  • the smaller series resistance of the ESD makes more current flow through the bottom of the drain 209.
  • the surface current is less likely to reach the current peak due to current concentration. Therefore, under the same area, a higher ESD pulse is required.
  • the thermal breakdown of the surface makes the device failure, which is specifically manifested as a higher current capability and high robustness.
  • the source-drain ion implantation process is a vertical ion implantation process.
  • the semiconductor substrate 200 is a P-type semiconductor substrate, and the source-drain ion implantation process is an N-type doping process. Since the source and drain ion implantation process adopts the vertical ion implantation process, and the oblique ion implantation process in the traditional process is omitted, the depth of the source region 208 and the drain region 207 is reduced, and the source and drain electrodes 209 formed finally are located below the gate.
  • the region has a slanted morphology, as shown in FIG. 2E.
  • the current path at the bottom of the drain 209 (as shown by P2 in FIG.
  • the surface resistance of the drain 209 is large and the bottom resistance is small, so that more current flows through the bottom of the drain 209 during electrostatic discharge, so that the conductive area at the bottom of the drain 209 increases, and the conductive area on the surface of the drain 209 Decrease, so that the surface current is less likely to reach the current peak due to current concentration.
  • the inclined ion implantation process is omitted, which reduces the process steps and achieves the purpose of further saving process costs.
  • the source-drain ion implantation process is an As ion implantation process, the implantation energy is 2 KeV, and the implantation dose is 5*10 14 cm -3 .
  • multiple vertical ion implantations are performed to form the source region 208 and the drain region 207.
  • the step of performing the source-drain ion implantation process includes: forming a patterned mask on the semiconductor substrate 200 to expose the regions where the source and drain regions are to be formed; performing source-drain ion implantation , To form a source region 208 in the region where the source region is to be formed in the semiconductor substrate 200, and form a drain region 207 in the region where the drain region is to be formed in the semiconductor substrate 200.
  • the process of forming the patterned mask includes coating to form a photoresist layer, and performing a photolithography process to form the patterned mask. The foregoing process is a process well known to those skilled in the art, and will not be repeated here.
  • the source-drain ion implantation process in step S4, the lightly doped ion implantation process in step S2 and the pocket ion implantation process in step S3 are all performed on the source region 207 and the drain region 207
  • the same mask or the same patterned mask can be used, which saves the process steps while saving the mask.
  • the manufacturing method of the semiconductor device further includes forming a dielectric layer on the surface of the semiconductor substrate 200, forming a contact through hole in the dielectric layer, and filling the contact through hole with a metal material In order to electrically connect the gate structure, the source and the drain, and so on.
  • the lightly doped source region 204, the source pocket ion implantation region 210, and the source region 208 are formed in a semiconductor device with an inclined shape under the gate structure.
  • the source electrode of the topography, the lightly doped drain region 203, the drain pocket ion implantation region 205, and the drain region 207 jointly constitute a drain 209 with an inclined topography under the gate structure,
  • the current path at the bottom of the drain 209 is smaller, and the series resistance at the bottom of the drain 209 is smaller, so that more current in the electrostatic discharge flows through the bottom of the drain 209.
  • the surface current is even less. It is easy to reach the current peak due to current concentration. Therefore, in the same area, a higher ESD pulse is required to make the surface thermal breakdown and the device to fail, which is manifested as a higher current capability, and thus has high robustness.
  • a semiconductor device is provided.
  • the semiconductor device is manufactured using the method described in the first embodiment, and includes a semiconductor substrate, a gate structure on the semiconductor substrate, and a gate structure on the gate.
  • the source electrode and the drain electrode in the semiconductor substrate on both sides of the electrode structure, the source electrode is composed of a lightly doped source region, a source region pocket ion implantation region, and a source region.
  • Inclined topography, the drain is composed of a lightly doped drain region, a drain pocket ion implantation region and a drain region, and has an inclined topography below the gate structure.
  • the semiconductor substrate is a P-type semiconductor substrate
  • the semiconductor device is a GGNMOS device.
  • the source and drain are the source and drain with a slanted topography under the gate structure, the current path at the bottom of the drain is smaller during the electrostatic discharge process, thereby causing more current in the electrostatic discharge Circulation through the bottom of the drain, at this time, the surface current is less likely to reach the current peak due to current concentration, so under the same area, it can have a higher current capacity and high robustness.

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Abstract

本申请提供一种半导体器件的制作方法和半导体器件，所述制作方法包括：提供半导体衬底(200)，在所述半导体衬底(200)上形成有栅极结构；执行轻掺杂源漏离子注入工艺，以在所述栅极结构两侧的所述半导体衬底(200)中形成轻掺杂源区(204)和轻掺杂漏区(203)；执行袋区离子注入，以在所述轻掺杂源区(204)和轻掺杂漏区(203)底部分别形成源区袋型离子注入区(210)和漏区袋型离子注入区(205)；以及执行源漏离子注入，以在所述栅极两侧的所述半导体衬底中形成源区(208)和漏区(207)，其中，所述轻掺杂源区(204)、所述源区袋型离子注入区(210)和所述源区(208)共同构成在所述栅极结构下方具有倾斜的形貌的源极，所述轻掺杂漏区(203)、所述漏区袋型离子注入区(205)和所述漏区(207)共同构成在所述栅极结构下方具有倾斜的形貌的漏极(209)。

Description

一种半导体器件的制作方法和半导体器件
相关申请的交叉引用
本申请要求于2019年09月04日提交中国专利局、申请号为2019108327902、发明名称为“一种半导体器件的制作方法和半导体器件”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体制造领域，具体而言涉及一种半导体器件的制作方法和半导体器件。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成示例性技术。
GGNMOS(Gate Grounded NMOS)是常用的ESD防护器件，典型的GGNMOS器件如图1A所示，其包括半导体衬底100，在半导体衬底100中形成有P阱101和N阱102，其中GGNMOS器件形成在P阱101中，在半导体衬底100上形成有栅极结构103，在栅极结构103两侧的半导体衬底100中还形成有源极104和漏极105，其中栅极结构103和源极104和衬底的引出端106一起构成GGNMOS器件的阳极，漏极105单独引出作为阴极，在衬底引出端106和源极104、漏极105之间分别设置有隔离结构107。当ESD浪涌出现在阳极时，漏极105和衬底中的P阱101组成的二极管反偏，浪涌达到一定大小会使该二极管发生雪崩击穿，产生的雪崩电流流过P阱101，由于P阱具备电阻，产生压降；当产生的压降超过源极104和P阱101之间的二极管的开启电压，会使该二极管正偏。这样，NMOS管的寄生NPN开启，泄放ESD电流，直到浪涌消失，从而起到静电保护的效果。
为满足ESD(Electro-StaticDischarge，静电释放)鲁棒性(robustness，过ESD电流能力)设计的要求，通常需要比普通器件大十倍甚至几十倍的layout(版图)面积；此外，GGNMOS在BCD(Bi-polar CMOSDMOS)工艺上面流片，为了工艺兼容性和节约掩模版(mask)资源，不会特别增加有益于提高ESD保护能力的注入层次。一种典型的形成上述GGNMOS器件的方法包括：提供P型半导体衬底；在所述半导体衬底上形成P型阱区，在所述P型阱区上方形成栅极结构；执行N型源漏离子注入以形成位于栅极结构两侧的半导体衬底中的源漏极；在所述半导体衬底上形成通孔，所述通孔用以填充导电材料以将所述源漏极和所述栅极结构接电引出；执行ESD离子注入，以在所述源漏极下方形成P型离子注入区，从而降低NMOS漏极与P型阱区之间的击穿电压。当ESD现象发生在NMOS器件的漏极时，漏极接触孔下面的PN结首先被击穿，静电放电电流便会由该PN结界面泄放掉，因此该NMOS器件漏极不会因为静电尖端放电的现象而被静电损伤。但是，源漏极的形成过程中，为防止电流集中在表面，采用包含倾斜离子注入的源漏离子注入，形成的源漏极在栅极结构下方的具有较垂直的形貌，以增大导电面积，如图1B所示，使得源漏极底部的电流路径(如图1B中P2所示)较大，大于源漏极表面的电流路径(如图1B中P1所示)，使得静电放电时电流更容易集中表面，单位面积过电流保护能力较低。
因此，有必要提供一种新的半导体器件的制造方法和半导体器件，用以解决现有技术中的问题。
发明内容
根据本申请的各种实施例，提供一种半导体器件的制造方法和半导体器件。一种半导体器件的制作方法，包括：
提供半导体衬底，在所述半导体衬底上形成有栅极结构；
执行轻掺杂源漏离子注入工艺，以在所述栅极结构两侧的所述半导体衬底中形成轻掺杂源区和轻掺杂漏区；
执行袋区离子注入工艺，以在所述轻掺杂源区和轻掺杂漏区底部分别形成源区袋型离子注入区和漏区袋型离子注入区；以及
执行源漏离子注入工艺，以在所述栅极两侧的所述半导体衬底中形成源区和漏区，其中，所述轻掺杂源区、所述源区袋型离子注入区和所述源区共同构成在所述栅极结构下方具有倾斜的形貌的源极，所述轻掺杂漏区、所述漏区袋型离子注入区和所述漏区共同构成在所述栅极结构下方具有倾斜的形貌的漏极。
一种半导体器件，采用上任意一项所述的制作方法制作。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例或示例性技术中的技术方案，下面将对实施例或示例性技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。图1A为示例性的GGNMOS器件的结构示意图；
图1B为图1A对应的GGNMOS器件的局部放大示意图；
图2A-图2E为本申请的一个实施例中的半导体器件的制作过程中形成的半导体器件的结构示意图；
图3为一个实施例中的半导体器件的制作方法的流程图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使本申请的公开内容更加透彻全面。
实施例一
为了解决现有技术中的问题，本申请提供了半导体器件的制作方法和半导体器件，包括：
提供半导体衬底，在所述半导体衬底上形成有栅极结构；
执行轻掺杂源漏离子注入工艺，以在所述栅极结构两侧的所述半导体衬底中形成轻掺杂源区和轻掺杂漏区；
执行袋区离子注入，以在所述轻掺杂源区和轻掺杂漏区底部分别形成源区袋型离子注入区和漏区袋型离子注入区；以及
执行源漏离子注入，以在所述栅极两侧的所述半导体衬底中形成源区和漏区，其中，所述轻掺杂源区、所述源区袋型离子注入区和所述源区共同构成在所述栅极结构下方具有倾斜的形貌的源极，所述轻掺杂漏区、所述漏区袋型离子注入区和所述漏区共同构成在所述栅极结构下方具有倾斜的形貌的漏极。
下面参考图2A-图2E和图3对本申请中一种半导体器件的制作方法进行示例性说明，其中图2A-图2E为一实施例中半导体器件的制作过程中形成的半导体器件的结构示意图；图3为本申请一个实施例中半导体器件的制作方法的流程图。
首先参看图3，执行步骤S1：提供半导体衬底，在所述半导体衬底上形成有栅极结构。
如图2A所示，提供半导体衬底200，在半导体衬底200上形成有栅极结构，栅极结构包括栅介电层201和栅极材料层202。
在其中一个实施例中，半导体衬底200可以是以下所提到的材料中的至少一种：Si、Ge、SiGe、SiC、SiGeC、InAs、GaAs、InP、InGaAs或者其它III/V化合物半导体，还包括这些半导体构成的多层结构等，或者为绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。
在其中一个实施例中，所述半导体器件为GGNMOS器件，所述半导体衬底200为P型半导体衬底。
在其中一个实施例中，P型半导体衬底是通过离子注入或者扩散工艺形成的具有P型阱区的衬底。在其他实施例中，P型半导体衬底是通过离子掺杂气相外延等工艺形成在半导体衬底上的掺杂层。
在其中一个实施例中，P型半导体衬底为通过扩散工艺形成在Si衬底中的P型掺杂的离子阱，掺杂浓度为1×10 14/cm 3-2×10 14/cm 3。
在其中一个实施例中，在半导体衬底200上形成栅极结构的步骤包括：执行热氧化工艺在所述半导体衬底表面形成热氧化层；执行化学气相沉积工艺在所述半导体衬底200表面形成多晶硅材料层；对所述热氧化层和所述多晶硅材料层执行图案化工艺以形成所述栅介电层201和栅极材料层202。
需要理解的是，上述在半导体衬底200表面形成栅极结构的方法仅仅是示例性地，任何形成栅极结构的方法均适用于本申请。
在其中一个实施例中，在半导体衬底200中还形成有N型掺杂的离子阱，隔离结构等本领域技术人员所熟知的结构，在此不再赘述。
接着，继续参看图3，执行步骤S2：执行轻掺杂源漏离子注入工艺，以在所述栅极结构两侧的所述半导体衬底中形成轻掺杂源区和轻掺杂漏区。
如图2B所示，执行轻掺杂源漏(LDD)离子注入工艺后，在栅极结构两侧的半导体衬底200中分别形成轻掺杂源区204和轻掺杂漏区203。轻掺杂源区204和轻掺杂漏区203一方面抑制了热电子效应，另一方面为后续高浓度的源区和漏区掺杂提供了扩散缓冲层。
在其中一个实施例中，所述执行轻掺杂源漏离子注入工艺的步骤包括：在所述半导体衬底200上形成图案化的掩膜以露出拟形成源区和拟形成漏区的区域；执行轻掺杂源漏离子注入，以在所述半导体衬底200中所述拟形成源区的区域中形成轻掺杂源离子注入区204，在所述半导体衬底200中所述拟形成漏区的区域中形成轻掺杂漏离子注入区203。其中，形成所述图案化 的掩膜的过程包括涂覆形成光刻胶层，执行光刻工艺形成所述图案化的掩膜。上述过程为本领域技术人员所熟知的过程，在此不再赘述。
在其中一个实施例中，所述半导体衬底200为P型半导体衬底，所述轻掺杂源漏离子注入工艺为N型掺杂工艺。
在其中一个实施例中，所述轻掺杂源漏离子注入工艺注入的离子为P离子，注入能量的范围为45KeV-60KeV，注入剂量的范围为1*10 13cm -3-2*10 13cm -3。
在其中一个实施例中，所述轻掺杂源漏离子注入工艺为P离子注入工艺，注入能量为50KeV，注入剂量为1.5*E13cm -3。
接着，继续参看图3，执行步骤S3：执行袋区离子注入，以在所述轻掺杂源区和轻掺杂漏区底部分别形成源区袋型离子注入区和漏区袋型离子注入区。
如图2C所示，执行袋区(pocket或halo)离子注入工艺之后，在半导体衬底200中形成分别位于轻掺杂源区204下方的靠近所述栅极结构一侧的源区袋型(pocket或halo)离子注入区210和轻掺杂漏区203下方的靠近所述栅极结构一侧的漏区袋型(pocket或halo)离子注入区205。
在其中一个实施例中，所述半导体衬底200为P型半导体衬底，所述轻掺杂源漏离子注入工艺为N型掺杂工艺。在形成源漏区之前形成源区袋型离子注入区210和漏区袋型离子注入区205，可以在后续形成源区和漏区之后改变半导体衬底200的局部掺杂浓度，避免因为半导体器件尺寸的减小带来源区和漏区贯通而使器件失去栅控制性。
在其中一个实施例中，所述执行袋区离子注入工艺的步骤包括：在所述半导体衬底200上形成图案化的掩膜以露出拟形成源区和拟形成漏区的区域；执行袋区离子注入，以在所述半导体衬底200中所述拟形成源区的区域中形成源区袋型离子注入区210，所述拟形成漏区的区域中形成漏区袋型离子注入区205。其中，形成所述图案化的掩膜的过程包括涂覆形成光刻胶层，执行光刻工艺形成所述图案化的掩膜。上述过程为本领域技术人员所熟知的 过程，在此不再赘述。
在其中一个实施例中，上述步骤S2中的轻掺杂离子注入工艺和本步骤S3中的袋区离子注入工艺都是向源区和漏区执行离子注入，可以使用同一个掩膜版或同一个图案化的掩膜，在节省掩膜版的同时节省了工艺步骤。
在其中一个实施例中，所述袋区离子注入工艺为倾斜离子注入工艺，所述袋区离子注入工艺为B离子注入工艺，注入能量的范围为45KeV-60KeV，注入剂量的范围为3*10 12cm -3-5*10 12cm -3。
在其中一个实施例中，所述袋区离子注入工艺为B离子注入工艺，离子注入的倾斜角度为45°，注入能量为50KeV，注入剂量为4*10 12cm -3。
接着，继续参看图3，执行步骤S4：执行源漏离子注入，以在所述栅极两侧的所述半导体衬底中形成源区和漏区。
在其中一个实施例中，在形成所述源漏极之前在所述栅极结构两侧形成间隙壁。
如图2D所示，在执行源漏离子注入之前，在栅极结构两侧形成间隙壁206。间隙壁206避免后续重掺杂的源漏离子注入进入到栅极结构下方的沟道区域，抑制热电子效应。
在其中一个实施例中，所述间隙壁206可以采用氮化硅、氧化硅或者氮氧化硅等介质材料。
在其中一个实施例中，形成所述间隙壁206的步骤包括：首先，在所述半导体衬底200上形成氮化硅层，接着，在所述氮化硅层上形成图案化的掩膜层；然后，以所述图案化的掩膜层为掩膜，对所述氮化硅层进行刻蚀，以露出所述半导体衬底和栅极结构，得到如图2D所示的间隙壁206。
形成间隙壁206后，执行源漏离子注入工艺，形成源区和漏区。继续参看图2D，执行源漏离子注入工艺后形成源区208和漏区207。
半导体衬底200中形成的轻掺杂源区204、源区袋型离子注入区210和源区208共同构成源极，轻掺杂漏区203、漏区袋型离子注入区205和漏区 207共同构成漏极，由于源区袋型离子注入区210和漏区袋型离子注入区205分别位于半导体衬底中轻掺杂源区204和轻掺杂漏区203底部靠近栅极结构的一侧，阻止了垂直离子注入形成的源区和漏区的横向扩展，使得最终形成的源极和漏极在栅极结构下方具有倾斜的形貌。如图2E所示，漏极209在栅极结构下方具有倾斜的形貌，在后期静电放电过程中，漏极209底部的电流路径(如图2E中P2所示)较小，漏极209底部的串联电阻较小，使得静电放电更多的电流通过漏极209底部流通，此时，表面电流更不容易因电流集中而达到电流峰值，因此在相同的面积下，需要更高的ESD脉冲才能使表面达到热击穿使器件失效，具体表现为更高的电流能力，具有高的鲁棒性。
在其中一个实施例中，所述源漏离子注入工艺为垂直离子注入工艺。所述半导体衬底200为P型半导体衬底，所述源漏离子注入工艺为N型掺杂工艺。由于源漏离子注入工艺采用垂直离子注入工艺，而略去传统工艺中的倾斜离子注入工艺，使得源区208和漏区207深度减小，最终形成的源极和漏极209位于栅极下方的区域具有倾斜的形貌，如图2E所示，静电放电过程中，漏极209底部的电流路径(如图2E中P2所示)小于表面的电流路径(如图2E中P1所示)，即在ESD静电保护过程中，漏极209表面电阻大，底部电阻小，从而静电放电中更多的电流通过漏极209底部流通，使得漏极209底部的导电面积增加，漏极209表面的导电面积减小，使得表面电流更不容易因电流集中而达到电流峰值。同时，由于仅采用垂直离子注入工艺，而略去了倾斜离子注入工艺，减少了工艺步骤，达到进一步节省工艺成本的目的。
在其中一个实施例中，所述源漏离子注入工艺为As离子注入工艺，注入能量为2KeV，注入剂量为5*10 14cm -3。
在其中一个实施例中，执行多次垂直离子注入以形成所述源区208和漏区207。
在其中一个实施例中，所述执行源漏离子注入工艺的步骤包括：在所述半导体衬底200上形成图案化的掩膜以露出拟形成源区和漏区的区域；执行源漏离子注入，以在所述半导体衬底200中所述拟形成源区的区域中形成源 区208，在所述半导体衬底200中所述拟形成漏区的区域中形成漏区207。其中，形成所述图案化的掩膜的过程包括涂覆形成光刻胶层，执行光刻工艺形成所述图案化的掩膜。上述过程为本领域技术人员所熟知的过程，在此不再赘述。
在其中一个实施例中，本步骤S4中的源漏离子注入工艺与上述步骤S2中的轻掺杂离子注入工艺和步骤S3中的袋区离子注入工艺都是向源区207和漏区207执行离子注入，可以使用同一个掩膜版或同一个图案化的掩膜，在节省掩膜版的同时节省了工艺步骤。
至此，已经对根据本申请的一种半导体器件的制造方法进行了示例性说明。在其中一个实施例中，所述半导体器件的制造方法还包括在所述半导体衬底200表面形成介质层，在所述介质层中形成接触通孔，以及在所述接触通孔中填充金属材料以将所述栅极结构、所述源极和漏极电接出等步骤。根据本申请，通过在半导体器件中形成由所述轻掺杂源区204、所述源区袋型离子注入区210和所述源区208共同构成的在所述栅极结构下方具有倾斜的形貌的源极，所述轻掺杂漏区203、所述漏区袋型离子注入区205和所述漏区207共同构成的在所述栅极结构下方具有倾斜的形貌的漏极209，使得在静电放电过程中，漏极209底部的电流路径较小，漏极209底部的串联电阻较小，从而使静电放电中更多的电流通过漏极209底部流通，此时，表面电流更不容易因电流集中而达到电流峰值，因此在相同的面积下，需要更高的ESD脉冲才能使表面达到热击穿使器件失效，具体表现为更高的电流能力，因而具有高的鲁棒性。
实施例二
在其中一个实施例中，提供了一种半导体器件，所述半导体器件采用如实施例一所述的方法制造，包括半导体衬底、位于所述半导体衬底上的栅极结构，位于所述栅极结构两侧的所述半导体衬底中的源极和漏极，所述源极 由轻掺杂源区、源区袋型离子注入区和源区共同构成，在所述栅极结构下方具有倾斜的形貌，所述漏极由轻掺杂漏区、漏区袋型离子注入区和漏区共同构成，在所述栅极结构下方具有倾斜的形貌。
在其中一个实施例中，所述半导体衬底为P型半导体衬底，所述半导体器件为GGNMOS器件。
由于源极和漏极为在所述栅极结构下方具有倾斜的形貌的源极和漏极，使得在静电放电过程中，漏极底部的电流路径较小，从而使静电放电中更多的电流通过漏极底部流通，此时，表面电流更不容易因电流集中而达到电流峰值，因此在相同的面积下，能拥有更高的电流能力，具有高的鲁棒性。
需要说明的是，本方案中涉及到的各步骤的限定，在不影响具体方案实施的前提下，并不认定为对步骤先后顺序做出限定，写在前面的步骤可以是在先执行的，也可以是在后执行的，甚至也可以是同时执行的，只要能实施本方案，都应当视为属于本申请的保护范围。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
本申请已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本申请限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本申请并不局限于上述实施例，根据本申请的教导还可以做出更多种的变型和修改，这些变型和修改均落在本申请所要求保护的范围以内。本申请的保护范围由附属的权利要求书及其等效范围所界定。

Claims (15)

  1. 一种半导体器件的制作方法，包括：
    提供半导体衬底，在所述半导体衬底上形成有栅极结构；
    执行轻掺杂源漏离子注入工艺，以在所述栅极结构两侧的所述半导体衬底中形成轻掺杂源区和轻掺杂漏区；
    执行袋区离子注入工艺，以在所述轻掺杂源区和轻掺杂漏区底部分别形成源区袋型离子注入区和漏区袋型离子注入区；以及
    执行源漏离子注入工艺，以在所述栅极两侧的所述半导体衬底中形成源区和漏区，其中，所述轻掺杂源区、所述源区袋型离子注入区和所述源区共同构成在所述栅极结构下方具有倾斜的形貌的源极，所述轻掺杂漏区、所述漏区袋型离子注入区和所述漏区共同构成在所述栅极结构下方具有倾斜的形貌的漏极。
  2. 如权利要求1所述的制作方法，其中所述源漏离子注入工艺为垂直离子注入。
  3. 如权利要求1所述的制作方法，其中在所述执行袋区离子注入工艺之后，所述执行源漏离子注入工艺之前，还包括在所述栅极结构两侧形成间隙壁的步骤。
  4. 如权利要求1所述的制作方法，其中所述轻掺杂源漏离子注入工艺的注入能量的范围包括45KeV-60KeV，注入剂量的范围包括1*10 13cm -3-2*10 13cm -3。
  5. 如权利要求1所述的制作方法，其中所述袋区离子注入工艺为倾斜离子注入工艺。
  6. 如权利要求1所述的制作方法，其中所述袋区离子注入工艺的注入能量的范围包括45KeV-60KeV，注入剂量的范围包括3*10 12cm -3-5*10 12cm -3。
  7. 如权利要求1所述的制作方法，其中所述轻掺杂源漏离子注入工艺和所述袋区离子注入工艺是在同一个图案化的掩膜下进行的离子注入工艺。
  8. 如权利要求1所述的制作方法，其中所述轻掺杂源漏离子注入工艺、 所述袋区离子注入工艺和所述源漏离子注入工艺是在同一个图案化的掩膜下进行的离子注入工艺。
  9. 如权利要求1所述的制作方法，其中所述半导体衬底包括P型半导体衬底，所述轻掺杂源漏离子注入工艺为N型掺杂工艺。
  10. 如权利要求1所述的制作方法，其中所述轻掺杂源漏离子注入工艺为P离子注入工艺，注入能量为50KeV，注入剂量为1.5*E13cm -3。
  11. 如权利要求1所述的制作方法，其中所述袋区离子注入工艺为B离子注入工艺，离子注入的倾斜角度为45°。
  12. 如权利要求1所述的制作方法，其中所述栅极结构包括栅介电层和栅极材料层。
  13. 如权利要求1所述的制作方法，其中所述半导体衬底为通过扩散工艺形成在硅衬底中的P型掺杂的离子阱。
  14. 一种半导体器件，采用如权利要求1所述的制作方法制作。
  15. 如权利要求14所述的半导体器件，其中所述半导体器件包括GGNMOS器件。
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