WO2023098174A1 - 静电放电保护结构 - Google Patents

静电放电保护结构 Download PDF

Info

Publication number
WO2023098174A1
WO2023098174A1 PCT/CN2022/115047 CN2022115047W WO2023098174A1 WO 2023098174 A1 WO2023098174 A1 WO 2023098174A1 CN 2022115047 W CN2022115047 W CN 2022115047W WO 2023098174 A1 WO2023098174 A1 WO 2023098174A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
well region
electrostatic discharge
protection structure
discharge protection
Prior art date
Application number
PCT/CN2022/115047
Other languages
English (en)
French (fr)
Inventor
梁旦业
Original Assignee
无锡华润上华科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 无锡华润上华科技有限公司 filed Critical 无锡华润上华科技有限公司
Publication of WO2023098174A1 publication Critical patent/WO2023098174A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction

Definitions

  • the invention relates to the technical field of semiconductors, in particular to an electrostatic discharge protection structure.
  • electrostatic protection is related to the reliability of the chip. With the improvement of electrostatic protection requirements, it is necessary to continuously optimize the protection structure responsible for electrostatic discharge (ESD) on the chip.
  • ESD electrostatic discharge
  • FIG. 1 shows a structure of an ESD protection network clamped at the I/O port and the power supply.
  • ESD3 for the electrostatic discharge protection structure ESD3, if a GGNMOS (Gate Ground NMOS, gate grounded NMOS) device with the same working voltage transformed from 5V NMOS is selected, the electrostatic discharge protection structure ESD3 and MOS transistor M3 will The trigger voltage is the same, so ESD3 cannot protect M3. Therefore, it is necessary to use an electrostatic discharge protection structure with low trigger voltage; at the same time, the electrostatic discharge protection structure ESD5 is used as the protection of the power supply clamp. discharge protection structure.
  • the electrostatic discharge protection structure is required to have strong robustness. From the perspective of latch-up protection, the ESD protection structure is required to have a high sustain voltage.
  • the invention provides an electrostatic discharge protection structure.
  • the electrostatic discharge protection structure includes: a substrate having a first conductivity type; a source region and a drain region both having a second conductivity type opposite to the first conductivity type, and spaced apart on the substrate Middle; a gate structure disposed on the substrate between the source region and the drain region, the source region and the gate structure are commonly electrically connected to a first potential terminal, and the drain The region is electrically connected to the second potential terminal; the first doped region has the first conductivity type and is floating, and is arranged in the substrate on the side of the drain region away from the gate structure, And it is spaced apart from the drain region, and the doping concentration of the first doping region is greater than the doping concentration of the substrate.
  • the distance between the first doped region and the drain region is set according to the trigger voltage required by the electrostatic discharge protection structure.
  • the electrostatic discharge protection structure includes a second doped region having a first conductivity type and disposed in the substrate between the gate structure and the source region, the The second doped region is floating.
  • the ESD protection structure includes a SAB layer, and the SAB layer covers the upper surface of the substrate of the first doped region and the second doped region.
  • the electrostatic discharge protection structure includes a first isolation structure, and the first isolation structure is located in the substrate between the gate structure and the source region.
  • the electrostatic discharge protection structure includes a deep well region with a second conductivity type, and the deep well region is formed in the substrate; a first well region with a first conductivity type is formed on the top of the deep well region.
  • Well region, the source region, the drain region and the first doped region are formed on the top of the first well region, the doping concentration of the first doped region is greater than that of the first The doping concentration of the well region.
  • a first well lead-out region with a first conductivity type is formed at the top of the first well region, and the first well lead-out region is located at a side of the source region away from the gate structure. side, and the lead-out region of the first well region is electrically connected to the first potential terminal.
  • the electrostatic discharge protection structure includes a second well region with a second conductivity type, the second well region is located at the top of the deep well region and surrounds the first well region; the second well region A second well region lead-out region with a second conductivity type is formed on the top of the inside, the doping concentration of the second well region lead-out region is greater than the doping concentration of the second well region; the second well region lead-out region Electrically connected to the third potential terminal; an isolation structure is provided between the first well region lead-out region and the source region; an isolation structure is provided between the first well region lead-out region and the second well region lead-out region isolation structure.
  • the electrostatic discharge protection structure includes a third well region with the first conductivity type, the doping concentration of the third well region is greater than the doping concentration of the substrate; the top in the third well region is formed There is a third well region lead-out region, the third well region lead-out region has the first conductivity type and the doping concentration is greater than the doping concentration of the third well region; the third well region lead-out region is electrically connected to the fourth Potential terminal.
  • the potential of the third potential terminal is different from the potentials of the first potential terminal, the second potential terminal and the fourth potential terminal; and the potentials of the first potential terminal and the fourth potential terminal same or different.
  • the first potential terminal is a cathode terminal
  • the second potential terminal is an anode terminal
  • the potential of the anode terminal is different from that of the cathode terminal
  • the electrostatic discharge protection structure is GGNMOS.
  • the electrostatic discharge protection structure includes at least two interdigital units, each of which includes a gate structure, a source region, and a drain region; every two adjacent The interdigital unit is a pair, the drain regions of a pair of interdigital units are close to each other, the first doped region is located between two mutually close drain regions, and a pair of interdigital unit
  • the cells are axisymmetric about the corresponding first doped region.
  • the first doped region with the first conductivity type is disposed in the substrate on the side of the drain region with the second conductivity type away from the gate structure, and the first doped region It is spaced apart from the drain region and is floating, and the doping concentration of the first doping region is greater than that of the substrate.
  • Increasing the set first doped region can reduce the avalanche breakdown voltage of the collector junction (that is, the PN junction formed between the drain region and the substrate) of the parasitic NPN transistor in the electrostatic discharge protection structure, thereby reducing static electricity.
  • Figure 1 is a structure of an ESD protection network clamped at the I/O port and the power supply.
  • FIG. 2 is a schematic cross-sectional view of a GGNMOS device.
  • FIG. 3 is a schematic diagram of the GGNMOS device shown in FIG. 2 and its internal equivalent triode circuit.
  • FIG. 4 is a schematic cross-sectional view of a GGNMOS_P+ device.
  • FIG. 5 is an IV curve diagram of a TLP test of a GGNMOS device and a GGNMOS_P+ device with the same chip area.
  • FIG. 6 is a simulated distribution diagram of current density after the parasitic NPN junction of the GGNMOS device is turned on.
  • FIG. 7 is a simulated distribution diagram of the current density after the parasitic NPN junction of the GGNMOS_P+ device is turned on.
  • FIG. 8 is a TLP test IV diagram of a hanging resistance experiment of a GGNMOS device.
  • FIG. 9 is a TLP test IV diagram of the hanging resistance experiment of the GGNMOS_P+ device.
  • FIG. 10 is a schematic cross-sectional view of a GGNMOS_P+ device with a P-type ESD implantation region.
  • FIG. 11 is a schematic diagram of a current path after the GGNMOS_P+ device without a P-type ESD injection region is turned on.
  • FIG. 12 is a schematic diagram of a current path after the GGNMOS_P+ device with a P-type ESD injection region is turned on.
  • FIG. 13 is an IV diagram of TLP testing of different GGNMOS_P+ devices with P-type ESD implantation regions introduced with different implantation conditions.
  • FIG. 14 is a schematic cross-sectional view of an ESD protection structure according to an embodiment of the present invention.
  • FIG. 15 is a schematic cross-sectional view of an ESD protection structure according to another embodiment of the present invention.
  • FIG. 2 is a schematic cross-sectional view of a GGNMOS device.
  • a P-type substrate 10 P_substrate
  • Deep_NWell deep N well
  • Pwell first well region 109
  • At least two interdigital units 100 are formed in and above 109, and each interdigital unit 100 includes a gate structure 101 formed on the substrate 10, and gate structures 101 formed in the substrate 10 and respectively located on both sides of the gate structure 101.
  • source region 103 and drain region 102 is a schematic cross-sectional view of a GGNMOS device.
  • P_substrate P-type substrate 10
  • Deep_NWell deep N well
  • Pwell first well region 109
  • FIG. 3 is a schematic diagram of the GGNMOS device shown in FIG. 2 and its internal equivalent triode circuit. Referring to FIG. 2 and FIG. 3 , during operation of the GGNMOS device, a parasitic NPN transistor Q is formed between the drain region 102 , the first well region 109 and the source region 103 .
  • the trigger voltage of the GGNMOS device shown in FIG. 2 is determined by the collector junction of the parasitic NPN transistor Q (that is, the N+/Pwell PN junction between the drain region 102 and the first well region 109) avalanche breakdown voltage. Therefore, an improved GGNMOS device reduces the breakdown voltage (BV) of Q by adding a P+ESD injection region under the drain region 102 , thereby reducing the trigger voltage of the GGNMOS device.
  • the triggering of GGNMOS devices can also be accelerated by introducing currents generated in other ways.
  • One of the commonly used methods is to couple a certain voltage on the gate structure 101 of the GGNMOS device to introduce channel current, which can achieve a trigger voltage lower than breakdown voltage purposes.
  • FIG. 4 is a schematic cross-sectional view of a GGNMOS_P+ device.
  • the GGNMOS_P+ device compared with the GGNMOS structure shown in FIG. The source region 103 and the drain region 102 located on both sides of the gate structure 101, and, the difference is that the GGNMOS_P+ device is formed with a second Doped region 105 (P-type).
  • the TLP test is performed on GGNMOS devices and GGNMOS_P+ devices with the same chip area, and the test results are shown in Figure 5. It can be seen that compared with GGNMOS devices, GGNMOS_P+ devices have higher overcurrent capability. Specifically, in the GGNMOS_P+ device, after the parasitic NPN junction in each interdigital unit 100 is turned on, the addition of the second doped region 105 at the source end of the GGNMOS_P+ device makes the electron current path go to the first well region 109 .
  • FIG. 6 is a simulated distribution diagram of current density after the parasitic NPN junction of the GGNMOS device is turned on. FIG.
  • FIG. 7 is a simulated distribution diagram of the current density after the parasitic NPN junction of the GGNMOS_P+ device is turned on. Comparing Figure 6 and Figure 7, it can be seen that the second doped region 105 added in the GGNMOS_P+ device helps to improve the distribution of the current path, and no current aggregation effect will be formed near the surface of the channel region. Referring to Figure 5, it can make the secondary breakdown The point delay appears, showing that the ESD robustness of the GGNMOS_P+ device is stronger.
  • the GGNMOS_P+ structure also has the advantage of high sustain voltage due to the longer current path of the GGNMOS_P+ device, resulting in an increased sustain voltage.
  • FIG. 8 and FIG. 9 are the TLP test IV diagrams of the hanging resistance (Res) experiment of the GGNMOS device and the GGNMOS_P+ device under the same chip area in the same process.
  • FIG. 10 is a schematic cross-sectional view of a GGNMOS_P+ device with a P-type ESD implantation region.
  • a common method is to perform P-type ESD implantation under the drain region 102 to form a P-type ESD implantation region 116 (P_ESD_IMP). .
  • FIG. 11 is a schematic diagram of a current path after the GGNMOS_P+ device without a P-type ESD injection region is turned on.
  • FIG. 12 is a schematic diagram of a current path after the GGNMOS_P+ device with a P-type ESD injection region is turned on. It can be seen from FIG. 11 and FIG. 12 that after adding the P-type ESD injection region 116, the area where the current of the GGNMOS_P+ device can be distributed is smaller.
  • FIG. 13 is the IV curves of TLP tests of different GGNMOS_P+ devices with P-type ESD implantation regions introduced with different implantation conditions. Slice comparisons of different doses and energies were made for the P-type ESD implantation region.
  • the trigger voltage of the GGNMOS_P+ device with the P-type ESD implantation region 116 has been reduced to varying degrees , but compared with the GGNMOS_P+ device without P-type ESD injection region (No_P_ESD_IMP), the current capability is severely degraded. That is, although the trigger voltage of the GGNMOS_P+ device with the P-type ESD injection region 116 can be reduced, it cannot obtain high overcurrent capability and high sustain voltage.
  • GGNMOS_P+ device has the advantages of high overcurrent capability and high sustain voltage
  • the trigger voltage cannot be reduced by introducing channel current, and introducing the P-type ESD injection region 116 will reduce the current capability and increase the masking capacity. Stencil, process production cost increased. None of the existing devices can achieve low trigger voltage while achieving high overcurrent capability and high sustain voltage.
  • the following embodiments provide an ESD protection structure.
  • FIG. 14 is a schematic cross-sectional view of an ESD protection structure according to an embodiment of the present invention.
  • FIG. 15 is a schematic cross-sectional view of an ESD protection structure according to another embodiment of the present invention.
  • the electrostatic discharge protection structure includes a substrate 10 , a source region 103 , a drain region 102 , a gate structure 101 and a first doped region 104 .
  • the substrate 10 has a first conductivity type. Both the source region 103 and the drain region 102 have a second conductivity type opposite to the first conductivity type, and are spaced apart in the substrate 10 .
  • the gate structure 101 is disposed on the substrate between the source region 103 and the drain region 102 .
  • the first doped region 104 has a first conductivity type, is arranged in the substrate on the side of the drain region 102 away from the gate structure 101, and is spaced apart from the drain region 102, so that The doping concentration of the first doped region 104 is greater than the doping concentration of the substrate 10 .
  • the source region 103 and the gate structure 101 are electrically connected to a first potential terminal (cathode terminal, Cathode), and the drain region 102 is electrically connected to a second potential terminal (anode region, Anode).
  • the first doped region 104 is floating.
  • the floating setting of the first doped region 104 may mean that the first doped region 104 is not connected to any external circuit.
  • the upper surface of the substrate of the first doped region 104 is covered with a SAB layer 108, so as to avoid the formation of metal silicide on the upper surface of the substrate of the first doped region 104, thereby avoiding the first doping
  • the region 104 is connected to an external circuit to realize the floating setting of the first doped region 104 .
  • the setting of the first doped region 104 can reduce the avalanche breakdown voltage of the collector junction of the parasitic NPN transistor of the ESD protection structure, thereby helping to reduce the trigger voltage of the ESD protection structure.
  • the electrostatic discharge protection structure may be GGNMOS. In another embodiment, the electrostatic discharge protection structure may be GGPMOS.
  • the first conductivity type is P-type
  • the second conductivity type is N-type
  • the first conductivity type is N type
  • the second conductivity type is P type.
  • the electrostatic discharge protection structure will be described below by taking the first conductivity type as P-type and the second conductivity type as N-type as an example.
  • the ESD protection structure includes a second doped region 105 .
  • the second doped region 105 is floating and has the first conductivity type, and is disposed in the substrate between the gate structure 101 and the source region 103 .
  • a floating second doped region 105 is provided between the gate structure 101 and the source region 103, which can improve the current path distribution of the electrostatic discharge protection structure, and no current accumulation will be formed near the surface of the channel region. effect, which delays the appearance of the secondary breakdown point, which helps to enhance the ESD robustness of the electrostatic discharge protection structure; moreover, because the second doped region 105 makes the current path when the electrostatic discharge protection structure is turned on longer, The sustain voltage of the electrostatic discharge protection structure may be increased.
  • the SAB layer 108 may cover the upper surface of the substrate of the first doped region 104 and the second doped region 105, and cover the substrate of the source region 103 and the drain. Region 102 is part of the upper surface of the substrate.
  • the metal silicide is formed on the exposed substrate surface of the source region 103 and the drain region 102, and the metal silicide The substance will not be formed on the upper surface of the substrate of the first doped region 104 and the second doped region 105, thereby avoiding the metal silicide and other conductive structures above the substrate 10 so that the first doped region 104 and the adjacent
  • the conduction of the drain region 102 and the conduction of the second doped region 105 with the adjacent source region 103 help to improve the performance of the ESD protection structure.
  • the SAB layer 108 may also cover other regions of the substrate 10 , and the exposed upper surface of the substrate 10 not covered by the SAB layer may be formed with a metal silicide layer.
  • the ESD protection structure may include a first isolation structure 115 located on the substrate between the gate structure 101 and the source region 103 middle.
  • the function of the first isolation structure 115 is similar to that of the second doped region 105, and it can also improve the current path distribution of the electrostatic discharge protection structure, and help avoid the formation of current aggregation effect near the surface of the channel region, and enhance the improving the ESD robustness of the ESD protection structure and increasing the sustain voltage of the ESD protection structure.
  • the first isolation structure 115 may be shallow trench isolation (STI). But not limited thereto, the first isolation structure 115 may also be junction isolation or local oxidation of silicon isolation (LOCOS).
  • the ESD protection structure may include a deep well region 114 (Deep_NWell) having a second conductivity type, and the deep well region 114 is formed in the substrate 10 (P_substrate).
  • the top of the deep well region 114 is formed with a first well region 109 (Pwell) of the first conductivity type, and the source region 103, the drain region 102 and the first doped region 104 are formed in At the top of the first well region 109 , the doping concentration of the first doped region 104 is greater than the doping concentration of the first well region 109 .
  • Forming the first well region 109 is helpful for the isolation protection of the electrostatic discharge protection structure.
  • the collector junction of the parasitic NPN transistor Q is the PN junction between the drain region 102 and the first well region 109 , that is, the PN junction of N+/Pwell.
  • the source region 103 and the drain region 102 with the second conductivity type and the first doped region 104 with the first conductivity type can be It is directly formed in the substrate 10 of the first conductivity type, which helps to simplify the process flow.
  • the collector junction of the parasitic NPN transistor Q is the PN junction between the drain region 102 and the substrate 10 , that is, the PN junction of N+/P_substrate.
  • a first well region lead-out region 106 with the first conductivity type is formed on the top of the first well region 109 , and the first well region lead-out region 106 is located at The source region 103 is away from the side of the gate structure 101 , and the first well region lead-out region 106 is electrically connected to the first potential terminal (Cathode).
  • Cathode first potential terminal
  • the electrostatic discharge protection structure may further include a second well region 110 (Nwell) having a second conductivity type, the second well region 110 is located at the top of the deep well region 114 and surrounds the first well region 109 ;
  • the top of the second well region 110 is formed with a second well region lead-out region 111 having a second conductivity type, and the doping concentration of the second well region lead-out region 111 is greater than that of the second well region 110 impurity concentration; the second well region lead-out region 111 is electrically connected to the third potential terminal (ISO).
  • ISO third potential terminal
  • An isolation structure (that is, a second isolation structure 107) is provided between the first well region lead-out region 106 and the source region 103; the first well region lead-out region 106 and the second well region lead-out region 111 There is an isolation structure between them.
  • the depths of the second isolation structure 107, the first isolation structure 115, and the isolation structures between the first well region lead-out region 106 and the second well region lead-out region 111 can be the same, so that these isolation structures can It is formed by the same process, which helps to save the manufacturing cost.
  • the electrostatic discharge protection structure may further include a third well region 112 (Pwell) having a first conductivity type, and the doping concentration of the third well region 112 is greater than that of the substrate 10 doping concentration; the top of the third well region 112 is formed with a third well region lead-out region 113, and the third well region lead-out region 113 has a first conductivity type and a doping concentration greater than that of the third well region The doping concentration of 112; the third well region lead-out region 113 is electrically connected to the fourth potential terminal (Psub).
  • Pwell third well region 112 having a first conductivity type, and the doping concentration of the third well region 112 is greater than that of the substrate 10 doping concentration
  • the top of the third well region 112 is formed with a third well region lead-out region 113, and the third well region lead-out region 113 has a first conductivity type and a doping concentration greater than that of the third well region
  • the depths of the first well region 109 , the second well region 110 and the third well region 112 may be the same. But not limited thereto, the depths of the first well region 109 , the second well region 110 and the third well region 112 may be different.
  • the distance k between the first doped region 104 and the drain region 102 can be adjusted according to the trigger voltage required by the electrostatic discharge protection structure. In different processes K values can vary.
  • the first doped region 104 can be formed by doping with a separate reticle, by increasing the first doped The lower the concentration of the impurity region 104 , the lower the trigger voltage of the ESD protection structure.
  • the doping depth and doping concentration of the first doped region 104 and the second doped region 105 , the first well region lead-out region 106 and the third well region lead-out region 113 may be the same. That is, the first doped region 104 and the second doped region 105, the first well region lead-out region 106 and the third well region lead-out region 113 can be obtained by doping with the same mask, which helps to save costs; Compared with the technical scheme in which the doped region 104 is made by a separate mask, the adjustable range of the doping concentration of the first doped region 104 is relatively narrow, and it is necessary to coordinate the adjustment between the first doped region 104 and the drain region 102. The size of the pitch to obtain the target trigger voltage.
  • the potential of the third potential terminal is different from the potentials of the first potential terminal, the second potential terminal and the fourth potential terminal.
  • the potentials of the first potential end and the fourth potential end are the same or different.
  • the first potential terminal is a cathode terminal (Cathode)
  • the second potential terminal is an anode terminal (Anode)
  • the potential of the anode terminal is different from the potential of the cathode terminal.
  • the electrostatic discharge protection structure may include at least two interdigital units 100, and each interdigital unit 100 includes a gate structure 101, a source region 103 and a drain region 102 . Every two adjacent interdigital units 100 form a pair, the drain regions 102 of a pair of interdigital units 100 are close to each other and the source regions 103 are far away from each other, and the first doped region 104 can be located between two Between two drain regions 102 that are close to each other and are shared by two interdigital units 100, and a pair of said interdigital units 100 are axially symmetrical with respect to the corresponding first doped region 104, thus helping to reduce electrostatic discharge The chip area occupied by the protection structure. But not limited thereto, the drain region 102 of each interdigital unit 100 may individually correspond to one first doped region 104 .
  • the first doped region 104 of the first conductivity type is disposed in the substrate on the side of the drain region 102 of the second conductivity type away from the gate structure 101, and is floating.
  • the first doped region 104 is spaced apart from the drain region 102 , and the doping concentration of the first doped region 104 is greater than the doping concentration of the substrate 10 .
  • the addition of the first doped region 104 can reduce the avalanche breakdown voltage of the collector junction of the parasitic NPN transistor (that is, the PN junction formed between the drain region 102 and the substrate 10) in the electrostatic discharge protection structure, and then Can reduce the trigger voltage of the electrostatic discharge protection structure, and compared with the traditional electrostatic discharge protection structure (such as traditional GGNMOS), under the same chip area, the ESD robustness of the electrostatic discharge protection structure of the present invention is higher; in addition , the ESD protection structure of the present invention does not need to introduce the P-type ESD injection region 116 in the GGNMOS_P+ device of FIG. 10 , and adding the first doped region 104 will not reduce the current capability of the ESD protection structure.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本发明提供一种静电放电保护结构。该静电放电保护结构中，衬底具有第一导电类型；源极区和漏极区均具有与第一导电类型相反的第二导电类型，且间隔设置在衬底中；栅极结构设置在源极区和漏极区之间的衬底上；浮空设置的第一掺杂区具有第一导电类型，设置在漏极区的远离栅极结构的一侧的衬底中，且与漏极区间隔设置，第一掺杂区的掺杂浓度大于衬底的掺杂浓度；源极区和栅极结构共同电连接至第一电位端，漏极区电连接至第二电位端。增加第一掺杂区能够降低静电放电保护结构的寄生NPN晶体管的集电结的雪崩击穿电压，有助于降低静电放电保护结构的触发电压。

Description

静电放电保护结构 技术领域
本发明涉及半导体技术领域，特别涉及一种静电放电保护结构。
背景技术
在芯片设计中，静电防护关系到芯片的可靠性。随着静电防护要求的提高，需要对芯片上负责静电放电(Electro-Static discharge，ESD)的保护结构进行不断的优化。
图1示出了一种在I/O口和电源钳位的ESD保护网络的结构。如图1所示，对于静电放电保护结构ESD3，若选用由5V NMOS改造成的相同工作电压的GGNMOS(Gate Ground NMOS，栅极接地NMOS)器件，会使静电放电保护结构ESD3和MOS管M3的触发电压相同，导致ESD3起不到保护M3的作用。因此，需要使用低触发电压的静电放电保护结构；同时静电放电保护结构ESD5作为电源钳位的保护，因成本原因需要采用兼容性较好的静电放电保护结构，但也同样需要低触发电压的静电放电保护结构。此外，从降低成本和缩小面积的角度考虑，需要静电放电保护结构具有强的鲁棒性。从闩锁防护的角度考虑，需要静电放电保护结构具有高的维持电压。
发明内容
为了降低静电放电保护结构的触发电压，本发明提供一种静电放电保护结构。
本发明提供的静电放电保护结构包括：衬底，具有第一导电类型；源极区和漏极区，均具有与所述第一导电类型相反的第二导电类型，间隔设置在所述衬底中；栅极结构，设置在所述源极区和所述漏极区之间的衬底上，所述源极区和所述栅极结构共同电连接至第一电位端，所述漏极区电连接至第二电位端；第一掺杂区，具有第一导电类型且为浮空设置，设置在所述漏极区的远离所述栅极结构的一侧的所述衬底中，且与所述漏极区间隔设置，所述第一掺杂区的掺杂浓度大于所述衬底的掺杂浓度。
可选的，所述第一掺杂区与所述漏极区之间的间距根据所述静电放电保护结构所需的触发电压的大小设置。
可选的，静电放电保护结构包括第二掺杂区，所述第二掺杂区具有第一导电类型，设置在所述栅极结构和所述源极区之间的衬底中，所述第二掺杂区为浮空设置。
可选的，静电放电保护结构包括SAB层，所述SAB层覆盖所述第一掺杂区和所述第二掺杂区的衬底上表面。
可选的，静电放电保护结构包括第一隔离结构，所述第一隔离结构位于所述栅极结构和所述源极区之间的衬底中。
可选的，静电放电保护结构包括具有第二导电类型的深阱区，所述深阱区形成于所述衬底中；所述深阱区内的顶部形成有具有第一导电类型的第一阱区，所述源极区、所述漏极区和所述第一掺杂区形成于所述第一阱区内的顶部，所述第一掺杂区的掺杂浓度大于所述第一阱区的掺杂浓度。
可选的，所述第一阱区内的顶部形成有具有第一导电类型的第一阱区引出区，所述第一阱区引出区位于所述源极区远离所述栅极结构的一侧，且所述第一阱区引出区电连接至所述第一电位端。
可选的，静电放电保护结构包括具有第二导电类型的第二阱区，所述第二阱区位于所述深阱区内的顶部且环绕所述第一阱区；所述第二阱区内的顶部形成有具有第二导电类型的第二阱区引出区，所述第二阱区引出区的掺杂浓度大于所述第二阱区的掺杂浓度；所述第二阱区引出区电连接至第三电位端；所述第一阱区引出区与所述源极区之间设置有隔离结构；所述第一阱区引出区与所述第二阱区引出区之间设置有隔离结构。
可选的，静电放电保护结构包括具有第一导电类型的第三阱区，所述第三阱区的掺杂浓度大于所述衬底的掺杂浓度；所述第三阱区内的顶部形成有第三阱区引出区，所述第三阱区引出区具有第一导电类型且掺杂浓度大于所述第三阱区的掺杂浓度；所述第三阱区引出区电连接至第四电位端。
可选的，所述第三电位端的电位与所述第一电位端、所述第二电位端和所述第四电位端的电位不同；且所述第一电位端与所述第四电位端的电位相同或不同。
可选的，所述第一电位端为阴极端，所述第二电位端为阳极端，所述阳极端的电位与所述阴极端的电位不同。
可选的，所述静电放电保护结构为GGNMOS。
可选的，静电放电保护结构包括至少两个叉指单元，每个所述叉指单元包括一所述栅极结构、一所述源极区和一所述漏极区；每两个相邻的所述叉指单元为一对，一对所述叉指单元的漏极区相互靠近，所述第一掺杂区位于两个相互靠近的漏极区之间，且一对所述 叉指单元关于对应的第一掺杂区轴对称。
本发明提供的静电放电保护结构中，具有第一导电类型的第一掺杂区设置在具有第二导电类型的漏极区的远离栅极结构的一侧的衬底中，第一掺杂区与漏极区间隔设置且为浮空设置，所述第一掺杂区的掺杂浓度大于所述衬底的掺杂浓度。增加设置的第一掺杂区能够降低静电放电保护结构中的寄生NPN晶体管的集电结(也即形成于漏极区和衬底之间的PN结)的雪崩击穿电压，进而能够降低静电放电保护结构的触发电压，而且与传统的静电放电保护结构(例如传统的GGNMOS)相比，在相同的芯片面积下，本发明的静电放电保护结构的ESD鲁棒性较高。
附图说明
图1为一种在I/O口和电源钳位的ESD保护网络的结构。
图2为一种GGNMOS器件的剖面示意图。
图3为图2所示的GGNMOS器件及其内部的等效三极管电路的示意图。
图4为一种GGNMOS_P+器件的剖面示意图。
图5为相同芯片面积的GGNMOS器件和GGNMOS_P+器件的TLP测试的IV曲线图。
图6为GGNMOS器件的寄生NPN结开启后的电流密度仿真分布图。
图7为GGNMOS_P+器件的寄生NPN结开启后的电流密度仿真分布图。
图8为GGNMOS器件的挂电阻实验的TLP测试IV图。
图9为GGNMOS_P+器件的挂电阻实验的TLP测试IV图。
图10为带有P型ESD注入区的GGNMOS_P+器件的剖面示意图。
图11为不带P型ESD注入区的GGNMOS_P+器件导通后的电流路径示意图。
图12是带有P型ESD注入区的GGNMOS_P+器件导通后的电流路径示意图。
图13为引入不同注入条件的P型ESD注入区的不同GGNMOS_P+器件的TLP测试的IV图。
图14为本发明一实施例的静电放电保护结构的剖面示意图。
图15为本发明另一实施例的静电放电保护结构的剖面示意图。
附图标记说明：10-衬底；100-叉指单元；101-栅极结构；102-漏极区；103-源极区；104-第一掺杂区；105-第二掺杂区；106-第一阱区引出区；107-第二隔离结构；108-SAB层； 109-第一阱区；110-第二阱区；111-第二阱区引出区；112-第三阱区；113-第三阱区引出区；114-深阱区；115-第一隔离结构；116-P型ESD注入区。
具体实施方式
以下结合附图和具体实施例对本发明提出的用于ESD保护的GGNMOS器件作进一步详细说明。根据下面说明，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
图2为一种GGNMOS器件的剖面示意图。如图2所示，该GGNMOS器件中，P型的衬底10(P_substrate)中设置有深N阱(Deep_NWell)，该深N阱内设置有第一阱区109(Pwell)，第一阱区109中及上方形成有至少两个叉指单元100，每个叉指单元100包括形成在衬底10上的栅极结构101、以及形成在衬底10中且分别位于栅极结构101两侧的源极区103和漏极区102。
图3为图2所示的GGNMOS器件及其内部的等效三极管电路的示意图。参考图2和图3，该GGNMOS器件在工作过程中，漏极区102、第一阱区109及源极区103之间构成寄生NPN晶体管Q。当阳极端(Anode)出现正的ESD脉冲时，漏端的漏极区102与第一阱区109之间的N+/Pwell结反偏，即Q的集电结反偏；当ESD脉冲电压达到一定大小时，Q出现雪崩击穿，产生雪崩电流；雪崩电流经过阱电阻R流到第一阱区引出区106，Q的基极b处的电位被抬高；当该雪崩电流继续增大，使基极b处的电位被抬高达到Q的发射结的正偏压降时，整个Q处于放大状态，形成发射极e电流，表现为GGNMOS器件被触发；由于Q放大状态下的发射极e电流相比通过源极区(source)外侧的第一阱区引出区106流出的电流更大，相应的传输线路脉冲(TLP)测试的电流电压(IV)曲线上会出现负阻区(snapback区，即回掷区)，阳极端的ESD电流将主要由Q泄放。
由上面的分析可以看出，图2所示的GGNMOS器件的触发电压决定于寄生NPN晶体管Q的集电结(即漏极区102与第一阱区109之间的N+/Pwell的PN结)的雪崩击穿电压。因此，一种改进GGNMOS器件通过在漏极区102下方增加一P+ESD注入区的方式来降低Q的击穿电压(BV)，进而降低GGNMOS器件的触发电压。此外，通过引入其他途径产生的电流，也可以加快GGNMOS器件的触发，其中常用的方法之一是在GGNMOS器件的栅极结构101上耦合一定的电压以引入沟道电流，可以实现触发电压低于击穿电压 的目的。
图4为一种GGNMOS_P+器件的剖面示意图。如图4所示，该GGNMOS_P+器件，相较于图2所示的GGNMOS结构，每个叉指单元100同样包括形成在衬底10上的栅极结构101、以及形成在衬底10中且分别位于栅极结构101两侧的源极区103和漏极区102，并且，不同的是，该GGNMOS_P+器件在每个叉指单元100的栅极结构101和源极区103之间形成有第二掺杂区105(P型)。
对相同芯片面积的GGNMOS器件和GGNMOS_P+器件进行TLP测试，其测试结果如图5所示，可以看出，相比GGNMOS器件，GGNMOS_P+器件具有较高的过电流能力。具体的，在GGNMOS_P+器件中，每个叉指单元100中的寄生NPN结开启后，GGNMOS_P+器件中源端的第二掺杂区105的加入使电子电流路径往第一阱区109体内走。图6为GGNMOS器件的寄生NPN结开启后的电流密度仿真分布图。图7为GGNMOS_P+器件的寄生NPN结开启后的电流密度仿真分布图。对比图6和图7可知，GGNMOS_P+器件中增加的第二掺杂区105有助于改善电流路径分布，在沟道区表面附近不会形成电流聚集效应，参考图5，可以使二次击穿点延后出现，表现出来是GGNMOS_P+器件的ESD鲁棒性更强。由于GGNMOS_P+器件的电流路径更长，导致维持电压增加，所以GGNMOS_P+结构也有高维持电压的优点。
对于GGNMOS_P+结构，源端加入了第二掺杂区105，形成了沟道电流的阻挡结构，即使在ESD脉冲下，栅极结构101上通过电阻耦合到一定的电压，也无法形成沟道电流。因此，GGNMOS_P+器件无法通过引入沟道电流来降低触发电压。图8和图9是在同一工艺中，相同芯片面积下的GGNMOS器件和GGNMOS_P+器件的挂电阻(Res)实验的TLP测试IV图。可以发现，图8中，当挂电阻Res＝160k欧姆(ohm)时，GGNMOS器件可以实现触发电压的降低；与之不同的是，图9中GGNMOS_P+结构不管挂电阻多大，都无法实现触发电压的降低。
图10为带有P型ESD注入区的GGNMOS_P+器件的剖面示意图。对于降低GGNMOS_P+器件的触发电压，一种思路是降低漏端的击穿电压，如图10所示，常用的方法是在漏极区102下方进行P型ESD注入形成P型ESD注入区116(P_ESD_IMP)。但是在制作工艺上，加入P型ESD注入区116需要增加P型ESD注入的掩模版，同时由于P型ESD注入区116和源端的第二掺杂区105的共同挤压作用，使GGNMOS_P+器件导 通后寄生NPN结的电子电流分布的区域很小，容易出现电流集中效应，使得热击穿提前出现。图11为不带P型ESD注入区的GGNMOS_P+器件导通后的电流路径示意图。图12是带有P型ESD注入区的GGNMOS_P+器件导通后的电流路径示意图。从图11和图12可以看到，增加P型ESD注入区116后，GGNMOS_P+器件电流可以分布的区域更小。
图13为引入不同注入条件的P型ESD注入区的不同GGNMOS_P+器件的TLP测试的IV曲线。对P型ESD注入区做了不同剂量和能量的分片对比，经过实际流片验证，如图13所示，虽然带有P型ESD注入区116的GGNMOS_P+器件的触发电压都有不同程度的降低，但与无P型ESD注入区(No_P_ESD_IMP)的GGNMOS_P+器件相比，电流能力退化严重。也即，带有P型ESD注入区116的GGNMOS_P+器件的触发电压虽能降低，但却又无法获得高过电流能力和高维持电压。
因此，上述的GGNMOS_P+器件虽然有高过电流能力和高维持电压的优点，但是触发电压不能通过引入沟道电流来降低，且引入P型ESD注入区116会带来电流能力的降低且增加了掩模版，工艺制作成本提高。已有的器件均无法在获得高过电流能力和高维持电压的同时实现低触发电压。
为了降低静电放电保护结构的触发电压，且使得静电放电保护结构保持高的ESD鲁棒性，具有高过电流能力和高维持电压，以下实施例提供一种静电放电保护结构。
图14为本发明一实施例的静电放电保护结构的剖面示意图。图15为本发明另一实施例的静电放电保护结构的剖面示意图。如图14和图15所示，所述静电放电保护结构包括衬底10、源极区103、漏极区102、栅极结构101和第一掺杂区104。
所述衬底10具有第一导电类型。所述源极区103和所述漏极区102均具有与所述第一导电类型相反的第二导电类型，且间隔设置在所述衬底10中。栅极结构101设置在所述源极区103和所述漏极区102之间的衬底上。
第一掺杂区104具有第一导电类型，设置在所述漏极区102的远离所述栅极结构101的一侧的所述衬底中，且与所述漏极区102间隔设置，所述第一掺杂区104的掺杂浓度大于所述衬底10的掺杂浓度。所述源极区103和所述栅极结构101共同电连接至第一电位端(阴极端，Cathode)，所述漏极区102电连接至第二电位端(阳极区，Anode)，所述第一掺杂区104为浮空设置。
所述第一掺杂区104浮空设置可以指：第一掺杂区104不连接任何外电路。本实施例 中，在所述第一掺杂区104的衬底上表面覆盖有SAB层108，以避免第一掺杂区104的衬底上表面形成金属硅化物，进而可以避免第一掺杂区104与外电路连接，以实现第一掺杂区104的浮空设置。所述第一掺杂区104的设置可以降低静电放电保护结构的寄生NPN晶体管的集电结的雪崩击穿电压，进而有助于降低静电放电保护结构的触发电压。
本实施例中，所述静电放电保护结构可以为GGNMOS。另一实施例中，所述静电放电保护结构可以为GGPMOS。
本实施例中，所述第一导电类型为P型，所述第二导电类型为N型。另一实施例中，所述第一导电类型为N型，所述第二导电类型为P型。以下以第一导电类型为P型，第二导电类型为N型为例对静电放电保护结构进行说明。
一实施例中，如图14所示，所述静电放电保护结构包括第二掺杂区105。所述第二掺杂区105浮空设置且具有第一导电类型，设置在所述栅极结构101和所述源极区103之间的衬底中。在所述栅极结构101和所述源极区103之间设置浮空的第二掺杂区105，可以改善静电放电保护结构的电流路径分布，且在沟道区表面附近不会形成电流聚集效应，使二次击穿点延后出现，有助于增强静电放电保护结构的ESD鲁棒性；而且，由于设置第二掺杂区105使得静电放电保护结构导通时的电流路径更长，可以增加所述静电放电保护结构的维持电压。
如图14所示，SAB层108可以覆盖所述第一掺杂区104和所述第二掺杂区105的衬底上表面、以及覆盖所述源极区103的衬底和所述漏极区102的衬底的部分上表面。在衬底10上生成金属硅化物层(图中未示出)时，由于SAB层108的阻挡，金属硅化物在源极区103和漏极区102露出的衬底表面上形成，且金属硅化物不会在第一掺杂区104和第二掺杂区105的衬底上表面形成，进而可以避免金属硅化物等位于衬底10上方的导电结构使得第一掺杂区104与相邻的漏极区102导通以及使得第二掺杂区105与相邻的源极区103导通，有助于提高静电放电保护结构的性能。但不限于此，所述SAB层108还可以覆盖衬底10的其它区域，不被SAB层覆盖且露出的衬底10的上表面均可以形成有金属硅化物层。
另一实施例中，如图15所示，静电放电保护结构可以包括第一隔离结构115，所述第一隔离结构115位于所述栅极结构101和所述源极区103之间的衬底中。第一隔离结构115与所述第二掺杂区105的功能类似，也可以改善所述静电放电保护结构的电流路径分 布，且有助于避免在沟道区表面附近形成电流聚集效应，增强所述静电放电保护结构的ESD鲁棒性和增加所述静电放电保护结构的维持电压。所述第一隔离结构115可以为浅沟槽隔离(STI)。但不限于此，所述第一隔离结构115还可以为结隔离或局部硅氧化隔离(LOCOS)。
如图14和图15所示，所述静电放电保护结构可以包括具有第二导电类型的深阱区114(Deep_NWell)，所述深阱区114形成于所述衬底10(P_substrate)中。所述深阱区114内的顶部形成有具有第一导电类型的第一阱区109(Pwell)，所述源极区103、所述漏极区102和所述第一掺杂区104形成于所述第一阱区109内的顶部，所述第一掺杂区104的掺杂浓度大于所述第一阱区109的掺杂浓度。形成第一阱区109有助于所述静电放电保护结构的隔离保护。则寄生NPN晶体管Q的集电结为漏极区102与第一阱区109之间的PN结，也即N+/Pwell的PN结。
需要说明的是，在其它实施例中，对于不需要隔离保护的器件结构，具有第二导电类型的源极区103和漏极区102、以及具有第一导电类型的第一掺杂区104可以直接形成于具有第一导电类型的衬底10中，如此有助于简化工艺流程。则寄生NPN晶体管Q的集电结为漏极区102与衬底10之间的PN结，也即N+/P_substrate的PN结。
如图14和图15所示，本实施例中，所述第一阱区109内的顶部形成有具有第一导电类型的第一阱区引出区106，所述第一阱区引出区106位于所述源极区103远离所述栅极结构101的一侧，且所述第一阱区引出区106电连接至所述第一电位端(Cathode)。
所述静电放电保护结构还可以包括具有第二导电类型的第二阱区110(Nwell)，所述第二阱区110位于所述深阱区114内的顶部且环绕所述第一阱区109；所述第二阱区110内的顶部形成有具有第二导电类型的第二阱区引出区111，所述第二阱区引出区111的掺杂浓度大于所述第二阱区110的掺杂浓度；所述第二阱区引出区111电连接至第三电位端(ISO)。
所述第一阱区引出区106与所述源极区103之间设置有隔离结构(即第二隔离结构107)；所述第一阱区引出区106与所述第二阱区引出区111之间设置有隔离结构。参考图15，所述第二隔离结构107、所述第一隔离结构115以及第一阱区引出区106与第二阱区引出区111之间的隔离结构的深度可以相同，如此这些隔离结构可以通过同一工艺制作形成，有助于节省制造成本。
如图14和图15所示，所述静电放电保护结构还可以包括具有第一导电类型的第三阱区112(Pwell)，所述第三阱区112的掺杂浓度大于所述衬底10的掺杂浓度；所述第三阱区112内的顶部形成有第三阱区引出区113，所述第三阱区引出区113具有第一导电类型且掺杂浓度大于所述第三阱区112的掺杂浓度；所述第三阱区引出区113电连接至第四电位端(Psub)。
参考图14和图15，所述第一阱区109、所述第二阱区110和所述第三阱区112的深度可以相同。但不限于此，第一阱区109、所述第二阱区110和所述第三阱区112的深度可以不同。
需要说明的是，所述第一掺杂区104和所述漏极区102之间的间距k(如图15所示)可以根据静电放电保护结构所需要的触发电压的大小调整，不同工艺中K值可以不同。在不考虑节省掩模版的前提下，且第一掺杂区104与漏极区102之间的间距固定时，第一掺杂区104可以利用单独的掩模版掺杂形成，通过增加第一掺杂区104的浓度，所述静电放电保护结构的触发电压越低。
为了节省掩模版，所述第一掺杂区104和第二掺杂区105、第一阱区引出区106和第三阱区引出区113的掺杂深度和掺杂浓度可以相同。即第一掺杂区104和第二掺杂区105、第一阱区引出区106和第三阱区引出区113可以采用同一掩模版掺杂获得，有助于节约成本；但是，与第一掺杂区104采用单独的掩模版制作的技术方案相比，如此第一掺杂区104的掺杂浓度的可调范围较窄，需要配合调整第一掺杂区104与漏极区102之间的间距大小来获得目标触发电压。
本实施例中，所述第三电位端的电位与所述第一电位端、所述第二电位端和所述第四电位端的电位不同。所述第一电位端与所述第四电位端的电位相同或不同。作为示例，所述第一电位端为阴极端(Cathode)，所述第二电位端为阳极端(Anode)，所述阳极端的电位与所述阴极端的电位不同。
如图14所示，本实施例中，所述静电放电保护结构可以包括至少两个叉指单元100，每个所述叉指单元100包括一所述栅极结构101、一所述源极区103和一所述漏极区102。每两个相邻的所述叉指单元100为一对，一对所述叉指单元100的漏极区102相互靠近而源极区103相互远离，所述第一掺杂区104可以位于两个相互靠近的漏极区102之间并被两个叉指单元100共用，且一对所述叉指单元100关于对应的第一掺杂区104轴对称，如 此，有助于减小静电放电保护结构占用的芯片面积。但不限于此，每个叉指单元100的漏极区102可以单独对应一个第一掺杂区104。
本发明的静电放电保护结构中，具有第一导电类型的第一掺杂区104设置在具有第二导电类型的漏极区102的远离栅极结构101的一侧的衬底中，浮空设置的第一掺杂区104与漏极区102间隔设置，所述第一掺杂区104的掺杂浓度大于所述衬底10的掺杂浓度。增加设置的第一掺杂区104能够降低静电放电保护结构中的寄生NPN晶体管的集电结(也即形成于漏极区102和衬底10之间的PN结)的雪崩击穿电压，进而能够降低静电放电保护结构的触发电压，而且与传统的静电放电保护结构(例如传统的GGNMOS)相比，在相同的芯片面积下，本发明的静电放电保护结构的ESD鲁棒性较高；此外，本发明的静电放电保护结构无需引入图10的GGNMOS_P+器件中的P型ESD注入区116，增加第一掺杂区104也不会降低静电放电保护结构的电流能力。
上述描述仅是对本发明较佳实施例的描述，并非对本发明权利范围的任何限定，任何本领域技术人员在不脱离本发明的精神和范围内，都可以利用上述揭示的方法和技术内容对本发明技术方案做出可能的变动和修改，因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化及修饰，均属于本发明技术方案的保护范围。

Claims (13)

  1. 一种静电放电保护结构，其特征在于，包括：
    衬底，具有第一导电类型；
    源极区和漏极区，均具有与所述第一导电类型相反的第二导电类型，间隔设置在所述衬底中；
    栅极结构，设置在所述源极区和所述漏极区之间的衬底上；
    第一掺杂区，具有第一导电类型，设置在所述漏极区的远离所述栅极结构的一侧的所述衬底中，且与所述漏极区间隔设置，所述第一掺杂区的掺杂浓度大于所述衬底的掺杂浓度；
    所述源极区和所述栅极结构共同电连接至第一电位端，所述漏极区电连接至第二电位端，所述第一掺杂区为浮空设置。
  2. 如权利要求1所述的静电放电保护结构，其特征在于，所述第一掺杂区与所述漏极区之间的间距根据所述静电放电保护结构所需的触发电压的大小设置。
  3. 如权利要求1所述的静电放电保护结构，其特征在于，包括第二掺杂区，具有第一导电类型，设置在所述栅极结构和所述源极区之间的衬底中，所述第二掺杂区为浮空设置。
  4. 如权利要求3所述的静电放电保护结构，其特征在于，包括SAB层，所述SAB层覆盖所述第一掺杂区和所述第二掺杂区的衬底上表面。
  5. 如权利要求1所述的静电放电保护结构，其特征在于，包括第一隔离结构，所述第一隔离结构位于所述栅极结构和所述源极区之间的衬底中。
  6. 如权利要求1所述的静电放电保护结构，其特征在于，包括具有第二导电类型的深阱区，所述深阱区形成于所述衬底中；所述深阱区内的顶部形成有具有第一导电类型的第一阱区，所述源极区、所述漏极区和所述第一掺杂区形成于所述第一阱区内的顶部，所述第一掺杂区的掺杂浓度大于所述第一阱区的掺杂浓度。
  7. 如权利要求6所述的静电放电保护结构，其特征在于，所述第一阱区内的顶部形成有具有第一导电类型的第一阱区引出区，所述第一阱区引出区位于所述源极区远离所述栅极结构的一侧，且所述第一阱区引出区电连接至所述第一电位端。
  8. 如权利要求7所述的静电放电保护结构，其特征在于，包括具有第二导电类型的第二阱区，所述第二阱区位于所述深阱区内的顶部且环绕所述第一阱区；所述第二阱区内的顶部形成有具有第二导电类型的第二阱区引出区，所述第二阱区引出区的掺杂浓度大于所述第二阱区的掺杂浓度；所述第二阱区引出区电连接至第三电位端；
    所述第一阱区引出区与所述源极区之间设置有隔离结构；所述第一阱区引出区与所述第二阱区引出区之间设置有隔离结构。
  9. 如权利要求8所述的静电放电保护结构，其特征在于，包括具有第一导电类型的第三阱区，所述第三阱区的掺杂浓度大于所述衬底的掺杂浓度；所述第三阱区内的顶部形成有第三阱区引出区，所述第三阱区引出区具有第一导电类型且掺杂浓度大于所述第三阱区的掺杂浓度；所述第三阱区引出区电连接至第四电位端。
  10. 如权利要求9所述的静电放电保护结构，其特征在于，所述第三电位端的电位与所述第一电位端、所述第二电位端和所述第四电位端的电位不同；且所述第一电位端与所述第四电位端的电位相同或不同。
  11. 如权利要求1所述的静电放电保护结构，其特征在于，所述第一电位端为阴极端，所述第二电位端为阳极端，所述阳极端的电位与所述阴极端的电位不同。
  12. 如权利要求1所述的静电放电保护结构，其特征在于，所述静电放电保护结构为GGNMOS。
  13. 如权利要求1所述的静电放电保护结构，其特征在于，包括至少两个叉指单元，每个所述叉指单元包括一所述栅极结构、一所述源极区和一所述漏极区；每两个相邻的所述叉指单元为一对，一对所述叉指单元的漏极区相互靠近，所述第一掺杂区位于两个相互靠近的漏极区之间，且一对所述叉指单元关于对应的第一掺杂区轴对称。
PCT/CN2022/115047 2021-11-30 2022-08-26 静电放电保护结构 WO2023098174A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202111443893.3A CN116207090A (zh) 2021-11-30 2021-11-30 静电放电保护结构
CN202111443893.3 2021-11-30

Publications (1)

Publication Number Publication Date
WO2023098174A1 true WO2023098174A1 (zh) 2023-06-08

Family

ID=86511643

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/115047 WO2023098174A1 (zh) 2021-11-30 2022-08-26 静电放电保护结构

Country Status (2)

Country Link
CN (1) CN116207090A (zh)
WO (1) WO2023098174A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117790500B (zh) * 2024-02-19 2024-05-10 成都芯翼科技有限公司 一种用于m-lvds端口的静电放电保护结构

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110042716A1 (en) * 2009-08-20 2011-02-24 Tai-Hsiang Lai ESD protection device structure
CN107346786A (zh) * 2016-05-05 2017-11-14 中芯国际集成电路制造(上海)有限公司 Ggnmos 晶体管、多指 ggnmos 器件及电路
CN110265391A (zh) * 2019-06-05 2019-09-20 南京邮电大学 一种内嵌浮空n+区的ligbt型esd防护器件
CN111326507A (zh) * 2018-12-17 2020-06-23 爱思开海力士有限公司 静电放电保护装置
CN214848631U (zh) * 2021-07-08 2021-11-23 湖南静芯微电子技术有限公司 低压带栅单向可控硅静电防护器件

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110042716A1 (en) * 2009-08-20 2011-02-24 Tai-Hsiang Lai ESD protection device structure
CN107346786A (zh) * 2016-05-05 2017-11-14 中芯国际集成电路制造(上海)有限公司 Ggnmos 晶体管、多指 ggnmos 器件及电路
CN111326507A (zh) * 2018-12-17 2020-06-23 爱思开海力士有限公司 静电放电保护装置
CN110265391A (zh) * 2019-06-05 2019-09-20 南京邮电大学 一种内嵌浮空n+区的ligbt型esd防护器件
CN214848631U (zh) * 2021-07-08 2021-11-23 湖南静芯微电子技术有限公司 低压带栅单向可控硅静电防护器件

Also Published As

Publication number Publication date
CN116207090A (zh) 2023-06-02

Similar Documents

Publication Publication Date Title
US6498357B2 (en) Lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process
US9520488B2 (en) Silicon-controlled rectifier electrostatic discharge protection device and method for forming the same
US11574903B2 (en) Positive strike SCR, negative strike SCR, and a bidirectional ESD structure that utilizes the positive strike SCR and the negative strike SCR
US6830966B2 (en) Fully silicided NMOS device for electrostatic discharge protection
US20020185682A1 (en) Additional n-type LDD/pocket implant for improving short-channel NMOS ESD robustness
TWI515862B (zh) 靜電放電保護電路
US6521487B1 (en) Method for making a thyristor
US5844280A (en) Device for protecting a semiconductor circuit
CN104704636B (zh) 具有用于负电压操作的隔离式scr的esd保护电路
CN103187413A (zh) 用于esd的垂直bjt和scr
TW201843802A (zh) 高電壓靜電放電保護裝置、電路及其製作方法
KR20040023477A (ko) 실리콘 게르마늄 기술용 정전 방전 보호 실리콘 제어정류기(ｅｓｄ-ｓｃｒ)
WO2023098174A1 (zh) 静电放电保护结构
KR100364588B1 (ko) 정전류를 방전하기 위하여 바이폴러 트랜지스터에 의해 구현된 보호회로를 구비한 반도체장치 및 그 제조공정
US8598625B2 (en) ESD protection device with tunable design windows
US12002890B2 (en) Semiconductor protection device
CN110690270A (zh) 一种内嵌硅控整流器的pmos器件及其实现方法
WO2023284472A1 (zh) Ggnmos晶体管结构、esd保护器件及电路
US9281304B2 (en) Transistor assisted ESD diode
JP2012094797A (ja) 半導体装置及びその製造方法
CN110518010B (zh) 一种内嵌硅控整流器的pmos器件及其实现方法
CN114883381A (zh) 可控硅静电防护器件及其制造方法
KR102454469B1 (ko) Esd 보호용 scr 소자
TW201724458A (zh) 場效電晶體及半導體裝置
WO2024093701A1 (zh) 静电放电保护器件

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22899990

Country of ref document: EP

Kind code of ref document: A1