WO2021039631A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2021039631A1
WO2021039631A1 PCT/JP2020/031634 JP2020031634W WO2021039631A1 WO 2021039631 A1 WO2021039631 A1 WO 2021039631A1 JP 2020031634 W JP2020031634 W JP 2020031634W WO 2021039631 A1 WO2021039631 A1 WO 2021039631A1
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semiconductor layer
source electrode
electrode
semiconductor device
gate electrode
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French (fr)
Japanese (ja)
Inventor
優人 山際
柳原　学
佐藤　高広
正洋 引田
弘明 上野
雄介 木下
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Panasonic Intellectual Property Management Co Ltd
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Panasonic Intellectual Property Management Co Ltd
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Priority to US17/637,352 priority Critical patent/US12439661B2/en
Priority to JP2021542839A priority patent/JP7649974B2/ja
Publication of WO2021039631A1 publication Critical patent/WO2021039631A1/ja
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    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
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    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
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    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
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    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H10D30/4755—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs
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    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
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    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
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    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
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    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
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    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
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    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
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    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/257—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes
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    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs

Definitions

  • the present invention relates to a semiconductor device having a nitride semiconductor layer, and more particularly to a semiconductor device used for a switching power supply circuit, an inverter, or the like.
  • Group III-V nitride compound semiconductors represented by gallium nitride (GaN), so-called nitride semiconductors, general formula In x Ga y Al 1-x -y N (0 ⁇ x ⁇ 1,0 ⁇ y ⁇ It is a compound semiconductor composed of aluminum (Al), gallium (Ga), and indium (In), which are group III elements, and nitrogen (N), which is a group V element, represented by 1, x + y ⁇ 1).
  • Nitride semiconductors can form various mixed crystals, and heterojunction interfaces can be easily formed.
  • Heterojunction of nitride semiconductors is characterized in that a high-concentration two-dimensional electron gas layer (2DEG layer) is generated at the interface by spontaneous polarization and piezo polarization.
  • Field effect transistors FETs: Field Effect Transistors
  • FETs Field Effect Transistors
  • FIG. 9 shows a cross-sectional view of an FET using a conventional nitride semiconductor.
  • the potential of the substrate 901 is generally connected to the source electrode 912, which has a low potential.
  • FIG. 10 shows a half-bridge structure in which a high-side first FET 91 and a low-side second FET 92 using a conventional nitride semiconductor are integrated.
  • the substrate 901 is connected to the source electrode 922 of the second FET 92 whose potential is stable in order to suppress the generation of noise from the substrate 901 during switching.
  • FIG. 11A shows the waveforms of the drain-source voltage Vds and the drain current Ids during switching of the conventional low-side second FET
  • FIG. 11B shows the drain-source voltage during switching of the conventional high-side first FET. It is a waveform of Vds and drain current Ids.
  • the drain source voltage Vds rises to about 50V due to the current collapse.
  • conventionally there is a problem that the conduction loss of the first FET becomes large and the channel temperature of the first FET on the high side easily exceeds the absolute maximum rated temperature.
  • an object of the present disclosure is to provide a semiconductor device that suppresses the generation of current collapse in a half-bridge structure in which FETs using nitride semiconductors are integrated.
  • a third semiconductor layer is formed in a part between the lower part of the source electrode of the FET and the gate electrode, separated from the gate electrode.
  • the electrons captured in the nitride semiconductor layer under the source electrode are recombined by the Hall current injected from the third semiconductor layer formed under the source electrode of the FET. Therefore, there is an effect of suppressing the generation of current collapse.
  • FIG. 1A is a plan view of the semiconductor device according to the first embodiment.
  • FIG. 1B is a cross-sectional view between A and A of the semiconductor device according to the first embodiment.
  • FIG. 1C is a cross-sectional view between BB of the semiconductor device according to the first embodiment.
  • FIG. 1D is an equivalent circuit diagram of the semiconductor device according to the first embodiment.
  • FIG. 2A is a switching circuit diagram according to the first embodiment.
  • FIG. 2B is a switching waveform in the first embodiment.
  • FIG. 2C is an operation diagram of the FET in the on state of the first embodiment.
  • FIG. 3A is a cross-sectional view of the semiconductor device according to the first embodiment.
  • FIG. 3B is a plan view of the semiconductor device according to the first embodiment.
  • FIG. 3C is a plan view of the semiconductor device according to the first embodiment.
  • FIG. 4A is a plan view of the semiconductor device according to the first modification of the first embodiment.
  • FIG. 4B is a cross-sectional view between A and A in the first modification of the first embodiment.
  • FIG. 4C is another example of the cross-sectional view between A and A in the first modification of the first embodiment.
  • FIG. 4D is a plan view of another configuration of the semiconductor device according to the first modification of the first embodiment.
  • FIG. 5A is a plan view of the semiconductor device according to the second modification of the first embodiment.
  • FIG. 5B is a cross-sectional view between A and A in the second modification of the first embodiment.
  • FIG. 5C is a cross-sectional view between BB in the second modification of the first embodiment.
  • FIG. 5D is an operation diagram of the FET in the off state of the modification 2 of the first embodiment.
  • FIG. 6A is a plan view of the semiconductor device according to the second embodiment.
  • FIG. 6B is a cross-sectional view between A and A in the second embodiment.
  • FIG. 6C is a plan view of the semiconductor device in the modified example of the second embodiment.
  • FIG. 7A is a plan view of the semiconductor device according to the third embodiment.
  • FIG. 7B is a cross-sectional view between A and A in the third embodiment.
  • FIG. 8A is an operation diagram of the bidirectional FET in the off state of the third embodiment.
  • FIG. 8B is an operation diagram of the bidirectional FET in the on state of the third embodiment.
  • FIG. 8C is an operation diagram of the bidirectional FET in the off state of the third embodiment.
  • FIG. 8D is an operation diagram of the bidirectional FET in the on state of the third embodiment.
  • FIG. 9 is a cross-sectional view of a conventional semiconductor device.
  • FIG. 10 is a cross-sectional view of a half bridge composed of a conventional semiconductor device.
  • FIG. 11A is a low-side switching waveform of a conventional half bridge.
  • FIG. 11B is a high-side switching waveform of a conventional half bridge.
  • FIG. 1A shows a plan view of the semiconductor device 10 according to the first embodiment of the present disclosure.
  • a first FET 1 first field effect transistor 1
  • first source electrode 112 a first source electrode 112
  • second gate electrode 113 a second drain electrode 121
  • second source electrode 122 a second source electrode 122
  • second FET 2 second field effect transistor 2
  • FIG. 1B shows a cross-sectional view taken along the line AA of FIG. 1A.
  • FIG. 1C shows a cross-sectional view taken along the line BB of FIG. 1A.
  • a buffer layer 102, a GaN channel layer 103 (first nitride semiconductor layer 103), and an AlGaN barrier layer 104 (second nitride semiconductor layer 104) having a bandgap larger than that of the GaN channel layer 103 on a substrate 101 made of Si. ) Are formed in this order.
  • the buffer layer 102 is composed of, for example, a multilayer structure composed of AlN and AlGaN, and the total film thickness is, for example, about 2.1 ⁇ m.
  • the GaN channel layer 103 is made of, for example, undoped GaN, and the layer thickness is, for example, about 1.6 ⁇ m.
  • the composition of the AlGaN barrier layer 104 is, for example, Al 0.17 Ga 0.83 N, and the layer thickness is, for example, about 60 nm.
  • a high-concentration 2DEG layer 105 is formed at the interface between the GaN channel layer 103 and the AlGaN barrier layer 104 due to the effects of piezo polarization and spontaneous polarization.
  • a first drain electrode 111 forming a first FET 1, a first source electrode 112, a first gate electrode 113, and a second drain electrode 121 forming a second FET 2 on the AlGaN barrier layer 104, a first The source electrode 122 of 2 and the second gate electrode 123 are formed.
  • the first drain electrode 111, the first source electrode 112, the second drain electrode 121, and the second source electrode 122 are, for example, a laminate of titanium (Ti) and aluminum (Al), and are respectively formed on the 2DEG layer 105. Make ohmic contact with it.
  • the first gate electrode 113 and the second gate electrode 123 are, for example, a laminate of nickel (Ni) and gold (Au), and are in Schottky contact with the AlGaN barrier layer 104. Further, the first gate electrode 113 and the second gate electrode 123 may be formed of a P-type semiconductor.
  • Each of the first drain electrodes 111 is connected to the first drain integrated wiring 11.
  • Each of the first gate electrodes 113 is connected to the first gate integrated wiring 13.
  • Each of the second source electrodes 122 is connected to the second source integrated wiring 22.
  • the second gate electrode 123 is connected to the second gate integrated wiring 23, respectively.
  • the first source electrode 112 and the second drain electrode 121 are each connected to the intermediate centralized wiring 12.
  • FIG. 1D shows an equivalent circuit of the semiconductor device 10 according to the first embodiment.
  • the semiconductor device 10 according to the first embodiment is a half bridge, the first FET 1 is on the high side, and the second FET 2 is on the low side.
  • the substrate 101 when a half bridge including a high-side first FET 1 and a low-side second FET 2 is configured, the substrate 101 is electrically connected to a floating or second source electrode 122. ..
  • the second source electrode 122 When the substrate 101 is electrically connected to the second source electrode 122, the second source electrode 122 is generally fixed at a stable potential of a low voltage, so that the substrate 101 is connected to the second source electrode 122. As a result, the voltage fluctuation of the substrate 101 is eliminated, and the generation of noise can be suppressed.
  • the first FET 1 is separated from the first gate electrode 113 between the lower portion of the first source electrode 112 and the first gate electrode 113 on the AlGaN barrier layer 104.
  • the third semiconductor layer 114 is selectively formed.
  • the third semiconductor layer 114 is formed by electrical contact so as to be embedded in a part of the first source electrode 112.
  • the third semiconductor layer 114 is made of, for example, GaN, and is preferably a P-type semiconductor.
  • FIG. 2A is a typical example of a switching circuit using a half bridge.
  • a first FET1 on the high side and a second FET2 on the low side forming a half bridge are connected to both ends of the high voltage power supply 71.
  • One end of the inductor 72 is connected to the midpoint of the half bridge, and the load 73 is connected to the other end of the inductor 72.
  • FIG. 2B shows the operation waveform of the switching circuit of FIG. 2A.
  • the first FET 1 is in the off state, and the drain-source voltage Vds_H of the first FET 1 is the high voltage power supply 71. It becomes the voltage of.
  • the voltage of the high voltage power supply 71 is, for example, about 400V.
  • the first FET 1 During the period T2 in which a voltage equal to or higher than the threshold voltage is applied to the gate-source voltage Vgs_H of the first FET 1, the first FET 1 is in the ON state, and a current flows through the load 73 via the drain and the source.
  • FIG. 2C shows the operation of the first FET 1 when the first FET 1 is in the ON state.
  • the voltage of the first drain electrode 111 is fixed at 400 V, and the voltage of the substrate 101 is fixed at 0 V. Since the first FET 1 is in the ON state, the drain source voltage Vds_H is about 1 V. Therefore, the voltage of the first source electrode 112 is about 399V.
  • a downward electric field E_S-SUB is applied between the first source electrode 112 and the substrate 101. By this E_S-SUB electric field, electrons are captured in the buffer layer 102, the GaN channel layer 103, and the AlGaN barrier layer 104 near the first source electrode 112.
  • the third semiconductor layer 114 of the P-type semiconductor is formed of the AlGaN barrier layer 104 between the lower portion of the first source electrode 112 and the first gate electrode 113. It is formed on the surface, and a hole current Ih_S flows from the third semiconductor layer 114 toward the substrate 101.
  • the hole current Ih_S can suppress the narrowing of the 2DEG layer 105 and suppress the increase in on-resistance by recombining with the electrons captured in the buffer layer 102, the GaN channel layer 103, and the AlGaN barrier layer 104. ..
  • the third semiconductor layer 114 is formed so that a part of the first source electrode 112 overlaps with the first drain electrode 111.
  • the distance to the first source electrode 112 can be reduced, and the size of the semiconductor device 10 can be reduced.
  • the third semiconductor layer 114A is planarly separated from the first source electrode 112, and is separated from the first source electrode 112 by the source connection portion 116.
  • the configuration may be such that the third semiconductor layer 114A is electrically connected.
  • the source connection portion 116 and the first source electrode 112 may be made of different materials. For example, by using a material having better ohmic contact with respect to the third semiconductor layer 114A than the first source electrode 112 as the source connecting portion 116, for example, a metal material containing palladium (Pd), the third semiconductor layer 114A It is possible to increase the hole current Ih_S with respect to the substrate 101 and suppress an increase in on-resistance.
  • the third semiconductor layer 114B may have a structure that surrounds the periphery of the first source electrode 112. With such a structure, an increase in on-resistance can be suppressed in the entire region of the first source electrode 112.
  • the third semiconductor layer 114C may be formed in an island shape along the first source electrode 112.
  • FIG. 4A shows a plan view of the semiconductor device 10D according to the first modification of the first embodiment of the present disclosure.
  • FIG. 4B shows a cross-sectional view taken along the line AA of FIG. 4A.
  • a contact portion between the first source electrode 112 and the AlGaN barrier layer 104 is formed between the third semiconductor layer 114D and the first gate electrode 113. ..
  • the distance from the first drain electrode 111 to the first source electrode 112 can be made smaller than that in FIG. 1A of the first embodiment.
  • a hole current flows from the third semiconductor layer 114D toward the substrate 101, and an increase in on-resistance can be suppressed.
  • the thickness of the AlGaN barrier layer 104 below the third semiconductor layer 114E is the thickness of the AlGaN barrier layer 104 in other regions. It may be thinner than the thickness. Since the AlGaN barrier layer 104 below the third semiconductor layer 114E is thin, the hole current Ih_S injected from the third semiconductor layer 114E can be increased, and the buffer layer 102, the GaN channel layer 103, and the AlGaN barrier can be increased. Since the electrons captured in the layer 104 can be efficiently recombined, the increase in on-resistance can be further suppressed.
  • the on-resistance does not increase.
  • the third semiconductor layer 114F may be formed in an island shape as shown in FIG. 4D.
  • FIG. 5A shows a plan view of the semiconductor device 10G according to the second modification of the first embodiment of the present disclosure.
  • 5B shows a cross-sectional view taken along the line AA of FIG. 5A
  • FIG. 5C shows a cross-sectional view taken along the line BB of FIG. 5A.
  • the fourth semiconductor layer 115 connected to the first drain electrode 111 of the first FET 1 is formed, and the second drain electrode 121 of the second FET 2 is formed.
  • a fifth semiconductor layer 125 to be connected is formed.
  • the fourth semiconductor layer 115 and the fifth semiconductor layer 125 are made of, for example, GaN, and are preferably P-type semiconductors.
  • FIG. 5D shows the operation of the first FET 1G when the first FET 1G is off. Since the first FET 1G is in the off state, the drain-source voltage Vds_H of the first FET 1G is about 400 V. Therefore, a downward electric field E_D-SUB is applied between the first drain electrode 111 and the substrate 101, and a lateral electric field E_DS is applied between the first drain electrode 111 and the first gate electrode 113. ..
  • the E_D-SUB electric field and the E_DS electric field capture electrons in the buffer layer 102, the GaN channel layer 103, and the AlGaN barrier layer 104 in the vicinity of the first drain electrode 111.
  • the fourth semiconductor layer 115 of the P-type semiconductor is formed on the surface of the AlGaN barrier layer 104, and the first FET is turned off.
  • the first drain electrode 111 has a power supply voltage of 400 V
  • the first source electrode 112 and the first gate electrode 113 have a voltage of about 0 V
  • the substrate 101 has a voltage of 0 V.
  • the hole current Ih_D flows from the fourth semiconductor layer 115 toward the substrate and the direction of the first gate electrode 113.
  • the hole current Ih_D can suppress the narrowing of the 2DEG layer 105 and suppress the increase in on-resistance by recombining with the electrons captured in the buffer layer 102, the GaN channel layer 103, and the AlGaN barrier layer 104. ..
  • the fifth semiconductor layer 125 provided in the second FET 2 can also suppress the narrowing of the 2DEG layer 105 and suppress the increase in on-resistance by the same mechanism.
  • the fourth semiconductor layer 115 is formed so as to be separated from the first gate electrode 113.
  • the fourth semiconductor layer 115 and the first drain electrode 111 are electrically connected to each other.
  • the fifth semiconductor layer 125 is formed so as to be separated from the second gate electrode 123.
  • the fifth semiconductor layer 125 and the second drain electrode 121 are electrically connected to each other.
  • FIG. 6A shows a plan view of the semiconductor device 10H according to the second embodiment.
  • FIG. 6B shows a cross section taken along the line AA of FIG. 6A.
  • the same components as those in the first embodiment, that is, the components in which the parts excluding the alphabet of the symbols have the same numbers, will be omitted because they have already been described.
  • the first source electrode of the first FET 1H and the second drain electrode of the second FET 2H are shared to form a common electrode 130.
  • the intermediate integrated wiring 12 is connected to the common electrode 130.
  • the common electrode 130 also serves as the first source electrode of the first FET 1H and the second drain electrode of the second FET 2H, the diagram of the first embodiment is shown.
  • the chip area can be reduced as compared with the case where the first source electrode 112 and the second drain electrode 121 shown in 1A are individually present.
  • a fifth semiconductor layer 125J connected to the common electrode 130 may be formed.
  • the hole current Ih_D flows in the state where the FET is off, and the buffer layer 102 and the GaN channel layer
  • the narrowing of the 2DEG layer 105 can be suppressed and the increase in on-resistance can be suppressed.
  • the third semiconductor layer 114J and the fifth semiconductor layer 125J may be in contact with each other at both ends of the common electrode 130 in the longitudinal direction.
  • FIG. 7A is a semiconductor device 10K according to the third embodiment, and shows a plan view of the semiconductor device 10K including the bidirectional FET 3 (bidirectional field effect transistor 3).
  • FIG. 7B shows a cross section taken along the line AA of FIG. 7A.
  • a first source electrode 311 constituting a bidirectional FET 3, a second source electrode 321 and a first gate electrode 313, and a second gate electrode 323 are formed on the AlGaN barrier layer 104.
  • Each of the first source electrodes 311 is connected to the first source integrated wiring 31.
  • Each of the second source electrodes 321 is connected to the second source integrated wiring 32.
  • Between the first source electrode 311 and the second source electrode 321 is a first gate electrode 313 close to the first source electrode 311 and a second gate close to the second source electrode 321. Electrodes are formed.
  • a third semiconductor is separated from the first gate electrode 313 between the lower portion of the first source electrode 311 and the first gate electrode 313 on the AlGaN barrier layer 104.
  • Layer 314 is formed.
  • the third semiconductor layer 314 is formed by electrical contact so as to be embedded in a part of the first source electrode 311.
  • a fourth semiconductor layer 324 is formed on the AlGaN barrier layer 104 between the lower portion of the second source electrode 321 and the second gate electrode 323, separated from the second gate electrode 323. ..
  • the fourth semiconductor layer 324 is formed by electrical contact so as to be embedded in a part of the second source electrode 321.
  • the interruption and conduction operation of the bidirectional FET 3 according to the third embodiment will be described.
  • the voltage of the second source electrode 321 is higher than that of the first source electrode 311 and the voltage of the first gate electrode 313 is equal to or less than the threshold voltage of the first source electrode 311.
  • the 2DEG layer 105 below the first gate electrode 313 is depleted, and a current does not flow from the second source electrode 321 to the first source electrode 311.
  • a voltage equal to or higher than the threshold voltage is applied to the first source electrode 311, the 2DEG layer 105 below the first gate electrode 313 becomes conductive, and the second gate electrode 313 becomes conductive. A current flows from the source electrode 321 of the above to the first source electrode 311.
  • the voltage of the first source electrode 311 is higher than that of the second source electrode 321, a voltage whose voltage of the second gate electrode 323 is equal to or lower than the threshold voltage is applied to the second source electrode 321.
  • the 2DEG layer 105 below the second gate electrode 323 is depleted, and a current does not flow from the first source electrode 311 to the second source electrode 321.
  • the 2DEG layer 105 below the second gate electrode 323 becomes conductive, and the first A current flows from the source electrode 311 of the above to the second source electrode 321.
  • the first gate electrode 313 and the second gate electrode 323 with reference to the first source electrode 311 and the second source electrode 321 respectively, the first source electrode 311 and the second source electrode 311 and the second source electrode 321 can be controlled. It is possible to control the interruption and continuity of the bidirectional current with the source electrode 321.
  • FIG. 8A shows the operation of the transistor when the bidirectional FET 3 is in the off state and the voltage of the second source electrode 321 is higher than that of the first source electrode 311.
  • the voltage of the second source electrode 321 is, for example, about 400 V.
  • the voltage of the substrate 101 is, for example, 0V.
  • the magnitude relationship between the voltages of the first source electrode 311 and the second source electrode 321 changes depending on the operation of the system. Therefore, the potential of the substrate 101 is changed to the potential of the first source electrode 311 and the second source electrode 321. It is common to float without connecting directly to.
  • FIG. 8B shows the operation immediately after the bidirectional FET 3 is switched from the off state to the on state.
  • the voltage of the first source electrode 311 is set to 0V, which is the reference voltage
  • the voltage of the second source electrode 321 drops from 400V to about 2V. Since the voltage of the substrate 101 immediately after the bidirectional FET 3 is switched to the ON state is that the substrate 101 is floating, the voltage of the substrate 101 is the capacitance from the second source electrode 321 to the substrate 101 and the voltage from the first source electrode 311.
  • the voltage of the substrate 101 is approximately if the ratio of the capacitance from the second source electrode 321 to the substrate 101 and the capacitance from the first source electrode 311 to the substrate 101 is 1: 1. It becomes -199V.
  • a downward electric field E_S1-SUB is applied between the first source electrode 311 and the substrate 101.
  • E_S1-SUB electrons are captured in the buffer layer 102, the GaN channel layer 103, and the AlGaN barrier layer 104 near the first source electrode 311.
  • the third semiconductor layer 314 of the P-type semiconductor is formed on the surface of the AlGaN barrier layer 104, and when the bidirectional FET 3 is switched to the on state, the third semiconductor layer 314 is formed.
  • the hole current Ih_S1 flows from the semiconductor layer 314 of the above toward the substrate 101.
  • the hole current Ih_S1 can suppress the narrowing of the 2DEG layer 105 and suppress the increase in on-resistance by recombination with the electrons captured in the buffer layer 102, the GaN channel layer 103, and the AlGaN barrier layer 104. ..
  • FIG. 8C shows the operation in the off state of the bidirectional FET 3.
  • the voltage of the second source electrode 321 is, for example, 0 V, which is a reference voltage
  • the voltage of the first source electrode 311 is, for example, about 400 V.
  • the voltage of the substrate 101 is 0V.
  • FIG. 8D shows the behavior when the bidirectional FET switches from the off state to the on state.
  • the voltage of the second source electrode 321 is 0V
  • the voltage of the first source electrode 311 drops from 400V to about 2V
  • the voltage of the substrate 101 becomes about -199V.
  • a downward electric field E_S2-SUB is generated from the second source electrode 321 with respect to the substrate 101, and electrons are captured in the buffer layer 102, the GaN channel layer 103, and the AlGaN barrier layer 104 near the second source electrode 321. Will be done.
  • the fourth semiconductor layer 324 of the P-type semiconductor is formed on the surface of the AlGaN barrier layer 104, and when the bidirectional FET 3 is switched to the ON state, the second semiconductor layer 324 is formed.
  • the hole current Ih_S2 flows from the semiconductor layer 324 of No. 4 toward the substrate 101.
  • the hole current Ih_S2 can suppress the narrowing of the 2DEG layer 105 and suppress the increase in on-resistance by recombination with the electrons captured in the buffer layer 102, the GaN channel layer 103, and the AlGaN barrier layer 104. ..
  • the semiconductor device according to the present disclosure can be used as a half bridge, which is a typical configuration of a switching power supply. It can also be used as a full bridge composed of two half bridges or a three-phase inverter composed of three half bridges. It can also be used for active clamp type flyback converters.
  • First FET First field effect transistor
  • Second FET Second field effect transistor
  • Bidirectional FET bidirectional field effect transistor
  • Semiconductor device 11 1st drain aggregated wiring 12 Intermediate aggregated wiring 13 1st gate aggregated wiring 22 2nd source aggregated wiring 23 2nd gate aggregated wiring 31 1st source aggregated wiring 32 2nd source aggregated wiring 33 1st Gate Consolidated Wiring 34 2nd Gate Consolidated Wiring 71 High Voltage Power Supply 72 inductor 73 Load 101 Board 102 Buffer Layer 103 GaN Channel Layer (1st Nitride Semiconductor Layer) 104 AlGaN barrier layer (second nitride semiconductor layer) 105 Two-dimensional electron gas layer (2DEG layer) 111 1st drain electrode 112, 311 1st source electrode 113, 313 1st gate electrode 114, 314 3rd semiconductor layer 115, 324 4th semiconductor layer 121 2nd drain electrode 122, 321 2nd Source electrode 123, 323 Second gate electrode 125 Fifth semiconductor layer 130 Common

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  • Junction Field-Effect Transistors (AREA)
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4293726A3 (en) * 2022-05-26 2024-03-06 United Microelectronics Corp. Hemt with stair-like compound layer at drain
JP2024135349A (ja) * 2023-03-22 2024-10-04 株式会社東芝 半導体装置及びその製造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007526633A (ja) * 2004-02-12 2007-09-13 インターナショナル レクティファイアー コーポレイション Ｉｉｉ族窒化膜双方向スイッチ
JP2008098434A (ja) * 2006-10-12 2008-04-24 Matsushita Electric Ind Co Ltd 窒化物半導体トランジスタ及びその製造方法
JP2013125918A (ja) * 2011-12-16 2013-06-24 Sumitomo Electric Ind Ltd 半導体装置
WO2014188651A1 (ja) * 2013-05-20 2014-11-27 パナソニックＩｐマネジメント株式会社 半導体装置
JP2015173151A (ja) * 2014-03-11 2015-10-01 株式会社東芝 半導体装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4730529B2 (ja) 2005-07-13 2011-07-20 サンケン電気株式会社 電界効果トランジスタ
JP2008099434A (ja) 2006-10-11 2008-04-24 Sony Corp 電子機器、電源供給方法および電源供給システム
JP5879805B2 (ja) 2011-08-09 2016-03-08 富士通株式会社 スイッチング素子及びこれを用いた電源装置
JP6553336B2 (ja) 2014-07-28 2019-07-31 エア・ウォーター株式会社 半導体装置
JP6834546B2 (ja) 2017-02-03 2021-02-24 サンケン電気株式会社 半導体装置及びその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007526633A (ja) * 2004-02-12 2007-09-13 インターナショナル レクティファイアー コーポレイション Ｉｉｉ族窒化膜双方向スイッチ
JP2008098434A (ja) * 2006-10-12 2008-04-24 Matsushita Electric Ind Co Ltd 窒化物半導体トランジスタ及びその製造方法
JP2013125918A (ja) * 2011-12-16 2013-06-24 Sumitomo Electric Ind Ltd 半導体装置
WO2014188651A1 (ja) * 2013-05-20 2014-11-27 パナソニックＩｐマネジメント株式会社 半導体装置
JP2015173151A (ja) * 2014-03-11 2015-10-01 株式会社東芝 半導体装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4293726A3 (en) * 2022-05-26 2024-03-06 United Microelectronics Corp. Hemt with stair-like compound layer at drain
US12224333B2 (en) 2022-05-26 2025-02-11 United Microelectronics Corp. HEMT with stair-like compound layer at drain
JP2024135349A (ja) * 2023-03-22 2024-10-04 株式会社東芝 半導体装置及びその製造方法

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