WO2021036805A1 - 信号生成电路及其方法、数字时间转换电路及其方法 - Google Patents
信号生成电路及其方法、数字时间转换电路及其方法 Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
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- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/005—Time-to-digital converters [TDC]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/14—Time supervision arrangements, e.g. real time clock
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
- H03L7/0996—Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/24—Automatic control of frequency or phase; Synchronisation using a reference signal directly applied to the generator
Definitions
- the embodiments of the present disclosure relate to a signal generation circuit, a signal generation method, a digital time conversion circuit, and a digital time conversion method.
- the time of the chip in the electronic system can refer to the clock signal cycle.
- the period of the clock signal is generally on the order of nanoseconds. For example, if a clock signal period is 20 nanoseconds (ns), the accuracy of the counter obtained from the clock signal may be 20 ns, that is, the resolution of the counter cannot be lower than 20 ns. However, this resolution or accuracy is difficult to meet actual application requirements in scientific research, military applications, consumer electronics and other fields.
- the time period is small to a certain extent (for example, in the order of picoseconds), it is difficult to control parameters such as signal jitter and phase noise, so that the integrity of the signal cannot be guaranteed. Therefore, it is difficult to further increase the frequency and reduce the time period.
- the signal generating circuit includes: a first generating circuit configured to generate a periodic first output signal based on a first frequency control word and a reference time unit; and a second generating circuit configured to generate a periodic first output signal based on a second frequency control word and a reference time unit
- the unit generates a periodic second output signal.
- the first frequency control word includes a first integer part and a first decimal part
- the second frequency control word includes a second integer part and a second decimal part.
- the first integer part is equal to the second integer part, and the first decimal part is connected to the second decimal part.
- the parts are not equal, and the period of the first output signal is not equal to the period of the second output signal.
- the period difference between the period of the first output signal and the period of the second output signal is related to the reference time unit and the decimal difference between the first fractional part and the second fractional part.
- the first generation circuit includes a first digitally controlled oscillator sub-circuit and a first conversion sub-circuit.
- the first digitally controlled oscillator sub-circuit is configured to generate a first intermediate signal based on the first frequency control word and the reference time unit.
- the first conversion sub-circuit is configured to convert the first intermediate signal into a first output signal.
- the second generating circuit includes a second digitally controlled oscillator sub-circuit and a second conversion sub-circuit.
- the second digitally controlled oscillator sub-circuit is configured to generate a second intermediate signal based on the second frequency control word and the reference time unit.
- the second conversion sub-circuit is configured to convert the second intermediate signal into a periodic second output signal.
- the first intermediate signal is generated in an interleaved manner by pulses with a first original period and pulses with a second original period.
- the first average period of the first intermediate signal is expressed by the following formula:
- T h (1-r h ) ⁇ T A +r h ⁇ T B ,
- T h represents the first average period of the first intermediate signal
- rh represents the first fractional part
- T A represents the first original period
- T B represents the second original period.
- the second intermediate signal is The pulses of the original period and the pulses with the second original period are generated in an interleaved manner, and the second average period of the second intermediate signal is expressed by the following formula:
- T l (1-r l ) ⁇ T A +r l ⁇ T B ,
- T l represents the second averaging period of the second intermediate signal
- r l represents the second fractional part
- the first conversion sub-circuit includes a first filter configured to filter out high frequency components in the first intermediate signal to obtain the first output signal.
- the parameters of the first filter are determined based on the average frequency of the first intermediate signal and the least significant digit of the first fractional part.
- the parameters of the first filter include the bandwidth of the first filter, and the bandwidth of the first filter is determined according to the following formula:
- Bwlp1 is the bandwidth of the first filter
- r LSB1 is the value corresponding to the least significant bit of the first fractional part
- F h is the first frequency control word
- ⁇ is the reference time unit.
- the second conversion sub-circuit includes a second filter configured to filter out high frequency components in the second intermediate signal to obtain the second output signal.
- the parameters of the second filter are determined based on the average frequency of the second intermediate signal and the least significant digit of the second fractional part.
- the parameters of the second filter include the bandwidth of the second filter, and the bandwidth of the second filter is determined according to the following formula:
- Bwlp2 is the bandwidth of the second filter
- r LSB2 is the value corresponding to the least significant bit of the second fractional part
- F l is the second frequency control word
- ⁇ is the reference time unit.
- both the first digitally controlled oscillator subcircuit and the second digitally controlled oscillator subcircuit include a time average frequency direct period synthesizer.
- the signal generating circuit further includes a reference time unit generating circuit, and the reference time unit generating sub-circuit is configured to generate a reference time unit.
- the reference time unit generation circuit includes a plurality of D flip-flops.
- the reference time unit generation circuit includes: a voltage controlled oscillator configured to oscillate at a predetermined oscillation frequency; a phase-locked loop circuit configured to lock the output frequency of the voltage controlled oscillator to the reference output frequency ; And K output terminals, configured to output K output signals with evenly spaced phases, where K is a positive integer greater than 1.
- the reference output frequency is expressed as f ⁇
- the reference time unit is the time span between any two adjacent output signals output by the K output terminals
- the signal generation circuit further includes a control circuit.
- the control circuit is configured to determine the first frequency control word and the second frequency control word, and output the first frequency control word to the first generation circuit, and output the second frequency control word to the second generation circuit.
- At least one embodiment of the present disclosure also provides a digital time conversion circuit.
- the digital time conversion circuit includes: any one of the signal generation circuits described above; and a time generation circuit configured to receive a digital signal, a first output signal, and a second output signal; and based on the digital signal, the first output signal, and the second output signal; The second output signal generates a first time pulse signal or a second time pulse signal corresponding to the digital signal.
- the first minimum time interval between the rising edge and the falling edge of the first time pulse signal is related to the reference time unit, the first fractional part, and the second fractional part; or, the second time pulse signal includes the first sub-pulse signal and the first sub-pulse signal.
- the second minimum time interval between the rising edge of the first sub-pulse signal and the rising edge of the second sub-pulse signal is related to the reference time unit, the first fractional part and the second fractional part.
- the digital time conversion circuit also includes a phase detector circuit.
- the phase detector circuit is configured to determine the phase relationship between the first output signal and the second output signal to generate an indication signal indicating that the phase of the first output signal is aligned with the phase of the second output signal.
- the time generating circuit is configured to generate the first time pulse signal or the second time pulse signal based on the digital signal, the first output signal, the second output signal, and the indication signal.
- the first generating circuit includes a first digitally controlled oscillator sub-circuit configured to generate a first intermediate signal based on the first frequency control word and a reference time unit and configured to convert the first intermediate signal into The first conversion sub-circuit of the first output signal
- the second generation circuit includes a second digitally controlled oscillator sub-circuit configured to generate a second intermediate signal based on the second frequency control word and the reference time unit, and a second digitally controlled oscillator sub-circuit configured to convert the first A second conversion sub-circuit for converting two intermediate signals into a periodic second output signal.
- the first generating circuit is further configured to output a first rising edge control word corresponding to the rising edge of the first intermediate signal and a first falling edge control word corresponding to the falling edge of the first intermediate signal when the first intermediate signal is generated. Word, and the first fractional frequency control word corresponding to the period switching of the first intermediate signal.
- the second generation circuit is also configured to output a second rising edge control word corresponding to the rising edge of the second intermediate signal and a second falling edge control word corresponding to the falling edge of the second intermediate signal when the second intermediate signal is generated. Word, and the second decimal frequency control word corresponding to the period switching of the second intermediate signal.
- the phase detector circuit is configured to: based on the first rising edge control word, the second rising edge control word, the first falling edge control word, the second falling edge control word, the first fractional frequency control word, and the second fractional frequency control word Generate indication signal.
- the phase detector circuit is configured to: the first rising edge control word is equal to the second rising edge control word, the first falling edge control word is equal to the second falling edge control word, and the first fractional frequency control In the case where both the word and the second decimal frequency control word are equal to zero, an indication signal is generated.
- the first minimum time interval or the second minimum time interval is expressed as:
- DeltaT represents the first minimum time interval or the second minimum time interval
- n represents the bit width of the digital signal
- t R represents the period difference between the period of the first output signal and the period of the second output signal
- t R represents for:
- rh represents the first decimal part of the first frequency control word
- r l represents the second decimal part of the second frequency control word
- ⁇ represents the reference time unit
- At least one embodiment of the present disclosure also provides a signal generation method.
- the signal generation method includes: generating a periodic first output signal based on a first frequency control word and a reference time unit; and generating a periodic second output signal based on a second frequency control word and a reference time unit.
- the first frequency control word includes a first integer part and a first decimal part
- the second frequency control word includes a second integer part and a second decimal part.
- the first integer part is equal to the second integer part, and the first decimal part is connected to the second decimal part.
- the parts are not equal, and the period of the first output signal is not equal to the period of the second output signal.
- the period difference between the period of the first output signal and the period of the second output signal is related to the reference time unit and the decimal difference between the first fractional part and the second fractional part.
- generating the periodic first output signal based on the first frequency control word and the reference time unit includes: generating a first intermediate signal based on the first frequency control word and the reference time unit; and converting the first intermediate signal It is the first output signal.
- Generating the periodic second output signal based on the second frequency control word and the reference time unit includes: generating the second intermediate signal based on the second frequency control word and the reference time unit; and converting the second intermediate signal into the second output signal.
- the first intermediate signal is generated in an interleaved manner by pulses with a first original period and pulses with a second original period.
- the first average period of the first intermediate signal is expressed by the following formula:
- T h (1-r h ) ⁇ T A +r h ⁇ T B ,
- T h represents an average of the first cycle of the first intermediate signal
- r h represents a first fractional part
- T A represents the first original period
- T B represents the second original period.
- the second intermediate signal is generated in an interleaved manner by pulses with the first original period and pulses with the second original period, and the second average period of the second intermediate signal is expressed by the following formula:
- T l (1-r l ) ⁇ T A +r l ⁇ T B ,
- T l represents a second average period of the second intermediate signal
- r l represent the fractional part of a second
- T A represents the first original period
- T B represents the second original period
- converting the first intermediate signal into the first output signal includes filtering out high frequency components in the first intermediate signal to convert the first intermediate signal into the first output signal.
- converting the second intermediate signal into the second output signal includes filtering out high frequency components in the second intermediate signal to convert the second intermediate signal into the second output signal.
- At least one embodiment of the present disclosure also provides a digital time conversion method applied to the above-mentioned digital time conversion circuit.
- the digital time conversion method includes: receiving a digital signal, a first output signal, and a second output signal; and generating a first time pulse signal or a second time pulse corresponding to the digital signal based on the digital signal, the first output signal, and the second output signal signal.
- the digital time conversion method further includes: determining the phase relationship between the first output signal and the second output signal to generate an indication signal indicating that the phase of the first output signal is aligned with the phase of the second output signal.
- generating the periodic first output signal based on the first frequency control word and the reference time unit includes generating the first intermediate signal based on the first frequency control word and the reference time unit, and converting the first intermediate signal into The first output signal
- generating a periodic second output signal based on the second frequency control word and the reference time unit includes generating a second intermediate signal based on the second frequency control word and the reference time unit, and converting the second intermediate signal into a second output signal.
- the digital time conversion method further includes: obtaining a first rising edge control word corresponding to the rising edge of the first intermediate signal, and a first falling edge control corresponding to the falling edge of the first intermediate signal when the first intermediate signal is generated.
- Determining the phase relationship between the first output signal and the second output signal to generate the indication signal includes: based on the first rising edge control word, the second rising edge control word, the first falling edge control word, the second falling edge control word, and the first A fractional frequency control word and a second fractional frequency control word generate an indication signal.
- the indication signal indicating that the phase of the first output signal is aligned with the phase of the second output signal includes: the first rising edge control word is equal to the second rising edge control word, the first falling edge control word is equal to the second falling edge control word, And when the first fractional frequency control word and the second fractional frequency control word are both equal to zero, an indication signal is generated.
- FIG. 1A shows a schematic block diagram of a signal generating circuit according to some embodiments of the present disclosure
- FIG. 1B shows a schematic block diagram of a signal generating circuit according to some embodiments of the present disclosure
- FIG. 2 shows a block diagram of a signal generating circuit in the case where both the first frequency control word and the second frequency control word include corresponding decimal parts according to some embodiments of the present disclosure
- Fig. 3 shows a schematic diagram of the principle of time average frequency according to some embodiments of the present disclosure
- Fig. 6 shows a schematic diagram of a first output signal and a second output signal according to some embodiments of the present disclosure
- FIG. 7 shows a schematic diagram of K reference signals with evenly spaced phases and reference time units according to some embodiments of the present disclosure
- Fig. 8 shows a schematic diagram of a reference time unit generating circuit according to some embodiments of the present disclosure
- FIG. 9 shows a schematic diagram of another reference time unit generating circuit according to some embodiments of the present disclosure.
- FIG. 10 shows a circuit diagram of a time average frequency direct period synthesizer based on a time average frequency direct period synthesis circuit architecture according to some embodiments of the present disclosure
- Figure 11 shows a circuit diagram of a phase locked loop according to some embodiments of the present disclosure
- FIG. 12 shows a block diagram of a signal generation circuit in a case where the second frequency control word is an integer according to some embodiments of the present disclosure
- FIG. 13A shows a block diagram of a digital time conversion circuit according to some embodiments of the present disclosure
- FIG. 13B shows a schematic diagram of a first time pulse signal according to some embodiments of the present disclosure
- FIG. 13C shows a schematic diagram of a second time pulse signal according to some embodiments of the present disclosure
- FIG. 14A shows a block diagram of a digital time conversion circuit according to some embodiments of the present disclosure
- Fig. 14B shows an example of the phase detector circuit in Fig. 14A
- FIG. 14C shows another example of the phase detector circuit in FIG. 14A
- FIG. 15A shows a block diagram of a digital time conversion circuit according to some embodiments of the present disclosure
- FIG. 15B shows an example of the phase detector circuit in FIG. 15A
- FIG. 15C shows another example of the phase detector circuit in FIG. 15A
- FIG. 16 shows a flowchart of a signal generation method according to some embodiments of the present disclosure.
- FIG. 17 shows a flowchart of a digital time conversion method according to some embodiments of the present disclosure.
- Digital time conversion can refer to the conversion of digital information input by the user into a pulse signal with a corresponding length of time. For example, if the input integer n, the length of time can be obtained pulse n ⁇ T R, wherein T R is the minimum resolution of the pulse.
- the digital time conversion can be realized by various methods such as the traditional delay method, the variable slope charging method, the cursor method, and the edge interpolation method.
- the traditional delay method can be realized by a buffer. Because the buffer is greatly affected by environmental factors and the signal stability is not good, the traditional delay method cannot guarantee the accuracy and precision of the time. The linearity of the variable slope charging method is poor, and the accuracy of the time cannot be guaranteed.
- the vernier method is difficult to identify the phase of the pulse signal, and with the increase of the test range, the required logic devices increase geometrically.
- the edge interpolation method needs to insert a resistor in the circuit, which increases power consumption and area.
- Embodiments according to the present disclosure provide a signal generation circuit, a signal generation method, a digital time conversion circuit, and a digital time conversion method.
- Various circuits and methods for example, a signal generation circuit, a signal generation method, a digital time conversion circuit, and a digital time conversion method) according to the embodiments of the present disclosure are simple to implement, and can achieve extremely high time accuracy and accuracy at the same time.
- the method based on the time average frequency can obtain pulse signals with extremely small period differences (e.g., on the order of picoseconds).
- the digital time conversion circuit or the digital time conversion method according to the embodiments of the present disclosure it is possible to obtain time interval pulses with sufficiently small time resolution and extremely high stability and accuracy.
- VLSI Functional Tester Timing Generator
- IC Pulse Parametric Tester Phase Locked Loop.
- PLL Phase Locked Loop.
- ATE Automatic Test Equipment
- DDFS Direct Digital Frequency Synthesis
- Radar Radar
- At least one embodiment of the present disclosure provides a signal generation circuit.
- 1A to 1B show block diagrams of signal generating circuits according to some embodiments of the present disclosure.
- the signal generating circuit 10 may include a first generating circuit 101 and a second generating circuit 102.
- a first generation circuit 101 may be configured to control word F h ⁇ and generating a periodic reference time unit of the first output signal S h based on the first frequency.
- the second generating circuit 102 may be configured to generate a periodic second output signal S l based on the second frequency control word F l and the reference time unit ⁇ . For example, the first output signal S h period and the second period of the output signal S l is not equal.
- the time difference between the time length of the period of the first output signal S h and the time length of the period of the second output signal S 1 represents the time resolution.
- the time resolution can reach up to 50%. On the order of seconds.
- the period difference between the period of the first output signal Sh and the period of the second output signal S l may be the same as the reference time unit ⁇ , the first frequency control word F h, and the second frequency control word F l Related.
- the period between the first output signal S h period and the period of the second output signal S l is the difference between the reference time unit, and ⁇ decimal fractional part of the difference between the first and the second related to the fractional part.
- the reference time unit ⁇ may be a time span (e.g., phase difference) between any two adjacent reference signals of K reference signals with evenly spaced phases, where K is a positive integer greater than one. Therefore, the reference time unit ⁇ can correspond to K reference signals with evenly spaced phases.
- the input of the reference time unit ⁇ to the first generation circuit 101 and the second generation circuit 102 shown in some diagrams of the embodiments of the present disclosure may represent K corresponding to the reference time unit ⁇ .
- the reference signals whose phases are evenly spaced are input to the first generating circuit 101 and the second generating circuit 102.
- the signal generating circuit 10 may further include a reference time unit generating circuit 103.
- the reference time unit generating circuit 103 may be configured to generate K reference signals with evenly spaced phases, where the time span between any two adjacent reference signals of the K reference signals with evenly spaced phases (for example, the phase difference ) Is the reference time unit ⁇ .
- the reference time unit generation circuit 103 can be implemented by a twisted ring counter (ie, Johnson Counter).
- the reference time unit generating circuit 103 can be implemented by a multi-stage voltage controlled oscillator.
- the first frequency control word F h may include a first integer part and a first fractional part
- the second frequency control word F l may include a second integer part and a second fractional part, the first integer part and the first fractional part.
- the two integer parts are the same, and the first fractional part and the second fractional part are not equal.
- the first frequency control word F h can be 8.25
- the second frequency control word F l can be 8.125, that is, the first integer part is 8, the first fractional part is 0.25, the second integer part is 8, and the second fractional part is 8. The part is 0.125.
- one of the first frequency control word F h and the second frequency control word F 1 can be an integer, that is, the first fractional part or the second fractional part can be zero.
- the first fractional part is not zero, and the second fractional part is zero.
- the first frequency control word F h may be 8.125
- the second frequency control word F l may be 8. At this time, The first integer part is 8, the first decimal part is 0.125, the second integer part is 8, and the second decimal part is 0.
- the first frequency control word F h and a second control both the frequency word F l are integers.
- the first fractional part and the second fractional part can both be zero.
- the first frequency control word F h can be 9, and the second frequency control word F l can be 8.
- the first integer part is 9, the first fractional part is 0, the second integer part is 8, and the first integer part is 0.
- the second decimal part is 0.
- the period between the first output signal S h period and the period of the second output signal S l is the difference between the reference time unit and related to the difference ⁇ between the first portion and the second integer the integer portion.
- the embodiment of the signal generating circuit 10 will be described later in the case where the first frequency control word F h and the second frequency control word F l both include corresponding fractional parts (that is, the first fractional part and the second fractional part are not 0). and performing a second example of the signal generating circuit under control of a frequency F l is an integer word (the second fractional part is zero) of the case 10.
- the signal generating circuit 10 may further include a control circuit 104.
- the control circuit 104 may be configured to determine the first frequency control word F h and the second frequency control word F l , and output the first frequency control word F h to the first generating circuit 101, and output the second frequency control word F 1 to the first frequency control word F l Two generation circuit 102.
- the first frequency control word F h and the second frequency control word F 1 can be input to the control circuit 104 by a user through an input device.
- the first frequency control word F h and the second frequency control word F 1 may be stored in a storage device in advance, and may be read by the control circuit 104.
- the first frequency control word F h and the second frequency control word F l can also be automatically generated by the control circuit 104.
- Figure 2 shows a block diagram of a signal generation circuit in the case where the first control word frequency F h and F l second frequency control word includes a respective fractional portion of the embodiment according to some of the present disclosure.
- the first frequency control word F h may include a first integer part and a first fractional part
- the second frequency control word F l may include a second integer part and a second decimal part.
- the part is the same as the second integer part, and the first fractional part and the second fractional part are not equal.
- both the first fractional part and the second fractional part may not be equal to zero.
- the signal generating circuit 20 may include a first generating circuit 201 and a second generating circuit 202.
- the first generating circuit 201 may include a first digitally controlled oscillator (Digitally Controlled Oscillator, DCO) sub-circuit 2011 and a first conversion sub-circuit 2012.
- the second generation circuit 202 may include a second DCO sub-circuit 2021 and a second conversion sub-circuit 2022.
- the first DCO sub-circuit 2011 may be configured to generate the first intermediate signal Sh1 based on the first frequency control word F h and the reference time unit ⁇ , and the first conversion sub-circuit 2012 may be configured to convert the first intermediate signal Sh1 Converted to the first output signal Sh .
- the second DCO sub-circuit 2021 may be configured to generate the second intermediate signal S l1 based on the second frequency control word F l and the reference time unit ⁇ , and the second conversion sub-circuit 2022 may be configured to convert the second intermediate signal S l1 Converted to the second output signal S l .
- the first DCO sub-circuit 2011 may be implemented based on Time Average Frequency (TAF).
- TAF Time Average Frequency
- the method based on the TAF technology can use two or more periods with different lengths to generate the clock frequency.
- the TAF technology uses pulses of two different time periods (the first period T 1 and the second period T 2 ) to synthesize the clock signal as an example for description.
- two time periods can be obtained: first The period T 1 and the second period T 2 .
- the first period T 1 and the second period T 2 can be expressed by equations (1) and (2), respectively.
- a clock signal including two different periods (different frequencies) can be generated in an interleaved manner.
- the average period of the generated clock signal is T TAF , as shown in equation (3).
- the average frequency of the generated clock signal is 1/T TAF .
- T TAF (1-r) ⁇ T 1 +r ⁇ T 2 Formula (3)
- the fractional part r of the frequency control word F can control the probability of the second period T 2.
- the fractional part r of the frequency control word F can control the switching frequency between the first period T 1 and the second period T 2 (hereinafter referred to as period switching).
- period switching the clock signal generated by 1 T 1 T 2 T 1 T mode cycle 2 cycle T obtained, i.e., T 1 T 1 T 2 T 1 T 2 T 1 T 1 T 2 T 1 T 2 T 1 T 2 T 1 T 2 T 1 T 2 T 1 T 2 T 1 T 2 .
- the generated clock signal is obtained by the pattern period T 1 T 2 of the cycle, i.e., T 1 T 2 T 1 T 2 T 1 T 2 .
- the period TAF art manner used in the period of the clock signal generated based on the difference between the TAF art two different periodic manner based TAF technique used a T 1 and T 2 are It may be referred to as the original period, and the period T TAF of the clock signal generated based on the TAF technology may be referred to as the averaging period.
- the frequency 1/T TAF of the clock signal generated based on the TAF technology can be referred to as the average frequency.
- the first DCO sub-circuit 2011 can be realized.
- the first intermediate signal Sh1 generated by the first DCO sub-circuit 2011 passes through the first original period (for example, corresponding to the first period T 1 described above) and the second original period (For example, corresponding to the second period T 2 described above) is generated in an interleaved manner, that is, the first intermediate signal Sh1 is interleaved by a pulse having a first original period and a pulse having a second original period. Way generated.
- the first averaging period Th of the generated first intermediate signal Sh1 can be expressed by formula (4).
- T h represents the first average period of the first intermediate signal Sh1
- rh represents the first fractional part of the first frequency control word F h
- I h represents the first integer part of the first frequency control word F h.
- the example implementation of the first DCO sub-circuit 2011 has been described above.
- the second DCO sub-circuit 2021 may be implemented in the same or similar manner as the first DCO sub-circuit 2011, that is, the second DCO sub-circuit 2021 and the first DCO sub-circuit 2011 may have the same or similar structure. It should be noted that the second DCO sub-circuit 2021 may also be implemented in a different manner from the first DCO sub-circuit 2011.
- the second intermediate signal S l1 generated by the second DCO sub-circuit 2021 is generated in an interleaved manner through the first original period and the second original period, that is, the second intermediate signal S 11 is also generated by having The pulses of the first primitive period and the pulses of the second primitive period are generated in an interleaved manner.
- the first integer part of the first frequency control word F h is the same as the second integer part of the second frequency control word F l , it is used to synthesize the first intermediate signal Sh1 It is the same as the original period of the second intermediate signal S 11 , that is, both are the first original period and the second original period.
- the second average period T l of the second intermediate signal S l1 can be expressed by formula (5):
- T l represents the second average period of the second intermediate signal S l1
- r l represents the second fractional part of the second frequency control word F l
- I l represents the second integer part of the second frequency control word F 1
- I l I h
- ⁇ represents the reference time unit.
- the first intermediate signal S h1 cyclically cycles in the pattern of T A T B
- the second intermediate signal S l1 cycles in the pattern of T A T A T A T B.
- the pattern cycles through cycles.
- the first average period of the first intermediate signal S h1 may be (T A +T B )/2
- the second average period of the second intermediate signal S 11 may be (3T A +T B )/4.
- the first DCO sub-circuit 2011 and the second DCO sub-circuit 2021 may include a time average frequency direct period synthesizer based on the TAF-DPS circuit architecture.
- the time average frequency direct period synthesizer based on the TAF-DPS circuit architecture will be described later with reference to FIG. 10.
- TAF-DPS circuit architecture is only an implementation of the TAF technology, and the embodiments of the present disclosure are not limited thereto.
- other circuit structures based on TAF technology may be used to implement the first DCO sub-circuit 2011 and the second DCO sub-circuit 2021.
- the frequency difference between the average frequency of the first intermediate signal S h1 and the average frequency of the second intermediate signal S l1 can be obtained by formula (6 ) Means.
- the period difference between the first average period Th of the first intermediate signal S h1 and the second average period T l of the second intermediate signal S 11 can be expressed by equation (7).
- f R represents the frequency difference between the average frequency of the first intermediate signal S h1 and the average frequency of the second intermediate signal S l1
- t R ′ represents the frequency difference of the first intermediate signal S h1
- the frequency difference between the average frequency of the first intermediate signal S h1 and the average frequency of the second intermediate signal S l1 can be determined according to the first fractional part of the first frequency control word F h and the second The second fractional part of the frequency control word F l is determined.
- the difference between the first fractional part and the second fractional part is very small, the average frequency of the first intermediate signal S h1 and the average frequency of the second intermediate signal S l1 The frequency difference between is also very small.
- the second averaging period T l of the second intermediate signal S l1 is also based on the first original period.
- the original period and the second original period are obtained by averaging time, that is, the size of the first intermediate signal S h1 is not equal to T h in each period, and the size of the second intermediate signal S l1 is not equal to T in each period l .
- the relationship among the first original period T A , the second original period T B , and the first average period Th of the first intermediate signal may satisfy: T A ⁇ T h ⁇ T B.
- the above equation (7) only represents the period difference between the first average period of the first intermediate signal S h1 and the second average period of the second intermediate signal S 11.
- rh 0.125 (that is, the binary value is 0.001B)
- the value corresponding to the least significant bit of rh is 0.125.
- r h 0.75 (i.e., binary value 0.11B) a
- r h is the least significant bit corresponding to the value of 0.25 (i.e., binary value 0.01B). Equation (8) shows that after The first averaging period T h of the first intermediate signal Sh1 obtained by averaging over four periods.
- u 1 -log 2 r LSB1 , r LSB1 is the value corresponding to the least significant bit of the first fractional part rh of the first frequency control word F h.
- the first sub-converter circuit 2012 may be configured to convert a first intermediate signal having one period of S h1 (i.e., a first averaging period) of the first output signal S h.
- the first conversion sub-circuit 2012 may include a first filter, and the first filter may be configured to filter high frequency components in the first intermediate signal Sh1 to obtain the first output signal Sh .
- the first intermediate signal Sh1 output by the first DCO sub-circuit 2011 includes high-frequency components and low-frequency components. By filtering out high frequency components in a first intermediate signal S h1 it may include only one cycle to obtain a first output signal S h.
- the first intermediate signal Sh1 can be converted into a conventional clock signal having a cycle.
- the high frequency and low frequency components of the first intermediate signal S h1 may switch the period of the first intermediate signal S h1 of speed or frequency.
- the first intermediate signal S h1 DCO by the first sub-circuit output 2011 may include two cycles: a first cycle of the original and the second original period T A T B, thus the present disclosure in some embodiments " switching period "may refer to the first original period T a or T B second original period T B second period to the original switching of the first original period T a.
- Minimum frequency components e.g., S h1 for the first intermediate signal a frequency greater than the speed or frequency of the first intermediate signal S h1 is the period of the switching of the high frequency component of the first intermediate signal S h1 of the first intermediate frequency is less than or equal to minimum frequency component of the speed or frequency of the signal S h1 is the period of the switching frequency component of the first intermediate signal S h1.
- the minimum value of the periodic switching speed or frequency of the first intermediate signal Sh1 may be f h1 ⁇ r LSB (for example, when F h is 8.125, it is f h1 ⁇ 0.125), where r LSB1 is the first least significant bit of the control word corresponding to the value of the frequency F h r h of the fractional part of the first, f h1 is the average frequency of the first intermediate signal S h1.
- the bandwidth of the first filter may be configured to be less than or equal to f h1 ⁇ r LSB , so as to filter out high frequency components in the first intermediate signal Sh1.
- the first filter outputs the first output signal S h have only one cycle.
- the value 5, 2012 after treatment by the first conversion sub-circuit, a first intermediate signal S h1 is converted to have only one type of a first period signal S h output, wherein the first output signal S h cycle Is the value of the first average period Th of the first intermediate signal Sh1.
- the first output signal S h period T A + T B) / 2.
- the parameters of the first filter may be determined according to the average frequency of the first intermediate signal Sh1 and the least significant digit of the first fractional part.
- the parameters of the first filter may include the bandwidth of the first filter, and the bandwidth of the first filter may be determined according to equation (9).
- the bandwidth of the first filter r LSB1 a first fractional portion of the least significant bit r h is a value corresponding to a first frequency F h of the control word, Is the average frequency of the first intermediate signal Sh1 , and ⁇ is the reference time unit.
- the first conversion sub-circuit 2012 can filter out the high-frequency components in the first intermediate signal Sh1 to obtain a first output including only one period.
- Signal Sh .
- the first filter may be implemented as an analog filter or a digital filter.
- the first filter is a low-pass filter.
- the second switching sub-circuit 2022 may be configured to convert a first intermediate signal having one period of S h1 (i.e., a second average period) of the first output signal S h.
- the second conversion sub-circuit 2022 may include a second filter, and the second filter may be configured to filter out high frequency components in the second intermediate signal S 11 to obtain the second output signal S 1 .
- the second intermediate signal S 11 output by the second DCO sub-circuit 2021 includes high-frequency components and low-frequency components. By filtering out the high frequency components in the second intermediate signal S l1 , the second output signal S l including only one period can be obtained. That is, through the second conversion sub-circuit 2022, the second intermediate signal S 11 can be converted into a conventional clock signal having a cycle.
- the high frequency and low frequency components of the second intermediate signal S l1 can switch the period of the second intermediate signal S l1 of speed or frequency.
- Minimum frequency component velocity period e.g., the second intermediate signal S l1, greater than the second intermediate frequency signal S l1 or switching frequency to a high frequency component of the second intermediate signal S l1 of the second intermediate frequency is less than or equal to minimum frequency component of the speed signal S l1 or period of the switching frequency to a low frequency component of the second intermediate signal S l1.
- the minimum value of the periodic switching speed or frequency of the second intermediate signal S 11 may be f h2 ⁇ r LSB2 (for example, when F l is 8.125, it is f h2 ⁇ 0.125), where r LSB2 is the second The value corresponding to the least significant bit of the second fractional part r l of the frequency control word F l , and f h2 is the average frequency of the second intermediate signal S l1.
- the bandwidth of the second filter may be configured to be less than or equal to f h2 ⁇ r LSB2 , so as to filter out the high frequency components of the second intermediate signal S 11.
- the second filter output signal output from the second S l have only one cycle.
- the parameters of the second filter may be determined according to the average frequency of the second intermediate signal S 11 and the least significant bit of the second fractional part r l of the second frequency control word F l.
- the parameters of the second filter may include the bandwidth of the second filter, and the bandwidth of the second filter may be determined according to equation (10).
- Bwlp2 represents the bandwidth of the second filter
- r LSB2 represents the value corresponding to the least significant bit of the second fractional part r l of the second frequency control word F l
- ⁇ represents the reference time unit. That is to say, as long as the bandwidth of the second filter satisfies equation (10), the second conversion sub-circuit 2022 can filter out the high-frequency components in the second intermediate signal S l1 , and can obtain a second output including only one period.
- Signal S l represents the bandwidth of the second filter
- r LSB2 represents the value corresponding to the least significant bit of the second fractional part r l of the second frequency control word F l
- ⁇ represents the reference time unit. That is to say, as long as the bandwidth of the second filter satisfies equation (10), the second conversion sub-circuit 2022 can filter out the high-frequency components in the second intermediate signal S
- the second filter may also be implemented as an analog filter or a digital filter.
- the second filter may be a low-pass filter.
- the first conversion sub-circuit 2012 may include a first phase locked loop. In this case, the loop bandwidth of the first phase-locked loop included in the first conversion sub-circuit 2012 can be determined according to equation (9).
- the second conversion sub-circuit 2022 may include a second phase locked loop. In this case, the loop bandwidth of the second phase-locked loop included in the first conversion sub-circuit 2012 can be determined according to equation (10).
- An example structure of a phase locked loop according to an embodiment of the present disclosure will be described later with reference to FIG. 11.
- the first intermediate signal S h1 and the second intermediate signal S l1 with very small frequency difference can be converted into the first output signal Sh and the first output signal Sh with very small period difference.
- formula (11) may represent a period between the first period and the output signal S h output period of the second difference signal S l.
- t R represents the period difference between the period of the first output signal Sh and the period of the second output signal S l
- rh represents the first fractional part of the first frequency control word F h
- r l Represents the second fractional part of the second frequency control word F l
- I h represents the first integer part of the first frequency control word F h
- I l represents the second integer part of the second frequency control word F l
- I l I h
- ⁇ represents the reference time unit.
- the period difference t R between the period of the first output signal Sh and the period of the second output signal S l is equal to the first average period T h of the first intermediate signal Sh1 It is equal to the period difference t R ′ between the second average period T l of the second intermediate signal S 11.
- FIG. 6 shows a schematic diagram of the first output signal Sh and the second output signal S 1 according to an embodiment of the present disclosure.
- the edges of the phase aligned output signal S h of the first phase and the second output signal S l (i.e., phase aligned) to the time when after a period, the first output a first signal S h
- the time difference between the rising edge of two cycles and the rising edge of the first cycle of the second output signal S 1 is t R.
- the time difference between the rising edge of the second cycle of the first output signal S h and the rising edge of the second cycle of the second output signal S 1 is 2t R.
- the time difference between the rising edge of the fifth cycle of the fifth cycle of the first rising edge of the output signal S h and the second output signal S l is 5t R.
- the time difference between the rising edges of the mth cycle of the output signal S 1 is m ⁇ t R , where m is an integer greater than or equal to 1.
- the period difference between the period of the first output signal Sh and the period of the second output signal S l t R can be 1 femtosecond (fs), so the signal generating circuit provided according to the embodiment of the present disclosure can obtain a signal with a time resolution of the order of femtosecond.
- the temporal resolution may refer to the length of the time period between the time length of the time period of the first output signal S h of the second differential output signal S l.
- a signal with a time resolution of the order of picoseconds (ps) can be obtained.
- FIG. 7 shows a schematic diagram of a reference time unit ⁇ according to an embodiment of the present disclosure.
- Fig. 8 shows a schematic diagram of a reference time unit generating circuit according to some embodiments of the present disclosure.
- the reference time unit generating circuit may include a twisted ring counter.
- the twist ring counter may include multiple D flip-flops.
- the twisted ring counter may include K/2 flip-flops connected in series.
- the flip-flop may be a D flip-flop.
- the number of bits of the twisted ring counter is K/2.
- the output terminals of each flip-flop of the twisted ring counter are combined into K output terminals for outputting K reference signals with evenly spaced phases.
- FIG. 9 shows a schematic diagram of another reference time unit generating circuit according to some embodiments of the present disclosure.
- the reference time unit generating circuit may include a first voltage-controlled oscillator (VCO) 901, a phase-locked loop circuit 902, and K output terminals 903.
- the first voltage controlled oscillator 901 is configured to oscillate at a predetermined oscillation frequency.
- the phase locked loop circuit 902 is configured to lock the output frequency of the first voltage controlled oscillator 901 to a reference output frequency.
- the phase-locked loop circuit 902 may include a first phase detector (PFD), a first loop filter (LPF), and a first frequency divider (FN).
- PFD phase detector
- LPF first loop filter
- FN first frequency divider
- the first phase detector may be a frequency phase detector.
- the first loop filter may be a low-pass filter.
- the frequency division coefficient of the first frequency divider is N 0 , N 0 is a real number, and N 0 is greater than or equal to 1.
- a reference signal with a reference frequency can be input to the first phase detector, then the first loop filter, then the first voltage-controlled oscillator, and finally the first voltage-controlled oscillator.
- the signal with the predetermined oscillation frequency f vco1 generated by the oscillator can be divided by the frequency divider to obtain the frequency division frequency f vco1 /N 0 of the frequency division signal, and the frequency division frequency f vco1 /N 0 is fed back to the first phase detector ,
- the first phase detector is used to compare the reference frequency of the reference signal with the frequency division frequency f vco1 /N 0 , when the frequency and phase of the reference frequency and frequency division frequency f vco1 /N 0 are equal, the error between the two is zero At this time, the phase-locked loop circuit 902 is in a locked state.
- the reference time unit generation circuit can be implemented by a delay-locked loop (DLL), or the reference time unit generation circuit can be implemented by an LC voltage-controlled oscillator and a differentiator.
- DLL delay-locked loop
- the reference time unit generation circuit can be implemented by an LC voltage-controlled oscillator and a differentiator.
- FIG. 10 shows a circuit diagram of a time average frequency direct period synthesizer based on the TAF-DPS circuit architecture according to some embodiments of the present disclosure.
- the TAF-DPS circuit architecture in FIG. 10 can be used to generate a synthesized clock signal having an average period of T TAF as shown in equation (3).
- the time average frequency direct period synthesizer 100 may include a first input module, a second input module 1030, and an output module 1040.
- the first input module includes a first logic control circuit 1010 and a second logic control circuit 1020.
- the first logic control circuit 1010 includes a first adder 1011, a first register 1012, and a second register 1013.
- the second logic control circuit 1020 may include a second adder 1021, a third register 1022, and a fourth register 1023.
- the second input module 1030 includes a first K ⁇ 1 multiplexer 1031, a second K ⁇ 1 multiplexer 1032, and a 2 ⁇ 1 multiplexer 1033.
- the first K ⁇ 1 multiplexer 1031 and the second K ⁇ 1 multiplexer 1032 respectively include multiple input terminals for receiving K (K is an integer greater than 1) reference signals with evenly spaced phases, Control input and output.
- the 2 ⁇ 1 multiplexer 1033 includes a control input terminal, an output terminal, a first input terminal for receiving the output of the first K ⁇ 1 multiplexer 1031, and a first input terminal for receiving the second K ⁇ 1 multiplexer.
- the second input terminal of the output of the user 1032 For example, the time span (for example, the phase difference) between any two adjacent reference signals of the K reference signals with evenly spaced phases may correspond to the reference time unit ⁇ .
- the output module 1040 includes a trigger circuit.
- the trigger circuit is used to generate pulse trains.
- the trigger circuit includes a D flip-flop 1041, a first inverter 1042, and a second inverter 1043.
- the D flip-flop 1041 includes a data input terminal, a clock input terminal for receiving the output from the output terminal of the 2 ⁇ 1 multiplexer 1033, and an output terminal for outputting the first clock signal CLK1.
- the first inverter 1042 includes an input terminal for receiving the first clock signal CLK1 and an output terminal for outputting a signal to the data input terminal of the D flip-flop 1041.
- the second inverter 1043 includes an input terminal for receiving the first clock signal CLK1 and an output terminal for outputting the second clock signal CLK2.
- the output terminal of the trigger circuit or the output terminal of the second inverter 1043 can be used as the output terminal of the TAF-DPS frequency synthesizer.
- the first clock signal CLK1 is output to the control input terminal of the 2 ⁇ 1 multiplexer 1033, and the output terminal of the first inverter 1042 is connected to the data input terminal of the D flip-flop 1041.
- the first adder 1011 may add the frequency control word F and the most significant bits (for example, 5 bits) stored in the first register 1012, and then add them at the rising edge of the second clock signal CLK2 The result is saved in the first register 1012; or, the first adder 1011 can add the frequency control word F and all the information stored in the first register 1012, and then save the addition result at the rising edge of the second clock signal CLK2 To the first register 1012. At the rising edge of the next second clock signal CLK2, the most significant bit stored in the first register 1012 will be stored in the second register 1013 and used as the selection signal of the first K ⁇ 1 multiplexer 1031 One signal is selected from K multi-phase input signals as the output signal of the first K ⁇ 1 multiplexer 1031.
- the second adder 1021 may add the frequency control word F/2 and the most significant bit stored in the third register 1022, and then save the addition result in the third register 1022 at the rising edge of the second clock signal CLK2 .
- the information stored in the third register 1022 will be stored in the fourth register 1023 and used as the selection signal of the second K ⁇ 1 multiplexer 1023 for slave K
- One of the two multi-phase input signals is selected as the output signal of the second K ⁇ 1 multiplexer 1023.
- the 2 ⁇ 1 multiplexer 1033 can select the output signal from the first K ⁇ 1 multiplexer 1031 and the second K ⁇ 1 multiplexer at the rising edge of the first clock signal CLK1
- One of the output signals of the converter 1032 is used as the output signal of the 2 ⁇ 1 multiplexer 1033 to be the input clock signal of the D flip-flop 1041.
- one of the output terminal of the D flip-flop 1041 and the output terminal of the second inverter 1043 can be used as the output of the time average frequency direct cycle synthesizer 100.
- the output of the time average frequency direct cycle synthesizer of the first generating circuit is the first intermediate signal
- the output of the time average frequency direct cycle synthesizer of the second generating circuit is the second intermediate signal.
- the selection signal output by the second register 1013 can be used to select the falling edge of the synthesized clock signal generated by the time average frequency direct cycle synthesizer 100
- the selection signal output by the fourth register 1023 can be used to select the time average frequency direct cycle synthesis
- the signal fed back by the first register 1012 to the first adder 1011 can be used to control the period switching of the synthesized clock generated by the time average frequency direct cycle synthesizer 100.
- the selection signal output by the second register 1013 may be called a falling edge control word
- the selection signal output by the fourth register 1023 may be called a rising edge control word
- the first register 1012 is fed back to the first adder 1011.
- the signal is called the fractional frequency control word.
- FIG. 11 shows a circuit diagram of a phase locked loop according to some embodiments of the present disclosure.
- the phase locked loop 110 may include a second phase detector 1101, a second loop filter 1102, a second voltage controlled oscillator 1103, and a second frequency divider 1104.
- the second voltage controlled oscillator may be configured to generate an oscillation signal having a predetermined oscillation frequency f vco2 according to a control variable.
- the second voltage controlled oscillator may be a digital voltage controlled oscillator.
- the second frequency divider may be configured to divide the frequency of the oscillation signal to obtain a frequency-divided signal having the allocated frequency f vco 2 /N 1.
- the frequency division coefficient of the second frequency divider is N 1 , N 1 is a real number, and N 1 is greater than or equal to 1.
- the second phase detector may be configured to receive the input signal and compare the difference between the frequency f in of the input signal and the frequency division frequency f vco 2 /N 1 of the frequency division signal to output the difference variable.
- the second phase detector may be a frequency phase detector.
- the second loop filter may be configured to filter high frequency components in the difference variable to generate a control variable for controlling the second voltage controlled oscillator.
- the second voltage-controlled oscillator may also be configured to generate and output a target signal with a target frequency f o when the frequency f in of the input signal is equal to the frequency f vco 2 /N 1 of the frequency-divided signal.
- the phase-locked loop is in a locked state.
- the first conversion sub-circuit 2012 may include a first phase-locked loop.
- the first phase-locked loop may be implemented as the phase-locked loop 110 shown in FIG. 11.
- the input signal is the first intermediate signal Sh1 and the target signal is the first output signal Sh .
- the bandwidth of the second loop filter 1102 of the phase-locked loop 110 can be determined according to equation (9).
- the second conversion sub-circuit 2022 may include a second phase locked loop.
- the second phase locked loop may be implemented as the phase locked loop 110 shown in FIG. 11.
- the bandwidth of the second loop filter 1102 of the phase-locked loop 110 can be determined according to equation (10).
- FIG 12 shows a block diagram of some embodiments according to the present embodiment of the disclosure
- the second frequency F l is the control word signal generating circuit in the case of an integer.
- the first frequency control word F h may include a first integer part and a first fractional part
- the second frequency control word F l includes a second integer part and a second fractional part
- the second fractional part is 0. That is, the second frequency control word F l is an integer
- the second frequency control word F l ie, the second integer part
- the first fractional part is not 0
- the first fractional part and the second fractional part are not equal. Is not equal to the first output signal S h period and the second period of the output signal S l.
- the signal generating circuit 120 may include a first generating circuit 1210 and a second generating circuit 1220.
- the first generation circuit 1210 may include a first Digitally Controlled Oscillator (DCO) sub-circuit 1211 and a first conversion sub-circuit 1212.
- the second generating circuit 1220 may include a second DCO sub-circuit 1221, and the output of the second DCO sub-circuit 1221 is used as the second output signal S 1 .
- DCO Digitally Controlled Oscillator
- the period between the first output signal S h period and the period of the second output signal S l with the reference time difference ⁇ units and a first control word frequency F h is related to the first fractional part.
- the first DCO sub-circuit 1211 may be configured to generate the first intermediate signal Sh1 based on the first frequency control word F h and the reference time unit ⁇ , and the first conversion sub-circuit 1212 may be configured to convert the first intermediate signal Sh1 Converted to the first output signal Sh .
- the second DCO sub-circuit 1221 may be configured to generate the periodic second output signal S l based on the second frequency control word F l and the reference time unit ⁇ . Since the second frequency control word F l is an integer, the second output signal S l generated by the second DCO sub-circuit 1221 includes only one period. For example, the second output signal S l generated by the second DCO sub-circuit 1221 includes only A pulse with a first primitive period TA.
- the first DCO sub-circuit 1211 may be implemented based on TAF technology.
- the first sub-circuit DCO 1211 generates a first intermediate signal S h1 is the first original period and the second period of the original generated in a staggered manner, i.e., a first intermediate signal S h1 by having The pulses of the first primitive period and the pulses of the second primitive period are generated in an interleaved manner.
- the first averaging period Th of the generated first intermediate signal Sh1 can be expressed by formula (4).
- the second DCO sub-circuit 1221 may be implemented based on TAF technology.
- the second control word frequency F l is an integer (i.e., a second frequency control word F l second fractional part is zero)
- the second average period of the second output signal S l T l for the first A primitive period T A is, the second sub-circuit 1221 generates a DCO second output signal S l having one cycle, i.e., the first original period T A.
- the frequency difference between the average frequency of the first intermediate signal S h1 and the average frequency of the second output signal S l can be obtained by (13) Representation. Further, the difference between the average period of the first period the average period of a first intermediate signal S h1 T h and second output signals S l may be obtained by formula (14), respectively.
- f R represents the frequency difference between the average frequency of the first intermediate signal S h1 and the average frequency of the second output signal S l
- t R ′ represents the frequency difference of the first intermediate signal S h1 the average period between the first period and the average period T h a second difference between the output signal S l
- r h represents a first frequency a first control word fractional part F h
- I h denotes a first frequency F h of the control word
- the frequency difference between the average frequency of the first intermediate signal S h1 and the average frequency of the second output signal S l can be determined according to the first fractional part of the first frequency control word F h .
- the frequency difference between the average frequency of the first intermediate signal S h1 and the average frequency of the second output signal S 1 is also very small.
- the first intermediate signal Sh1 and the first intermediate signal Sh1 and the first intermediate signal S h1 and the first intermediate signal S h1 with very small frequency difference can be obtained through the first DCO sub-circuit 1211 and the second DCO sub-circuit 1221 Two output signal S l .
- equation (14) only expresses the difference between the first average period of the first intermediate signal S h1 and the average period of the second output signal S l Period difference.
- the first sub-converter circuit 1212 may be configured to convert a first intermediate signal having one period of S h1 (i.e., a first averaging period) of the first output signal S h.
- the first conversion sub-circuit 1212 may include a first filter, and the first filter may be configured to filter out high frequency components in the first intermediate signal Sh1 to obtain the first output signal Sh .
- the first intermediate signal S h1 DCO first sub-circuit 1211 outputs a high-frequency and low frequency components comprises. By filtering out high frequency components in a first intermediate signal S h1 it may include only one cycle to obtain a first output signal S h.
- the high frequency and low frequency components of the first intermediate signal S h1 may switch the period of the first intermediate signal S h1 of speed or frequency.
- the first intermediate signal S h1 of the first sub-circuit DCO output 1212 may include two cycles: a first cycle of the original and the second original period T A T B, thus the present disclosure in some embodiments " switching period "may refer to the first original period T a or T B second original period T B second period to the original switching of the first original period T a.
- Minimum frequency component of the speed or frequency of the cycle for example, the first intermediate signal S h1, the intermediate frequency is greater than a first switching signal S h1 high-frequency component is a first intermediate signal S h1, the first frequency is less than or equal to the minimum speed of the intermediate frequency component of the signal S h1 period of the switching frequency or a low frequency component of the first intermediate signal S h1.
- the minimum value of the periodic switching speed or frequency of the first intermediate signal Sh1 may be f h1 ⁇ r LSB (for example, when F h is 8.125, it is f h1 ⁇ 0.125), where r LSB1 is the first least significant bit of the control word corresponding to the value of the frequency F h r h of the fractional part of the first, f h1 is the average frequency of the first intermediate signal S h1.
- the bandwidth of the first filter may be configured to be less than or equal to f h1 ⁇ r LSB , so as to filter out the high frequency components of the first intermediate signal Sh1.
- the first filter outputs the first output signal S h have only one cycle.
- the parameters of the first filter may be determined according to the average frequency of the first intermediate signal Sh1 and the least significant digit of the first fractional part.
- the parameters of the first filter may include the bandwidth of the first filter, and the bandwidth of the first filter may be determined according to equation (9).
- the first filter may be implemented as an analog filter or a digital filter.
- the first filter may be a low-pass filter.
- the first conversion sub-circuit 1212 may include a first phase-locked loop.
- the loop bandwidth of the first phase-locked loop included in the first conversion sub-circuit 1212 can be determined according to equation (9).
- the first phase-locked loop may be implemented as the phase-locked loop 110 described in FIG. 11.
- a first intermediate frequency little difference signal S h1 and second output signals may be converted to S l period little difference output signal S h of the first and second output signals S l.
- formula (15) may represent a period between the first period and the output signal S h output period of the second difference signal S l.
- t R represents the period difference between the period of the first output signal Sh and the period of the second output signal S l
- rh represents the first fractional part of the first frequency control word F h
- I h Represents the integer part of the first frequency control word F h
- I l represents the second integer part of the second frequency control word F l
- I l I h
- ⁇ represents the reference time unit
- the second frequency control word F l The second decimal part is zero.
- the period difference t R between the period of the first output signal Sh and the period of the second output signal S l is equal to the first average period T h of the first intermediate signal Sh1 It is equal to the period difference t R ′ between the average period of the second output signal S 1.
- the time difference between the rising edges of the m-th period of S l is m ⁇ t R , where m is an integer greater than or equal to 1.
- the period between the first output signal S h period and the period of the second output signal S l t R may be a difference between 1fs Therefore, the signal generating circuit provided according to the embodiment of the present disclosure can obtain a signal with a time resolution of femtosecond level.
- the temporal resolution may refer to the length of the time period between the time length of the time period of the first output signal S h of the second differential output signal S l.
- a signal with a time resolution of the order of picoseconds (ps) can be obtained.
- FIG. 13A shows a block diagram of a digital time conversion circuit according to at least one embodiment of the present disclosure.
- the digital time conversion circuit 130 may include a signal generation circuit 131 and a time generation circuit 132.
- the signal generating circuit 131 may include a first generating circuit 1311 and a second generating circuit 1312.
- a first generation circuit 1311 may be configured to control word F h ⁇ and generating a periodic reference time unit of the first output signal S h based on the first frequency.
- the second generating circuit 1312 may be configured to generate the periodic second output signal S l based on the second frequency control word F l and the reference time unit ⁇ .
- the signal generating circuit 131 may be implemented according to the signal generating circuit described in any of the above embodiments.
- the time generating circuit 132 may be configured to receive a digital signal, a first output signal Sh, and a second output signal S l , and generate a signal corresponding to the digital signal based on the digital signal, the first output signal Sh, and the second output signal S l The first time pulse signal or the second time pulse signal.
- time generating circuit 132 may be configured to generate a first time difference between the pulse signal or the second pulse signal based on a period of time between the digital signal, and the output signal S h of the first period and the second period of the output signal S l.
- the digital signal may have n bits expressed as ⁇ n-1:0>, where n may represent the bit width of the digital signal, and n is an integer greater than or equal to 1.
- time generating circuit 132 may be configured to generate a first time period based on the pulse signal is a difference between the bit width of the digital signal and the periodic output signal S h of the first period and the second output signal S l to the digital signal corresponding to Or the second time pulse signal.
- the first time pulse signal may be a single signal.
- the first minimum time between rising and falling edges of the pulse signal a first time interval and the period related to the difference between the first output signal S h period and the second period of the output signal S l.
- the first minimum time interval represents the minimum time interval between the rising edge and the falling edge of the first time pulse signal
- the first minimum time interval may refer to the difference between the rising edge and the falling edge of the first time pulse signal in one cycle. That is, the first minimum time interval may refer to the pulse width of a single pulse in the first time pulse signal.
- the second time pulse signal may include a first sub-pulse signal and a second sub-pulse signal.
- the second minimum time interval between the rising edge of the first sub-pulse signal and the rising edge of the second sub-pulse signal is related to the reference time unit, the period of the first output signal Sh , and the second output signal S The period difference between the periods of l is related.
- the second minimum time interval represents the minimum time interval between the rising edge of the first sub-pulse signal and the rising edge of the second sub-pulse signal.
- the second minimum time interval may refer to the first sub-pulse signal.
- the time interval between two rising edges and the corresponding first rising edge of the second sub-pulse signal may only include a single rising edge
- the second sub-pulse signal may only include a single rising edge
- the second minimum time interval may refer to the rising edge of the first sub-pulse signal and the rising edge of the second sub-pulse signal.
- the first minimum time interval and the second minimum time interval may be equal.
- the first minimum time interval or the second minimum time interval can be represented by equation (16).
- DeltaT represents the minimum time interval of the first or second minimum time separation
- n represents the digital signal corresponding to a value (e.g., bit width of the digital signal)
- t R denotes a first period of an output signal S h
- t R may represent the minimum time resolution of the digital time converter, that is, the time corresponding to the Least Significant bit (LSB) of the digital signal.
- LSB Least Significant bit
- the difference between the first period signal S h output period of the second period and the output signal S l may be represented by the formula (11) or (15). Further, in some embodiments, as previously described, from the first output signal S h S l and the time phase alignment of the second output signal through the m cycles, the first output signal S h of the m-th cycle The time difference between the rising edge of and the rising edge of the mth cycle of the second output signal S 1 is m ⁇ t R , where m is an integer greater than or equal to 1.
- the time generating circuit 132 may include a first counter, a second counter, and a decoder.
- a first counter may be configured to output a first timing signal from the phase of the second output signal S h S l S h aligned period begins a first count output signal.
- the second counter may be configured to start a second cycle of the output signal S l from the first counting and the second output signal S h output timing signal S l phase-aligned.
- a decoder may be configured to The first time pulse signal is set to 1 at the time corresponding to the rising edge of the cycle, and when the number of cycles of the second output signal S 1 is equal to the value corresponding to the digital signal (for example, the bit width n of the digital signal), the rising edge of the n-th period of the second output signal S l is the time corresponding to a first time pulse signal is set to zero.
- a first time pulse signal with a pulse width of DeltaT can be generated.
- the decoder may be configured to: when the number of the first output signal S h is equal to the period of the digital signal corresponding to a value (e.g., n-bit wide digital signal), the first in the first output signal S h At the time corresponding to the rising edge of n cycles, the first sub-pulse signal of the second time pulse signal is set to 1, and the number of cycles of the second output signal S l is equal to the value corresponding to the digital signal (for example, the bit width of the digital signal) case n) at time n periods rising edge of the second output signal S l of the second sub-pulse corresponding to a second time pulse signal in the signal set.
- the second time pulse signal including the first sub-pulse signal and the second sub-pulse signal can be generated, and the second minimum time interval corresponding to the first sub-pulse signal and the second sub-pulse signal is DeltaT.
- the pulse width can be generated to be on the order of femtoseconds.
- the time for determining the phase of the second output signal and the first output signal S l S h aligned, digital to time converter circuit 130 may further include a phase detector circuit.
- Phase detector circuit may be configured to determine the phase relationship of the first output signal S h S l and second output signals to generate a first indication signal indicative of the phase of the output signal S h of the second output signal S l aligned.
- the time generating circuit 132 may be configured to generate the first time pulse signal or the second time pulse signal based on the digital signal, the first output signal Sh , the second output signal S 1, and the indication signal.
- Figure 14A shows a block diagram of a digital time conversion circuit according to some embodiments of the present disclosure.
- the digital time conversion circuit 140 may include a signal generation circuit 141, a time generation circuit 142, and a phase detector circuit 143.
- the signal generating circuit 141 may include a first generating circuit 1411 and a second generating circuit 1412.
- a first generation circuit 1411 may be configured to control word F h ⁇ and generating a periodic reference time unit of the first output signal S h based on the first frequency.
- the second generating circuit 1412 may be configured to generate the periodic second output signal S l based on the second frequency control word F l and the reference time unit ⁇ .
- the time generating circuit 142 may be configured to receive the digital signal, the first output signal Sh, and the second output signal S l , and generate a signal corresponding to the digital signal based on the digital signal, the first output signal Sh, and the second output signal S l.
- the first time pulse signal or the second time pulse signal may be configured to receive the digital signal, the first output signal Sh, and the second output signal S l , and generate a signal corresponding to the digital signal based on the digital signal, the first output signal Sh, and the second output signal S l.
- the signal generating circuit 141 may be implemented by adopting the signal generating circuit in some embodiments described according to FIG. 2.
- the signal generating circuit 141 may include a first generating circuit 1411 and a second generating circuit 1412.
- the first generation circuit 1411 may include a first DCO sub-circuit 1413 and a first conversion sub-circuit 1414.
- the second generation circuit 1412 may include a second DCO sub-circuit 1415 and a second conversion sub-circuit 1416.
- the first DCO sub-circuit 1413 may be configured to: generate a first intermediate signal S h1 based on the first frequency control word F h and a reference time unit ⁇ ; when generating the first intermediate signal S h1 , it outputs the same as the first intermediate signal S h1 corresponding to the rising edge of the first rising edge of the control word, with the falling edge of the first intermediate signal S h1 corresponding to the first falling edge of the control word, and a period with the first intermediate signal S h1 corresponding first switching Decimal frequency control word.
- the first conversion sub-circuit 1414 may be configured to convert the first intermediate signal Sh1 into the first output signal Sh .
- the first falling edge control word corresponds to the selection signal output by the second register 1013 in the first DCO sub-circuit
- the first The rising edge control word corresponds to the selection signal output by the fourth register 1023 in the first DCO sub-circuit
- the first fractional frequency control word corresponds to the first register 1012 in the first DCO sub-circuit which is fed back to the first adder 1011 signal.
- the second DCO sub-circuit 1415 may be configured to: generate a second intermediate signal S l1 based on the second frequency control word F l and the reference time unit ⁇ ; when generating the second intermediate signal S l1 , output the second intermediate signal S l1 l1 rising edge corresponding to the rising edge of a second control word, the falling edge of the second intermediate signal S l1 corresponding to the falling edge of the second control word, and a second intermediate signal S l1 corresponding to the second period of the switching Decimal frequency control word.
- the second conversion sub-circuit may be configured to convert the second intermediate signal S 11 into a second output signal.
- the second DCO sub-circuit includes the time average frequency direct period synthesizer described in FIG.
- the second falling edge control word corresponds to the selection signal output by the second register 1013 in the second DCO sub-circuit
- the second The rising edge control word corresponds to the selection signal output by the fourth register 1023 in the second DCO sub-circuit
- the second fractional frequency control word corresponds to the first register 1012 in the second DCO sub-circuit which is fed back to the first adder 1011. signal.
- the first frequency control word F h may include a first integer part and a first fractional part
- the second frequency control word F l may include a second integer part and a second fractional part
- the first integer part and The second integer part is the same, and the first fractional part and the second fractional part are not equal.
- both the first fractional part and the second fractional part may not be equal to zero.
- the phase detector circuit 143 can be configured to: based on the first rising edge control word, the second rising edge control word, the first falling edge control word, the second falling edge control word, the first fractional frequency control word, and the second fractional frequency control word generating a first output signal indicative of the phase of S h phase of the second output signal S l alignment indication signals. Since the metastable state occurs when the phase difference between the phase of the first output signal Sh and the phase of the second output signal S l is extremely small, the first output signal Sh and the second output signal S are directly compared. The phase relationship of l is difficult.
- the first rising edge control word, the first falling edge control word, and the first fractional frequency control word output by the first DCO sub-circuit and the second rising edge control word, the second falling edge control word and the second DCO sub-circuit output a second fractional frequency control word can be a first signal S h output and the phase relationship of the second output signal S l, whereby a phase difference between the phase of the first output signal S h and the phase of the second output signal S l is The phase comparison can still be performed in very small cases.
- An example of the phase detector circuit 143 will be described below with reference to FIG. 14B.
- Figure 14B shows a schematic diagram of a phase detector circuit 143 according to some embodiments of the present disclosure.
- the phase detector circuit 143 may include a first data comparator sub-circuit 1431, a second data comparator sub-circuit 1432, a third data comparator sub-circuit 1433, a fourth comparator sub-circuit 1434, and an indication signal generator. Circuit 1435.
- the first data comparator sub-circuit 1431 may be configured to compare the first rising edge control word with the second rising edge control word and output the first comparison result.
- the second data comparator sub-circuit 1432 may be configured to compare the first falling edge control word with the second falling edge control word and output the second comparison result.
- the third data comparator sub-circuit 1433 may be configured to compare the first fractional frequency control word with zero and output a third comparison result.
- the fourth data comparator sub-circuit 1434 may be configured to compare the second fractional frequency control word with zero and output a fourth comparison result.
- the indication signal generation sub-circuit 1435 may be configured to: the first comparison result indicates that the first rising edge control word is equal to the second rising edge control word, and the second comparison result indicates the first falling edge control word and the second falling edge control word is equal to the third comparison result indicates that the first fractional frequency control word is equal to zero, and the fourth case where the comparison result indicates that the second fractional frequency control word equal to zero, indicating that the first phase of the output signal S h output and the second output signal S l Phase alignment indication signal; and in other cases (for example, the first comparison result indicates that the first rising edge control word is not equal to the second rising edge control word or the second comparison result indicates that the first falling edge control word and the second If the falling edge control word is not equal or the third comparison result indicates that the first decimal frequency control word is not equal to zero or the fourth comparison result indicates that the second decimal frequency control word is not equal to zero),
- the first data comparator sub-circuit 1431, the second data comparator sub-circuit 1432, the third data comparator sub-circuit 1433, the fourth comparator sub-circuit 1434, and the indication signal generation sub-circuit 1435 can be implemented by a combinational logic circuit. Implement.
- the phase detector circuit 143 may also include a series connection The fifth register 1436 and the sixth register 1437, and the seventh register 1438 and the eighth register 1439 connected in series. 10 the falling edge control word output by the second register 1013 passes through the first register 1012 and the second register 1013, and the rising edge control word output by the fourth register 1023 passes through the third register 1022 and the fourth register 1023.
- a fifth register 1436 and a sixth register 1437 connected in series can be set.
- a seventh register 1438 and an eighth register 1439 connected in series can be set.
- the fifth register 1436 may be configured to receive the first fractional frequency control word sent by the first DCO sub-circuit, and the third data comparator sub-circuit 1433 may be configured to output the first fractional number output by the sixth register 1437. The frequency control word is compared with zero and the third comparison result is output.
- the seventh register 1438 may be configured to receive the second fractional frequency control word sent by the second DCO sub-circuit, and the fourth data comparator sub-circuit 1434 may be configured to combine the second fractional frequency control word output by the eighth register 1439 with zero. The comparison is performed and the fourth comparison result is output.
- the fifth register 1436 and the seventh register 1438 may have the same configuration as the first register 1012 in FIG. 10, and the sixth register 1437 and the eighth register 1439 may have the same configuration as the second register 1013 in FIG. 10.
- FIG. 14C shows an example in which the fifth register 1436 and the sixth register 1437 are configured to buffer the first fractional frequency control word sent by the first DCO sub-circuit.
- the embodiment of the present disclosure is not limited thereto.
- the fifth register 1436 and the sixth register 1437 may be provided between the third data comparator sub-circuit 1433 and the indication signal generation sub-circuit 1435, and be configured to buffer the comparison result of the third data comparator sub-circuit 1433 to The first comparison result, the second comparison result, and the third comparison result are synchronized.
- the seventh register 1438 and the eighth register 1439 may be provided between the fourth data comparator sub-circuit 1434 and the indication signal generation sub-circuit 1435, and be configured to buffer the comparison result of the fourth data comparator sub-circuit 1434, So that the first comparison result, the second comparison result, and the fourth comparison result are synchronized.
- Figure 15A shows a block diagram of a digital time conversion circuit according to some embodiments of the present disclosure.
- the digital time conversion circuit 150 may include a signal generation circuit 151, a time generation circuit 152, and a phase detector circuit 153.
- the signal generating circuit 151 may include a first generating circuit 1511 and a second generating circuit 1512.
- a first generation circuit 1511 may be configured to control word F h ⁇ and generating a periodic reference time unit of the first output signal S h based on the first frequency.
- the second generating circuit 1512 may be configured to generate the periodic second output signal S l based on the second frequency control word F l and the reference time unit ⁇ .
- the time generating circuit 152 may be configured to receive a digital signal, a first output signal Sh, and a second output signal S l , and generate a signal corresponding to the digital signal based on the digital signal, the first output signal Sh, and the second output signal S l The first time pulse signal or the second time pulse signal.
- the signal generating circuit 151 may be implemented by adopting the signal generating circuit in some embodiments described according to FIG. 12.
- the signal generating circuit 131 may include a first generating circuit 1511 and a second generating circuit 1512.
- the first generation circuit 1511 may include a first DCO sub-circuit 1513 and a first conversion sub-circuit 1514.
- the second generation circuit 1512 may include a second DCO sub-circuit 1515.
- the first frequency control word F h may include a first integer part and a first fractional part
- the second frequency control word F l includes a second integer part and a second fractional part
- the second fractional part is 0, that is, the second frequency control word F l can be an integer
- the second frequency control word F l (that is, the second integer part) is equal to the first integer part of the first frequency control word F h
- the first fractional part is not Is 0, that is, the first fractional part and the second fractional part are not equal.
- the first sub-circuit DCO 1513 may be configured to: ⁇ S h1 of generating a first intermediate signal based on a first control word frequency F h and a reference time unit; outputting a first intermediate signal S when generating a first intermediate signal h1 of S h1 corresponding to the rising edge of the first rising edge of the control word, with the falling edge of the first intermediate signal S h1 corresponding to the first falling edge of the control word, and a period with the first intermediate signal S h1 corresponding first switching Decimal frequency control word.
- the first conversion sub-circuit 1514 may be configured to convert the first intermediate signal Sh1 into the first output signal Sh .
- the first falling edge control word corresponds to the selection signal output by the second register 1013 of the first DCO sub-circuit
- the first rising The edge control word corresponds to the selection signal output by the fourth register 1023 of the first DCO sub-circuit
- the first fractional frequency control word corresponds to the signal fed back to the first adder 1011 from the first register 1012 of the first DCO sub-circuit.
- the second DCO sub-circuit 1515 may be configured to generate the periodic second output signal S l based on the second frequency control word F l and the reference time unit ⁇ .
- the second DCO sub-circuit includes the time average frequency direct period synthesizer 100 described in FIG. 10
- the second falling edge control word corresponds to the selection signal output by the second register 1013 of the second DCO sub-circuit
- the second The rising edge control word corresponds to the selection signal output by the fourth register 1023 of the second DCO sub-circuit.
- the phase detector circuit 153 may be configured to generate an instruction based on the first rising edge control word, the second rising edge control word, the first falling edge control word, the second falling edge control word, and the first fractional frequency control word.
- the phase relationship between the first output signal Sh and the second output signal S l can be obtained, so that the phase difference between the phase of the first output signal Sh and the phase of the second output signal S l is still very small. Perform phase comparison.
- An example of the phase detector circuit 153 will be described below with reference to FIG. 15B.
- FIG. 15B shows a schematic diagram of the phase detector circuit 153 according to some embodiments of the present disclosure.
- the phase detector circuit 153 may include a first data comparator sub-circuit 1531, a second data comparator sub-circuit 1532, and a third data comparator sub-circuit 1533. Since the second DCO second frequency sub-circuit 1515 using control word F l is an integer, as compared with the phase detector circuit 143 in FIG. 14B, the phase detector circuit 153 may not include a fourth data comparator sub-circuit.
- the first data comparator sub-circuit 1531 may be configured to compare the first rising edge control word with the second rising edge control word and output the first comparison result.
- the second data comparator sub-circuit 1532 may be configured to compare the first falling edge control word with the second falling edge control word and output the second comparison result.
- the third data comparator sub-circuit 1533 may be configured to compare the first fractional frequency control word with zero and output a third comparison result.
- the indication signal generating sub-circuit 1535 may be configured to: the first comparison result indicates that the first rising edge control word is equal to the second rising edge control word, and the second comparison result indicates the first falling edge control word and the second falling edge control word It is equal to the third signal indicating the comparison result indicates a case where the control word is equal to zero, outputting a first output signal indicative of the phase of S h and the second output signal S l of the aligned first fractional frequency; and in the remaining cases (e.g., The first comparison result indicates that the first rising edge control word is not equal to the second rising edge control word or the second comparison result indicates that the first falling edge control word is not equal to the second falling edge control word or the third comparison result indicates the first case of fractional frequency control word is not equal to zero), the phase of the second phase is not output an output signal S l a signal indicative of the first output signal or the output
- the first data comparator sub-circuit 1431, the second data comparator sub-circuit 1432, the third data comparator sub-circuit 1433, and the indication signal generation sub-circuit 1435 may be implemented by a combinational logic circuit.
- the phase detector circuit 153 may also It includes a fifth register 1536 and a sixth register 1537 connected in series. 10 the falling edge control word output by the second register 1013 passes through the first register 1012 and the second register 1013, and the rising edge control word output by the fourth register 1023 passes through the third register 1022 and the fourth register 1023. Therefore, in order to keep the first fractional frequency control word, the rising edge control word, and the falling edge control word output by the first DCO sub-circuit synchronized, a fifth register 1536 and a sixth register 1537 connected in series can be set.
- the fifth register 1536 may be configured to receive the first fractional frequency control word sent by the first DCO sub-circuit 1513, and the third data comparator sub-circuit 1533 may be configured to output the first output of the sixth register 1537.
- the fractional frequency control word is compared with zero and the third comparison result is output.
- the fifth register 1536 may have the same configuration as the first register 1012 in FIG. 10, and the sixth register 1537 may have the same configuration as the second register 1013 in FIG. 10.
- FIG. 15C shows an example in which the fifth register 1536 and the sixth register 1537 are configured to buffer the first fractional frequency control word sent by the first DCO sub-circuit.
- the embodiment of the present disclosure is not limited thereto.
- the fifth register 1536 and the sixth register 1537 may be provided between the third data comparator sub-circuit 1533 and the indication signal generation sub-circuit 1535, and be configured to buffer the comparison result of the third data comparator sub-circuit 1533 to The first comparison result, the second comparison result, and the third comparison result are synchronized.
- FIG. 16 shows a flowchart of a signal generation method according to at least one embodiment of the present disclosure.
- the signal generation method may include steps S161 and S162.
- Step S161 Generate a periodic first output signal based on the first frequency control word and the reference time unit;
- Step S162 Generate a periodic second output signal based on the second frequency control word and the reference time unit.
- the first frequency control word may include a first integer part and a first fractional part
- the second frequency control word may include a second integer part and a second fractional part
- the first frequency control word may include a second integer part and a second decimal part.
- the integer part is equal to the second integer part
- the first fractional part and the second fractional part are not equal
- the period of the first output signal is not equal to the period of the second output signal.
- step S161 may include: generating a first intermediate signal based on the first frequency control word and a reference time unit; and converting the first intermediate signal into a first output signal.
- the first intermediate signal may be generated based on the TAF method.
- the method of generating the first intermediate signal reference may be made to the various embodiments described previously, and the description thereof will be omitted here.
- converting the first intermediate signal into the first output signal may include: filtering out high frequency components in the first intermediate signal to convert the first intermediate signal into the first output signal.
- step S162 may include: generating a second intermediate signal based on the second frequency control word and a reference time unit; and converting the second intermediate signal into a second output signal.
- the second intermediate signal may be generated based on the TAF method.
- the method of generating the second intermediate signal reference may be made to the various embodiments described previously, and the description thereof will be omitted here.
- converting the second intermediate signal into the second output signal may include: filtering out high frequency components in the second intermediate signal to convert the second intermediate signal into the second output signal.
- the period difference between the period of the first output signal and the period of the second output signal is related to the reference time unit and the decimal difference between the first fractional part and the second fractional part. Therefore, by setting the appropriate reference time unit ⁇ , the first frequency control word and the second frequency control word, a signal with a time resolution of femtosecond or picosecond order can be obtained.
- the first frequency control word may include a first integer part and a first fractional part
- the second frequency control word may include a second integer part and a second fractional part
- the first frequency control word may include a second integer part and a second decimal part.
- the second fractional part is 0, that is, the second frequency control word F l can be an integer
- the second frequency control word (ie, the second integer part) is equal to the first integer part of the first frequency control word
- the first fractional part is not Is 0, that is, the first fractional part and the second fractional part are not equal.
- step S161 may include: generating a first intermediate signal based on the first frequency control word and a reference time unit; and converting the first intermediate signal into a first output signal.
- the first intermediate signal may be generated based on the TAF method.
- the method of generating the first intermediate signal reference may be made to the various embodiments described previously, and the description thereof will be omitted here.
- converting the first intermediate signal into the first output signal may include: filtering out high frequency components in the first intermediate signal to convert the first intermediate signal into the first output signal.
- the periodic second output signal may be generated based on the TAF method.
- step S162 may include: generating the periodic second output signal based on the second frequency control word and the reference time unit.
- the second output signal has only one period.
- the period difference between the period of the first output signal and the period of the second output signal is related to the reference time unit and the first fractional part of the first frequency control word F h. Therefore, by setting an appropriate reference time unit ⁇ and the first frequency control word, a signal with a time resolution of the order of femtoseconds or picoseconds can be obtained.
- FIG. 17 shows a flowchart of a digital time conversion method according to at least one embodiment of the present disclosure.
- the digital time conversion method may include steps S171, S172, S173, and S174.
- Step S171 Generate a periodic first output signal based on the first frequency control word and the reference time unit.
- step S171 For some implementations of step S171, reference may be made to step S161 described above.
- Step S172 Generate a periodic second output signal based on the second frequency control word and the reference time unit.
- step S172 reference may be made to step S162 described above.
- step S171 may be performed by the first generating circuit described in any of the foregoing embodiments
- step S172 may be performed by the second generating circuit described in any of the foregoing embodiments.
- a periodic first output signal and a periodic second output signal can be generated, wherein the period difference between the period of the first output signal and the period of the second output signal is the same as the reference time unit, the first The frequency control word is related to the second frequency control word.
- the period difference between the period of the first output signal and the period of the second output signal is related to the reference time unit and the decimal difference between the first fractional part and the second fractional part.
- the period difference between the period of the first output signal and the period of the second output signal is related to the reference time unit and the first fractional part of the first frequency control word F h. Therefore, depending on the implementation of step S172, the period difference between the period of the first output signal and the period of the second output signal may be represented by equation (11) or equation (15).
- Step S173 Receive the digital signal, the first output signal, and the second output signal.
- the digital signal may have n bits expressed as ⁇ n-1:0>, where n may represent the bit width of the digital signal, and n is an integer greater than or equal to 1.
- Step S174 Generate a first time pulse signal or a second time pulse signal corresponding to the digital signal based on the digital signal, the first output signal, and the second output signal.
- steps S173 and S174 can be performed by the time generating circuit and the phase detector circuit described in any of the above embodiments.
- the characteristics of the first time pulse signal refer to the above description of the first time pulse signal in the embodiment of the digital time conversion circuit
- the characteristics of the second time pulse signal refer to the implementation in the digital time conversion circuit above.
- the relevant description of the second time pulse signal in the example refer to the characteristics of the first time pulse signal in the embodiment of the digital time conversion circuit.
- step S174 may include generating a first time pulse signal or a second time pulse signal corresponding to the digital signal based on the bit width of the digital signal, the first output signal, and the second output signal.
- the rising edge of the mth cycle of the first output signal and the first output signal is m ⁇ t R , where m is an integer greater than or equal to 1.
- step S174 may include: counting the period of the first output signal from the moment when the phase of the first output signal is aligned with the phase of the second output signal (for example, counting from 1); The period of the second output signal is counted when the phase of the output signal is aligned with the phase of the second output signal; the first time pulse signal is set to 1 at the time corresponding to the rising edge of the nth period of the first output signal, And the first time pulse signal is set to 0 at the time corresponding to the rising edge of the nth cycle of the second output signal. For example, the period of the first output signal is counted from the moment when the phase of the first output signal is aligned with the phase of the second output signal.
- the period of the first output signal is the period of the first output signal.
- the nth cycle For example, the period of the second output signal is counted from the moment when the phase of the first output signal is aligned with the phase of the second output signal.
- the period of the second output signal is the period of the second output signal.
- the nth cycle thus, a first time pulse signal with a pulse width (that is, the first minimum time interval) of DeltaT can be generated.
- step S174 may include: setting the first sub-pulse signal to 1 at a time corresponding to the rising edge of the nth cycle of the first output signal, and setting the first sub-pulse signal to 1 at the rising edge of the nth cycle of the second output signal
- the second sub-pulse signal of the second time pulse signal is set to 1 at the corresponding moment. For example, the period of the first output signal is counted from the moment when the phase of the first output signal is aligned with the phase of the second output signal. When the count value is n, the period of the first output signal is the period of the first output signal. The nth cycle.
- the period of the second output signal is counted from the moment when the phase of the first output signal is aligned with the phase of the second output signal.
- the count value is n
- the period of the second output signal is the period of the second output signal. The nth cycle.
- the second time pulse signal including the first sub-pulse signal and the second sub-pulse signal can be generated, and the second minimum time interval corresponding to the first sub-pulse signal and the second sub-pulse signal is DeltaT.
- the digital time conversion method may further include: determining the phase relationship between the first output signal and the second output signal to generate an indication signal indicating that the phase of the first output signal is aligned with the phase of the second output signal.
- step S174 may include: generating the first time pulse signal or the second time pulse signal based on the digital signal, the first output signal, the second output signal, and the indicator signal. For example, in step S174, in the case where the indication signal is received (the indication signal indicates that the phase of the first output signal is aligned with the phase of the second output signal), the period of the first output signal and the second output signal The period of the signal is counted.
- the pulse width can be generated in the order of femtoseconds or picoseconds.
- generate a second time pulse signal including a first sub-pulse signal and a second sub-pulse signal whose time interval is on the order of femtosecond or picosecond.
- the digital time conversion method described in FIG. 17 may be applied to digital time conversion circuits according to various embodiments of the present disclosure.
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Abstract
Description
Claims (27)
- 一种信号生成电路,包括:第一生成电路,被配置为基于第一频率控制字和基准时间单位生成周期性的第一输出信号;以及第二生成电路,被配置为基于第二频率控制字和所述基准时间单位生成周期性的第二输出信号,其中,所述第一频率控制字包括第一整数部分和第一小数部分,所述第二频率控制字包括第二整数部分和第二小数部分,所述第一整数部分等于所述第二整数部分,所述第一小数部分与所述第二小数部分不相等,所述第一输出信号的周期与所述第二输出信号的周期不相等。
- 如权利要求1所述的信号生成电路,其中,所述第一输出信号的周期与所述第二输出信号的周期之间的周期差与所述基准时间单位以及所述第一小数部分与所述第二小数部分之间的小数差有关。
- 如权利要求1所述的信号生成电路,其中,所述第一生成电路包括第一数字控制振荡器子电路和第一转换子电路,所述第一数字控制振荡器子电路被配置为基于所述第一频率控制字和所述基准时间单位生成第一中间信号,所述第一转换子电路被配置为将所述第一中间信号转换为所述第一输出信号;所述第二生成电路包括第二数字控制振荡器子电路和第二转换子电路,所述第二数字控制振荡器子电路被配置为基于所述第二频率控制字和所述基准时间单位生成第二中间信号,所述第二转换子电路被配置为将所述第二中间信号转换为第二输出信号,其中,所述第一中间信号是通过具有第一原始周期的脉冲和具有第二原始周期的脉冲以交错方式生成的,所述第一中间信号的第一平均周期通过下式表示:T h=(1-r h)·T A+r h·T B,其中,T h表示所述第一中间信号的第一平均周期,r h表示所述第一小数部分,T A表示所述第一原始周期,T B表示所述第二原始周期,其中,所述第二中间信号是通过具有所述第一原始周期的脉冲和具 有所述第二原始周期的脉冲以交错方式生成的,所述第二中间信号的第二平均周期通过下式表示:T l=(1-r l)·T A+r l·T B,其中,T l表示所述第二中间信号的第二平均周期,r l表示所述第二小数部分。
- 如权利要求3所述的信号生成电路,其中,所述第一转换子电路包括第一滤波器,所述第一滤波器被配置为滤除所述第一中间信号中的高频分量以得到所述第一输出信号。
- 如权利要求4所述的信号生成电路,其中,所述第一滤波器的参数根据所述第一中间信号的平均频率和所述第一小数部分的最低有效位确定。
- 如权利要求3所述的信号生成电路,其中,所述第二转换子电路包括第二滤波器,所述第二滤波器被配置为滤除所述第二中间信号中的高频分量以得到第二输出信号。
- 如权利要求7所述的信号生成电路,其中,所述第二滤波器的参数根据所述第二中间信号的平均频率和所述第二小数部分的最低有效位确定。
- 如权利要求3所述的信号生成电路,其中,所述第一数字控制 振荡器子电路和所述第二数字控制振荡器子电路均包括时间平均频率直接周期合成器。
- 如权利要求1-10中任一项所述的信号生成电路,还包括基准时间单位生成电路,其中,所述基准时间单位生成子电路被配置为生成所述基准时间单位。
- 如权利要求11所述的信号生成电路,其中,所述基准时间单位生成电路包括多个D触发器。
- 如权利要求11所述的信号生成电路,其中,所述基准时间单位生成电路包括:压控振荡器,被配置为以预定振荡频率振荡;锁相环回路电路,被配置为将所述压控振荡器的输出频率锁定为基准输出频率;以及K个输出端,被配置为输出K个相位均匀间隔的输出信号,其中,K为大于1的正整数,其中,所述基准输出频率表示为f Δ,所述基准时间单位是所述K个输出端输出的任意两个相邻的输出信号之间的时间跨度,所述基准时间单位表示为Δ,并且Δ=1/(K·f Δ)。
- 如权利要求1-10中任一项所述的信号生成电路,还包括:控制电路,其中,所述控制电路被配置为确定所述第一频率控制字和所述第二频率控制字,并输出所述第一频率控制字至所述第一生成电路,输出所述第二频率控制字至所述第二生成电路。
- 一种数字时间转换电路,包括:如权利要求1-14中任一项所述的信号生成电路;以及时间生成电路,被配置为接收数字信号、所述第一输出信号以及所述第二输出信号;以及基于所述数字信号、所述第一输出信号以及所述第二输出信号生成与所述数字信号对应的第一时间脉冲信号或第二时间脉冲信号,其中,所述第一时间脉冲信号的上升沿和下降沿之间的第一最小时 间间隔与所述基准时间单位、所述第一小数部分、所述第二小数部分有关;或者,所述第二时间脉冲信号包括第一子脉冲信号和第二子脉冲信号,所述第一子脉冲信号的上升沿和第二子脉冲信号的上升沿之间的第二最小时间间隔与所述基准时间单位、所述第一小数部分、所述第二小数部分有关。
- 如权利要求15所述的数字时间转换电路,还包括鉴相器电路,其中,所述鉴相器电路被配置为确定所述第一输出信号和所述第二输出信号的相位关系以生成指示所述第一输出信号的相位与所述第二输出信号的相位对齐的指示信号,所述时间生成电路被配置为基于所述数字信号、所述第一输出信号、所述第二输出信号和所述指示信号生成所述第一时间脉冲信号或所述第二时间脉冲信号。
- 如权利要求16所述的数字时间转换电路,其中,所述第一生成电路包括被配置为基于所述第一频率控制字和所述基准时间单位生成第一中间信号的所述第一数字控制振荡器子电路和被配置为将所述第一中间信号转换为所述第一输出信号的第一转换子电路,并且所述第二生成电路包括被配置为基于所述第二频率控制字和所述基准时间单位生成第二中间信号的第二数字控制振荡器子电路和被配置为将所述第二中间信号转换为第二输出信号的第二转换子电路,所述第一生成电路还被配置为在生成所述第一中间信号时输出与所述第一中间信号的上升沿相对应的第一上升沿控制字、与所述第一中间信号的下降沿相对应的第一下降沿控制字、以及与所述第一中间信号的周期切换相对应的第一小数频率控制字,所述第二生成电路还被配置为在生成第二中间信号时输出与所述第二中间信号的上升沿相对应的第二上升沿控制字、与所述第二中间信号的下降沿相对应的第二下降沿控制字、以及与所述第二中间信号的周期切换相对应的第二小数频率控制字,并且所述鉴相器电路被配置为:基于所述第一上升沿控制字、所述第二上升沿控制字、所述第一下降沿控制字、所述第二下降沿控制字、所述第一小数频率控制字和所述第二小数频率控制字生成所述指示信号。
- 如权利要求17所述的数字时间转换电路,其中,所述鉴相器电路被配置为:在所述第一上升沿控制字等于所述第二上升沿控制字、所述第一下降沿控制字等于所述第二下降沿控制字、以及所述第一小数频率控制字和第二小数频率控制字均等于零的情况下,生成所述指示信号。
- 如权利要求15-18中任一项所述的数字时间转换电路,其中,所述第一最小时间间隔或所述第二最小时间间隔表示为:DeltaT=n·t R,其中,DeltaT表示所述第一最小时间间隔或所述第二最小时间间隔,n表示所述数字信号的位宽,t R表示所述第一输出信号的周期与所述第二输出信号的周期之间的周期差,且t R表示为:t R=(r h-r l)·Δ,其中,r h表示所述第一小数部分,r l表示所述第二小数部分,Δ表示所述基准时间单位。
- 一种信号生成方法,包括:基于第一频率控制字和基准时间单位生成周期性的第一输出信号;以及基于第二频率控制字和所述基准时间单位生成周期性的第二输出信号,其中,所述第一频率控制字包括第一整数部分和第一小数部分,所述第二频率控制字包括第二整数部分和第二小数部分,所述第一整数部分等于所述第二整数部分,所述第一小数部分与所述第二小数部分不相等,所述第一输出信号的周期与所述第二输出信号的周期不相等。
- 如权利要求20所述的信号生成方法,其中,所述第一输出信号的周期与所述第二输出信号的周期之间的周期差与所述基准时间单位以及所述第一小数部分与所述第二小数部分之间的小数差有关。
- 如权利要求20或21所述的信号生成方法,其中,基于第一频率控制字和基准时间单位生成周期性的第一输出信号包括:基于所述第一频率控制字和所述基准时间单位生成第一中间信 号;以及将所述第一中间信号转换为所述第一输出信号,基于所述第二频率控制字和所述基准时间单位生成周期性的第二输出信号包括:基于所述第二频率控制字和所述基准时间单位生成第二中间信号;以及将所述第二中间信号转换为第二输出信号,其中,所述第一中间信号是通过具有第一原始周期的脉冲和具有第二原始周期的脉冲以交错方式生成的,所述第一中间信号的第一平均周期通过下式表示:T h=(1-r h)·T A+r h·T B,其中,T h表示所述第一中间信号的第一平均周期,r h表示所述第一小数部分,T A表示所述第一原始周期,T B表示所述第二原始周期,其中,所述第二中间信号是通过具有所述第一原始周期的脉冲和具有所述第二原始周期的脉冲以交错方式生成的,所述第二中间信号的第二平均周期通过下式表示:T l=(1-r l)·T A+r l·T B,其中,T l表示所述第二中间信号的第二平均周期,r l表示所述第二小数部分,T A表示所述第一原始周期,T B表示所述第二原始周期。
- 如权利要求22所述的信号生成方法,其中,将所述第一中间信号转换为所述第一输出信号包括:滤除所述第一中间信号中的高频分量以将所述第一中间信号转换为所述第一输出信号。其中,将所述第二中间信号转换为第二输出信号包括:滤除所述第二中间信号中的高频分量以将所述第二中间信号转换为所述第二输出信号。
- 一种应用于权利要求15-19中任一项所述的数字时间转换电路的数字时间转换方法,包括:接收所述数字信号、所述第一输出信号以及所述第二输出信号;以及基于所述数字信号、所述第一输出信号以及所述第二输出信号生成与所述数字信号对应的第一时间脉冲信号或第二时间脉冲信号。
- 如权利要求24所述的数字时间转换方法,还包括:确定所述第一输出信号和所述第二输出信号的相位关系以生成指示所述第一输出信号的相位与所述第二输出信号的相位对齐的指示信号,其中,基于所述数字信号、所述第一输出信号以及所述第二输出信号生成与所述数字信号对应的第一时间脉冲信号或第二时间脉冲信号包括:基于所述数字信号、所述第一输出信号、所述第二输出信号和所述指示信号生成所述第一时间脉冲信号或所述第二时间脉冲信号。
- 如权利要求25所述的数字时间转换方法,其中,基于第一频率控制字和基准时间单位生成周期性的第一输出信号包括:基于所述第一频率控制字和所述基准时间单位生成第一中间信号、以及将所述第一中间信号转换为所述第一输出信号,基于第二频率控制字和所述基准时间单位生成周期性的第二输出信号包括:基于所述第二频率控制字和所述基准时间单位生成第二中间信号、以及将所述第二中间信号转换为第二输出信号,所述数字时间转换方法还包括:当生成所述第一中间信号时获得与所述第一中间信号的上升沿相对应的第一上升沿控制字、与所述第一中间信号的下降沿相对应的第一下降沿控制字、以及与所述第一中间信号的周期切换相对应的第一小数频率控制字;以及当生成所述第二中间信号时获得与所述第二中间信号的上升沿相对应的第二上升沿控制字、与所述第二中间信号的下降沿相对应的第二下降沿控制字、以及与所述第二中间信号的周期切换相对应的第二小数频率控制字,其中,确定所述第一输出信号和所述第二输出信号的相位关系以生成指示所述第一输出信号的相位与所述第二输出信号的相位对齐的指示信号包括:基于所述第一上升沿控制字、所述第二上升沿控制字、所述第一下降沿控制字、所述第二下降沿控制字、所述第一小数频率控制字和所述 第二小数频率控制字生成所述指示信号。
- 如权利要求26所述的数字时间转换方法,其中,基于所述第一上升沿控制字、所述第二上升沿控制字、所述第一下降沿控制字、所述第二下降沿控制字、所述第一小数频率控制字和所述第二小数频率控制字生成所述指示信号,包括:在所述第一上升沿控制字等于所述第二上升沿控制字、所述第一下降沿控制字等于所述第二下降沿控制字、以及所述第一小数频率控制字和第二小数频率控制字均等于零的情况下,生成所述指示信号。
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