WO2020198917A1 - 光通信驱动电路及方法、光通信发送端、系统、交通工具 - Google Patents

光通信驱动电路及方法、光通信发送端、系统、交通工具 Download PDF

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Publication number
WO2020198917A1
WO2020198917A1 PCT/CN2019/080373 CN2019080373W WO2020198917A1 WO 2020198917 A1 WO2020198917 A1 WO 2020198917A1 CN 2019080373 W CN2019080373 W CN 2019080373W WO 2020198917 A1 WO2020198917 A1 WO 2020198917A1
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Prior art keywords
signal
control word
frequency
frequency signal
periodic
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PCT/CN2019/080373
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English (en)
French (fr)
Inventor
李彦孚
修黎明
李鑫
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/769,297 priority Critical patent/US11474556B2/en
Priority to CN201980000436.1A priority patent/CN110168966B/zh
Priority to PCT/CN2019/080373 priority patent/WO2020198917A1/zh
Publication of WO2020198917A1 publication Critical patent/WO2020198917A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G06F1/105—Distribution of clock signals, e.g. skew in which the distribution is at least partially optical
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/50—Transmitters
    • H04B10/501—Structural aspects
    • H04B10/503—Laser transmitters
    • H04B10/504—Laser transmitters using direct modulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/50—Transmitters
    • H04B10/516—Details of coding or modulation

Definitions

  • the present disclosure relates to an optical communication driving circuit and method, an optical communication sending end, a system, and a vehicle.
  • Optical communication is an important way of communication between cars, and the modulation of optical signals is the focus of optical communication.
  • the modulation process of the optical signal includes converting the information to be sent into a clock signal, and then modulating the optical signal with the clock signal, so that the content of the information to be sent is carried in the optical signal.
  • the embodiments of the present disclosure provide an optical communication driving circuit and method, an optical communication transmitting end, a system, and a vehicle.
  • At least one embodiment of the present disclosure provides an optical communication drive circuit, including: a clock circuit configured to take an initial frequency signal as input and output a clock signal under the control of the information to be sent, the clock signal including alternating current A first frequency signal and a second frequency signal, the first frequency signal and the second frequency signal have different frequencies and are generated based on the initial frequency signal; a modulation circuit configured to use the clock output by the clock circuit The signal modulates the optical signal to obtain a modulated optical signal.
  • the clock circuit includes: a control sub-circuit configured to generate a control word sequence according to the information to be sent, the control word sequence including a first control word that appears alternately And a second control word; a processing sub-circuit configured to obtain the first frequency signal based on the frequency of the initial frequency signal and the first control word in the control word sequence generated by the control sub-circuit; The frequency of the initial frequency signal and the second control word in the control word sequence generated by the control subcircuit obtain the second frequency signal.
  • control sub-circuit is configured to sequentially select each of the information in the information to be sent based on the corresponding relationship between the bits and the control word.
  • the control word corresponding to the bit obtains the control word sequence.
  • control sub-circuit is configured to select the corresponding relationship between the corresponding bit and the control word according to the communication mode, and in different communication modes, the bit and the control word The corresponding relationship is at least partially different.
  • the processing sub-circuit includes: a frequency divider configured to generate K signals with uniform phase intervals according to the initial frequency signal, where K is an integer greater than 2;
  • the synthesizer is configured to generate the first frequency signal based on the K uniformly spaced signals generated by the frequency divider and the first control word, and based on the K uniformly spaced signals and the first control word Two control words generate the second frequency signal.
  • the frequency synthesizer is configured to generate a first periodic signal and a second periodic signal based on the K signals with evenly spaced phases and the first control word, And generate the first frequency signal based on the first periodic signal and the second periodic signal; generate a third periodic signal and a fourth periodic signal based on the K signals with uniform phase intervals and the second control word Signal and generate the second frequency signal based on the third periodic signal and the fourth periodic signal.
  • At least one embodiment of the present disclosure provides an optical communication sending end, the optical communication sending end includes a light-emitting unit and the optical communication drive circuit as described in any one of the preceding items, and the optical communication drive circuit is configured to The optical signal is modulated to obtain a modulated optical signal.
  • At least one embodiment of the present disclosure provides an optical communication system, the system includes a sending end and a receiving end, and the sending end is the optical communication sending end described in any one of the preceding items.
  • At least one embodiment of the present disclosure provides a vehicle including the optical communication transmitter described in any one of the preceding items.
  • At least one embodiment of the present disclosure provides an optical communication driving method, including: taking an initial frequency signal as an input, and outputting a clock signal under the control of the information to be sent, the clock signal including a first frequency signal and a first frequency signal that appear alternately. Two frequency signals, the first frequency signal and the second frequency signal have different frequencies and are generated based on the initial frequency signal; the clock signal is used to modulate the optical signal to obtain a modulated optical signal.
  • the output of a clock signal under the control of the information to be sent by taking an initial frequency signal as input includes: generating a control word sequence according to the information to be sent, and the control word The sequence includes a first control word and a second control word that appear alternately; the first frequency signal is obtained based on the frequency of the initial frequency signal and the first control word, and the first frequency signal is obtained based on the frequency of the initial frequency signal and the first control word.
  • the second control word obtains the second frequency signal.
  • the generating the control word according to the information to be sent includes: based on the corresponding relationship between bits and the control word, sequentially selecting the The control word corresponding to each bit in the information to be sent is obtained to obtain the control word sequence.
  • Said generating the control word sequence according to the information to be sent further includes: selecting the corresponding relationship between the bit and the control word according to the communication mode, and in different communication modes, the corresponding relationship between the bit and the control word is at least The parts are different.
  • the first frequency signal is obtained based on the frequency of the initial frequency signal and the first control word
  • the control word to obtain the second frequency signal includes: generating K signals with evenly spaced phases according to the initial frequency signal, where K is an integer greater than 2; based on the K signals with evenly spaced phases and the first control The word generates the first frequency signal, and the second frequency signal is generated based on the K signals with evenly spaced phases and the second control word.
  • the first frequency signal is generated based on the K uniformly spaced signals and the first control word
  • the first frequency signal is generated based on the K uniformly spaced signals
  • the second control word generating the second frequency signal includes: generating a first periodic signal and a second periodic signal based on the K signals with uniform phase intervals and the first control word, and based on the first control word
  • a periodic signal and the second periodic signal generate the first frequency signal
  • a third periodic signal and a fourth periodic signal are generated, and based on all The third periodic signal and the fourth periodic signal generate the second frequency signal.
  • the first periodic signal and the second periodic signal are generated based on the K uniformly spaced signals and the first control word.
  • the first frequency signal is generated based on the first periodic signal and the second periodic signal
  • the first frequency signal is generated based on the third periodic signal and the fourth periodic signal
  • FIG. 1 is a schematic diagram of hardware implementation of FSK in conventional technology
  • Figure 2 is a waveform diagram of a clock signal generated by using the FSK hardware structure shown in Figure 1;
  • FIG. 3 shows a schematic structural diagram of an optical communication driving circuit provided by an embodiment of the present disclosure
  • FIG. 4 is a waveform diagram of a clock signal generated by the clock circuit in FIG. 3;
  • Figure 5 shows a schematic structural diagram of a clock circuit provided by an embodiment of the present disclosure
  • FIG. 6 shows a schematic structural diagram of a processing sub-circuit provided by an embodiment of the present disclosure
  • Fig. 7 is a waveform diagram of K signals with evenly spaced phases generated by the frequency divider in Fig. 6;
  • Figure 8 is a schematic diagram of the principle of clock signal synthesis using a TAF-DPS frequency synthesizer
  • FIG. 9 is a schematic structural diagram of a TAF-DPS frequency synthesizer provided by the present disclosure.
  • FIG. 10 shows a schematic structural diagram of an optical communication transmitting end provided by an embodiment of the present disclosure
  • FIG. 11 shows a schematic structural diagram of an optical communication system provided by an embodiment of the present disclosure
  • FIG. 12 shows a schematic diagram of communication between vehicles provided by an embodiment of the present disclosure
  • FIG. 13 shows another schematic diagram of communication between vehicles provided by an embodiment of the present disclosure
  • FIG. 14 shows a flowchart of an optical communication driving method provided by an embodiment of the present disclosure
  • FIG. 15 shows a flowchart of an optical communication driving method provided by an embodiment of the present disclosure.
  • the binary frequency shift keying (Frequency-shift keying, FSK) technology can realize the aforementioned process of converting the information to be sent into a clock signal, and the generated clock signal has better anti-noise and anti-attenuation performance.
  • bits 0 and 1 of the information to be sent are respectively represented by waveforms of corresponding periods in two frequency signals with different frequencies. For example, bit 0 selects the waveform representation of 2 cycles in the first frequency signal, and bit 1 selects the waveform representation of 3 cycles in the second frequency signal, so that the waveforms of different cycles and different frequencies are used to represent bits 0 and 1 respectively.
  • bit 0 selects the waveform representation of 2 cycles in the first frequency signal
  • bit 1 selects the waveform representation of 3 cycles in the second frequency signal, so that the waveforms of different cycles and different frequencies are used to represent bits 0 and 1 respectively.
  • the time period occupied by the waveform of 2 cycles in the first frequency signal and the waveform of 3 cycles in the second frequency signal is equal, so that the
  • FIG. 1 is a schematic diagram of the hardware implementation of FSK in the conventional technology.
  • FSK sends two channels of frequency signals f 1 and f 2 to the input terminals of two gate circuits 11 and 12 respectively, and passes the analog signal ⁇ ak ⁇ of the information to be sent and the inverted signal of the analog signal ⁇ ak ' ⁇ to control the two gate circuits 11 and 12 for waveform selection, and then add the outputs of the two gate circuits 11 and 12 through the adder 13 to obtain the output signal e t , that is, the clock signal.
  • the aforementioned frequency signal refers to periodic high and low level signals.
  • Figure 2 is a waveform diagram of the clock signal generated by the FSK hardware structure shown in Figure 1.
  • bit 0 corresponds to the dotted line in the figure
  • bit 1 corresponds to the solid line in the figure. It can be seen that there is a significant delay between the solid line and the dotted line, that is, the part shown by ⁇ t in Figure 2. Delays may cause errors in the number of waveforms in a time period.
  • FIG. 3 shows a schematic structural diagram of an optical communication driving circuit provided by an embodiment of the present disclosure.
  • the optical communication driving circuit is applied to the optical communication transmitting end, and includes a clock circuit 200 and a modulation circuit 300.
  • the input of the input terminal of the clock circuit 200 is an initial frequency signal
  • the input of the control terminal of the clock circuit 200 is an analog signal corresponding to the information to be sent
  • the output terminal of the clock circuit 200 is connected to the input terminal of the modulation circuit 300
  • the output terminal of the modulation circuit 300 is connected The control end of the light-emitting unit 100 in the optical communication transmitting end.
  • the clock circuit 200 is configured to take an initial frequency signal as input and output a clock signal under the control of the information to be sent.
  • the clock signal includes a first frequency signal and a second frequency signal that alternately appear, the first frequency signal and the second frequency signal It has different frequencies and is generated based on the initial frequency signal.
  • the modulation circuit 300 is configured to use the clock signal output by the clock circuit 200 to perform a modulation operation on the optical signal.
  • the light signal is generated by the light emitting unit 100, and a modulated light signal, such as a light pulse signal, is obtained by modulating the light signal.
  • a clock circuit is used to generate a clock signal.
  • the generated clock signal includes a first frequency signal and a second frequency signal that alternately appear.
  • the first frequency signal and the second frequency signal have different frequencies, They are all generated based on the initial frequency signal, that is to say, the clock circuit uses an initial frequency signal as an input, and at the same time it controls with the information to be sent to output the clock signal.
  • the clock circuit uses an initial frequency signal as an input, and at the same time it controls with the information to be sent to output the clock signal.
  • the waveform selection of the two frequency signals is used to generate a clock signal, which avoids the inversion of the analog signal of the information to be sent and the waveform selection through the inverted signal.
  • the output delay caused by the process avoids the bit error caused by the output delay and improves the communication quality.
  • the clock signal generated by the solution provided by the present disclosure does not have the aforementioned delay, a smaller time period can be used to represent the bits in the information to be sent, which can increase the data transmission rate.
  • the clock circuit 200 uses an initial frequency f i signal as an input signal, an analog signal under control of information to be transmitted ⁇ a k ⁇ , the output clock signal e t.
  • the initial frequency signal may be generated by a voltage-controlled oscillator, for example, an LC Voltage Controlled Oscillator (LCVCO) is used as a vibration source to generate the foregoing initial frequency signal.
  • LCVCO LC Voltage Controlled Oscillator
  • the optical communication driving circuit may further include a voltage-controlled oscillator, and the output terminal of the voltage-controlled oscillator is electrically connected to the input terminal of the clock circuit 200.
  • the information to be sent can be generated by a device equipped with an optical communication sending end.
  • the information to be sent can be generated by the car’s trip computer.
  • the information may be an analog signal, which may be directly output to the clock circuit 200.
  • the clock signal is generated based on the initial frequency signal, that is, in the embodiment of the present disclosure, the frequency of the portion of the clock signal corresponding to bit 0 in the information to be sent (the first frequency signal) is equal to The frequency of the initial frequency signal is proportional.
  • the frequency of the part of the clock signal corresponding to bit 1 in the information to be sent (the second frequency signal) is also proportional to the frequency of the initial frequency signal, and the frequency of the first frequency signal is proportional to the frequency of the second frequency signal.
  • the frequency of the frequency signal is different in proportion to the frequency of the initial frequency signal.
  • proportional means that the first frequency signal or the second frequency signal can be obtained by multiplying the frequency of the clock signal by a value, and the value is an integer or a finite decimal.
  • the light emitting unit 100 may be a laser, and the laser generated by the laser has the advantages of good monochromaticity and high brightness, and is very suitable as a light source for optical communication.
  • the modulation circuit 300 is a laser modulator, which is used to modulate the laser light generated by the laser to obtain a modulated laser signal.
  • the laser modulator can control the on and off of the laser by the high and low levels of the clock signal, thereby generating a laser pulse signal, which is the aforementioned modulated laser signal, and carries the aforementioned information to be sent.
  • Fig. 4 is a waveform diagram of a clock signal generated by the clock circuit in Fig. 3.
  • bit 0 corresponds to the dotted line part in the figure
  • bit 1 corresponds to the solid line part in the figure. It can be seen that there is no delay between the solid line part and the dotted line part, thereby avoiding bit errors due to delay.
  • the frequency of the signal representing bit 1 is both f1
  • the frequency of the signal representing bit 0 is both f2.
  • bit 1 uses 3 cycles
  • the f1 waveform of bit 0 is represented by the f2 waveform of 2 cycles
  • the bit 1 is represented by the f1 waveform of 2 cycles
  • the bit 0 is represented by the f2 waveform of 1 cycle.
  • FIG. 5 shows a schematic structural diagram of a clock circuit provided by an embodiment of the present disclosure.
  • the clock circuit 200 may include:
  • the control sub-circuit 201 is configured to generate a control word sequence according to the information to be sent, and the control word sequence includes a first control word and a second control word that appear alternately;
  • the processing sub-circuit 202 is configured to obtain a first frequency signal based on the frequency of the initial frequency signal and the first control word in the control word sequence generated by the control sub-circuit 201, and based on the frequency of the initial frequency signal and the control word generated by the control sub-circuit 201
  • the second control word in the sequence gets the second frequency signal.
  • the processing sub-circuit 202 is configured to output a clock signal whose output frequency is equal to the frequency of the initial frequency signal divided by the control word, and the frequency of the first frequency signal in the clock signal is equal to the frequency of the initial frequency signal divided by the first control word, The frequency of the second frequency signal in the clock signal is equal to the frequency of the initial frequency signal divided by the second control word.
  • control word sequence refers to a signal used to control the frequency of the clock signal.
  • the control word sequence is generated according to the information to be sent, so that the information to be sent can be restored at the receiving end by demodulating the received signal.
  • the frequency of the clock signal generated by the clock circuit is equal to the frequency of the initial frequency signal divided by the control word, the generation of a clock signal of any frequency can be achieved through the control control word.
  • the frequency of the clock signal is fixed.
  • the present disclosure enriches the diversity of the clock signal.
  • the control word sequence includes the first control word and the second control word that appear alternately.
  • the frequency of the clock signal is equal to the frequency of the initial frequency signal divided by the control word. Therefore, the clock signal output by the processing sub-circuit 202 includes the alternate first frequency. Signal and second frequency signal.
  • the information to be sent is a series of binary bit streams, which contain binary numbers bit 0 and bit 1. Therefore, if the information to be sent is directly used to control the frequency of the clock signal, only bits 0 and 1 can be generated. Corresponding to the two frequencies, these two frequencies are fixed.
  • bits 0 and 1 can be mapped to different control words, that is, the first control word in different control word sequences can be different, and the second control word in different control word sequences can also be Different, different frequencies are selected through different control words to realize the output of clock signals of different frequencies.
  • the frequency of the output clock signal can be accurately controlled by the control word.
  • the first control word and the second control word that appear alternately correspond to the bit 0 and the bit 1 alternately appearing in the information to be sent, and the alternate appearance here is not limited to the alternation of a 0 and a 1.
  • the first control word and the second control word can also be an unlimited number of first control words alternating with an unlimited number of second control words.
  • the message to be sent is 10011101.
  • the alternation of 0 and 1 here is not limited to the alternation of 1 0 and 1 1, nor is it limited to the alternation of a certain number of 0s and the same number of 1s.
  • control sub-circuit 201 is configured to sequentially select the control word corresponding to each bit in the information to be sent according to the order of the bits in the information to be sent based on the correspondence between the bits and the control word. Get the control word sequence.
  • a preset control word is selected, so that the clock circuit can output a clock signal corresponding to the control word and a frequency that meets the communication requirements.
  • the same bit in the information to be sent corresponds to the same waveform in the clock signal to ensure correct demodulation at the receiving end.
  • bit 0 corresponds to the first value (that is, the first control word in the control word sequence), and bit 1 corresponds to the second value (that is, the second control word in the control word sequence). word).
  • the control sub-circuit 201 sequentially selects corresponding values as the control word according to the order of the bits in the information to be sent, and controls the output of the clock signal. If the bit in the information to be sent is 10010, the control sub-circuit 201 sequentially selects the second value, the first value, the first value, the second value, and the first value to periodically control the processing sub-circuit 202 to control the processing sub-circuit The output of circuit 202.
  • the control sub-circuit 201 may include at least two control word registers for storing the aforementioned control words. When the control sub-circuit 201 receives the information to be sent, it can read the corresponding control word from the register according to the corresponding bit.
  • the aforementioned correspondence between bits and control words may include the mapping between bits and register addresses, for example, bit 0 is mapped to the address of a register storing the first value, and bit 1 is mapped to the address of a register storing the second value.
  • control sub-circuit 201 is configured to select the corresponding relationship between the bit and the control word according to the communication mode. In different communication modes, the corresponding relationship between the bit and the control word is at least partially different. the same.
  • a bit refers to information contained in one bit of a binary number, such as bit 0 or bit 1.
  • the optical communication transmitter may have 3 communication modes, where the first communication mode corresponds to the correspondence between the first kind of bit and the control word, the second communication mode corresponds to the second correspondence between the bit and the control word, and the third communication The mode corresponds to the correspondence between the third bit and the control word.
  • bit 0 corresponds to the first value
  • bit 1 corresponds to the second value
  • bit 0 corresponds to the fourth value
  • bit 0 corresponds to the third value
  • bit 1 corresponds to the fifth value.
  • the control word corresponding to bit 0 is different, and the control word corresponding to bit 1 is also different, that is, the bit and the control word in the first communication mode and the second communication mode
  • the corresponding relationship is completely different; in the second communication mode and the third communication mode, the control word corresponding to bit 0 is the same, and the control word corresponding to bit 1 is different, that is, the bit and control in the second communication mode and the third communication mode Correspondence of words is partially different.
  • each communication mode corresponds to a mapping relationship between bits and register addresses. For example, in the first communication mode, bit 0 is mapped to the address of the register storing the first value, and bit 1 is mapped to the second The address of the register of the value; in the second communication mode, bit 0 is mapped to the address of the register that stores the third value, and bit 1 is mapped to the address of the register that stores the fourth value; in the third communication mode, bit 0 is mapped to The address of the register storing the third value, bit 1 is mapped to the address of the register storing the fifth value.
  • the communication mode can be set as required.
  • the communication mode may include a private communication mode and an open communication mode.
  • the private communication mode can be customized at the sending and receiving ends. Only the sending and receiving ends can use this mode to modulate and demodulate data information at the same time; while the open communication mode can be a standard communication mode. This mode can be used to modulate and demodulate data information.
  • the receiving end when the optical communication transmitting end adopts one of the aforementioned communication modes for signal modulation, correspondingly, the receiving end also adopts the same communication mode for signal demodulation.
  • the sending end uses the first communication mode selection control word to generate a clock signal, and then uses the clock signal for optical modulation, then correspondingly, the receiving end also needs to work in the first communication mode, according to the waveform and data in the communication mode
  • the relationship between bits is demodulated to obtain data information (that is, the aforementioned information to be sent).
  • the transmitting end determines the control word corresponding to each bit, and thus the waveform in the clock signal corresponding to each bit
  • the relationship between the waveform of the signal received by the receiving end and the bit is also determined.
  • the corresponding relationship between the waveform and the data bit in each communication mode may be stored in the receiving end in advance, and the receiving end may select the corresponding relationship between the waveform and the data bit in the corresponding communication mode when performing data demodulation.
  • the communication mode of the sending end and the receiving end can be determined through negotiation, and the manner of detailed negotiation is not limited in the present disclosure.
  • FIG. 6 shows a schematic structural diagram of a processing sub-circuit provided by an embodiment of the present disclosure.
  • the processing sub-circuit 202 includes a frequency divider 221 and a frequency synthesizer 222.
  • the input end of the frequency divider 221 is an initial frequency signal
  • the output end of the frequency divider 221 is connected to the input end of the frequency synthesizer 222
  • the output end of the frequency synthesizer 222 is connected to the modulation circuit 300.
  • the frequency divider 221 is configured to generate K signals with evenly spaced phases according to the initial frequency signal, and K is an integer greater than 2.
  • the frequency synthesizer 222 is configured to generate a first frequency signal based on the K uniformly spaced signals generated by the frequency divider 221 and the first control word, and generate a second frequency signal based on the K uniformly spaced signals and the second control word. , Get the clock signal.
  • the processing sub-circuit is composed of two parts. Among them, the frequency divider is responsible for generating K uniformly spaced signals according to the frequency signal, and the frequency synthesizer is responsible for generating K uniformly spaced signals and control words according to the frequency signal. Generate a clock signal.
  • FIG. 7 is a waveform diagram of K signals with evenly spaced phases generated by the frequency divider in FIG. 6.
  • the waveforms of any two signals are the same (that is, the period and amplitude are the same), and the waveforms of the K signals are evenly arranged.
  • the phase difference between any two adjacent signals is the basic time unit ⁇ , K signals
  • the frequencies of are all f i , and K is an integer greater than 1.
  • the frequency divider 221 may be implemented by a Johnson counter (Johnson Counter, or twisted loop counter) to generate the K signals with uniformly spaced phases.
  • the frequency divider 221 may also be implemented by using a circular traveling-wave oscillator (RTWO), which is a transmission line-based clock generation technology, which can easily generate the K signals with evenly spaced phases.
  • RTWO circular traveling-wave oscillator
  • the frequency divider 221 can also be implemented by a differential latch to generate the K signals with evenly spaced phases.
  • the frequency synthesizer 222 may be a Time Average Frequency (TAF) direct period synthesis (Direct Period Synthesis, DPS) frequency synthesizer, where TAF refers to a fixed period of time, different
  • TAF Time Average Frequency
  • DPS Direct Period Synthesis
  • the frequency synthesizer 222 is configured to generate a first periodic signal and a second periodic signal based on K signals with evenly spaced phases and a first control word, and based on the first periodic signal And the second periodic signal to generate the first frequency signal; based on the K signals with evenly spaced phases and the second control word, the third periodic signal and the fourth periodic signal are generated, and the second periodic signal is generated based on the third periodic signal and the fourth periodic signal Frequency signal.
  • the control word sequence includes a first control word and a second control word that appear alternately.
  • Both the first control word and the second control word can be integers or decimals, so each value can be divided into integers. Part and decimal part. For example, if the first control word is 5.4, the integer part is 5 and the decimal part is 0.4. For another example, if the second control word is 6, the integer part is 6 and the decimal part is 0.
  • the first frequency signal consists of only a periodic signal of T A ; when the fractional part in the second control word is 0, the second frequency signal consists of only T C Periodic signal composition.
  • FIG 8 is a schematic diagram of the principle of clock signal synthesis using a TAF-DPS frequency synthesizer.
  • the TAF-DPS frequency synthesizer uses the concept of time average frequency to synthesize the output clock signal.
  • the following takes the synthesis of the first frequency signal as an example for description: the TAF-DPS frequency synthesizer receives K signals with uniform phase intervals and the first control word respectively.
  • the first control word F I+r, where I is an integer part and r is a decimal part; the phase difference between any two adjacent signals in the K signals with uniform phase intervals is the basic time unit ⁇ .
  • the first frequency signal may include two parts of the clock cycle T A and T B.
  • the TAF-DPS frequency synthesizer can generate any frequency.
  • the output first frequency signal can be changed immediately.
  • the TAF-DPS frequency synthesizer realizes the output of the clock signal by alternately generating the first frequency signal and the second frequency signal.
  • Fig. 9 is a schematic structural diagram of a TAF-DPS frequency synthesizer provided by the present disclosure.
  • the TAF-DPS frequency synthesizer may include a first input module, a second input module 23 and an output module 24.
  • the first input module includes a first logic control circuit 21 and a second logic control circuit 22.
  • the second input module 23 includes a first K ⁇ 1 multiplexer 231, a second K ⁇ 1 multiplexer 232, and a 2 ⁇ 1 multiplexer 233.
  • the first K ⁇ 1 multiplexer 231 and the second K ⁇ 1 multiplexer 232 respectively include a plurality of input terminals, a control input terminal, and an output terminal for receiving K signals with evenly spaced phases.
  • the 2 ⁇ 1 multiplexer 233 includes a control input terminal, an output terminal, a first input terminal for receiving the output of the first K ⁇ 1 multiplexer 231, and a first input terminal for receiving the second K ⁇ 1 multiplexer.
  • the second input terminal of the output of the user 232 includes a control input terminal, an output terminal, a first input terminal for receiving the output of the first K ⁇ 1 multiplexer 231, and a first input terminal for receiving the second K ⁇ 1 multiplexer.
  • the control input of the first K ⁇ 1 multiplexer 231 is controlled by the first logic control circuit 21 to select output signals from K signals with evenly spaced phases, and the second K ⁇ 1 multiplexer 232 Under the control of the second logic control circuit 22, the control input terminal selects an output signal from K signals with evenly spaced phases.
  • the 2 ⁇ 1 multiplexer 233 can select the first output signal from the first K ⁇ 1 multiplexer 231 and the second K ⁇ 1 multiplexer at the rising edge of the first clock signal CLK1 One of the second output signals of the converter 232 is used as the output signal of the 2 ⁇ 1 multiplexer 233.
  • the first logic control circuit 21 includes a first adder 211, a first register 212 and a second register 213.
  • the second logic control circuit 22 includes a second adder 221, a third register 222, and a fourth register 223.
  • the first adder 211 may add the first control word F and the most significant bits (for example, 5 bits) stored in the first register 212, and then add the result at the rising edge of the second clock signal CLK2 Save to the first register 212; or, the first adder 211 may add the first control word F and all the information stored in the first register 212, and then save the addition result at the rising edge of the second clock signal CLK2 To the first register 212.
  • the most significant bit stored in the first register 212 will be stored in the second register 213 and used as the selection signal of the first K ⁇ 1 multiplexer 231
  • One signal is selected from K multiphase input signals as the first output signal of the first K ⁇ 1 multiplexer 231.
  • the second adder 221 may add half F/2 of the first control word and the most significant bit stored in the first register 212, and then save the addition result to the third register 222 at the rising edge of the second clock signal CLK2 in. At the next rising edge of the first clock signal CLK1, the information stored in the third register 222 will be stored in the fourth register 223 and used as the selection signal of the second K ⁇ 1 multiplexer 223 for slave K One of the two multi-phase input signals is selected as the second output signal of the second K ⁇ 1 multiplexer 223.
  • the output module 24 includes a trigger circuit.
  • the trigger circuit is used to generate pulse trains.
  • the trigger circuit includes a D flip-flop 241, a first inverter 242, and a second inverter 243.
  • the D flip-flop 241 includes a data input terminal, a clock input terminal for receiving the output from the output terminal of the 2 ⁇ 1 multiplexer 233, and an output terminal for outputting the first clock signal CLK1.
  • the first inverter 242 includes an input terminal for receiving the first clock signal CLK1 and an output terminal for outputting a signal to the data input terminal of the D flip-flop 241.
  • the second inverter 243 includes an input terminal for receiving the first clock signal CLK1 and an output terminal for outputting the second clock signal CLK2.
  • the output terminal of the trigger circuit or the output terminal of the second inverter 243 can be used as the output terminal of the TAF-DPS frequency synthesizer, that is, to generate a clock signal.
  • the first clock signal CLK1 is connected to the control input terminal of the 2 ⁇ 1 multiplexer 233, and the output terminal of the first inverter 242 is connected to the data input terminal of the D flip-flop 241.
  • the optical communication drive circuit may further include a filter connected between the output terminal of the clock circuit 200 and the input terminal of the modulation circuit 300.
  • the filter is configured to filter the clock signal output by the clock circuit 200 and then input it into the modulation circuit 300.
  • FIG. 10 shows a schematic structural diagram of an optical communication transmitting end provided by an embodiment of the present disclosure.
  • the optical communication transmitting end includes a light emitting unit 100 and an optical communication driving circuit 101 as shown in FIG. 3.
  • the optical communication driving circuit 101 is configured to modulate the optical signal generated by the light emitting unit 100 to obtain a modulated optical signal.
  • FIG. 11 shows a schematic structural diagram of an optical communication system provided by an embodiment of the present disclosure.
  • the system includes a transmitting end 10 and a receiving end 20, and the transmitting end 10 is an optical communication transmitting end as shown in FIG.
  • the receiving end 20 includes a photodetector 200 and a demodulator 201, and the output end of the photodetector 200 is connected to the input end of the demodulator 201.
  • the photodetector 200 is configured to receive optical signals and convert the optical signals into electrical signals;
  • the demodulator 201 is configured to demodulate data information from the electrical signals, that is, the information to be sent at the transmitting end.
  • the receiving terminal 20 may also include an amplifier, which is connected between the output terminal of the photodetector and the input terminal of the modulation circuit.
  • the amplifier is configured to amplify the electrical signal output by the photodetector, so that the electrical signal input to the demodulator is large enough to accurately demodulate the data information.
  • the photodetector 200 may be a photodiode, such as an avalanche photodiode (APD).
  • APD avalanche photodiode
  • the demodulator when the demodulator demodulates, the same communication mode as the transmitting end is used to demodulate the signal.
  • the sending end uses the first communication mode selection control word to generate a clock signal, and then uses the clock signal for optical modulation, then correspondingly, the demodulator also needs to work in the first communication mode, according to the waveform and the waveform in the communication mode.
  • the relationship between the data bits is demodulated to obtain data information (that is, the aforementioned information to be sent).
  • the relationship between the waveform and the data bit in each communication mode may be stored in the demodulator in advance.
  • the input end of the sending end 10 is electrically connected to the output end of the trip computer 00, and the output end of the receiving end 20 is electrically connected to the input end of the trip computer 00.
  • the trip computer 00 sends the information to be sent to the sending end 10, and the sending end 10 sends the information to be sent to the trip computer 00 connected to the receiving end 20 through an optical signal.
  • the two trip computers 00 in Fig. 11 are respectively located on different vehicles.
  • At least one embodiment of the present disclosure provides a vehicle.
  • the vehicle includes an optical communication transmitter as shown in FIG. 10.
  • the information to be sent received by the optical communication transmitter can be provided by a control computer in the vehicle (such as a trip computer).
  • the vehicle further includes a receiving end.
  • the receiving end may be the receiving end in the optical communication system as shown in FIG. 10, which is used to receive optical signals and convert the optical signals into electrical signals. Demodulate data information from electrical signals. The data information demodulated by the receiving end can be output to the control computer in the vehicle.
  • the optical communication transmitting end and receiving end may be arranged at the head or tail of the vehicle.
  • the sender and receiver of optical communication can be set on the head of the car at the same time to communicate with other cars through the sender and receiver of the car head.
  • the sender and receiver of optical communication can also be set at the rear of the car to communicate with other cars through the sender and receiver of the rear of the car.
  • the transmitting end and receiving end of the optical communication can also be arranged on other parts of the car, which is not limited in the present disclosure.
  • the vehicle can have the following two communication methods, which will be described below with reference to FIGS. 12 and 13.
  • Fig. 12 shows a schematic diagram of communication between vehicles provided by an embodiment of the present disclosure. Referring to FIG. 12, when two vehicles are driving toward each other (meeting cars), both vehicles perform optical communication with each other through the sending end and the receiving end set on the head.
  • FIG. 13 shows another schematic diagram of communication between vehicles provided by an embodiment of the present disclosure.
  • the vehicle located at the rear performs optical communication with the vehicle located in the front through the transmitting end and receiving end located at the head through the transmitting end and receiving end located at the rear.
  • the aforementioned vehicles include but are not limited to automobiles, and may also be other vehicles such as airplanes and trains.
  • FIG. 14 shows a flowchart of an optical communication driving method provided by an embodiment of the present disclosure. The method can be executed by the optical communication driving circuit shown in FIG. 3. Referring to FIG. 14, the steps of the method include:
  • Step 301 Take an initial frequency signal as input, and output a clock signal under the control of the information to be sent.
  • the clock signal includes a first frequency signal and a second frequency signal that alternately appear, and the first frequency signal and the second frequency signal have different frequencies and are generated based on the initial frequency signal.
  • the initial frequency signal can be generated by using a voltage-controlled oscillator, for example, an inductor-capacitor voltage-controlled oscillator (LCVCO) is used as a vibration source to generate the aforementioned initial frequency signal.
  • a voltage-controlled oscillator for example, an inductor-capacitor voltage-controlled oscillator (LCVCO) is used as a vibration source to generate the aforementioned initial frequency signal.
  • LCVCO inductor-capacitor voltage-controlled oscillator
  • This step 301 may be performed by the clock circuit in the optical communication driving circuit shown in FIG. 3.
  • Step 302 Use a clock signal to modulate the optical signal to obtain a modulated optical signal.
  • the optical signal may be a laser generated by a laser.
  • the laser has the advantages of good monochromaticity and high brightness, and is very suitable as a light source for optical communication.
  • using the clock signal to modulate the optical signal is to modulate the laser generated by the laser to obtain the modulated laser signal.
  • the switching of the laser can be controlled by the high and low level of the clock signal to generate a laser pulse signal, which is the aforementioned modulated laser signal, and carries the aforementioned information to be sent.
  • This step 302 may be performed by the modulation circuit in the optical communication driving circuit shown in FIG. 3.
  • the generated clock signal includes a first frequency signal and a second frequency signal that alternately appear.
  • the first frequency signal and the second frequency signal have different frequencies, they are both generated based on the initial frequency signal. , That is to say, using an initial frequency signal as the input, and at the same time controlling with the information to be sent, the clock signal can be output.
  • the clock signal When generating the clock signal, since only one initial frequency signal is used as the input, and then the first frequency signal and the second frequency signal are alternately generated through the control of the information to be sent, there is no need to invert the analog signal of the information to be sent and pass
  • the analog signal of the information to be sent and the inverted signal are used to select the waveform of the two frequency signals to generate a clock signal, which avoids the process of inverting the analog signal of the information to be sent and selecting the waveform through the inverted signal.
  • the output delay avoids bit errors caused by output delay and improves the communication quality.
  • the clock signal generated by the solution provided by the present disclosure does not have the aforementioned delay, a smaller time period can be used to represent the bits in the information to be sent, which can increase the data transmission rate.
  • FIG. 15 shows a flowchart of an optical communication driving method provided by an embodiment of the present disclosure. The method can be executed by the optical communication driving circuit shown in FIG. 3. Referring to FIG. 15, the steps of the method include:
  • Step 401 Generate a control word sequence according to the information to be sent, and the control word sequence includes a first control word and a second control word that appear alternately.
  • a control word sequence is generated according to the information to be sent, and the control word sequence includes a first control word and a second control word that appear alternately, including: based on the correspondence between bits and control words, according to The order of the bits in the information to be sent selects the control words corresponding to each bit in the information to be sent in order to obtain the control word sequence.
  • a preset control word is selected, so that the clock circuit can output a clock signal corresponding to the control word and a frequency that meets the communication requirements.
  • control word sequence further includes: selecting the correspondence between the corresponding bit and the control word according to the communication mode, and the correspondence between the bit and the control word is at least partially different in different communication modes.
  • the optical communication can be selected in the private communication mode or the open communication mode through clock signals of different frequencies.
  • Step 402 Obtain a first frequency signal based on the frequency of the initial frequency signal and the first control word, and obtain a second frequency signal based on the frequency of the initial frequency signal and the second control word.
  • the clock signal includes a first frequency signal and a second frequency signal that alternately appear, and the first frequency signal and the second frequency signal have different frequencies and are generated based on the initial frequency signal.
  • the frequency of the first frequency signal in the clock signal is equal to the frequency of the initial frequency signal divided by the first control word
  • the frequency of the second frequency signal in the clock signal is equal to the frequency of the initial frequency signal divided by the second control word.
  • the initial frequency signal can be generated by using a voltage-controlled oscillator, for example, an inductor-capacitor voltage-controlled oscillator (LCVCO) is used as a vibration source to generate the aforementioned initial frequency signal.
  • a voltage-controlled oscillator for example, an inductor-capacitor voltage-controlled oscillator (LCVCO) is used as a vibration source to generate the aforementioned initial frequency signal.
  • LCVCO inductor-capacitor voltage-controlled oscillator
  • steps 401 and 402 an initial frequency signal is used as input, and a clock signal is output under the control of the information to be sent.
  • the steps 401 and 402 can be executed by the clock circuit in the optical communication driving circuit shown in FIG. 3.
  • the frequency of the clock signal generated here is equal to the frequency of the initial frequency signal divided by the control word, the generation of a clock signal of any frequency can be achieved through the control control word.
  • the frequency of the clock signal is fixed.
  • the present disclosure enriches the diversity of the clock signal.
  • the control word sequence includes the first control word and the second control word that appear alternately.
  • the frequency of the clock signal is equal to the frequency of the initial frequency signal divided by the control word. Therefore, the output clock signal includes the first frequency signal and the second control word alternately. Frequency signal.
  • obtaining the first frequency signal based on the frequency of the initial frequency signal and the first control word, and obtaining the second frequency signal based on the frequency of the initial frequency signal and the second control word includes:
  • the frequency signal generates K uniformly spaced signals, where K is an integer greater than 2.
  • the first frequency signal is generated based on K uniformly spaced signals and the first control word, and the first frequency signal is generated based on K uniformly spaced signals and the second control word.
  • the clock circuit is composed of two parts. Among them, the frequency divider is responsible for generating K uniformly spaced signals based on the frequency signal, and the frequency synthesizer is responsible for generating K uniformly spaced signals and control words based on the frequency signal. Clock signal.
  • the first frequency signal is generated based on K signals with evenly spaced phases and the first control word
  • the second frequency signal is generated based on K signals with evenly spaced phases and the second control word
  • the signal and the second control word generate a third periodic signal and a fourth periodic signal, and a second frequency signal is generated based on the third periodic signal and the fourth periodic signal.
  • the first periodic signal and the second periodic signal are generated based on the K signals with evenly spaced phases and the first control word, and the first periodic signal and the second periodic signal are generated based on the K signals with evenly spaced phases and the second control word.
  • the third periodic signal and the fourth periodic signal including:
  • T A I* ⁇
  • T B (I+1)* ⁇
  • T C J* ⁇
  • T D (J+1)* ⁇
  • ⁇ is any two of the K signals with evenly spaced phases the phase difference between adjacent signals
  • I is the integer part of the first control words
  • J is the integer part of the second control word
  • T a is a first period signal
  • T C is The third periodic signal
  • T D is the fourth periodic signal.
  • generating the first frequency signal based on the first periodic signal and the second periodic signal, and generating the second frequency signal based on the third periodic signal and the fourth periodic signal includes:
  • T TAF1 (1-r)*T A +r*T B
  • T TAF2 (1-s)*T C +s*T D ,
  • T TAF1 is the period of the first frequency signal
  • r is the fractional part in the first control word
  • TAF2 is the period of the second frequency signal
  • s is the fractional part in the second control word, 0 ⁇ s ⁇ 1.
  • Step 403 Use a clock signal to modulate the optical signal to obtain a modulated optical signal.
  • the optical signal may be a laser generated by a laser.
  • the laser has the advantages of good monochromaticity and high brightness, and is very suitable as a light source for optical communication.
  • using the clock signal to modulate the optical signal is to modulate the laser generated by the laser to obtain the modulated laser signal.
  • the on-off of the laser can be controlled by the high and low levels of the clock signal to generate a laser pulse signal, which is the aforementioned modulated laser signal, and carries the aforementioned information to be sent.
  • This step 403 may be performed by the modulation circuit in the optical communication driving circuit shown in FIG. 3.

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Abstract

提供了一种光通信驱动电路及方法、光通信发送端、系统、交通工具。该光通信驱动电路包括时钟电路和调制电路。时钟电路，被配置为以一路初始频率信号为输入，在待发送信息的控制下输出时钟信号，所述时钟信号包括交替出现的第一频率信号和第二频率信号，所述第一频率信号和所述第二频率信号具有不同的频率且基于所述初始频率信号生成；调制电路，被配置为采用所述时钟信号对光信号进行调制，得到调制光信号。

Description

光通信驱动电路及方法、光通信发送端、系统、交通工具 技术领域
本公开涉及一种光通信驱动电路及方法、光通信发送端、系统、交通工具。
背景技术
汽车技术这几年发展迅速，无人驾驶汽车更是当下的热点。要实现汽车的无人驾驶，首先要解决的就是汽车之间的通信问题。
光通信是汽车之间通信的一种重要方式，而对光信号的调制是光通信的重点。光信号的调制过程包括将待发送信息转换成时钟信号，然后采用时钟信号调制光信号，以使得在光信号中携带有待发送信息的内容。
发明内容
本公开实施例提供了一种光通信驱动电路及方法、光通信发送端、系统、交通工具。
本公开至少一实施例提供了一种光通信驱动电路，包括：时钟电路，被配置为以一路初始频率信号为输入，在待发送信息的控制下输出时钟信号，所述时钟信号包括交替出现的第一频率信号和第二频率信号，所述第一频率信号和所述第二频率信号具有不同的频率且基于所述初始频率信号生成；调制电路，被配置为采用所述时钟电路输出的时钟信号对光信号进行调制，得到调制光信号。
在本公开实施例的一种实现方式中，所述时钟电路，包括：控制子电路，被配置为根据所述待发送信息产生控制字序列，所述控制字序列包括交替出现的第一控制字和第二控制字；处理子电路，被配置为基于所述初始频率信号的频率和所述控制子电路产生的所述控制字序列中的第一控制字得到所述第一频率信号，基于所述初始频率信号的频率和所述控制子电路产生的所述控制字序列中的第二控制字得到所述第二频率信号。
在本公开实施例的一种实现方式中，所述控制子电路，被配置为基于比特与控制字的对应关系，按照所述待发送信息中比特的顺序依次选取与所述待发 送信息中各个比特对应的控制字，得到所述控制字序列。
在本公开实施例的一种实现方式中，所述控制子电路，被配置为按照通信模式选择相应的比特与控制字的对应关系，在不同的所述通信模式下，所述比特与控制字的对应关系至少部分不相同。
在本公开实施例的一种实现方式中，所述处理子电路，包括：分频器，被配置为根据所述初始频率信号产生K个相位均匀间隔的信号，K为大于2的整数；频率合成器，被配置为基于所述分频器产生的K个相位均匀间隔的信号和所述第一控制字产生所述第一频率信号，基于所述K个相位均匀间隔的信号和所述第二控制字产生所述第二频率信号。
在本公开实施例的一种实现方式中，所述频率合成器，被配置为基于所述K个相位均匀间隔的信号和所述第一控制字，生成第一周期信号和第二周期信号，并基于所述第一周期信号和所述第二周期信号生成所述第一频率信号；基于所述K个相位均匀间隔的信号和所述第二控制字，生成第三周期信号和第四周期信号，并基于所述第三周期信号和所述第四周期信号生成所述第二频率信号。
在本公开实施例的一种实现方式中，所述频率合成器，被配置为按照如下公式生成所述第一周期信号、所述第二周期信号、所述第三周期信号和所述第四周期信号：T A＝I*Δ，T B＝(I+1)*Δ，T C＝J*Δ，T D＝(J+1)*Δ，所述Δ为K个相位均匀间隔的信号中的任意两个相邻信号之间的相位差，I为所述第一控制字中的整数部分，J为所述第二控制字中的整数部分，T A为所述第一周期信号，T B为所述第二周期信号，T C为所述第三周期信号，T D为所述第四周期信号。
在本公开实施例的一种实现方式中，所述频率合成器，被配置为按照如下公式生成所述第一频率信号和所述第二频率信号：T TAF1＝(1-r)*T A+r*T B，T TAF2＝(1-s)*T C+s*T D，其中，T TAF1为所述第一频率信号的周期，r为所述第一控制字中的小数部分，0≤r<1，T TAF2为所述第二频率信号的周期，s为所述第二控制字中的小数部分，0≤s<1。
本公开至少一实施例提供了光通信发送端，所述光通信发送端包括发光单元和如前任一项所述光通信驱动电路，所述光通信驱动电路被配置为对所述发光单元产生的光信号进行调制，得到调制光信号。
本公开至少一实施例提供了一种光通信系统，所述系统包括发送端和接收端，所述发送端为如前任一项所述光通信发送端。
本公开至少一实施例提供了一种交通工具，所述交通工具包括如前任一项 所述光通信发送端。
本公开至少一实施例提供了一种光通信驱动方法，包括：以一路初始频率信号为输入，在待发送信息的控制下输出时钟信号，所述时钟信号包括交替出现的第一频率信号和第二频率信号，所述第一频率信号和所述第二频率信号具有不同的频率且基于所述初始频率信号生成；采用所述时钟信号对光信号进行调制，得到调制光信号。
在本公开实施例的一种实现方式中，所述以一路初始频率信号为输入，在待发送信息的控制下输出时钟信号，包括：根据所述待发送信息产生控制字序列，所述控制字序列包括交替出现的第一控制字和第二控制字；基于所述初始频率信号的频率和所述第一控制字得到所述第一频率信号，基于所述初始频率信号的频率和所述第二控制字得到所述第二频率信号。
在本公开实施例的一种实现方式中，所述根据所述待发送信息产生控制字，包括：基于比特与控制字的对应关系，按照所述待发送信息中比特的顺序依次选取与所述待发送信息中各个比特对应的控制字，得到所述控制字序列。
在本公开实施例的一种实现方式中，在所述基于比特与控制字的对应关系，按照所述待发送信息中比特的顺序依次选取与所述待发送信息中各个比特对应的控制字之前，所述根据所述待发送信息产生控制字序列，还包括：按照通信模式选择相应的比特与控制字的对应关系，在不同的所述通信模式下，所述比特与控制字的对应关系至少部分不相同。
在本公开实施例的一种实现方式中，所述基于所述初始频率信号的频率和所述第一控制字得到所述第一频率信号，基于所述初始频率信号的频率和所述第二控制字得到所述第二频率信号，包括：根据所述初始频率信号产生K个相位均匀间隔的信号，K为大于2的整数；基于所述K个相位均匀间隔的信号和所述第一控制字产生所述第一频率信号，基于所述K个相位均匀间隔的信号和所述第二控制字产生所述第二频率信号。
在本公开实施例的一种实现方式中，所述基于所述K个相位均匀间隔的信号和所述第一控制字产生所述第一频率信号，基于所述K个相位均匀间隔的信号和所述第二控制字产生所述第二频率信号，包括：基于所述K个相位均匀间隔的信号和所述第一控制字，生成第一周期信号和第二周期信号，并基于所述第一周期信号和所述第二周期信号生成所述第一频率信号；基于所述K个相位均匀间隔的信号和所述第二控制字，生成第三周期信号和第四周期信号，并基 于所述第三周期信号和所述第四周期信号生成所述第二频率信号。
在本公开实施例的一种实现方式中，所述基于所述K个相位均匀间隔的信号和所述第一控制字，生成第一周期信号和第二周期信号，基于所述K个相位均匀间隔的信号和所述第二控制字，生成第三周期信号和第四周期信号，包括：按照如下公式生成所述第一周期信号、所述第二周期信号、所述第三周期信号和所述第四周期信号：T A＝I*Δ，T B＝(I+1)*Δ，T C＝J*Δ，T D＝(J+1)*Δ，所述Δ为K个相位均匀间隔的信号中的任意两个相邻信号之间的相位差，I为所述第一控制字中的整数部分，J为所述第二控制字中的整数部分，T A为所述第一周期信号，T B为所述第二周期信号，T C为所述第三周期信号，T D为所述第四周期信号。
在本公开实施例的一种实现方式中，所述基于所述第一周期信号和所述第二周期信号生成所述第一频率信号，基于所述第三周期信号和所述第四周期信号生成所述第二频率信号，包括：按照如下公式生成所述第一频率信号和所述第二频率信号：T TAF1＝(1-r)*T A+r*T B，T TAF2＝(1-s)*T C+s*T D，其中，T TAF1为所述第一频率信号的周期，r为所述第一控制字中的小数部分，0≤r<1，T TAF2为所述第二频率信号的周期，s为所述第二控制字中的小数部分，0≤s<1。
附图说明
图1为常规技术中FSK的硬件实现示意图；
图2为采用图1所示的FSK硬件结构产生的时钟信号的波形图；
图3示出了本公开实施例提供的一种光通信驱动电路的结构示意图；
图4为采用图3中的时钟电路产生的时钟信号的波形图；
图5示出了本公开实施例提供的一种时钟电路的结构示意图
图6示出了本公开实施例提供的一种处理子电路的结构示意图；
图7为采用图6中的分频器产生的K个相位均匀间隔的信号的波形图；
图8为采用TAF-DPS频率合成器进行时钟信号合成的原理示意图；
图9为本公开提供的一种TAF-DPS频率合成器的结构示意图；
图10示出了本公开实施例提供的一种光通信发送端的结构示意图；
图11示出了本公开实施例提供的一种光通信系统的结构示意图；
图12示出了本公开实施例提供的一种交通工具间通信的示意图；
图13示出了本公开实施例提供的另一种交通工具间通信的示意图；
图14示出了本公开实施例提供的一种光通信驱动方法的流程图；
图15示出了本公开实施例提供的一种光通信驱动方法的流程图。
具体实施方式
为使本公开的原理和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
二进制频移键控(Frequency-shift keying，FSK)技术能够实现前述将待发送信息转换成时钟信号的过程，且产生的时钟信号的抗噪声与抗衰减的性能较好。在FSK技术中，待发送信息的比特0和1分别采用两个频率不同的频率信号中相应周期的波形进行表示。例如比特0选择第一频率信号中2个周期的波形表示，比特1选择第二频率信号中的3个周期的波形表示，从而通过采用不同周期数、不同频率的波形来分别代表比特0和1。需要说明的是，这里的第一频率信号中2个周期的波形和第二频率信号中的3个周期的波形占用的时间周期相等，这样接收端能够准确解调出待发送信息。
图1为常规技术中FSK的硬件实现示意图。参见图1，FSK通过将两路频率信号f 1、f 2分别送入两个门电路11、12的输入端，通过待发送信息的模拟信号{a k}以及该模拟信号倒相后的信号{a k’}来分别控制两个门电路11、12进行波形选择，然后将两个门电路11、12的输出通过加法器13相加，得到输出信号e t，也即时钟信号。前述频率信号是指周期性的高低电平信号。
上述过程中，两路频率信号f 1、f 2中有一路信号f 2需要通过待发送信息的模拟信号倒相后的信号{a k’}来控制，导致该路门电路12的输出相对于另一路门电路11的输出存在延迟，容易造成一个时间周期内的波形数量出现误差，最终导致接收端无法正确解调出数据信息，造成通信误码。前述时间周期为预定长度的一段时间。
图2为采用图1所示的FSK硬件结构产生的时钟信号的波形图。参见图2，比特0对应图中的虚线部分，比特1对应图中的实线部分，可以看出实线部分和虚线部分之间存在明显延迟，即图2中Δt所示出的部分，该延迟造成一个时间周期内的波形数量可能出现误差。
图3示出了本公开实施例提供的一种光通信驱动电路的结构示意图。参见图3，该光通信驱动电路应用于光通信发送端，包括时钟电路200和调制电路 300。时钟电路200的输入端的输入为一路初始频率信号，时钟电路200的控制端的输入为待发送信息对应的模拟信号，时钟电路200的输出端连接调制电路300的输入端，调制电路300的输出端连接光通信发送端中的发光单元100的控制端。
时钟电路200被配置为以一路初始频率信号为输入，在待发送信息的控制下输出时钟信号，时钟信号包括交替出现的第一频率信号和第二频率信号，第一频率信号和第二频率信号具有不同的频率且基于初始频率信号生成。调制电路300被配置为采用时钟电路200输出的时钟信号对光信号进行调制操作。该光信号由发光单元100产生，通过对光信号进行调制，得到调制光信号，例如光脉冲信号。
在该光通信驱动电路中，采用时钟电路产生时钟信号，所产生的时钟信号包括交替出现的第一频率信号和第二频率信号，第一频率信号和第二频率信号虽然具有不同的频率，但都是基于初始频率信号生成的，也就是说该时钟电路采用一路初始频率信号作为输入，同时配合待发送信息进行控制，即可输出时钟信号。在该时钟电路产生时钟信号时，由于只采用一路初始频率信号作为输入，然后通过待发送信息的控制交替产生第一频率信号和第二频率信号，所以无需进行待发送信息的模拟信号倒相，并通过待发送信息的模拟信号和倒相后的信号来对两路频率信号进行波形选择产生时钟信号，避免了由于进行待发送信息的模拟信号倒相、通过倒相后的信号进行波形选择等过程造成的输出延迟，避免了由于输出延迟带来的误码，提高了通信质量。另外，由于本公开提供的方案产生的时钟信号没有上述延迟，因此可以采用更小的时间周期来表示待发送信息中的比特，可以提高数据传输速率。
示例性地，参见图3，时钟电路200采用初始频率信号f i作为输入信号，在待发送信息的模拟信号{a k}的控制下，输出时钟信号e t。
可选地，初始频率信号可以采用压控振荡器产生，例如采用电感电容压控振荡器(LC Voltage Controlled Oscillator，LCVCO)作为振源产生上述初始频率信号。也即，该光通信驱动电路还可以包括压控振荡器，压控振荡器的输出端与时钟电路200的输入端电连接。
待发送信息可以由配置光通信发送端的设备产生，例如该光通信发送端为汽车上的光通信发送端时，则该待发送信息可以由汽车的行车电脑产生，汽车的行车电脑产生的待发送信息可以为一模拟信号，可以直接输出给时钟电路 200。
在本实施例中，时钟信号是以初始频率信号作为基准生成的，也即，在本公开实施例中，时钟信号中对应待发送信息中比特0的部分(第一频率信号)的频率是与初始频率信号的频率成比例的，时钟信号中对应待发送信息中比特1的部分(第二频率信号)的频率也是与初始频率信号的频率成比例的，且第一频率信号的频率和第二频率信号的频率与初始频率信号的频率所成的比例不同。这一点，与常规技术中时钟信号中对应待发送信息中比特0的部分的频率和比特1的部分的频率分别与两路频率信号的频率成比例不同。这里，成比例是指将时钟信号的频率乘以一个数值即可得到第一频率信号或第二频率信号，且该数值为整数或有限小数。
示例性地，发光单元100可以为激光器，激光器产生的激光具有单色性好、亮度高等优点，非常适合作为光通信的光源。
相应地，调制电路300则为激光调制器，用以对激光器产生的激光进行调制，得到调制激光信号。激光调制器可以通过时钟信号的高低电平来控制激光的通断，从而产生激光脉冲信号，该激光脉冲信号也即前述调制激光信号，携带有前述待发送信息。
图4为采用图3中的时钟电路产生的时钟信号的波形图。参见图4，比特0对应图中的虚线部分，比特1对应图中的实线部分，可以看出实线部分和虚线部分之间不存在延迟，进而避免了由于延迟带来的误码。另外，在图4和图2提供的波形图中，表示比特1的信号的频率均为f1，表示比特0的信号的频率均为f2，可以看出在图2中，比特1用3个周期的f1波形表示，比特0用2个周期的f2波形表示；而在图4中，比特1用2个周期的f1波形表示，比特0用1个周期的f2波形表示，故采用图3中的时钟电路产生的时钟信号在表示待发送信息中的单个比特时，所占的时间周期更小，那么在传输相同数据量的情况下，传输时间变短。也即本公开提供的光通信驱动电路可以让传输的时间变短，也即传输带宽变宽。
图5示出了本公开实施例提供的一种时钟电路的结构示意图。参见图5，时钟电路200可以包括：
控制子电路201被配置为根据待发送信息产生控制字序列，控制字序列包括交替出现的第一控制字和第二控制字；
处理子电路202被配置为基于初始频率信号的频率和控制子电路201产生 的控制字序列中的第一控制字得到第一频率信号，基于初始频率信号的频率和控制子电路201产生的控制字序列中的第二控制字得到第二频率信号。
示例性地，处理子电路202被配置为输出频率等于初始频率信号的频率除以控制字的时钟信号，时钟信号中的第一频率信号的频率等于初始频率信号的频率除以第一控制字，时钟信号中的第二频率信号的频率等于初始频率信号的频率除以第二控制字。
这里，控制字序列是指用来控制时钟信号的频率的一路信号，控制字序列根据待发送信息产生，这样，在接收端可以通过解调接收到的信号还原出待发送信息。
由于时钟电路产生的时钟信号的频率等于初始频率信号的频率除以控制字，所以可以通过控制控制字来实现任意频率的时钟信号的产生。而现有技术中，时钟信号的频率是固定的，本公开相比现有技术丰富了时钟信号的多样性。另外，控制字序列包括交替出现的第一控制字和第二控制字，时钟信号的频率等于初始频率信号的频率除以控制字，因此处理子电路202输出的时钟信号包括交替出现的第一频率信号和第二频率信号。
根据前文可知，待发送信息为一串二进制比特流，包含的都是二进制数比特0和比特1，所以如果直接采用待发送信息进行时钟信号的频率的控制，那么只能产生与比特0和1对应的两个频率，这两个频率是固定的。而采用了上述控制字后，可以将比特0和1映射到不同的控制字，也即不同的控制字序列中的第一控制字可以不同，不同的控制字序列中的第二控制字也可以不同，通过不同的控制字来选择不同的频率，实现不同频率的时钟信号的输出。
例如，时钟电路200输出的时钟信号的频率为f o，初始频率信号的频率为f i，控制字为F，则f o＝f i/F。根据上式可知，通过控制字可以精确地控制输出的时钟信号的频率。
在本公开实施例中，交替出现的第一控制字和第二控制字是对应于待发送信息中交替出现的比特0和比特1，这里的交替出现不限定于是一个0和一个1这样交替，可以是不限定数量的0和不限定数量的1交替，相应地，第一控制字和第二控制字也可以是不限定数量的第一控制字和不限定数量的第二控制字交替。例如，待发送信息为10011101，这里的0和1交替并没限定是1个0和1个1交替，也没有限定是一定数量的0和相同数量的1交替。
在本公开实施例的一种实现方式中，控制子电路201被配置为基于比特与 控制字的对应关系，按照待发送信息中比特的顺序依次选取与待发送信息中各个比特对应的控制字，得到控制字序列。
按照这种方式选取预先设定好的控制字，使得时钟电路能够输出与控制字对应的且符合通信需求的频率的时钟信号。并且，由于存在上述对应关系，使得待发送信息中相同的比特在时钟信号中对应同样的波形，以保证接收端的正确解调。
例如，在该比特与控制字的对应关系中，比特0对应第一数值(也即控制字序列中的第一控制字)，比特1对应第二数值(也即控制字序列中的第二控制字)。控制子电路201按照待发送信息中比特的顺序依次选取对应的数值作为控制字，控制时钟信号的输出。如待发送信息中比特为10010，则控制子电路201依次选取第二数值、第一数值、第一数值、第二数值、第一数值对处理子电路202进行周期性地控制，以控制处理子电路202的输出。
控制子电路201可以包括至少两个控制字寄存器，用于存储上述控制字。当控制子电路201接收到待发送信息时，可以根据相应比特从寄存器中读取对应的控制字。上述比特与控制字的对应关系可以包括比特与寄存器地址的映射关系，如比特0映射到存储第一数值的寄存器的地址，比特1映射到存储第二数值的寄存器的地址。
在本公开实施例的一种实现方式中，控制子电路201被配置为按照通信模式选择相应的比特与控制字的对应关系，在不同的通信模式下，比特与控制字的对应关系至少部分不相同。
将控制字和通信模式关联起来，这样在通信过程中可以通过选择不同的模式，产生不同频率的时钟信号与对端(接收端)通信，通信更加灵活。
在上述实现方式中，比特是指二进制数的一位包含的信息，例如比特0或比特1。
例如，该光通信发送端可以具有3种通信模式，其中第一通信模式对应第一种比特与控制字的对应关系，第二通信模式对应第二种比特与控制字的对应关系，第三通信模式对应第三种比特与控制字的对应关系。示例性地，在第一种比特与控制字的对应关系中，比特0对应第一数值，比特1对应第二数值；示例性地，在第二种比特与控制字的对应关系中，比特0对应第三数值，比特1对应第四数值；示例性地，在第三种比特与控制字的对应关系中，比特0对应第三数值，比特1对应第五数值。可以看出，在第一通信模式和第二通信模式 下，比特0对应的控制字不同，比特1对应的控制字也不同，也即在第一通信模式和第二通信模式中比特与控制字的对应关系完全不同；在第二通信模式和第三通信模式下，比特0对应的控制字相同，比特1对应的控制字不同，也即在第二通信模式和第三通信模式中比特与控制字的对应关系部分不同。
在该实现方式中，每种通信模式均对应一种比特与寄存器地址的映射关系，如在第一通信模式下，比特0映射到存储第一数值的寄存器的地址，比特1映射到存储第二数值的寄存器的地址；在第二通信模式下，比特0映射到存储第三数值的寄存器的地址，比特1映射到存储第四数值的寄存器的地址；在第三通信模式下，比特0映射到存储第三数值的寄存器的地址，比特1映射到存储第五数值的寄存器的地址。
在本公开实施例中，通信模式可以根据需要设置。例如，通信模式可以包括私密通信模式和开放通信模式。私密通信模式可以是在收发两端自定义设置而成的，只有收发两端能够同时用这种模式调制和解调数据信息；而开放通信模式可以是标准通信模式，任何发送端和接收端均可以采用该模式调制和解调数据信息。
需要说明的是，在光通信发送端采用上述通信模式中的一种进行信号调制时，相应地，接收端也要采用相同的通信模式进行信号的解调。例如，发送端采用第一通信模式选择控制字产生时钟信号，然后采用该时钟信号进行光调制，那么相应地，接收端也需要工作在第一通信模式下，按照该通信模式下的波形与数据比特的关系，解调得到数据信息(也即前述待发送信息)。
在发送端确定了各个比特对应的控制字，从而确定了各个比特对应的时钟信号中的波形的前提下，接收端接收到的信号的波形和比特之间的关系也是确定的。示例性地，可以将各个通信模式下的波形与数据比特的对应关系事先存储在接收端中，接收端在进行数据解调时，选择对应通信模式下的波形与数据比特的对应关系即可。
另外，在光通信过程中，发送端和接收端的通信模式可以通过协商决定，详细协商的方式本公开不做限定。
图6示出了本公开实施例提供的一种处理子电路的结构示意图。参见图6，处理子电路202包括分频器221和频率合成器222。分频器221的输入端的输入为一路初始频率信号，分频器221的输出端连接频率合成器222的输入端，频率合成器222的输出端连接调制电路300。
分频器221被配置为根据初始频率信号产生K个相位均匀间隔的信号，K为大于2的整数。频率合成器222被配置为基于分频器221产生的K个相位均匀间隔的信号和第一控制字产生第一频率信号，基于K个相位均匀间隔的信号和第二控制字产生第二频率信号，得到时钟信号。
在该实现方式中，处理子电路由2个部分组成，其中，分频器负责根据频率信号产生K个相位均匀间隔的信号，而频率合成器则负责根据K个相位均匀间隔的信号和控制字产生时钟信号。
图7为采用图6中的分频器产生的K个相位均匀间隔的信号的波形图。参见图7，任意两个信号的波形相同(即周期和幅度相同)，且K个信号的波形均匀排布，任意两个相邻的信号之间的相位差为基本时间单元Δ，K个信号的频率均为f i，K为大于1的整数。
在本公开实施例中，分频器221可以采用约翰逊计数器(Johnson Counter，或称扭环计数器)实现，以产生上述K个相位均匀间隔的信号。分频器221也可以采用环形行波振荡器(Rotary Traveling-Wave Oscillator，RTWO)实现，这是一种基于传输线的时钟生成技术，可以很方便的产生上述K个相位均匀间隔的信号。除此之外，分频器221还可以通过差分锁存器来实现，产生上述K个相位均匀间隔的信号。
在本公开实施例中，频率合成器222可以为时间平均频率(Time Average Frequency，TAF)直接周期合成(Direct Period Synthesis，DPS)频率合成器，这里TAF是指在一个固定的时间周期里，不同宽度的波形的数量，示例性地，在本公开实施例中，利用TAF技术在一个时间周期里采用波形数量来表示光信号携带的数据是0还是1，例如将待发送信息中的比特0和1分别映射为同一时间周期里的2个波形和3个波形。
在本公开实施例的一种实现方式中，频率合成器222被配置为基于K个相位均匀间隔的信号和第一控制字，生成第一周期信号和第二周期信号，并基于第一周期信号和第二周期信号生成第一频率信号；基于K个相位均匀间隔的信号和第二控制字，生成第三周期信号和第四周期信号，并基于第三周期信号和第四周期信号生成第二频率信号。
在本公开实施例的一种实现方式中，频率合成器222，被配置为按照如下公式生成第一周期信号、第二周期信号、第三周期信号和第四周期信号：T A＝I*Δ，T B＝(I+1)*Δ，T C＝J*Δ，T D＝(J+1)*Δ，Δ为K个相位均匀间隔的信号中 的任意两个相邻信号之间的相位差，I为第一控制字中的整数部分，J为第二控制字中的整数部分，T A为第一周期信号，T B为第二周期信号，T C为第三周期信号，T D为第四周期信号。
在本公开实施例中，控制字序列包括交替出现的第一控制字和第二控制字，第一控制字和第二控制字均可以为整数或小数，因此每个数值又可以拆分为整数部分和小数部分。例如，第一控制字为5.4，则整数部分为5，小数部分为0.4。再例如，第二控制字为6，则整数部分为6，小数部分为0。
在本公开实施例的一种实现方式中，频率合成器222，被配置为按照如下公式生成第一频率信号和第二频率信号：T TAF1＝(1-r)*T A+r*T B，T TAF2＝(1-s)*T C+s*T D，其中，T TAF1为第一频率信号的周期，r为第一控制字中的小数部分，0≤r<1，T TAF2为第二频率信号的周期，s为第二控制字中的小数部分，0≤s<1。
当第一控制字中的小数部分为0时，第一频率信号则只由T A一个周期信号构成；当第二控制字中的小数部分为0时，第二频率信号则只由T C一个周期信号构成。
图8为采用TAF-DPS频率合成器进行时钟信号合成的原理示意图。参见图8，该TAF-DPS频率合成器利用时间平均频率概念来合成输出时钟信号。下面以第一频率信号的合成为例进行说明：TAF-DPS频率合成器分别接收K个相位均匀间隔的信号和第一控制字。第一控制字F＝I+r，其中I是整数部分，r是小数部分；K个相位均匀间隔的信号中的任意两个相邻的信号之间的相位差为基本时间单元Δ。TAF-DPS频率合成器首先根据基本时间单元Δ和第一控制字F，构建两种不同的时钟周期T A和T B，T A＝I·Δ，T B＝(I+1)·Δ。之后，TAF-DPS频率合成器以两种时钟周期交错产生的方式生成第一频率信号，第一频率信号可以包括时钟周期T A和T B两部分。最终输出的第一频率信号的周期可以通过公式T TAF1＝(1-r)*T A+r*T B＝F*△算得，T A或者T B出现的概率由r的值来控制。假定用于产生r位数的硬件资源满足要求，那么该TAF-DPS频率合成器可以产生任何频率。此外，由于每个单独的脉冲都是直接生成的，所以输出第一频率信号可以立即改变。TAF-DPS频率合成器通过交替地生成第一频率信号和第二频率信号，实现时钟信号的输出。
图9为本公开提供的一种TAF-DPS频率合成器的结构示意图。参见图9，TAF-DPS频率合成器可以包括第一输入模块、第二输入模块23以及输出模块 24。第一输入模块包括第一逻辑控制电路21、第二逻辑控制电路22。
参考图9，第二输入模块23包括第一K→1多路复用器231、第二K→1多路复用器232和2→1多路复用器233。第一K→1多路复用器231和第二K→1多路复用器232分别包括用于接收K个相位均匀间隔的信号的多个输入端、控制输入端和输出端。2→1多路复用器233包括控制输入端、输出端、用于接收第一K→1多路复用器231的输出的第一输入端和用于接收第二K→1多路复用器232的输出的第二输入端。
第一K→1多路复用器231的控制输入端在第一逻辑控制电路21的控制下，从K个相位均匀间隔的信号中选择输出信号，第二K→1多路复用器232的控制输入端在第二逻辑控制电路22的控制下，从K个相位均匀间隔的信号中选择输出信号。
2→1多路复用器233可以在第一时钟信号CLK1的上升沿时，选择来自第一K→1多路复用器231的第一输出信号和来自第二K→1多路复用器232的第二输出信号中的一个，作为2→1多路复用器233的输出信号。
参考图9，第一逻辑控制电路21包括第一加法器211、第一寄存器212和第二寄存器213。第二逻辑控制电路22包括第二加法器221、第三寄存器222和第四寄存器223。
第一加法器211可以将第一控制字F和第一寄存器212存储的最高有效位(most significant bits，例如，5比特)相加，然后在第二时钟信号CLK2的上升沿时将相加结果保存到第一寄存器212中；或者，第一加法器211可以将第一控制字F和第一寄存器212存储的所有信息相加，然后在第二时钟信号CLK2的上升沿时将相加结果保存到第一寄存器212中。在下一个第二时钟信号CLK2的上升沿时，第一寄存器212存储的最高有效位将被存储到第二寄存器213中，并作为第一K→1多路复用器231的选择信号，用于从K个多相位输入信号中选择一个信号作为第一K→1多路复用器231的第一输出信号。
第二加法器221可以将第一控制字的一半F/2和第一寄存器212存储的最高有效位相加，然后在第二时钟信号CLK2的上升沿时将相加结果保存到第三寄存器222中。在下一个第一时钟信号CLK1的上升沿时，第三寄存器222存储的信息将被存储到第四寄存器223中，并作为第二K→1多路复用器223的选择信号，用于从K个多相位输入信号中选择一个信号作为第二K→1多路复用器223的第二输出信号。
参考图9，输出模块24包括触发电路。触发电路用于生成脉冲串。触发电路包括D触发器241、第一反相器242和第二反相器243。D触发器241包括数据输入端、用于接收来自2→1多路复用器233的输出端的输出的时钟输入端和用于输出第一时钟信号CLK1的输出端。第一反相器242包括用于接收第一时钟信号CLK1的输入端和用于输出信号到D触发器241的数据输入端的输出端。第二反相器243包括用于接收第一时钟信号CLK1的输入端和用于输出第二时钟信号CLK2的输出端。触发电路的输出端或第二反相器243的输出端可以作为TAF-DPS频率合成器的输出端，也即产生时钟信号。
第一时钟信号CLK1连接到2→1多路复用器233的控制输入端，第一反向器242的输出端连接到D触发器241的数据输入端。
可选地，该光通信驱动电路还可以包括滤波器，该滤波器连接在时钟电路200的输出端和调制电路300的输入端之间。该滤波器被配置为对时钟电路200输出的时钟信号进行滤波，然后输入到调制电路300中。
图10示出了本公开实施例提供的一种光通信发送端的结构示意图。参见图10，光通信发送端包括发光单元100和如图3所示的光通信驱动电路101，光通信驱动电路101被配置为对发光单元100产生的光信号进行调制，得到调制光信号。
图11示出了本公开实施例提供的一种光通信系统的结构示意图。参见图11，系统包括发送端10和接收端20，该发送端10为如图10所示的光通信发送端。
在本公开实施例中，接收端20包括光电探测器200和解调器201，光电探测器200的输出端连接解调器201的输入端。光电探测器200被配置为接收光信号，并将光信号转换为电信号；解调器201被配置为从电信号中解调出数据信息，也即发送端的待发送信息。
可选地，该接收端20还可以包括放大器，该放大器连接在光电探测器的输出端和调制电路的输入端之间。该放大器被配置为对光电探测器输出的电信号进行放大，使得输入到解调器中的电信号足够大，进而能够准确解调出数据信息。
在本公开实施例的一种实现方式中，光电探测器200可以为光电二极管，例如雪崩光电二极管(Avalanche Photo Diode，APD)。
在本公开实施例的一种实现方式中，解调器在解调时，要采用与发送端相同的通信模式进行信号的解调。例如，发送端采用第一通信模式选择控制字产生时钟信号，然后采用该时钟信号进行光调制，那么相应地，解调器也需要工作在第一通信模式下，按照该通信模式下的波形与数据比特的关系，解调得到数据信息(也即前述待发送信息)。示例性地，各个通信模式下的波形与数据比特的关系可以事先存储在解调器中。
当上述光通信系统应用在交通工具上时，如图11所示，发送端10的输入端与行车电脑00的输出端电连接，接收端20的输出端与行车电脑00的输入端电连接。行车电脑00向发送端10发送待发送信息，发送端10通过光信号将该待发送信息发送到接收端20连接的行车电脑00。图11中两个行车电脑00分别位于不同的交通工具上。
本公开至少一实施例提供了一种交通工具，交通工具包括如图10所示的光通信发送端。
在交通工具中，光通信发送端接收到的待发送信息可以由交通工具中的控制电脑(如行车电脑)提供。
在本公开实施例中，交通工具还包括一接收端，该接收端可以为如图10所示的光通信系统中的接收端，用于接收光信号，并将光信号转换为电信号，然后从电信号中解调出数据信息。接收端解调出的数据信息可以输出给交通工具中的控制电脑。
在本公开实施例中，该光通信发送端和接收端可以设置在交通工具的头部或尾部。
以汽车为例，在汽车的头部可以同时设置光通信的发送端和接收端，以通过汽车头部的发送端和接收端与其他汽车通信。在汽车的尾部也可以同时设置光通信的发送端和接收端，以通过汽车尾部的发送端和接收端与其他汽车通信。当然除了设置在头部和尾部外，光通信的发送端和接收端还可以设置在汽车的其他部位，本公开对此不做限制。
由于在交通工具的头部和尾部都可以设置光通信的发送端和接收端，因此，交通工具可以有如下两种通信方式，下面结合图12和图13对这两种通信方式进行说明。
图12示出了本公开实施例提供的一种交通工具间通信的示意图。参见图12， 两个交通工具相向行驶(会车)时，两个交通工具均通过设置在头部的发送端和接收端与对方进行光通信。
图13示出了本公开实施例提供的另一种交通工具间通信的示意图。参见图13，两个交通工具同向行驶时，位于后方的交通工具通过设置在头部的发送端和接收端与位于前方的交通工具通过设置在尾部的发送端和接收端进行光通信。
在本公开实施例中，前述交通工具包括但不限于汽车，还可以是飞机、火车等其他交通工具。
图14示出了本公开实施例提供的一种光通信驱动方法的流程图。该方法可以由图3所示的光通信驱动电路执行，参见图14，该方法的步骤包括：
步骤301：以一路初始频率信号为输入，在待发送信息的控制下输出时钟信号。
时钟信号包括交替出现的第一频率信号和第二频率信号，第一频率信号和第二频率信号具有不同的频率且基于初始频率信号生成。
在本公开实施例中，初始频率信号可以采用还可以使用压控振荡器产生，例如采用电感电容压控振荡器(LCVCO)作为振源产生上述初始频率信号。
该步骤301可以由图3所示的光通信驱动电路中的时钟电路执行。
步骤302：采用时钟信号对光信号进行调制，得到调制光信号。
在本公开实施例中，光信号可以为激光器产生的激光，激光具有单色性好、亮度高等优点，非常适合作为光通信的光源。
相应地，采用时钟信号对光信号进行调制则为，对激光器产生的激光进行调制，得到调制激光信号。例如，可以通过时钟信号的高低电平来控制激光器的开关，从而产生激光脉冲信号，该激光脉冲信号也即前述调制激光信号，携带有前述待发送信息。
该步骤302可以由图3所示的光通信驱动电路中的调制电路执行。
在该光通信驱动方法中，产生的时钟信号包括交替出现的第一频率信号和第二频率信号，第一频率信号和第二频率信号虽然具有不同的频率，但都是基于初始频率信号生成的，也就是说采用一路初始频率信号作为输入，同时配合待发送信息进行控制，即可输出时钟信号。在产生该时钟信号时，由于只采用一路初始频率信号作为输入，然后通过待发送信息的控制交替产生第一频率信 号和第二频率信号，所以无需进行待发送信息的模拟信号倒相，并通过待发送信息的模拟信号和倒相后的信号来对两路频率信号进行波形选择产生时钟信号，避免了由于进行待发送信息的模拟信号倒相、通过倒相后的信号进行波形选择等过程造成的输出延迟，避免了由于输出延迟带来的误码，提高了通信质量。另外，由于本公开提供的方案产生的时钟信号没有上述延迟，因此可以采用更小的时间周期来表示待发送信息中的比特，可以提高数据传输速率。
图15示出了本公开实施例提供的一种光通信驱动方法的流程图。该方法可以由图3所示的光通信驱动电路执行，参见图15，该方法的步骤包括：
步骤401：根据待发送信息产生控制字序列，控制字序列包括交替出现的第一控制字和第二控制字。
在本公开实施例的一种实现方式中，根据待发送信息产生控制字序列，控制字序列包括交替出现的第一控制字和第二控制字，包括：基于比特与控制字的对应关系，按照待发送信息中比特的顺序依次选取与待发送信息中各个比特对应的控制字，得到控制字序列。
按照这种方式选取预先设定好的控制字，使得时钟电路能够输出与控制字对应的且符合通信需求的频率的时钟信号。
在本公开实施例的一种实现方式中，在基于比特与控制字的对应关系，按照待发送信息中比特的顺序依次选取与待发送信息中各个比特对应的控制字之前，根据待发送信息产生控制字序列，还包括：按照通信模式选择相应的比特与控制字的对应关系，在不同的通信模式下，比特与控制字的对应关系至少部分不相同。
将控制字的大小和通信模式关联起来，这样在通信过程中可以通过选择不同的模式，产生不同频率的时钟信号与对端通信，通信更加灵活。例如，可以通过不同频率的时钟信号选择在私密通信模式或开放通信模式下进行光通信。
步骤402：基于初始频率信号的频率和第一控制字得到第一频率信号，基于初始频率信号的频率和第二控制字得到第二频率信号。
时钟信号包括交替出现的第一频率信号和第二频率信号，第一频率信号和第二频率信号具有不同的频率且基于初始频率信号生成。时钟信号中的第一频率信号的频率等于初始频率信号的频率除以第一控制字，时钟信号中的第二频率信号的频率等于初始频率信号的频率除以第二控制字。
在本公开实施例中，初始频率信号可以采用还可以使用压控振荡器产生，例如采用电感电容压控振荡器(LCVCO)作为振源产生上述初始频率信号。
通过步骤401和402实现了以一路初始频率信号为输入，在待发送信息的控制下输出时钟信号。该步骤401和402可以由图3所示的光通信驱动电路中的时钟电路执行。
由于这里产生的时钟信号的频率等于初始频率信号的频率除以控制字，所以可以通过控制控制字来实现任意频率的时钟信号的产生。而现有技术中，时钟信号的频率是固定的，本公开相比现有技术丰富了时钟信号的多样性。另外，控制字序列包括交替出现的第一控制字和第二控制字，时钟信号的频率等于初始频率信号的频率除以控制字，因此输出的时钟信号包括交替出现的第一频率信号和第二频率信号。
在本公开实施例的一种实现方式中，基于初始频率信号的频率和第一控制字得到第一频率信号，基于初始频率信号的频率和第二控制字得到第二频率信号，包括：根据初始频率信号产生K个相位均匀间隔的信号，K为大于2的整数；基于K个相位均匀间隔的信号和第一控制字产生第一频率信号，基于K个相位均匀间隔的信号和第二控制字产生第二频率信号。
在该实现方式中，时钟电路由2个部分组成，其中，分频器负责根据频率信号产生K个相位均匀间隔的信号，而频率合成器则负责根据K个相位均匀间隔的信号和控制字产生时钟信号。
在本公开实施例的一种实现方式中，基于K个相位均匀间隔的信号和第一控制字产生第一频率信号，基于K个相位均匀间隔的信号和第二控制字产生第二频率信号，包括：基于K个相位均匀间隔的信号和第一控制字，生成第一周期信号和第二周期信号，并基于第一周期信号和第二周期信号生成第一频率信号；基于K个相位均匀间隔的信号和第二控制字，生成第三周期信号和第四周期信号，并基于第三周期信号和第四周期信号生成第二频率信号。
在本公开实施例的一种实现方式中，基于K个相位均匀间隔的信号和第一控制字，生成第一周期信号和第二周期信号，基于K个相位均匀间隔的信号和第二控制字，生成第三周期信号和第四周期信号，包括：
按照如下公式生成第一周期信号、第二周期信号、第三周期信号和第四周期信号：
T A＝I*Δ，T B＝(I+1)*Δ，T C＝J*Δ，T D＝(J+1)*Δ，Δ为K个相位均匀 间隔的信号中的任意两个相邻信号之间的相位差，I为第一控制字中的整数部分，J为第二控制字中的整数部分，T A为第一周期信号，T B为第二周期信号，T C为第三周期信号，T D为第四周期信号。
在本公开实施例的一种实现方式中，基于第一周期信号和第二周期信号生成第一频率信号，基于第三周期信号和第四周期信号生成第二频率信号，包括：
按照如下公式生成第一频率信号和第二频率信号：
T TAF1＝(1-r)*T A+r*T B，T TAF2＝(1-s)*T C+s*T D，
其中，T TAF1为第一频率信号的周期，r为第一控制字中的小数部分，0≤r<1，T TAF2为第二频率信号的周期，s为第二控制字中的小数部分，0≤s<1。
步骤403：采用时钟信号对光信号进行调制，得到调制光信号。
在本公开实施例中，光信号可以为激光器产生的激光，激光具有单色性好、亮度高等优点，非常适合作为光通信的光源。
相应地，采用时钟信号对光信号进行调制则为，对激光器产生的激光进行调制，得到调制激光信号。例如，可以通过时钟信号的高低电平来控制激光的通断，从而产生激光脉冲信号，该激光脉冲信号也即前述调制激光信号，携带有前述待发送信息。
该步骤403可以由图3所示的光通信驱动电路中的调制电路执行。
以上仅为本公开的示例性实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开所附权利要求书限定的保护范围之内。

Claims (19)

  1. 一种光通信驱动电路，其特征在于，所述光通信驱动电路包括：
    时钟电路，被配置为以一路初始频率信号为输入，在待发送信息的控制下输出时钟信号，所述时钟信号包括交替出现的第一频率信号和第二频率信号，所述第一频率信号和所述第二频率信号具有不同的频率且基于所述初始频率信号生成；
    调制电路，被配置为采用所述时钟电路输出的时钟信号对光信号进行调制，得到调制光信号。
  2. 如权利要求1所述的光通信驱动电路，其特征在于，所述时钟电路，包括：
    控制子电路，被配置为根据所述待发送信息产生控制字序列，所述控制字序列包括交替出现的第一控制字和第二控制字；
    处理子电路，被配置为基于所述初始频率信号的频率和所述控制子电路产生的所述控制字序列中的第一控制字得到所述第一频率信号，基于所述初始频率信号的频率和所述控制子电路产生的所述控制字序列中的第二控制字得到所述第二频率信号。
  3. 如权利要求2所述的光通信驱动电路，其特征在于，所述控制子电路，被配置为基于比特与控制字的对应关系，按照所述待发送信息中比特的顺序依次选取与所述待发送信息中各个比特对应的控制字，得到所述控制字序列。
  4. 如权利要求3所述的光通信驱动电路，其特征在于，所述控制子电路，被配置为按照通信模式选择相应的比特与控制字的对应关系，在不同的所述通信模式下，所述比特与控制字的对应关系至少部分不相同。
  5. 如权利要求2至4任一项所述的光通信驱动电路，其特征在于，所述处理子电路，包括：
    分频器，被配置为根据所述初始频率信号产生K个相位均匀间隔的信号，K为大于2的整数；
    频率合成器，被配置为基于所述分频器产生的K个相位均匀间隔的信号和所述第一控制字产生所述第一频率信号，基于所述K个相位均匀间隔的信号和所述第二控制字产生所述第二频率信号。
  6. 如权利要求5所述的光通信驱动电路，其特征在于，所述频率合成器，被配置为基于所述K个相位均匀间隔的信号和所述第一控制字，生成第一周期信号和第二周期信号，并基于所述第一周期信号和所述第二周期信号生成所述第一频率信号；基于所述K个相位均匀间隔的信号和所述第二控制字，生成第三周期信号和第四周期信号，并基于所述第三周期信号和所述第四周期信号生成所述第二频率信号。
  7. 如权利要求6所述的光通信驱动电路，其特征在于，所述频率合成器，被配置为按照如下公式生成所述第一周期信号、所述第二周期信号、所述第三周期信号和所述第四周期信号：
    T A＝I*Δ，T B＝(I+1)*Δ，T C＝J*Δ，T D＝(J+1)*Δ，所述Δ为K个相位均匀间隔的信号中的任意两个相邻信号之间的相位差，I为所述第一控制字中的整数部分，J为所述第二控制字中的整数部分，T A为所述第一周期信号，T B为所述第二周期信号，T C为所述第三周期信号，T D为所述第四周期信号。
  8. 如权利要求7所述的光通信驱动电路，其特征在于，所述频率合成器，被配置为按照如下公式生成所述第一频率信号和所述第二频率信号：
    T TAF1＝(1-r)*T A+r*T B，T TAF2＝(1-s)*T C+s*T D，
    其中，T TAF1为所述第一频率信号的周期，r为所述第一控制字中的小数部分，0≤r<1，T TAF2为所述第二频率信号的周期，s为所述第二控制字中的小数部分，0≤s<1。
  9. 一种光通信发送端，其特征在于，所述光通信发送端包括发光单元和如权利要求1至8任一项所述的光通信驱动电路，所述光通信驱动电路被配置为对所述发光单元产生的光信号进行调制，得到调制光信号。
  10. 一种光通信系统，所述系统包括发送端和接收端，其特征在于，所述发送端为如权利要求9所述光通信发送端。
  11. 一种交通工具，其特征在于，所述交通工具包括如权利要求9所述光通信发送端。
  12. 一种光通信驱动方法，其特征在于，所述方法包括：
    以一路初始频率信号为输入，在待发送信息的控制下输出时钟信号，所述时钟信号包括交替出现的第一频率信号和第二频率信号，所述第一频率信号和所述第二频率信号具有不同的频率且基于所述初始频率信号生成；
    采用所述时钟信号对光信号进行调制，得到调制光信号。
  13. 如权利要求12所述的方法，其特征在于，所述以一路初始频率信号为输入，在待发送信息的控制下输出时钟信号，包括：
    根据所述待发送信息产生控制字序列，所述控制字序列包括交替出现的第一控制字和第二控制字；
    基于所述初始频率信号的频率和所述第一控制字得到所述第一频率信号，基于所述初始频率信号的频率和所述第二控制字得到所述第二频率信号。
  14. 如权利要求13所述的方法，其特征在于，所述根据所述待发送信息产生控制字序列，包括：
    基于比特与控制字的对应关系，按照所述待发送信息中比特的顺序依次选取与所述待发送信息中各个比特对应的控制字，得到所述控制字序列。
  15. 如权利要求14所述的方法，其特征在于，在所述基于比特与控制字的对应关系，按照所述待发送信息中比特的顺序依次选取与所述待发送信息中各个比特对应的控制字之前，所述根据所述待发送信息产生控制字序列，还包括：
    按照通信模式选择相应的比特与控制字的对应关系，在不同的所述通信模式下，所述比特与控制字的对应关系至少部分不相同。
  16. 如权利要求13至15任一项所述的方法，其特征在于，所述基于所述初始频率信号的频率和所述第一控制字得到所述第一频率信号，基于所述初始频率信号的频率和所述第二控制字得到所述第二频率信号，包括：
    根据所述初始频率信号产生K个相位均匀间隔的信号，K为大于2的整数；
    基于所述K个相位均匀间隔的信号和所述第一控制字产生所述第一频率信号，基于所述K个相位均匀间隔的信号和所述第二控制字产生所述第二频率信号。
  17. 如权利要求16所述的方法，其特征在于，所述基于所述K个相位均匀间隔的信号和所述第一控制字产生所述第一频率信号，基于所述K个相位均匀间隔的信号和所述第二控制字产生所述第二频率信号，包括：
    基于所述K个相位均匀间隔的信号和所述第一控制字，生成第一周期信号和第二周期信号，并基于所述第一周期信号和所述第二周期信号生成所述第一频率信号；基于所述K个相位均匀间隔的信号和所述第二控制字，生成第三周期信号和第四周期信号，并基于所述第三周期信号和所述第四周期信号生成所述第二频率信号。
  18. 如权利要求17所述的方法，其特征在于，所述基于所述K个相位均匀间隔的信号和所述第一控制字，生成第一周期信号和第二周期信号，基于所述K个相位均匀间隔的信号和所述第二控制字，生成第三周期信号和第四周期信号，包括：
    按照如下公式生成所述第一周期信号、所述第二周期信号、所述第三周期信号和所述第四周期信号：
    T A＝I*Δ，T B＝(I+1)*Δ，T C＝J*Δ，T D＝(J+1)*Δ，所述Δ为K个相位均匀间隔的信号中的任意两个相邻信号之间的相位差，I为所述第一控制字中的整数部分，J为所述第二控制字中的整数部分，T A为所述第一周期信号，T B为所述第二周期信号，T C为所述第三周期信号，T D为所述第四周期信号。
  19. 如权利要求18所述的方法，其特征在于，所述基于所述第一周期信号和所述第二周期信号生成所述第一频率信号，基于所述第三周期信号和所述第 四周期信号生成所述第二频率信号，包括：
    按照如下公式生成所述第一频率信号和所述第二频率信号：
    T TAF1＝(1-r)*T A+r*T B，T TAF2＝(1-s)*T C+s*T D，
    其中，T TAF1为所述第一频率信号的周期，r为所述第一控制字中的小数部分，0≤r<1，T TAF2为所述第二频率信号的周期，s为所述第二控制字中的小数部分，0≤s<1。
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Publication number Priority date Publication date Assignee Title
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103828317A (zh) * 2011-09-30 2014-05-28 英特尔公司 频移通信的方法和设置
CN104022824A (zh) * 2014-06-21 2014-09-03 滁州惠智科技服务有限公司 一种具有通信功能的led路灯系统
US20160315702A1 (en) * 2012-06-30 2016-10-27 Intel Corporation Apparatus for visible light communications in accordance with ufsook and fsk dimming

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE432859B (sv) * 1982-10-22 1984-04-16 Ericsson Telefon Ab L M Forfarande att overfora en extra informationskanal over ett transmissionsmedium
JP2000078212A (ja) * 1998-08-28 2000-03-14 Aiphone Co Ltd Ｆｓｋ変調装置
US7741928B1 (en) * 2007-10-10 2010-06-22 Marvell International Ltd. Frequency modulation using a digital frequency locked loop
JP5320745B2 (ja) 2008-01-11 2013-10-23 沖電気工業株式会社 キャリア抑圧光パルス列生成装置及びキャリア抑圧光パルス列生成方法
CN101515828B (zh) * 2008-02-22 2011-10-26 华为技术有限公司 光发射机、光发射方法及光传输系统
US8705980B2 (en) * 2009-11-19 2014-04-22 Nec Corporation Optical modulation device and optical modulation method
RU2648265C2 (ru) * 2013-03-12 2018-03-23 Филипс Лайтинг Холдинг Б.В. Система связи, система освещения и способ передачи информации
CN104022924A (zh) * 2014-07-02 2014-09-03 浪潮电子信息产业股份有限公司 一种http通信内容检测的方法
CN105049118B (zh) * 2015-08-20 2017-10-20 华南理工大学 基于双重调制技术的可见光通信方法及其可见光通信系统
TW201832496A (zh) * 2017-02-17 2018-09-01 國立臺北科技大學 無線光通訊系統及其光發射器

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103828317A (zh) * 2011-09-30 2014-05-28 英特尔公司 频移通信的方法和设置
US20160315702A1 (en) * 2012-06-30 2016-10-27 Intel Corporation Apparatus for visible light communications in accordance with ufsook and fsk dimming
CN104022824A (zh) * 2014-06-21 2014-09-03 滁州惠智科技服务有限公司 一种具有通信功能的led路灯系统

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