WO2021031463A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2021031463A1
WO2021031463A1 PCT/CN2019/123980 CN2019123980W WO2021031463A1 WO 2021031463 A1 WO2021031463 A1 WO 2021031463A1 CN 2019123980 W CN2019123980 W CN 2019123980W WO 2021031463 A1 WO2021031463 A1 WO 2021031463A1
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WO
WIPO (PCT)
Prior art keywords
layer
wiring
auxiliary circuit
display panel
thin film
Prior art date
Application number
PCT/CN2019/123980
Other languages
English (en)
French (fr)
Inventor
吴绍静
Original Assignee
武汉华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US16/632,919 priority Critical patent/US11362116B2/en
Publication of WO2021031463A1 publication Critical patent/WO2021031463A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate

Definitions

  • This application relates to the field of display technology, and in particular to a display panel and a display device.
  • AMOLED Active-Matrix Organic Light-Emitting Diode
  • the current AMOLED display panel has a large frame, which cannot meet the needs of users.
  • the embodiments of the present application provide a display panel and a display device to solve the problem of a large display panel frame.
  • an embodiment of the present application provides a display panel, including:
  • a thin film transistor layer, the thin film transistor layer is disposed on the substrate layer, and a bending area is disposed on at least one side of the substrate layer adjacent to the thin film transistor layer;
  • GOA driving circuit where the GOA driving circuit is disposed on the substrate layer and located on at least one side of the thin film transistor layer, and the bending area is disposed between the GOA driving circuit and the thin film transistor layer;
  • An auxiliary circuit, the auxiliary circuit is arranged on the substrate layer and arranged corresponding to the bending area;
  • the GOA driving circuit is connected to the gate wiring in the thin film transistor layer through the auxiliary circuit.
  • the base layer includes a base substrate and a first insulating layer that are stacked in sequence;
  • a number of first grooves are arranged on the side of the substrate layer close to the auxiliary circuit, and the first grooves are arranged on the first insulating layer and located in the bending area.
  • the auxiliary circuit is provided along the surface of the substrate layer and the inner surface of the first groove.
  • the base layer includes a base substrate and a first insulating layer that are stacked in sequence;
  • a second groove is arranged on the side of the substrate layer close to the auxiliary circuit, and the second groove is arranged on the first insulating layer and located in the bending area, wherein the second groove The groove is filled with an organic layer.
  • the auxiliary circuit is provided along the surface of the substrate layer and the surface of the organic layer.
  • the auxiliary circuit includes a plurality of auxiliary circuit wirings connecting the GOA driving circuit and the gate wiring in the thin film transistor layer;
  • the auxiliary circuit wiring is arranged in a single row of hole wiring, multiple rows of hole wiring, wavy wiring or bending wiring in the bending area.
  • the display panel further includes:
  • VSS traces are arranged corresponding to the bending area, and a second insulating layer is provided between the VSS traces and the auxiliary circuit.
  • the display panel further includes:
  • planarization layer covers the thin film transistor layer, the VSS wiring and the substrate layer, and a through hole exposing the VSS wiring is provided on the planarization layer;
  • An anode layer, the anode layer is disposed on the planarization layer and is connected to the VSS wiring through the through hole;
  • the cathode layer is located on the anode layer and connected to the anode layer.
  • the display panel further includes:
  • planarization layer covers the thin film transistor layer, the VSS wiring and the substrate layer, and a through hole exposing the VSS wiring is provided on the planarization layer;
  • the cathode layer is located on the planarization layer and is connected to the VSS trace through the through hole.
  • the VSS wiring is arranged in a single row of hole wiring, multiple rows of hole wiring, wavy wiring, or bending wiring in the bending area.
  • an embodiment of the present application provides a display device, the display device includes a display panel, and the display panel includes:
  • a thin film transistor layer, the thin film transistor layer is disposed on the substrate layer, and a bending area is disposed on at least one side of the substrate layer adjacent to the thin film transistor layer;
  • GOA driving circuit where the GOA driving circuit is disposed on the substrate layer and located on at least one side of the thin film transistor layer, and the bending area is disposed between the GOA driving circuit and the thin film transistor layer;
  • An auxiliary circuit, the auxiliary circuit is arranged on the substrate layer and arranged corresponding to the bending area;
  • the GOA driving circuit is connected to the gate wiring in the thin film transistor layer through the auxiliary circuit.
  • the base layer includes a base substrate and a first insulating layer that are stacked in sequence;
  • a number of first grooves are arranged on the side of the substrate layer close to the auxiliary circuit, and the first grooves are arranged on the first insulating layer and located in the bending area.
  • the auxiliary circuit is provided along the surface of the substrate layer and the inner surface of the first groove.
  • the base layer includes a base substrate and a first insulating layer that are stacked in sequence;
  • a second groove is arranged on the side of the substrate layer close to the auxiliary circuit, and the second groove is arranged on the first insulating layer and located in the bending area, wherein the second groove The groove is filled with an organic layer.
  • the auxiliary circuit is provided along the surface of the substrate layer and the surface of the organic layer.
  • the auxiliary circuit includes a plurality of auxiliary circuit wirings connecting the GOA driving circuit and the gate wiring in the thin film transistor layer;
  • the auxiliary circuit wiring is arranged in a single row of hole wiring, multiple rows of hole wiring, wavy wiring or bending wiring in the bending area.
  • the display panel further includes:
  • VSS traces are arranged corresponding to the bending area, and a second insulating layer is provided between the VSS traces and the auxiliary circuit.
  • the display panel further includes:
  • planarization layer covers the thin film transistor layer, the VSS wiring and the substrate layer, and a through hole exposing the VSS wiring is provided on the planarization layer;
  • An anode layer, the anode layer is disposed on the planarization layer and is connected to the VSS wiring through the through hole;
  • the cathode layer is located on the anode layer and connected to the anode layer.
  • the display panel further includes:
  • planarization layer covers the thin film transistor layer, the VSS wiring and the substrate layer, and a through hole exposing the VSS wiring is provided on the planarization layer;
  • the cathode layer is located on the planarization layer and is connected to the VSS trace through the through hole.
  • the VSS wiring is arranged in the bending area as a single-row hole wiring, a multi-row hole wiring, a wave-shaped wiring or a bent wiring.
  • the display panel provided by the embodiment of the application includes a substrate layer, a thin film transistor layer, a GOA driving circuit, and an auxiliary circuit.
  • the thin film transistor layer is provided on the substrate layer, and a bending area is provided on at least one side adjacent to the thin film transistor on the substrate layer;
  • the GOA driving circuit is provided on the substrate layer, and Located on at least one side of the thin film transistor layer, the bending area is provided between the GOA driving circuit and the thin film transistor layer;
  • the auxiliary circuit is provided on the substrate layer and is connected to the bending area Corresponding arrangement; wherein the GOA driving circuit is connected to the gate wiring in the thin film transistor layer through the auxiliary circuit.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of the structure of the bending area of the display panel provided by the embodiment of the present application.
  • FIG. 3 is another schematic diagram of the structure of the bending area of the display panel provided by the embodiment of the present application.
  • FIG. 4 is another schematic diagram of the structure of the bending area of the display panel provided by the embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of an auxiliary circuit and/or VSS wiring provided by an embodiment of the present application.
  • FIG. 6 is another schematic diagram of the structure of the auxiliary circuit and/or VSS wiring provided by the embodiment of the present application.
  • FIG. 7 is another schematic diagram of the structure of the auxiliary circuit and/or VSS wiring provided by the embodiment of the present application.
  • FIG. 8 is a schematic diagram of another structure of a display panel provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • FIG. 10 is a schematic diagram of another structure of a display device provided by an embodiment of the present application.
  • the embodiments of the present application provide a display panel and a display device, which will be described in detail below.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • the display panel 10 may include a substrate layer 101, a thin film transistor layer 102, an auxiliary circuit 103, and a GOA driving circuit 104.
  • the substrate layer 101 may be formed of any insulating material with flexible characteristics.
  • the substrate layer 101 may be made of polyimide (PI), polycarbonate (PC), polyethersulfone (PES), polyethylene terephthalate (PET), polyethylene naphthalate It is formed of polymer materials such as ester (PEN), polyarylate (PAR) or glass fiber reinforced plastic (FRP).
  • the thin film transistor layer 102 is disposed on the substrate layer 101.
  • the thin film transistor layer 102 is located on one side of the bending region 1011a.
  • the thin film transistor layer 102 may include a source and drain layer, a gate layer, a gate insulating layer and other film structures. It can be understood that the GOA driving circuit 104 is a gate driving control circuit.
  • a bending area 1011a may be provided on at least one side of the substrate layer 101 adjacent to the thin film transistor layer 102.
  • the thin film transistor layer 102 may include four sides, an upper side, a lower side, a left side, and a right side. Specifically, as shown in FIG. 9 or FIG. 10, in FIG. 9 or FIG. 10, the thin film transistor layer 102 is located in the display area 2.
  • a bending area 1011a may be provided on at least one of the upper side, the left side, or the right side of the thin film transistor layer 102.
  • the lower side of the thin film transistor layer 102 does not need to provide the bending area 1011a.
  • bending regions 1011a may be provided on the upper, left and right sides of the thin film transistor layer 102.
  • the GOA driving circuit 104 is disposed on the substrate layer 101. Moreover, the GOA driving circuit 104 is located on at least one side of the thin film transistor layer 102. It can be understood that the GOA driving circuit 104 may be disposed on at least one of the upper side, the left side, or the right side of the thin film transistor layer 102. It should be noted that at this time, a bending area 1011a is provided between the GOA driving circuit 104 and the thin film transistor layer 102.
  • the auxiliary circuit 103 is disposed on the substrate layer 101. Moreover, the auxiliary circuit 103 can be arranged corresponding to the bending area 1011a. The auxiliary circuit 103 can be used to connect the thin film transistor layer 102 and the GOA driving circuit 104. Wherein, the GOA driving circuit 104 may be connected to the gate wiring in the thin film transistor layer 102 through the auxiliary circuit 103. It should be noted that the auxiliary circuit 103 may include multiple auxiliary circuit traces connecting the GOA driving circuit 104 and the gate traces in the thin film transistor layer 102.
  • the frame size of the display panel 10 is the distance from the cutting edge on the auxiliary circuit 103 to the light-emitting area of the thin film transistor layer 102.
  • the GOA driving circuit 104 is located between the thin film transistor layer 102 and the auxiliary circuit 103. Therefore, the frame of the display panel 10 provided by the embodiment of the present application is smaller than the frame of the display panel in the prior art.
  • the display panel 10 may further include a VSS wiring 105.
  • the base layer 101 may include a base substrate 1012 and a first insulating layer 1013 stacked in sequence.
  • a number of first grooves 1014 are provided on the side of the substrate layer 101 close to the auxiliary circuit 103. It should be noted that the first groove 1014 is disposed on the first insulating layer 1013 of the substrate layer 101 and is located in the bending area 1011a.
  • VSS usually refers to the voltage of the common ground terminal of the circuit.
  • the auxiliary circuit 103 can be arranged along the surface of the substrate layer 101 and the inner surface of the first groove 1014. That is, the auxiliary circuit 103 can cover the surface of the substrate layer 101 and the inner surface of the first groove 1014. It can be understood that the auxiliary circuit 103 is undulating at this time, which can facilitate the bending of the auxiliary circuit 103 and reduce the probability of the auxiliary circuit 103 breaking when the display panel 10 performs edge curved bending. It should be noted that the auxiliary circuit 103 can have various bending shapes. The bending shape of the auxiliary circuit 103 is mainly determined by the shape of the inner surface of the first groove 1014.
  • the VSS wiring 105 can be configured the same as the auxiliary circuit 103 to improve the bending resistance of the VSS wiring 105. That is, the VSS wiring 105 may be provided on the auxiliary circuit 103. In addition, the VSS trace 105 in the bending area 1011a may be arranged along the upper surface of the auxiliary circuit 103.
  • the display panel 10 may further include a VSS wiring 105, and the VSS wiring 105 is disposed on the auxiliary circuit 103.
  • the base layer 101 may include a base substrate 1012 and a first insulating layer 1013 stacked in sequence.
  • a second groove 1015 may be provided on the side of the substrate layer 101 close to the auxiliary circuit 103. It should be noted that the second groove 1015 is disposed on the first insulating layer 1013 of the substrate layer 101 and is located in the bending area 1011a. Wherein, the second groove 1015 is filled with an organic layer 118.
  • the auxiliary circuit 103 may be provided along the surface of the substrate layer 101 and the surface of the organic layer 118.
  • the organic layer 118 can play a certain buffering effect when the display panel 10 is bent on the edge of the curved surface, which is beneficial to release the stress generated when the auxiliary circuit 103 is bent, improve the bending resistance of the auxiliary circuit 103, and reduce the auxiliary circuit. 103 The probability of breaking when bending.
  • the auxiliary circuit 103 in the bending area 1011a may be grooved to form a plurality of third grooves 1016.
  • the third groove 1016 can facilitate stress relief of the auxiliary circuit 103 and the VSS trace 105.
  • the display panel 10 may further include a VSS wiring 105, and the VSS wiring is disposed on the auxiliary circuit 103.
  • the base layer 101 may include a base substrate 1012 and a first insulating layer 1013 stacked in sequence.
  • a fourth groove 1017 penetrating the auxiliary circuit 103 and the first insulating layer 1013 may be provided on the auxiliary circuit 103.
  • the fourth groove 1017 can facilitate stress relief of the VSS trace 105 and the auxiliary circuit 103.
  • the fourth groove 1017 may be filled with organic materials to form an organic layer 1018.
  • the organic layer 1018 can facilitate the stress relief of the auxiliary circuit 103 and the VSS wiring 105.
  • the auxiliary circuit 103 and the VSS trace 105 may be designed to be resistant to bending.
  • the auxiliary circuit 103 and the VSS trace 105 can be designed as a single row of hole traces as shown in FIG. 5, multiple rows of hole traces as shown in FIG. 6, and a wave-shaped trace as shown in FIG. Cable routing or bent routing. It should be noted that the hole, wave shape or bent shape in the auxiliary circuit 103 or the VSS trace 105 includes but is not limited to the illustration.
  • a mask can be used to form an auxiliary circuit 103 with a single row of holes or multiple rows of holes on the substrate layer 101; a mask can be used to form a single row of hole traces or multiple rows of hole traces on the auxiliary circuit 103 VSS traces 105 .
  • the auxiliary circuit 103 on the substrate layer 101 is set as a wave-shaped wiring; the VSS wiring 105 on the auxiliary circuit 103 is set as a wave-shaped wiring. Designing the auxiliary circuit 103 and the VSS wiring 105 as a single row of hole wiring, multiple rows of hole wiring or a wave-shaped wiring can facilitate the bending of the auxiliary circuit 103 and the VSS wiring 105.
  • auxiliary circuit traces of the auxiliary circuit 103 located in the bending area 1011a can be counted as single-row traces, multiple-row traces, wavy traces or bent traces.
  • the auxiliary circuit traces outside the bending area 1011a can use conventional settings.
  • the VSS trace 105 located in the bending area 1011a can be designed as a single row of hole traces, multiple rows of hole traces, wavy traces or bent traces.
  • the VSS trace 105 outside the bending area 1011a can be configured in a conventional manner.
  • the second insulating layer 106 can isolate the auxiliary circuit 103 and the VSS wiring 105 to prevent the auxiliary circuit 103 and the VSS wiring 105 from being short-circuited and causing a short circuit.
  • the display panel 10 provided by the embodiment of the present application may further include a planarization layer 107, an anode layer 108 and a cathode layer 109.
  • the planarization layer 107 covers the thin film transistor layer 102, the VSS wiring 105 and the substrate layer 101.
  • a through hole 1071 exposing the VSS wiring 105 is provided on the planarization layer 107.
  • the anode layer 108 is disposed on the planarization layer 107.
  • the anode layer 108 is connected to the VSS trace 105 through the through hole 1071.
  • the cathode layer 109 is located on the planarization layer 107 and part of the anode layer 108. In addition, the cathode layer 109 is connected to the anode layer 108.
  • the thickness of the cathode layer 109 is smaller than the thickness of the anode layer 108, so the bending resistance of the cathode layer 109 is better than the bending resistance of the anode layer 108.
  • the VSS trace 105 fails to connect to the display area of the display panel 10, thereby affecting the display effect of the display panel 10.
  • the anode layer 108 in the display panel 10 can be removed, and the cathode layer 109 is directly connected to the VSS trace 105.
  • the cathode layer 109 is located on the planarization layer 107.
  • the cathode layer 109 is connected to the VSS trace 105 through the through hole 1071.
  • the bending resistance of the cathode layer 109 is better than the bending resistance of the anode layer 108. Therefore, when the anode layer 108 is removed and the cathode layer 109 is directly connected to the VSS trace 105 through the via 1071, compared to the anode layer 108 being connected to the VSS trace 105, the VSS trace 105 and the display caused by the fracture can be reduced. The area connection fails, which affects the display effect of the display panel 10.
  • the cathode layer 109 is directly connected to the VSS wiring 105, compared to the cathode layer 109 being connected to the VSS wiring 105 through the anode layer 108, the contact resistance of the VSS wiring 105 can be reduced.
  • the reduced contact resistance of the VSS trace 105 can reduce the voltage drop of the VSS trace 105. Thereby, the light emission uniformity of the display panel 10 is improved.
  • the display panel 10 may further include other functional layers 110, a first encapsulation layer 111, a second encapsulation layer 112, a third encapsulation layer 113, a pixel definition layer 114 and a barrier 115.
  • the pixel definition layer 114 is disposed on the barrier 115 and the GOA driving circuit 104.
  • the other functional layer 110 is disposed on the anode layer 108 or the cathode layer 109.
  • the first encapsulation layer 111 covers the AMOLED functional layer 110, the pixel definition layer 114, the barrier 115, the planarization layer 107, the GOA driving circuit 104 and the substrate layer 101.
  • the second packaging layer 112 is disposed on the first packaging layer 111.
  • the third packaging layer 113 covers the second packaging layer 112, the first packaging layer 111 and the substrate layer 101.
  • first encapsulation layer 111 and the third encapsulation layer 113 are inorganic encapsulation layers.
  • the second encapsulation layer 112 is an organic encapsulation layer.
  • a barrier 115 close to the GOA driving circuit can be provided on the outer side of the GOA driving circuit 104. That is, the retaining wall 115 is arranged closely to and surrounds the GOA driving circuit 104 to prevent the sides of the GOA driving circuit 104 from being corroded, thereby affecting the performance of the GOA driving circuit 104. It should be noted that the thickness of the retaining wall 115 is greater than the thickness of the GOA driving circuit 104.
  • the display panel 10 may further include a crack detection circuit 116 and a crack prevention device 117.
  • the crack detection circuit 116 is disposed on the substrate layer 101 and can be used to detect whether the display panel 10 has cracks. It should be noted that the thin film transistor layer 102, the auxiliary circuit 103, and the GOA driving circuit 104 are located on the same side, and the crack detection circuit 116 is located on the other side. In addition, the crack detection circuit 116 is located in the first packaging layer 111.
  • the crack prevention device 117 is disposed on the substrate layer 101 and can be used to prevent cracks in the display panel 10. It should be noted that the crack prevention device 117 is located outside the third packaging layer 113.
  • the display panel 10 provided by the embodiment of the present application can reduce the frame of the display panel 10 by disposing the auxiliary circuit 103 between the thin film transistor layer 102 and the GOA driving circuit 104.
  • the auxiliary circuit 103 is disposed in the bending area 1011a of the substrate layer 101, which can increase the bending resistance of the auxiliary circuit 103, thereby improving the bending resistance of the display panel 10.
  • the embodiment of the present application also provides a display device, and the display device 1 may include the display panel 10 provided in the foregoing embodiment. As shown in FIG. 9, the display device 1 may include a display area 2 and a non-display area 3. It should be noted that the light-emitting area of the thin film transistor layer 102 in the display panel 10 is located in the display area 2, and the auxiliary circuit 103, the bending area 1011a, and the GOA driving electrode 104 other than the light-emitting area of the thin film transistor layer 102 The structures are all located in the non-display area 3.
  • FIG. 10 is another schematic structural diagram of a display device provided by an embodiment of the application.
  • the display device 1 may include the display panel 10 in the above embodiment. It should be noted that the thin film transistor layer 102 is included in the display area 2.
  • the auxiliary circuit 103 is located between the display area 2 and the GOA driving circuit 104.
  • the auxiliary circuit 103 is provided corresponding to the bending area 1011a. There is a cutting edge 1011b in the bending area 1011a. It is understandable that the frame of the display device 1 is the distance from the cutting edge 1011b to the display area 2 at this time.
  • the GOA driving circuit 104 is arranged between the auxiliary circuit 103 and the display area 2. Therefore, this solution can reduce the frame of the display device 1.
  • the display device 1 provided by the embodiment of the present application has a small frame, which can meet the needs of users and improve user experience.

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  • Engineering & Computer Science (AREA)
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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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Abstract

显示面板包括衬底层(101)、薄膜晶体管层(102)、辅助电路(103)和GOA驱动电路(104)。其中，薄膜晶体管层(102)设置于衬底层(101)上，且在衬底层(101)上临近薄膜晶体管至少一侧设置有弯折区(1011a)；GOA驱动电路(104)设置于衬底层(101)上，且位于薄膜晶体管层(102)的至少一侧，GOA驱动电路(104)与薄膜晶体管层(102)之间设置有弯折区(1011a)；辅助电路(103)设置于衬底层(101)上且与弯折区(1011a)对应设置。

Description

显示面板和显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板和显示装置。
 背景技术
随着有源矩阵有机发光二极体（Active-Matrix Organic Light-Emitting Diode，AMOLED）显示面板技术的发展，窄边框的AMOLED显示面板越来越被大众所喜爱。但由于各种因素限制，目前的AMOLED显示面板的边框仍然较大，无法满足用户的需求。
 技术问题
目前的AMOLED显示面板的边框较大，无法满足用户的需求。
 技术解决方案
本申请实施例提供了一种显示面板和显示装置，以解决显示面板边框较大的问题。
第一方面，本申请实施例提供了一种显示面板，包括：
衬底层；
薄膜晶体管层，所述薄膜晶体管层设置于所述衬底层上，且在所述衬底层上临近所述薄膜晶体管层的至少一侧设置有弯折区；
GOA驱动电路，所述GOA驱动电路设置于所述衬底层上，且位于所述薄膜晶体管层的至少一侧，所述GOA驱动电路与所述薄膜晶体管层之间设置有所述弯折区；
辅助电路，所述辅助电路设置于所述衬底层上且与所述弯折区对应设置；
其中，所述GOA驱动电路通过所述辅助电路与所述薄膜晶体管层中的栅极走线相连接。
在本申请实施例提供的显示面板中，所述衬底层包括依次层叠设置的衬底基板和第一绝缘层；
在所述衬底层靠近所述辅助电路的一侧设置有若干第一凹槽，所述第一凹槽设置于所述第一绝缘层上，且位于所述弯折区。
在本申请实施例提供的显示面板中，所述辅助电路沿所述衬底层的表面和所述第一凹槽的内表面设置。
在本申请实施例提供的显示面板中，所述衬底层包括依次层叠设置的衬底基板和第一绝缘层；
在所述衬底层靠近所述辅助电路的一侧设置有第二凹槽，所述第二凹槽设置于所述第一绝缘层上，且位于所述弯折区，其中，所述第二凹槽中填充有有机层。
在本申请实施例提供的显示面板中，所述辅助电路沿所述衬底层的表面和所述有机层的表面设置。
在本申请实施例提供的显示面板中，所述辅助电路包括多条连接所述GOA驱动电路和所述薄膜晶体管层中的栅极走线的辅助电路走线；
所述辅助电路走线在所述弯折区设置成单排孔走线、多排孔走线、波浪形走线或弯折形走线。
在本申请实施例提供的显示面板中，所述显示面板还包括：
VSS走线，所述VSS走线与所述弯折区对应设置，且所述VSS走线与所述辅助电路之间设置有第二绝缘层。
在本申请实施例提供的显示面板中，所述显示面板还包括：
平坦化层，所述平坦化层覆盖于所述薄膜晶体管层、VSS走线和衬底层上，在所述平坦化层上设置有一暴露所述VSS走线的通孔；
阳极层，所述阳极层设置于所述平坦化层上，且通过所述通孔与所述VSS走线相连；
阴极层，所述阴极层位于所述阳极层之上，且与所述阳极层相连。
在本申请实施例提供的显示面板中，所述显示面板还包括：
平坦化层，所述平坦化层覆盖于所述薄膜晶体管层、VSS走线和衬底层上，在所述平坦化层上设置有一暴露所述VSS走线的通孔；
阴极层，所述阴极层位于所述平坦化层之上，且通过所述通孔与所述VSS走线相连。
在本申请实施例提供的显示面板中，所述VSS走线在所述弯折区设置成单排孔走线、多排孔走线、波浪形走线或弯折形走线。
第二方面，本申请实施例提供了一种显示装置，该显示装置包括一显示面板，该显示面板包括：
衬底层；
薄膜晶体管层，所述薄膜晶体管层设置于所述衬底层上，且在所述衬底层上临近所述薄膜晶体管层的至少一侧设置有弯折区；
GOA驱动电路，所述GOA驱动电路设置于所述衬底层上，且位于所述薄膜晶体管层的至少一侧，所述GOA驱动电路与所述薄膜晶体管层之间设置有所述弯折区；
辅助电路，所述辅助电路设置于所述衬底层上且与所述弯折区对应设置；
其中，所述GOA驱动电路通过所述辅助电路与所述薄膜晶体管层中的栅极走线相连接。
在本申请实施例提供的显示装置中，所述衬底层包括依次层叠设置的衬底基板和第一绝缘层；
在所述衬底层靠近所述辅助电路的一侧设置有若干第一凹槽，所述第一凹槽设置于所述第一绝缘层上，且位于所述弯折区。
在本申请实施例提供的显示装置中，所述辅助电路沿所述衬底层的表面和所述第一凹槽的内表面设置。
在本申请实施例提供的显示装置中，所述衬底层包括依次层叠设置的衬底基板和第一绝缘层；
在所述衬底层靠近所述辅助电路的一侧设置有第二凹槽，所述第二凹槽设置于所述第一绝缘层上，且位于所述弯折区，其中，所述第二凹槽中填充有有机层。
在本申请实施例提供的显示装置中，所述辅助电路沿所述衬底层的表面和所述有机层的表面设置。
在本申请实施例提供的显示装置中，所述辅助电路包括多条连接所述GOA驱动电路和所述薄膜晶体管层中的栅极走线的辅助电路走线；
所述辅助电路走线在所述弯折区设置成单排孔走线、多排孔走线、波浪形走线或弯折形走线。
在本申请实施例提供的显示装置中，所述显示面板还包括：
VSS走线，所述VSS走线与所述弯折区对应设置，且所述VSS走线与所述辅助电路之间设置有第二绝缘层。
在本申请实施例提供的显示装置中，所述显示面板还包括：
平坦化层，所述平坦化层覆盖于所述薄膜晶体管层、VSS走线和衬底层上，在所述平坦化层上设置有一暴露所述VSS走线的通孔；
阳极层，所述阳极层设置于所述平坦化层上，且通过所述通孔与所述VSS走线相连；
阴极层，所述阴极层位于所述阳极层之上，且与所述阳极层相连。
在本申请实施例提供的显示装置中，所述显示面板还包括：
平坦化层，所述平坦化层覆盖于所述薄膜晶体管层、VSS走线和衬底层上，在所述平坦化层上设置有一暴露所述VSS走线的通孔；
阴极层，所述阴极层位于所述平坦化层之上，且通过所述通孔与所述VSS走线相连。
在本申请实施例提供的显示装置中，所述VSS走线在所述弯折区设置成单排孔走线、多排孔走线、波浪形走线或弯折形走线。
 有益效果
本申请实施例提供的显示面板包括衬底层、薄膜晶体管层、GOA驱动电路和辅助电路。其中，所述薄膜晶体管层设置于所述衬底层上，且在所述衬底层上临近所述薄膜晶体管至少一侧设置有弯折区；所述GOA驱动电路设置于所述衬底层上，且位于所述薄膜晶体管层的至少一侧，所述GOA驱动电路与所述薄膜晶体管层之间设置有所述弯折区；所述辅助电路设置于所述衬底层上且与所述弯折区对应设置；其中，所述GOA驱动电路通过所述辅助电路与所述薄膜晶体管层中的栅极走线相连接。本方案通过将辅助电路设置于薄膜晶体管层与GOA驱动电路之间，可以减小该显示面板的边框。
 附图说明
图1是本申请实施例提供的显示面板的结构示意图。
图2是本申请实施例提供的显示面板的弯折区的结构示意图。
图3是本申请实施例提供的显示面板的弯折区的另一结构示意图。
图4是本申请实施例提供的显示面板的弯折区的又一结构示意图。
图5是本申请实施例提供的辅助电路和/或VSS走线的结构示意图。
图6是本申请实施例提供的辅助电路和/或VSS走线的另一结构示意图。
图7是本申请实施例提供的辅助电路和/或VSS走线的又一结构示意图。
图8是本申请实施例提供的显示面板的另一结构示意图。
图9是本申请实施例提供的显示装置的结构示意图。
图10是本申请实施例提供的显示装置的另一结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请实施例提供了一种显示面板和显示装置，以下将分别进行详细说明。
请参阅图1，图1是本申请实施例提供的显示面板的结构示意图。该显示面板10可以包括衬底层101、薄膜晶体管层102、辅助电路103和GOA驱动电路104。
其中，衬底层101可以由具有柔性特征的任意绝缘材料形成。例如，该衬底层101可以由聚酰亚胺(PI)、聚碳酸酯(PC)、聚醚砜(PES)、聚对苯二甲酸乙二醇酯(PET)、聚萘二甲酸乙二醇酯(PEN)、多芳基化合物(PAR)或玻璃纤维增强塑料(FRP)等聚合物材料形成。
其中，薄膜晶体管层102设置于衬底层101上。并且，该薄膜晶体管层102位于弯折区1011a的一侧。该薄膜晶体管层102可以包括源漏极层、栅极层、栅极绝缘层等膜层结构。可以理解的是，该GOA驱动电路104为栅极驱动控制电路。
在一些实施例中，为了增加该显示面板10的耐弯折性，可以在衬底层101临近薄膜晶体管层102的至少一侧设置一弯折区1011a。可以理解的是，该薄膜晶体管层102可以包括上侧、下侧、左侧和右侧四侧。具体可以如图9或图10所示，在图9或图10中，薄膜晶体管层102位于显示区2中。
需要说明的是，在本申请实施例中，可以在该薄膜晶体管层102的上侧、左侧或右侧中的至少一侧设置弯折区1011a。而该薄膜晶体管层102的下侧则无需设置该弯折区1011a。优选的，在本申请实施例中，可以在该薄膜晶体管层102的上侧、左侧和右侧三侧均设置弯折区1011a。
需要说明的是，在本申请实施例的描述中，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
其中，GOA驱动电路104设置于衬底层101上。并且，该GOA驱动电路104位于薄膜晶体管层102的至少一侧。可以理解的是，该GOA驱动电路104可以设置在薄膜晶体管层102的上侧、左侧或右侧中的至少一侧。需要说明的是，此时该GOA驱动电路104与薄膜晶体管层102之间设置有弯折区1011a。
其中，辅助电路103设置于衬底层101上。并且，该辅助电路103可以与弯折区1011a对应设置。该辅助电路103可以用于连接薄膜晶体管层102和GOA驱动电路104。其中，该GOA驱动电路104可以通过辅助电路103与薄膜晶体管层102中的栅极走线相连接。需要说明的是，该辅助电路103可以包括多条连接GOA驱动电路104与薄膜晶体管层102中的栅极走线的辅助电路走线。
可以理解的是，显示面板10的边框大小为位于辅助电路103上的切割边至薄膜晶体管层102的发光区的距离。而在现有技术中，GOA驱动电路104位于薄膜晶体管层102和辅助电路103之间。因此，本申请实施例所提供的显示面板10的边框比现有技术中的显示面板的边框小。
在一些实施例中，请参阅图2，该显示面板10还可以包括VSS走线105。该衬底层101可以包括依次层叠设置的衬底基板1012和第一绝缘层1013。在该衬底层101靠近辅助电路103的一侧设置若干第一凹槽1014。需要说明的是，该第一凹槽1014设置于衬底层101的第一绝缘层1013上，且位于弯折区1011a。可以理解的是，VSS通常指电路公共接地端电压。
而辅助电路103可以沿衬底层101的表面和第一凹槽1014的内表面设置。即，该辅助电路103可以覆盖于衬底层101的表面和第一凹槽1014的内表面。可以理解的是，此时辅助电路103呈起伏状，可以有利于辅助电路103的弯折，降低辅助电路103在显示面板10进行边缘曲面弯折时出现断裂的几率。需要说明的是，该辅助电路103的弯折形状可以有多种。该辅助电路103的弯折形状主要是由第一凹槽1014的内表面形状决定。
此时，该VSS走线105可以与辅助电路103进行相同设置，以提高VSS走线105的耐弯折性。即，该VSS走线105可以设置于辅助电路103上。并且，处于弯折区1011a的VSS走线105可以沿辅助电路103的上表面设置。
在一些实施例中，请参阅图3，该显示面板10还可以包括VSS走线105，该VSS走线105设置于辅助电路103上。该衬底层101可以包括依次层叠设置的衬底基板1012和第一绝缘层1013。在该衬底层101靠近辅助电路103的一侧可以设置一第二凹槽1015。需要说明的是，该第二凹槽1015设置于衬底层101的第一绝缘层1013上，且位于弯折区1011a。其中，在该第二凹槽1015中填充有有机层118。此时，辅助电路103可以沿衬底层101的表面和有机层118的表面设置。
该有机层118可以在显示面板10进行边缘曲面弯折时，可以起到一定的缓冲作用，有利于释放辅助电路103弯折时产生的应力，提高辅助电路103的耐弯折性，降低辅助电路103在弯折时出现断裂的几率。
为了进一步提高该辅助电路103和VSS走线105的耐弯折性。在一些实施例中，可以对处于弯折区1011a中的辅助电路103进行挖槽，形成若干第三凹槽1016。该第三凹槽1016可以有利于辅助电路103和VSS走线105的应力释放。
在一些实施例中，请参阅图4，该显示面板10还可以包括VSS走线105，该VSS走线设置于辅助电路103上。该衬底层101可以包括依次层叠设置的衬底基板1012和第一绝缘层1013。在辅助电路103上可以设置一贯穿辅助电路103和第一绝缘层1013的第四凹槽1017。该第四凹槽1017可以有利于VSS走线105和辅助电路103的应力释放。
为了进一步提高该辅助电路103和VSS走线105的耐弯折性。可以在该第四凹槽1017内可以填充有有机材料，以形成一有机层1018。该有机层1018可以有利于辅助电路103和VSS走线105的应力释放。
为了提高辅助电路103和VSS走线105的耐弯折性。在一些实施例中，可以对辅助电路103和VSS走线105进行耐弯折设计。在一些实施例中，可以将辅助电路103和VSS走线105设计为如图5所示的单排孔走线、如图6所示的多排孔走线、如图7所示的波浪形走线或弯折形走线。需要说明的是，辅助电路103或VSS走线105中的孔洞以及波浪形状或弯折形状包括但不限于图示。
具体的，可以利用掩膜在衬底层101上形成单排孔或多排孔的辅助电路103；利用掩膜在辅助电路103上形成单排孔走线或多排孔走线的VSS走线105。或者将衬底层101上的辅助电路103设置为波浪形走线；将辅助电路103上的VSS走线105设置为波浪形走线。将辅助电路103和VSS走线105设计为单排孔走线、多排孔走线或波浪形走线可以有利于辅助电路103和VSS走线105的弯折。
在一些实施例中，为了提高工艺制程效率。可以将辅助电路103位于弯折区1011a的辅助电路走线计为单排孔走线、多排孔走线、波浪形走线或弯折形走线。而弯折区1011a之外的辅助电路走线则可以使用常规设置。
同理，可以将位于弯折区1011a的VSS走线105设计为单排孔走线、多排孔走线、波浪形走线或弯折形走线。而弯折区1011a之外的VSS走线105则可以使用常规设置。
可以理解的是，辅助电路103和VSS走线105之间具有第二绝缘层106。该第二绝缘层106可以隔离辅助电路103和VSS走线105，以避免辅助电路103与VSS走线105短接而导致短路。
请参阅图1，本申请实施例提供的显示面板10还可以包括平坦化层107、阳极层108和阴极层109。
其中，平坦化层107覆盖于薄膜晶体管层102、VSS走线105和衬底层101上。并且，在该平坦化层107上设置有一暴露VSS走线105的通孔1071。
其中，阳极层108设置于平坦化层107上。并且，该阳极层108通过通孔1071与VSS走线105相连。
其中，阴极层109位于平坦化层107和部分阳极层108之上。并且，该阴极层109与阳极层108相连。
需要说明的是，阴极层109的厚度比阳极层108的厚度小，因此阴极层109的耐弯折性比阳极层108的耐弯折性好。
为了避免由于显示面板10弯折时，阳极层108发生断裂导致VSS走线105与该显示面板10的显示区连接失败，进而影响显示面板10的显示效果。请参阅图8，在一些实施例中，可以将该显示面板10中的阳极层108去除，由阴极层109直接与VSS走线105相连。
此时，该阴极层109位于平坦化层107之上。并且，该阴极层109通过通孔1071与VSS走线105相连。
由于阴极层109的耐弯折性比阳极层108的耐弯折性好。因此，当去除阳极层108，直接由阴极层109通过通孔1071与VSS走线105相连时，相比于由阳极层108与VSS走线105相连，可以降低由于断裂导致VSS走线105与显示区连接失败，影响显示面板10的显示效果。
并且，将阴极层109直接与VSS走线105相连，相比于阴极层109通过阳极层108与VSS走线105相连，可以减小VSS走线105的接触电阻。而VSS走线105的接触电阻减小，可以减小VSS走线105的压降。从而提高显示面板10的发光均匀性。
请参阅图1或图8，该显示面板10还可以包括其他功能层110、第一封装层111、第二封装层112、第三封装层113、像素定义层114和挡墙115。
其中，像素定义层114设置于挡墙115和GOA驱动电路104上。其他功能层110设置于阳极层108或阴极层109上。第一封装层111覆盖于AMOLED功能层110、像素定义层114、挡墙115、平坦化层107、GOA驱动电路104和衬底层101上。第二封装层112设置于第一封装层111上。第三封装层113覆盖于第二封装层112、第一封装层111和衬底层101上。
需要说明的是，第一封装层111和第三封装层113为无机封装层。第二封装层112为有机封装层。
可以理解的是，由于GOA驱动电路104的侧边容易被腐蚀。因此，可以在该GOA驱动电路104的外侧设置一紧贴GOA驱动电路的挡墙115。即，挡墙115紧贴并环绕GOA驱动电路104设置，以避免GOA驱动电路104的侧边被腐蚀，进而影响该GOA驱动电路104的性能。需要说明的是，该挡墙115的厚度大于GOA驱动电路104的厚度。
在本申请实施例中，该显示面板10还可以包括裂纹检测电路116和裂纹防护装置117。
该裂纹检测电路116设置于衬底层101上，可以用于检测该显示面板10是否出现裂纹。需要说明的是，薄膜晶体管层102、辅助电路103、GOA驱动电路104、位于同一侧，而该裂纹检测电路116位于另一侧。并且，该裂纹检测电路116位于第一封装层111内。
该裂纹防护装置117设置于衬底层101上，可以用于防止该显示面板10出现裂纹。需要说明的是，该裂纹防护装置117位于第三封装层113之外。
由上可知，本申请实施例提供的显示面板10通过将辅助电路103设置于薄膜晶体管层102与GOA驱动电路104之间，可以减小该显示面板10的边框。并且，辅助电路103设置于衬底层101的弯折区1011a内，可以增加辅助电路103的耐弯折性，进而提高显示面板10的耐弯折性。
本申请实施例还提供了一种显示装置，该显示装置1可以包括上述实施例提供的显示面板10。如图9所示，该显示装置1可以包括显示区2和非显示区3。需要说明的是，显示面板10中的薄膜晶体管层102的发光区位于显示区域2，除该薄膜晶体管层102的发光区之外的辅助电路103、弯折区1011a和GOA驱动电极104等膜层结构均位于非显示区3。
请参阅图10，图10为本申请实施例提供的显示装置的另一结构示意图。该显示装置1可以包括上述实施例中的显示面板10。需要说明的是，薄膜晶体管层102包括于显示区域2内。此时，辅助电路103位于显示区域2和GOA驱动电路104之间。并且，辅助电路103设置与弯折区1011a对应设置。在该弯折区1011a内有一切割边1011b。可以理解的是，此时该显示装置1的边框为切割边1011b至显示区域2的距离。而在现有技术中，则是将GOA驱动电路104设置于辅助电路103和显示区域2之间。因此，本方案可以减小显示装置1的边框。
由上，本申请实施例提供的显示装置1的边框较小，可以满足用户的需求，提高用户体验。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种显示面板和显示装置进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种显示面板，其包括：
    衬底层；
    薄膜晶体管层，所述薄膜晶体管层设置于所述衬底层上，且在所述衬底层上临近所述薄膜晶体管层的至少一侧设置有弯折区；
    GOA驱动电路，所述GOA驱动电路设置于所述衬底层上，且位于所述薄膜晶体管层的至少一侧，所述GOA驱动电路与所述薄膜晶体管层之间设置有所述弯折区；
    辅助电路，所述辅助电路设置于所述衬底层上且与所述弯折区对应设置；
    其中，所述GOA驱动电路通过所述辅助电路与所述薄膜晶体管层中的栅极走线相连接。
  2. 如权利要求1所述的显示面板，其中，所述衬底层包括依次层叠设置的衬底基板和第一绝缘层；
    在所述衬底层靠近所述辅助电路的一侧设置有若干第一凹槽，所述第一凹槽设置于所述第一绝缘层上，且位于所述弯折区。
  3. 如权利要求2所述的显示面板，其中，所述辅助电路沿所述衬底层的表面和所述第一凹槽的内表面设置。
  4. 如权利要求1所述的显示面板，其中，所述衬底层包括依次层叠设置的衬底基板和第一绝缘层；
    在所述衬底层靠近所述辅助电路的一侧设置有第二凹槽，所述第二凹槽设置于所述第一绝缘层上，且位于所述弯折区，其中，所述第二凹槽中填充有有机层。
  5. 如权利要求4所述的显示面板，其中，所述辅助电路沿所述衬底层的表面和所述有机层的表面设置。
  6. 如权利要求1所述的显示面板，其中，所述辅助电路包括多条连接所述GOA驱动电路和所述薄膜晶体管层中的栅极走线的辅助电路走线；
    所述辅助电路走线在所述弯折区设置成单排孔走线、多排孔走线、波浪形走线或弯折形走线。
  7. 如权利要求1所述的显示面板，其中，所述显示面板还包括：
    VSS走线，所述VSS走线与所述弯折区对应设置，且所述VSS走线与所述辅助电路之间设置有第二绝缘层。
  8. 如权利要求7所述的显示面板，其中，所述显示面板还包括：
    平坦化层，所述平坦化层覆盖于所述薄膜晶体管层、VSS走线和衬底层上，在所述平坦化层上设置有一暴露所述VSS走线的通孔；
    阳极层，所述阳极层设置于所述平坦化层上，且通过所述通孔与所述VSS走线相连；
    阴极层，所述阴极层位于所述阳极层之上，且与所述阳极层相连。
  9. 如权利要求7所述的显示面板，其中，所述显示面板还包括：
    平坦化层，所述平坦化层覆盖于所述薄膜晶体管层、VSS走线和衬底层上，在所述平坦化层上设置有一暴露所述VSS走线的通孔；
    阴极层，所述阴极层位于所述平坦化层之上，且通过所述通孔与所述VSS走线相连。
  10. 如权利要求7所述的显示面板，其中，所述VSS走线在所述弯折区设置成单排孔走线、多排孔走线、波浪形走线或弯折形走线。
  11. 一种显示装置，包括一显示面板，其中，所述显示面板包括：
    衬底层；
    薄膜晶体管层，所述薄膜晶体管层设置于所述衬底层上，且在所述衬底层上临近所述薄膜晶体管层的至少一侧设置有弯折区；
    GOA驱动电路，所述GOA驱动电路设置于所述衬底层上，且位于所述薄膜晶体管层的至少一侧，所述GOA驱动电路与所述薄膜晶体管层之间设置有所述弯折区；
    辅助电路，所述辅助电路设置于所述衬底层上且与所述弯折区对应设置；
    其中，所述GOA驱动电路通过所述辅助电路与所述薄膜晶体管层中的栅极走线相连接。
  12. 如权利要求11所述的显示装置，其中，所述衬底层包括依次层叠设置的衬底基板和第一绝缘层；
    在所述衬底层靠近所述辅助电路的一侧设置有若干第一凹槽，所述第一凹槽设置于所述第一绝缘层上，且位于所述弯折区。
  13. 如权利要求12所述的显示装置，其中，所述辅助电路沿所述衬底层的表面和所述第一凹槽的内表面设置。
  14. 如权利要求11所述的显示装置，其中，所述衬底层包括依次层叠设置的衬底基板和第一绝缘层；
    在所述衬底层靠近所述辅助电路的一侧设置有第二凹槽，所述第二凹槽设置于所述第一绝缘层上，且位于所述弯折区，其中，所述第二凹槽中填充有有机层。
  15. 如权利要求14所述的显示装置，其中，所述辅助电路沿所述衬底层的表面和所述有机层的表面设置。
  16. 如权利要求11所述的显示装置，其中，所述辅助电路包括多条连接所述GOA驱动电路和所述薄膜晶体管层中的栅极走线的辅助电路走线；
    所述辅助电路走线在所述弯折区设置成单排孔走线、多排孔走线、波浪形走线或弯折形走线。
  17. 如权利要求11所述的显示装置，其中，所述显示面板还包括：
    VSS走线，所述VSS走线与所述弯折区对应设置，且所述VSS走线与所述辅助电路之间设置有第二绝缘层。
  18. 如权利要求17所述的显示装置，其中，所述显示面板还包括：
    平坦化层，所述平坦化层覆盖于所述薄膜晶体管层、VSS走线和衬底层上，在所述平坦化层上设置有一暴露所述VSS走线的通孔；
    阳极层，所述阳极层设置于所述平坦化层上，且通过所述通孔与所述VSS走线相连；
    阴极层，所述阴极层位于所述阳极层之上，且与所述阳极层相连。
  19. 如权利要求17所述的显示装置，其中，所述显示面板还包括：
    平坦化层，所述平坦化层覆盖于所述薄膜晶体管层、VSS走线和衬底层上，在所述平坦化层上设置有一暴露所述VSS走线的通孔；
    阴极层，所述阴极层位于所述平坦化层之上，且通过所述通孔与所述VSS走线相连。
  20. 如权利要求17所述的显示装置，其中，所述VSS走线在所述弯折区设置成单排孔走线、多排孔走线、波浪形走线或弯折形走线。
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