WO2021027673A1 - 一种体声波滤波器的封装结构及该滤波器的制造方法 - Google Patents

一种体声波滤波器的封装结构及该滤波器的制造方法 Download PDF

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WO2021027673A1
WO2021027673A1 PCT/CN2020/107341 CN2020107341W WO2021027673A1 WO 2021027673 A1 WO2021027673 A1 WO 2021027673A1 CN 2020107341 W CN2020107341 W CN 2020107341W WO 2021027673 A1 WO2021027673 A1 WO 2021027673A1
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Prior art keywords
chip
resonator
resonators
pin
acoustic wave
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PCT/CN2020/107341
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English (en)
French (fr)
Inventor
庞慰
蔡华林
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天津大学
诺思(天津)微系统有限责任公司
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Publication of WO2021027673A1 publication Critical patent/WO2021027673A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/02007—Details of bulk acoustic wave devices
    • H03H9/02015—Characteristics of piezoelectric layers, e.g. cutting angles
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/02007—Details of bulk acoustic wave devices
    • H03H9/02157—Dimensional parameters, e.g. ratio between two dimension parameters, length, width or thickness
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/10—Mounting in enclosures
    • H03H9/1007—Mounting in enclosures for bulk acoustic wave [BAW] devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/46—Filters
    • H03H9/54—Filters comprising resonators of piezoelectric or electrostrictive material

Definitions

  • the present invention relates to the technical field of filters, in particular to a packaging structure of a bulk acoustic wave filter and a method of manufacturing the filter.
  • the main purpose of the present invention is to provide a packaging structure of a bulk acoustic wave filter and a method for manufacturing the filter, which helps to reduce the size of the filter.
  • a packaging structure of a bulk acoustic wave filter is provided.
  • the bulk acoustic wave filter of the present invention includes: a first chip, a plurality of first resonators are arranged on the first chip, a plurality of the first resonators are connected in series to form a series circuit, and two adjacent first resonators
  • the first pin is connected to the line between the devices;
  • the second chip is provided with a plurality of second resonators, each of the second resonators is connected in series with an inductor, and each of the second resonators
  • One end of the inductor away from the inductor is provided with a second pin, and one end of the inductor away from the second resonator is provided with a ground pin;
  • the first chip and the second chip are superimposed to form a package structure In the inside of the packaging structure, the first pin and the second pin are bonded, so that a plurality of the first resonators and a plurality of the second resonators form a filter.
  • the packaging structure satisfies one or more of the following conditions: the thickness of the bottom electrode of the first resonator is different from the thickness of the bottom electrode of the second resonator; the piezoelectricity of the first resonator The thickness of the layer is different from the thickness of the piezoelectric layer of the second resonator; the thickness of the upper electrode of the first resonator is different from the thickness of the upper electrode of the second resonator.
  • the material of the piezoelectric layer of the first resonator is different from the material of the piezoelectric layer of the second resonator.
  • it further includes a first electrode provided on the first chip and a second electrode provided on the second chip, where the first electrode and the second electrode are positioned opposite to each other to form a capacitor.
  • the relative area and/or distance between the first electrode and the second electrode is set to make the capacitance value of the capacitor 0.005pF to 2pF.
  • the first chip is provided with a third pin
  • the second chip is provided with a fourth pin
  • the third pin and the fourth pin are used to communicate with the outside of the packaging structure.
  • the plate connection of the capacitor is provided with a third pin
  • the second chip is provided with a fourth pin
  • the third pin and the fourth pin are used to communicate with the outside of the packaging structure.
  • the first resonator and the second resonator satisfy one or both of the following conditions: the frequencies of the first resonator and the second resonator are different; the first resonance The electromechanical coupling coefficients of the second resonator and the second resonator are different.
  • the middle part is a plurality of the first resonators arranged in a row; on the layout of the second chip, the middle part is a plurality of resonators arranged in a row The second resonator.
  • a filter packaging method which is used to form the packaging structure of the bulk acoustic wave filter of the present invention.
  • the method is formed on the first surface of the first chip.
  • a plurality of second resonators, a plurality of second pins, and a ground pin are formed on the first surface, wherein each of the second resonators is connected to an inductor, and each of the inductors is connected in series to a Grounding pin;
  • the first surface of the first chip and the first surface of the second chip are arranged in parallel and opposed and then packaged to form the package structure, and the first pin and the second tube
  • the feet are bonded to form a filter.
  • multiple resonators in the filter are distributed on two chips, and the number of resonators on each chip is reduced compared with the prior art, that is, the resonator on each chip occupies
  • the area is reduced to achieve the purpose of reducing the size of the filter.
  • the area occupied by the resonator can be reduced to half of that in the prior art. Therefore, the filter with the package structure can help reduce the size of the filter.
  • FIG. 1 is a schematic diagram of a series-parallel resonator arranged on a chip in the prior art
  • Fig. 2 The impedance curve diagram of the filter in the prior art
  • Figure 3 is a schematic diagram of the first chip of the present invention.
  • Figure 4 is a schematic diagram of the second chip of the present invention.
  • Figure 5 is an impedance curve diagram of the filter of the present invention.
  • Fig. 6 is a comparison diagram of changes in electromechanical coupling coefficient of the filter of the present invention.
  • FIG. 7 is a schematic diagram of the capacitor of the present invention arranged in the packaging structure
  • FIG. 8 is a schematic diagram of the capacitor of the present invention arranged outside the packaging structure
  • Fig. 10 is a frequency-suppression curve diagram of the roll-off of the filter of the present invention.
  • Figure 11 is a comparison diagram of insertion loss of the filter of the present invention.
  • Fig. 12 is a flow chart of the packaging method of the filter of the present invention.
  • a packaging structure of a bulk acoustic wave filter in an embodiment of the present invention includes a first chip 1 and a second chip 2.
  • the first chip 1 is provided with a plurality of first resonators 11,
  • the first resonator 11 is connected in series to form a series circuit, the line between two adjacent first resonators 11 is connected to the first pin 12;
  • the second chip 2 is provided with a plurality of second resonators 21, each second The resonators 21 are connected in series with inductors, each second resonator 21 is provided with a second pin 22 at one end far away from the inductor, and the end of the inductor far away from the second resonator 21 is provided with a ground pin 23;
  • the first chip 1 It is superimposed with the second chip 2 to form a package structure.
  • the first pin 12 and the second pin 22 are bonded, so that a plurality of first resonators 11 and a plurality of second resonators 21 form a filter, That is, at this time, the first resonator 11 is a series resonator in the filter, and the second resonator 21 is a parallel resonator in the filter.
  • the first resonator 11 and the second resonator 21 are thin film bulk acoustic resonators.
  • the packaging structure of the bulk acoustic wave filter includes two chips.
  • a series-parallel resonator is provided on one chip, and the other chip is used for capping.
  • the area occupied by multiple resonators is large, and therefore, the area of the filter is larger; and the number of resonators cannot be reduced, so that the size of the filter cannot be reduced.
  • part of the resonators in the filter are arranged on another chip (that is, the second chip 2 described above) to reduce the number of resonators on each chip, so that each chip The occupied area of the upper resonator is reduced, so that the size of the chip can be reduced to achieve the purpose of reducing the volume of the filter.
  • series-parallel resonators When designing the filter, according to different roll-off requirements and passband matching characteristics and other indicators, series-parallel resonators will choose different electromechanical coupling coefficients and frequencies; in high-bandwidth designs, high electromechanical coupling coefficients and larger series-parallel frequencies The difference is necessary.
  • the series-parallel resonator is arranged on a chip. From the perspective of process realization, in order to ensure the flatness of each layer on the chip, the thickness of the lower electrode and the piezoelectric layer need to be the same, and only on the upper electrode Achieve different thicknesses for frequency shifting. Therefore, the frequency difference between series and parallel is limited.
  • the solid line in the figure is the impedance curve corresponding to the series resonator, and the dashed line is the impedance curve corresponding to the parallel resonator.
  • the frequency difference between series and parallel resonators is relatively small, especially the frequency of parallel resonators; at the same time, since the piezoelectric layer has the same thickness and is of the same material, the electromechanical coupling coefficients of the series and parallel resonators are also the same. Therefore, the filter with the existing structure has the problems of small frequency difference, the same electromechanical coupling coefficient, and poor performance.
  • the first resonator 11 and the second resonator 21 satisfy one or more of the following conditions: the frequencies of the first resonator 11 and the second resonator 21 are different; the first resonator 11 and the second resonator 21 The electromechanical coupling coefficient of the resonator 21 is different.
  • the thickness of the bottom electrode, piezoelectric layer and top electrode on different chips can be different, that is, the package structure meets the following conditions
  • a larger range of frequency difference can be achieved on the first chip 1 and the second chip 2.
  • the materials of the piezoelectric layer on the first chip 1 and the second chip 2 can also be different.
  • the series-parallel resonators have different electromechanical coupling coefficients, and there can be more types of resonator performance, so as to achieve the purpose of improving filter performance.
  • the dashed line and the solid line are the frequency-suppression curve in the prior art and the embodiments of the present invention respectively.
  • Additional capacitors are used in the filter to adjust the out-of-band zero point (notch) of the ground inductance to ensure higher suppression in the required frequency band.
  • Existing filters are generally realized by layout structure, but the capacitance value realized by layout structure is limited, generally less than 0.1F.
  • the capacitance to ground needs to be used to compensate, so the inductance The amount will increase.
  • the increase in inductance will first increase the Fs (lower impedance of the resonator) and Fp (higher impedance of the resonator) of the resonator, thus worsening the roll-off.
  • the inductance is realized by the layout and substrate wiring, and the longer The wiring will introduce greater loss, so the insertion loss of the entire filter also has a certain degree of deterioration.
  • the filter further includes a capacitor 3, which is provided in the packaging structure, and the capacitor includes a first electrode provided on the first chip 1 and a second chip 2 On the second electrode, in the package structure, the first electrode and the second electrode oppose each other to form a capacitor 3.
  • the capacitance value of the capacitor 3 can be 0.005pF to 2pF.
  • the capacitance value of the capacitor 3 is adjusted according to the relative area and/or distance between the first electrode and the second electrode, and the relative value of the first chip 1 and the second chip 2 is adjusted during adjustment. Position, in this way, the capacitance value can be changed, and a larger capacitance can be formed. Therefore, the ground inductance can be as small as possible, thereby improving the roll-off and insertion loss performance.
  • the inductance value of the ground inductance is 0.05 nH to 2 nH, preferably 0.1 nH to 1 nH.
  • the arrangement of the capacitor 3 can also adopt another structural form. As shown in Fig. 8, the capacitor 3 is provided outside the package structure.
  • the first chip 1 is provided with a third pin 13 and the second chip 2 is provided with a fourth tube.
  • Pin 24, third pin 13 and fourth pin 24 are connected to capacitor 3.
  • the capacitor 3 is arranged outside the filter package structure, where the capacitor 3 can be arranged separately or integrated.
  • the capacitor 3 outside the package structure is integrated and arranged on the outer wall of the second chip 2. To reduce the size of the chip.
  • the solid line in the figure corresponds to the large coupling capacitor
  • the dashed line corresponds to the small coupling capacitor. Comparing the impact of the small coupling capacitor and the large coupling capacitor on the filter performance, it can be seen that the large coupling capacitor can achieve better out-of-band suppression.
  • the capacitance value is preferably 0.01 pF to 1 pF.
  • a large coupling capacitor corresponds to a smaller inductance to ground.
  • Using a smaller inductance can improve roll-off.
  • the definition of roll-off is that for the same suppression, the smaller the corresponding frequency difference, the better the roll-off.
  • the graph is the suppression curve on the right side of the passband.
  • the solid line is the improved performance, and the dashed line is the previous performance. It can be seen from the figure that for the same suppression (such as -60dB), the solid line corresponds to a lower frequency, that is, a smaller frequency can roll off to a certain suppression.
  • the first chip 1 is also provided with an input pin 14 and an output pin 15, which are respectively connected to the head end and the tail end of the series circuit.
  • the middle part is a plurality of first resonators 11 arranged in a row, and on both sides are input pins 14, output pins 15, and first pins 12;
  • the middle part is A plurality of second resonators 21 arranged in a row, on both sides are second pins 22 and ground pins 23.
  • the layout of the first chip 1 and the second chip 2 there is no specific position limitation on the position of each pin, and it can form a series-parallel resonator structure of the filter.
  • Adopting the packaging structure of the bulk acoustic wave filter in the embodiment of the present invention makes the layout of the resonators on the first chip 1 and the second chip 2 more reasonable, avoids additional area increase, and at the same time, it is easier to perform operations such as packaging and cutting, and work efficiency higher.
  • the embodiment of the present invention also provides a filter packaging method, as shown in FIG. 12, including the following steps:
  • a plurality of first resonators and a plurality of first pins are formed on the first surface of the first chip, wherein the plurality of first resonators are connected in series, and the first tubes are connected between adjacent first resonators foot;
  • each second resonator is connected to an inductor, and each inductor is connected in series Connect a ground pin;
  • S3 The first surface of the first chip and the first surface of the second chip are arranged in parallel and opposed to each other and then packaged to form a package structure, and the first pin and the second pin are bonded to form a filter.
  • the first chip includes the mounting position of the first pin; the second chip includes the mounting position of the second pin and the ground pin; after the first resonator and the second resonator are installed, the The first pin is set in the mounting position of one pin, and the second pin and ground pin are set in the mounting position of the second pin and the ground pin.
  • the first pin and the second pin are positive. Pair bonding connection.
  • the first resonator (series resonator) and the second resonator (parallel resonator) are respectively arranged on two chips. Therefore, when packaging, it is necessary to ensure that the first pin and the second pin are bonded to enable the first One resonator and the second resonator form a series-parallel circuit.
  • the mounting positions are set at the designated positions of the first chip and the second chip, and after the first pin/second pin is set on the mounting position, when the package is mated, the two can be set directly opposite to ensure the key The accuracy of the combination.

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  • Physics & Mathematics (AREA)
  • Acoustics & Sound (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)

Abstract

本发明涉及滤波器技术领域，特别地涉及一种体声波滤波器的封装结构及方法，该封装结构，包括第一芯片，第一芯片上设置多个第一谐振器，多个第一谐振器串联形成串联电路，相邻的两个第一谐振器之间的线路上连接第一管脚；第二芯片，第二芯片上设置多个第二谐振器，每个第二谐振器均串联电感器，每个第二谐振器的远离电感器的一端设有第二管脚，电感器远离第二谐振器的一端设有接地管脚；第一芯片和所述第二芯片叠加形成封装结构，在封装结构的内部，第一管脚和所述第二管脚键合，使多个第一谐振器和多个第二谐振器构成滤波器。本发明的技术方案，谐振器所占面积最高可缩小一半，采用本封装结构的滤波器，其尺寸与现有的滤波器相比最高可缩小30％。

Description

一种体声波滤波器的封装结构及该滤波器的制造方法 技术领域
本发明涉及滤波器技术领域，特别地涉及一种体声波滤波器的封装结构及该滤波器的制造方法。
背景技术
随着通信设备小型化和高性能趋势的加快，对射频前端提出了更高的要求。在射频通信前端中，滤波器和双工器以及多工器占据了较大的尺寸，因此缩小滤波器的尺寸迫在眉睫。现有的滤波器封装受芯片尺寸限制，不能进一步缩小，因此减小滤波器的芯片尺寸是缩小封装最根本的解决方案。
现有的滤波器，如图1所示，一般在一颗芯片上制造串联和并联谐振器，通过在并联谐振器上加质量负载来改变频率，并利用串联和并联谐振器的频率差来进行滤波器的设计。
发明内容
有鉴于此，本发明的主要目的是提供一种体声波滤波器的封装结构及该滤波器的制造方法，有助于缩小滤波器的尺寸。
为实现上述目的，根据本发明的一个方面，提供了一种体声波滤波器的封装结构。
本发明的体声波滤波器包括：第一芯片，所述第一芯片上设置多个第一谐振器，多个所述第一谐振器串联形成串联电路，相邻的两个所述第一谐振器之间的线路上连接第一管脚；第二芯片，所述第二芯片上设置多个第二谐振器，每个所述第二谐振器均串联电感器，每个所述第二谐振器的远离所述电感器的一端设有第二管脚，所述电感器 远离所述第二谐振器的一端设有接地管脚；所述第一芯片和所述第二芯片叠加形成封装结构，在所述封装结构的内部，所述第一管脚和所述第二管脚键合，使多个所述第一谐振器和多个所述第二谐振器构成滤波器。
可选地，所述封装结构满足以下条件中的一项或几项：所述第一谐振器下电极的厚度和所述第二谐振器下电极的厚度不同；所述第一谐振器压电层的厚度和所述第二谐振器压电层的厚度不同；所述第一谐振器上电极的厚度和所述第二谐振器上电极的厚度不同。
可选地，所述第一谐振器压电层的材料和所述第二谐振器压电层的材料不同。
可选地，还包括设于所述第一芯片上的第一电极，以及设于所述第二芯片上的第二电极，所述第一电极和所述第二电极位置相对从而形成电容。
可选地，所述第一电极和所述第二电极之间的相对面积和/或距离被设置为使所述电容的电容值为0.005pF到2pF。
可选地，所述第一芯片设有第三管脚，所述第二芯片设有第四管脚，所述第三管脚和所述第四管脚用于与所述封装结构之外的电容的极板连接。
可选地，所述第一谐振器和所述第二谐振器满足以下条件中的一项或两项：所述第一谐振器和所述第二谐振器的频率不同；所述第一谐振器和所述第二谐振器的机电耦合系数不同。
可选地，在所述第一芯片的版图上，中部是呈1行排列的多个所述第一谐振器；在所述第二芯片的版图上，中部是呈1行排列的多个 所述第二谐振器。
根据本发明的另一个方面，提供了一种滤波器的封装方法，所述方法用于形成本发明中的体声波滤波器的封装结构，该方法中，在第一芯片的第一表面上形成多个第一谐振器和多个第一管脚，其中，多个所述第一谐振器串联连接，相邻的所述第一谐振器之间连接所述第一管脚；在第二芯片的第一表面上形成多个第二谐振器、多个第二管脚和接地管脚，其中，每个所述第二谐振器均连接电感器，每个所述电感器串联连接一所述接地管脚；将所述第一芯片的第一表面和所述第二芯片的第一表面平行相对设置然后封装以形成所述封装结构，并且将所述第一管脚和所述第二管脚键合从而构成滤波器。
根据本发明的技术方案，将滤波器中的多个谐振器分布到两块芯片上，与现有技术相比每块芯片上的谐振器的数量均减少，即每块芯片上的谐振器占用面积减少，从而达到缩小滤波器尺寸的目的，其中，谐振器所占面积最高可缩小至现有技术中的一半，因此，采用本封装结构的滤波器，有助于缩小滤波器的尺寸。
附图说明
为了说明而非限制的目的，现在将根据本发明的优选实施例、特别是参考附图来描述本发明，其中：
图1现有技术中一颗芯片上设置串并联谐振器的示意图；
图2现有的技术中滤波器的阻抗曲线图；
图3是本发明第一芯片的示意图；
图4是本发明第二芯片的示意图；
图5是本发明滤波器的阻抗曲线图；
图6是本发明滤波器机电耦合系数变化对比图；
图7是本发明电容设于封装结构之内的示意图；
图8是本发明电容设于封装结构之外的示意图；
图9是本发明滤波器大耦合电容和小耦合电容性能对比图；
图10是本发明滤波器的滚降的频率-抑制曲线图；
图11是本发明滤波器的插损对比图；
图12是本发明滤波器的封装方法的流程框图。
图中：
1：第一芯片；2：第二芯片；3：电容；11：第一谐振器；12：第一管脚；13：第三管脚；14：输入管脚；15：输出管脚；21：第二谐振器；22：第二管脚；23：接地管脚；24：第四管脚。
具体实施方式
如图3-11所示，本发明实施方式中的一种体声波滤波器的封装结构包括第一芯片1和第二芯片2，第一芯片1上设置多个第一谐振器11，多个第一谐振器11串联形成串联电路，相邻的两个第一谐振器11之间的线路上连接第一管脚12；第二芯片2上设置多个第二谐振器21，每个第二谐振器21均串联电感器，每个第二谐振器21的远离电感器的一端设有第二管脚22，电感器远离第二谐振器21的一端设有接地管脚23；第一芯片1和第二芯片2叠加形成封装结构，在封装结构的内部，第一管脚12和第二管脚22键合，使多个第一谐振器11和多个第二谐振器21构成滤波器，即此时第一谐振器11为滤波器中的串联谐振器，第二谐振器21为滤波器中的并联谐振器。其中，第一谐振器11和第二谐振器21为薄膜体声波谐振器。
在体声波滤波器的封装结构中包括两颗芯片，现有技术中，一颗芯片上设置串并联谐振器，另一颗芯片用于封盖。多个谐振器占用的面积大，因此，导致滤波器的面积较大；而谐振器的数量无法减少，导致滤波器的尺寸无法减小。
而在本发明实施例的技术方案中，将滤波器中的部分谐振器设置在另外一颗芯片上(即上述第二芯片2)，以减少每颗芯片上的谐振器数量，使每颗芯片上谐振器的占用面积减少，从而可缩小芯片的尺寸，达到缩小滤波器体积的目的。
如图1所示，现有的滤波器结构中，一颗芯片上设置五个串联谐振器和四个并联谐振器，共9个谐振器。采用本实施例技术方案，如 图3所示，第一芯片1上设置五个串联的第一谐振器11，如图4所示，第二芯片2上设置四个并联的第二谐振器21，第一芯片1和第二芯片2的面积与现有技术中的芯片的面积相比缩小近30％。
滤波器设计时，根据不同的滚降要求以及通带匹配特性等指标，串并联谐振器会选择不同的机电耦合系数及频率；高带宽设计中，高的机电耦合系数以及较大的串并联频率差则是必要的。
现有技术中，串并联谐振器设置在一颗芯片上，从工艺实现的角度考虑，为了保证芯片上每一层的平整度，需要下电极和压电层的厚度一致，只在上电极上实现不同的厚度来进行移频，因此，串并联的频率差有限，如图2所示，图中实线为串联谐振器对应的阻抗曲线，虚线为并联谐振器对应的阻抗曲线，由此图可以看出，串并联的频率差均较小，尤其是并联谐振器的频率；同时由于压电层厚度一致且是同种材料，串并联谐振器的机电耦合系数也相同。因此，现有结构的滤波器存在频率差小、机电耦合系数相同的问题，使用性能较差。
本实施例中，第一谐振器11和第二谐振器21满足以下条件中的一项或几项：第一谐振器11和第二谐振器21的频率不同；第一谐振器11和第二谐振器21的机电耦合系数不同。
当采用本发明技术方案中的在两颗芯片上分别设置串联谐振器和并联谐振器的结构时，不同芯片上的下电极，压电层以及上电极的厚度可以不同，即封装结构满足以下条件中的一项或几项：第一谐振器11下电极的厚度和第二谐振器21下电极的厚度不同；第一谐振器11压电层的厚度和第二谐振器21压电层的厚度不同；第一谐振器11上电极的厚度和第二谐振器21上电极的厚度不同。采用此结构，在第一芯片1和第二芯片2上可以实现更大范围的频率差。如图5所示，图中串联谐振器频率和并联谐振器频率均存在一定范围的频率差。
同时，第一芯片1和第二芯片2上压电层的材料也可以不同，串并联谐振器可是不同的机电耦合系数，谐振器性能可以有更多的种类，从而达到提升滤波器性能的目的。如图6所示，图中，虚线和实线分别是现有技术和本发明实施方式中的频率-抑制度曲线，当机电耦合系数增加变化自由度后，可以看到整体插损有一定的提升。
因此，采用两颗芯片均设置谐振器的结构形式，可以实现较大的频率差，以及不同的机电耦合系数，为滤波器设计提供了更多的灵活性，保证实现更好的性能，如匹配和带外抑制等性能。
滤波器中会使用额外的电容配合对地电感进行带外零点(notch)的调节，以此保证在需要的频段有较高的抑制。
现有的滤波器中一般利用版图结构来实现，但版图结构实现的电容值有限，一般小于0.1F，对于固定频率的notch，电容较小的情况下需要用对地的电感来弥补，因此电感量会增大。电感量增大首先会拉大谐振器的Fs(谐振器阻抗较低点)和Fp(谐振器阻抗高点)，因此会恶化滚降，同时电感由版图和基板走线来实现，更长的走线会引入更大的损耗，因此整个滤波器的插损也有一定程度的恶化。
本实施例的技术方案中，如图7所示，滤波器还包括电容3，电容3设于封装结构内，电容包括设于第一芯片1上的第一电极，以及设于第二芯片2上的第二电极，在封装结构中，第一电极和第二电极相对形成电容3。电容3的电容值可以为0.005pF到2pF，根据第一电极和第二电极之间的相对面积和/或距离调整电容3的电容值，调整时调节第一芯片1和第二芯片2的相对位置，通过此种方式能改变电容值的大小，可形成较大的电容，因此，对地电感可以尽量小，从而改善了滚降和插损等性能。对地电感的电感值为0.05nH至2nH，优选地为0.1nH至1nH。
电容3的布置还可采用另外一种结构形式，如图8所示，电容3设于封装结构外，第一芯片1上设有第三管脚13，第二芯片2上设有第四管脚24，第三管脚13和第四管脚24与电容3连接。此结构中将电容3设置在滤波器封装结构之外，其中，电容3可分立原件设置，也可是集成设置，优选地，封装结构之外的电容3，集成设置在在第二芯片2的外壁上，以缩小芯片体积。
如图9所示，图中实线对应大耦合电容，虚线对应小耦合电容，对比小耦合电容和大耦合电容对滤波器性能的影响，可以看出大耦合电容能够实现更好的带外抑制。电容值优选为0.01pF到1pF。
对于相同的带外零点位置，大耦合电容对应更小的对地电感，采 用小的电感可以改善滚降。滚降的定义是对于相同的抑制，对应的频率差越小滚降越好。如图10所示，该图是通带右侧的抑制曲线，实线是改善后的，虚线是之前的性能。从该图可以看出，对于相同的抑制(比如-60dB)，实线对应的频率更低，也就是较小的频率内可以滚降到一定的抑制。
采用更小的电感减少了电感的感值，感值小对应的Q值更高，因此损耗更小，所以插损性能越好，如图11所示，图中实线和虚线分别是改善之后和改善之前的性能。
作为本发明的优选实施方式，如图3和图4所示，第一芯片1上还设有输入管脚14和输出管脚15，分别连接串联电路的首端和尾端，在第一芯片1的版图上，中部是成1行排列的多个第一谐振器11，两侧是输入管脚14、输出管脚15和第一管脚12；在第二芯片2的版图上，中部是成1行排列的多个第二谐振器21，两侧是第二管脚22和接地管脚23。在第一芯片1和第二芯片2的版图上，对各管脚的位置并没有具体位置的限定，其能够形成滤波器的串并联谐振器结构即可。
采用本发明实施方式中的体声波滤波器的封装结构，使第一芯片1和第二芯片2上的谐振器布局更加合理，避免额外增加面积，同时，更易进行封装、切割等操作，工作效率更高。
本发明实施方式中还提供一种滤波器的封装方法，如图12所示，包括以下步骤：
S1：在第一芯片的第一表面上形成多个第一谐振器和多个第一管脚，其中，多个第一谐振器串联连接，相邻的第一谐振器之间连接第一管脚；
S2：在第二芯片的第一表面上形成多个第二谐振器、多个第二管脚和多个接地管脚，其中，每个第二谐振器均连接电感器，每个电感器串联连接一接地管脚；
S3：将第一芯片的第一表面和第二芯片的第一表面平行相对设置然后封装以形成封装结构，并且将第一管脚和第二管脚键合从而构成滤波器。
本实施例中，第一芯片上包括第一管脚的安装位；第二芯片上包 括第二管脚及接地管脚的安装位；第一谐振器和第二谐振器设置完成后，在第一管脚的安装位设置第一管脚，在第二管脚及接地管脚的安装位设置第二管脚及接地管脚，其中，对接封装时，第一管脚和第二管脚正对键合连接。
第一谐振器(串联谐振器)和第二谐振器(并联谐振器)分别设置在两颗芯片上，因此，在封装时，需要确保第一管脚和第二管脚键合，才能使第一谐振器和第二谐振器形成串并联电路。本实施例中，在第一芯片和第二芯片的指定位置设置安装位，安装位上设置第一管脚/第二管脚后，对接封装时时，两者能正对设置，进而可确保键合的精准性。
上述具体实施方式，并不构成对本发明保护范围的限制。本领域技术人员应该明白的是，取决于设计要求和其他因素，可以发生各种各样的修改、组合、子组合和替代。任何在本发明的精神和原则之内所作的修改、等同替换和改进等，均应包含在本发明保护范围之内。

Claims (9)

  1. 一种体声波滤波器的封装结构，其特征在于，包括：
    第一芯片，所述第一芯片上设置多个第一谐振器，多个所述第一谐振器串联形成串联电路，相邻的两个所述第一谐振器之间的线路上连接第一管脚；
    第二芯片，所述第二芯片上设置多个第二谐振器，每个所述第二谐振器均串联电感器，每个所述第二谐振器的远离所述电感器的一端设有第二管脚，所述电感器远离所述第二谐振器的一端设有接地管脚；
    所述第一芯片和所述第二芯片叠加形成封装结构，在所述封装结构的内部，所述第一管脚和所述第二管脚键合，使多个所述第一谐振器和多个所述第二谐振器构成滤波器。
  2. 根据权利要求1所述的体声波滤波器的封装结构，其特征在于，所述封装结构满足以下条件中的一项或几项：
    所述第一谐振器下电极的厚度和所述第二谐振器下电极的厚度不同；
    所述第一谐振器压电层的厚度和所述第二谐振器压电层的厚度不同；
    所述第一谐振器上电极的厚度和所述第二谐振器上电极的厚度不同。
  3. 根据权利要求1所述的体声波滤波器的封装结构，其特征在于，所述第一谐振器压电层的材料和所述第二谐振器压电层的材料不同。
  4. 根据权利要求1所述的体声波滤波器的封装结构，其特征在于，还包括设于所述第一芯片上的第一电极，以及设于所述第二芯片上的第二电极，所述第一电极和所述第二电极位置相对从而形成电容。
  5. 根据权利要求4所述的体声波滤波器的封装结构，其特征在于， 所述第一电极和所述第二电极之间的相对面积和/或距离被设置为使所述电容的电容值为0.005pF到2pF。
  6. 根据权利要求1所述的体声波滤波器的封装结构，其特征在于，所述第一芯片设有第三管脚，所述第二芯片设有第四管脚，所述第三管脚和所述第四管脚用于与所述封装结构之外的电容的极板连接。
  7. 根据权利要求1所述的体声波滤波器的封装结构，其特征在于，所述第一谐振器和所述第二谐振器满足以下条件中的一项或两项：
    所述第一谐振器和所述第二谐振器的频率不同；
    所述第一谐振器和所述第二谐振器的机电耦合系数不同。
  8. 根据权利要求1所述的体声波滤波器的封装结构，其特征在于，在所述第一芯片的版图上，中部是呈1行排列的多个所述第一谐振器；在所述第二芯片的版图上，中部是呈1行排列的多个所述第二谐振器。
  9. 一种滤波器的制造方法，其特征在于，所述方法用于形成权利要求1至8中任一项所述的体声波滤波器的封装结构，该方法包括：
    在第一芯片的第一表面上形成多个第一谐振器和多个第一管脚，其中，多个所述第一谐振器串联连接，相邻的所述第一谐振器之间连接所述第一管脚；
    在第二芯片的第一表面上形成多个第二谐振器、多个第二管脚和多个接地管脚，其中，每个所述第二谐振器均连接电感器，每个所述电感器串联连接一所述接地管脚；
    将所述第一芯片的第一表面和所述第二芯片的第一表面平行相对设置然后封装以形成所述封装结构，并且将所述第一管脚和所述第二管脚键合从而构成滤波器。
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