WO2021027169A1 - 一种tft阵列基板及其显示面板 - Google Patents

一种tft阵列基板及其显示面板 Download PDF

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WO2021027169A1
WO2021027169A1 PCT/CN2019/119059 CN2019119059W WO2021027169A1 WO 2021027169 A1 WO2021027169 A1 WO 2021027169A1 CN 2019119059 W CN2019119059 W CN 2019119059W WO 2021027169 A1 WO2021027169 A1 WO 2021027169A1
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layer
metal layer
metal
tft array
array substrate
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PCT/CN2019/119059
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English (en)
French (fr)
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明星
曹中涛
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武汉华星光电半导体显示技术有限公司
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Priority to US17/262,752 priority Critical patent/US12096664B2/en
Publication of WO2021027169A1 publication Critical patent/WO2021027169A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED

Definitions

  • the present invention relates to the field of flat display technology, in particular, a TFT array substrate and a display panel thereof.
  • OLED Organic Light-Emitting Diode
  • the OLED display device also has a particularly important characteristic, namely, bendability.
  • This bendable feature makes it an absolute advantage in portability, so it has become the focus of research and development in the industry.
  • the LTPS process it uses generally includes 10-15 processes, which is 2-3 more Mask process steps than rigid AMOLED.
  • the additional process steps are mainly to etch the inorganic thin film functional layer with poor stress and poor flexibility in the non-displayed bending area by photolithography and Dry process to form two deep holes (DH1 , DH2), and then fill the deep hole with a flexible organic PI material to form a filling layer (OILD), which is beneficial to its bending characteristics.
  • the TFT array substrate defines a display area 100' and a bending area 110'.
  • the display area 100' is provided with a normal TFT device functional layer
  • the bending area 110' is provided with a data line (Data Line) and a Vdd line (Vdd Line).
  • Metal layer where the data wiring is generally implemented by the first metal layer (SD1) 104' used as the source and drain in the display area, and the Vdd wiring is generally implemented by the second metal layer (SD2) 106' To implement.
  • the filling layer 102' formed of the filled organic PI material will be first on the filled upper part.
  • the edge of the deep hole (DH1) covers a part of the area and forms a symmetrically arranged side end, that is, at the position of 130' in Figs. 5 and 7.
  • the current method adopted in the industry is to use the first metal layer (SD1) 104' as the second data trace of the bending area 110'
  • a transition part of the metal layer 104' is designed on the covering area of the side end of the OILD layer 102', and only one OILD hole is opened at the transition part.
  • the OILD layer 102' on both sides is provided with openings, which causes the middle to be higher here, which will cause bending The bending stress is difficult to release.
  • the first metal layer (SD1) 104' is subsequently etched, because the position is higher, the first metal layer 104' may be over-cut and broken. Refer to the circled part 150' in FIG. 8 for the specific location.
  • One aspect of the present invention is to provide a TFT array substrate whose bending area adopts a new metal layer wiring structure design, which prevents the wiring of the first metal layer in the bending area from passing through the two holes of the OILD filling layer Between the openings, thereby effectively reducing the risk of subsequent disconnection due to excessive etching.
  • a TFT array substrate is defined with a display area and a bending area. It includes a substrate layer and a functional layer disposed thereon, wherein the functional layer includes an insulating layer and a metal layer.
  • the functional layer of the bending zone is provided with a filling layer through a deep hole, wherein the filling layer also extends from the side end of the upper opening to the side end of the deep hole edge, so
  • the metal layer includes a first metal layer, a second metal layer, and a second gate layer in the bending area, wherein the second gate layer, the first metal layer, and the second metal layer are provided with the The insulating layer in the functional layer.
  • the first metal layer is disposed on the side end of the filling layer, and is connected to the second gate layer through a via hole; wherein the second metal layer is disposed on the first metal layer On the outer side of the insulating layer.
  • the metal layer further includes a first gate layer in the bending area, and a gate insulating layer is provided between the first gate layer and the second gate layer
  • the insulating layer provided between the second gate layer and the first metal layer is an interlayer dielectric layer.
  • the interlayer dielectric layer may be a double-stacked structure, that is, it includes a first interlayer dielectric layer and a second interlayer dielectric layer, wherein the second gate layer and the first metal
  • the insulating layer spaced between the layers is usually the second interlayer dielectric layer, but is not limited to.
  • the insulating layer provided between the first metal layer and the second metal layer is a first flat layer, and the bottom of the filling layer side end covers the interlayer dielectric layer. Partial.
  • the second metal layer is connected to the first gate layer through a via hole.
  • a transition metal layer is further provided between the second metal layer and the first gate layer, and the second metal layer communicates with the transition metal layer through a via hole. Connected, the transition metal layer is connected to the first gate layer through a via hole.
  • the transition metal layer is preferably a first metal layer formed when the first metal layer is patterned.
  • the functional layer of the bending area further includes a buffer layer, the buffer layer is disposed on the substrate layer, and the filling layer penetrates the buffer layer downward to enter The substrate layer.
  • the substrate layer includes a PI layer and a barrier layer disposed thereon, and the bottom of the filling layer passes through the barrier layer to the surface of the PI layer.
  • the insulating layer between the first metal layer and the second metal layer in the bending area is a first flat layer, and the second metal layer is also covered with a first flat layer. Two flat layers.
  • another aspect of the present invention provides a display panel including the TFT array substrate related to the present invention.
  • the display panel is a flexible AMOLED display panel.
  • the beneficial effect of the present invention is: the TFT array substrate of the present invention adopts a new type of wiring structure in the bending area, and the original first metal layer and the original second metal layer are exchanged.
  • the original wiring position of the first metal layer in the bending area is changed to the original wiring position of the second metal layer, so that the position is occupied by the first flat layer
  • FIG. 1 is a cross-sectional structure diagram of a TFT array substrate provided in an embodiment of the present invention
  • FIG. 2 is a plan structure diagram of the TFT array substrate shown in FIG. 1, in which only the plan structure of the bending area is shown;
  • Figure 3 is a sectional view taken along line A-A of Figure 2;
  • Figure 4 is a sectional view taken along line B-B of Figure 2;
  • FIG. 5 is a cross-sectional structure diagram of a TFT array substrate involved in the prior art at the position of its first metal layer;
  • FIG. 6 is a schematic cross-sectional view of the TFT array substrate shown in FIG. 5 at the position of the second metal layer;
  • FIG. 7 is a plan structure diagram of the TFT array substrate shown in FIG. 5, in which only the plan structure of the bending area is shown;
  • Fig. 8 is a cross-sectional view taken along the line A'-A' of Fig. 7;
  • an embodiment of the present invention provides a TFT array substrate, which defines a display area 100 and a bending area 110.
  • the TFT array substrate includes a substrate layer 101, and the substrate layer 101 may specifically adopt a dual PI substrate structure, that is, a dual stack structure design of a PI layer combined with a barrier layer (Barrier), but is not limited to.
  • a buffer layer (Buffer) 1011 is provided on the substrate layer 101.
  • the buffer layer 1011 is provided with a TFT device functional layer, including a metal layer and an insulating layer, wherein the metal layer specifically includes an active layer (Active) 103, a first gate layer (GE1) ) 105, a second gate layer (GE2) 107, and a first metal layer (SD1) 104 used as a source and drain layer.
  • the insulating layer is arranged between different metal layers, which specifically includes a first gate insulating layer (GI1) 1031, a second gate insulating layer (GI2) 1032, a first interlayer dielectric layer (ILD1) 1051, and a second Interlayer dielectric layer (ILD2) 1071.
  • these metal layers and insulating layers can adopt a single-layer or stacked-layer structure as required.
  • a passivation layer PV may be further provided on the first metal layer 104 to protect the first metal layer 104 from the intrusion of external water vapor, and the problem of reduced service life due to the intruding water vapor may arise.
  • the second interlayer dielectric layer 1071 is further provided with a first flat layer (PLN1) 1091 and a second flat layer (PLN1) 1092, and a second metal layer (SD2) 106 and an anode are provided in the two flat layers.
  • the second metal layer 106 is connected to the anode metal layer 109 through a via hole, and the second metal layer 106 is also connected to the first metal layer 104 through a via hole.
  • the buffer layer 1011 provided on the substrate layer 101 is provided with a filling layer (OILD) 102, which is filled with an organic material, specifically an organic PI material, so as to better realize the bending at this position.
  • OILD filling layer
  • the filling layer 102 penetrates the second interlayer dielectric layer (ILD2) 1071, the first interlayer dielectric layer (ILD1) 1051, and the second gate insulating layer ( GI2) 1032 and the first gate insulating layer (GI1) 1031 and pass through the buffer layer 1011 down to the substrate layer 101, specifically through the barrier layer in the substrate layer 101 to reach its PI layer The surface, but not limited to.
  • the filling layer 102 is formed by filling the deep hole (DH), it is not limited to the filling structure in the hole. It has an upper opening 1022 formed on the surface of the original deep hole, and then at the side edge of the original deep hole. There are also two symmetrically arranged side end portions 1021 that cover the interlayer functional layer below it protruding outward, wherein the side end portions 1021 are provided on the second interlayer dielectric layer (ILD2) 1071, and The side end 1021 and the upper opening 1022 can be filled by the first flat layer 1091.
  • DH deep hole
  • a metal layer is also provided in the bending area for use as a data line (Data Line) or a Vdd line (Vdd Line), which includes a first gate layer, a second gate layer, The first metal layer and the second metal layer, and the specific wiring position relationship between these metal layers will be described separately below.
  • the positional relationship between the first metal layer and the second metal layer in the bending area 110 is also an important aspect of the present invention. The following will focus on it in conjunction with the diagram.
  • the first metal layer 1040 in the bending area provided in the bending area is generally used for data wiring.
  • the present invention adopts a transposition design.
  • the solution is that the wiring position of the first metal layer is changed and set to the wiring position of the original second metal layer, and the wiring position of the original second metal layer is changed to the wiring position of the original first metal layer .
  • the first metal layer (SD1) 1050 of the bending area is provided on one side end 1021 of the filling layer 102 of the bending area, which is also The inner side extends into the upper opening 1022 of the filling layer; and it is electrically connected to the second gate layer 1070 in the bending area through a via hole, and a bending area is provided on the outer side of the first metal layer 1040 in the bending area
  • the second metal layer 1060 is electrically connected to the first gate layer 1050 in the bending area through a transition first metal layer 1041 downward through the second metal layer 1060 in the bending area.
  • the metal layers arranged in the bending area 110 are arranged symmetrically along both sides of the filling layer 102.
  • the positional relationship between the first metal layer 1040 and the second metal layer 1060 in the bending area is converted, so that the wiring position of the first metal layer is changed and set to the position of the original second metal layer.
  • the original wire position of the second metal layer is changed to the original wire position of the first metal layer.
  • the first metal layer and the second metal layer are arranged with an upper and lower interval between the layers, and when the positions of the two are interchanged, there will be no OILD openings on the trace side of the first metal layer , There will be no problem that the position between the two holes is too high, thereby effectively reducing the risk of over-cutting and breaking.
  • another embodiment of the present invention provides a display panel which uses the TFT array substrate related to the present invention.

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Abstract

一种TFT阵列基板，定义有显示区（100）和弯折区（110），其包括衬底层（101）和设置于其上的功能层，功能层中包括有绝缘层和金属层；金属层在弯折区（110）包括第一金属层（104）、第二金属层（106）和第二栅极层（107）；第一金属层（104）设置在填充层（102）的侧端部上，并通过过孔与第二栅极层（107）相接；第二金属层（106）设置在位于第一金属层（104）的外侧位置的绝缘层上。

Description

一种TFT阵列基板及其显示面板 技术领域
本发明涉及平面显示技术领域，尤其是，其中的一种TFT阵列基板及其显示面板。
 背景技术
已知，随着显示技术的不断发展，平面显示装置已逐渐成为市场上的主流显示装置。这其中，业界开发出的OLED（Organic Light-Emitting Diode）显示面板，由于其重量轻、自发光、广视角、驱动电压低、发光效率高功耗低、响应速度快等优点，应用范围越来越广泛，逐渐被业界认为是代替液晶显示面板的下一代主流显示面板。
进一步的，OLED显示装置除了上述优点外，还具有一项尤为重要的特性，即可弯折性。这一可弯折特性使得其在便携性上获得了绝对的优势，因此，也就成为业界研究和开发的重点。
以其中的柔性折叠AMOLED为例，其采用的LTPS工艺流程一般包括10-15道工艺，比刚性的AMOLED多出2-3道Mask工艺步骤。这其中多出的工艺步骤主要是将周边非显示的弯折区里的应力较差、柔韧性不好的无机薄膜功能层用光刻和Dry工艺刻蚀形成上下相通的两个深孔（DH1、DH2），然后在所述深孔内填充上柔韧性较好的有机PI材料并形成填充层（OILD），从而有利于其弯折特性。
如图5、6所示，其图示了一种现有的柔性AMOLED采用的TFT阵列基板的结构示意图。如图5、6中所示，所述TFT阵列基板定义有显示区100’和弯折区110’。其中在所述显示区100’，其设置有通常的TFT器件功能层，而在所述弯折区110’，则是设置有分别用作数据走线（Data Line）和Vdd走线（Vdd Line）的金属层，其中数据走线一般是采用所述显示区用作源漏极的第一金属层（SD1）104’来实施，而Vdd走线一般是采用第二金属层（SD2）106’来实施。
根据业界常用的LTPS工艺流程，请参阅图5~8所示，在显示面板的外围弯折区110’中，由填充的有机PI材料形成的所述填充层102’会在填充的上部第一深孔（DH1）的孔边缘处覆盖一部分区域并形成对称设置的侧端部，即如图5和7中的130’位置处。为避免所述第一金属层（SD1）104’在所述填充层102’的边缘位置残留而导致short，业界目前采用的方法是将用作所述弯折区110’的数据走线的第一金属层104’转接处设计在所述OILD层102’侧端部的覆盖区域上，只在转接处开一个OILD孔。
但是，这种结构设计存在一个问题，即如图7所示的框线区域130’位置处，由于两侧的OILD层102’均设置了开口，导致此处中间高出，一方面会使得弯折应力难以释放，另一方面则是在后续所述第一金属层（SD1）104’进行蚀刻时，由于该处位置高出，所述第一金属层104’有过刻断线的风险，具体位置可参看图8中画圈部分150’处。
因此，确有必要来开发一种新型的TFT阵列基板，来克服现有技术中的缺陷。
 技术问题
本发明的一个方面是提供一种TFT阵列基板，其弯折区采用新的金属层走线结构设计，避免了其第一金属层在所述弯折区的走线经过OILD填充层的两孔开口之间，从而有效的降低其后续因过度蚀刻而断线的风险。
 技术解决方案
本发明采用的技术方案如下：
一种TFT阵列基板，其定义有显示区和弯折区。其包括衬底层和设置于其上的功能层，其中所述功能层中包括有绝缘层和金属层。其中所述弯折区的所述功能层中通过开深孔设置有填充层，其中所述填充层还在其上部开口的侧端部向外延伸出所述深孔边缘的侧端部，所述金属层在所述弯折区包括第一金属层、第二金属层和第二栅极层，其中所述第二栅极层、第一金属层和第二金属层之间设置有所述功能层中的绝缘层。其中所述第一金属层设置在所述填充层的侧端部上，并通过过孔与所述第二栅极层相接；其中所述第二金属层设置在位于所述第一金属层的外侧位置的所述绝缘层上。
进一步的，在不同实施方式中，其中所述金属层在所述弯折区还包括第一栅极层，其中所述第一栅极层和第二栅极层之间设置有栅极绝缘层，所述第二栅极层与所述第一金属层之间设置的所述绝缘层为层间电介质层。其中在不同实施方式中，所述层间电介质层可以是双层叠层结构，即包括第一层间电介质层和第二层间电介质层，其中所述第二栅极层与所述第一金属层之间间隔的所述绝缘层通常为所述第二层间电介质层，但不限于。
进一步的，在不同实施方式中，其中所述第一金属层和第二金属层之间设置的绝缘层为第一平坦层，其中所述填充层侧端部下方覆盖所述层间电介质层的局部。
进一步的，在不同实施方式中，其中所述第二金属层通过过孔与所述第一栅极层连接。
进一步的，在不同实施方式中，其中所述第二金属层和所述第一栅极层之间还设置有转接金属层，所述第二金属层通过过孔与所述转接金属层相接，所述转接金属层在通过过孔与所述第一栅极层连接。其中所述转接金属层优选为在所述第一金属层图案化时形成的第一金属层。
进一步的，在不同实施方式中，其中所述弯折区的功能层还包括有缓冲层，所述缓冲层设置在所述衬底层上，其中所述填充层向下贯穿所述缓冲层进入到所述衬底层中。
进一步的，在不同实施方式中，其中所述衬底层包括PI层和设置于其上的阻隔层，其中所述填充层的底部穿过所述阻隔层直到所述PI层的表面。
进一步的，在不同实施方式中，其中在所述弯折区的所述第一金属层和第二金属层之间的绝缘层为第一平坦层，所述第二金属层上还覆盖有第二平坦层。
进一步的，本发明的又一方面提供了一种显示面板，其包括本发明涉及的所述TFT阵列基板。
进一步的，在不同实施方式中，其中所述显示面板为柔性AMOLED显示面板。
 有益效果
相对于现有技术，本发明的有益效果是：本发明涉及的一种TFT阵列基板，其采用新型的弯折区走线结构，通过调换其原第一金属层和原所述第二金属层在其弯折区的走线位置，将原所述第一金属层在所述弯折区的走线位置变换为原第二金属层的走线位置，使得该处位置由第一平坦层所填平代替，进而也就不存在原所述第一金属层在所述弯折区的走线因经过OILD填充层的两孔开口之间，而导致的易断线问题。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明的一个实施方式中提供的一种TFT阵列基板的剖视结构图；
图2为图1所示的TFT阵列基板的平面结构图，其中仅图示其弯折区的平面结构；
图3为沿图2的A-A线的剖视图；
图4为沿图2的B-B线的剖视图；
图5为现有技术中涉及的一种TFT阵列基板，其中在其第一金属层位置处的剖视结构图；
图6为图5所示的TFT阵列基板，其中在其第二金属层的位置处的剖视结构示意图；
图7为图5所示的TFT阵列基板的平面结构图，其中仅图示其弯折区的平面结构；以及
图8为沿图7的A’-A’线的剖视图。
 本发明的实施方式
以下将结合附图和实施例，对本发明涉及的一种TFT阵列基板及其显示面板的技术方案作进一步的详细描述。
请参阅图1所示，本发明的一个实施方式提供了一种TFT阵列基板，其定义有显示区100和弯折区110。
其中所述TFT阵列基板包括衬底层101，其中所述衬底层101具体可以是采用双PI衬底结构，即PI层结合阻隔层（Barrier）的双叠层结构设计，但不限于。所述衬底层101上设置有缓冲层（Buffer）1011。
在所述显示区100，所述缓冲层1011上设置有TFT器件功能层，包括金属层和绝缘层，其中所述金属层具体为包括有源层（Active）103、第一栅极层（GE1）105、第二栅极层（GE2）107以及用作源漏极层的第一金属层（SD1）104。所述绝缘层设置在不同金属层之间，其具体包括第一栅极绝缘层（GI1）1031、第二栅极绝缘层（GI2）1032、第一层间电介质层（ILD1）1051和第二层间电介质层（ILD2）1071。其中这些金属层和绝缘层可根据需要采用单层或是叠层结构。其中所述第一金属层104上还可设置钝化层（PV），以保护所述第一金属层104免遭外部水汽的侵入，进而出现因侵入的水汽导致其使用寿命降低的问题。
进一步的，所述第二层间电介质层1071上还设置有第一平坦层（PLN1）1091和第二平坦层（PLN1）1092，两平坦层内设置有第二金属层（SD2）106和阳极金属层（ANO）109。所述第二金属层106和所述阳极金属层109之间通过过孔连接，所述第二金属层106还通过过孔与所述第一金属层104连接。
而在所述弯折区，由于其需要实现弯折功能，因此，其结构不同于显示区的结构。所述衬底层101上设置的缓冲层1011上会设置有一个填充层（OILD）102，其内填充有机材料，具体可以是有机PI材料，以便更好实现该位置处的弯折。
进一步的，其中所述填充层102贯穿设于所述弯折区110的所述第二层间电介质层（ILD2）1071、第一层间电介质层（ILD1）1051、第二栅极绝缘层（GI2）1032和第一栅极绝缘层（GI1）1031并向下穿过所述缓冲层1011直至所述衬底层101内，具体可以是穿过所述衬底层101中的阻隔层达到其PI层的表面，但不限于。
进一步的，其中虽然所述填充层102是通过填充深孔（DH）形成，但其并不是只限于孔内填充结构，其在原深孔表面形成有上部开口1022，然后在原深孔的侧边缘处还向外凸伸出有覆盖其下方层间功能层的两个对称设置的侧端部1021，其中所述侧端部1021设置在所述第二层间电介质层（ILD2）1071上，而所述侧端部1021以及所述上部开口1022则可由所述第一平坦层1091进行填平处理。
进一步的，所述弯折区内也会设置有金属层以用作数据走线（Data Line）或是Vdd走线（Vdd Line），这其中包括第一栅极层、第二栅极层、第一金属层和第二金属层，具体这些金属层之间的走线位置关系，以下将分别进行说明。而且，所述第一金属层和第二金属层在所述弯折区110的位置关系也是本发明涉及的一个重要方面。以下将结合图示对其进行重点描述。
其中所述第一金属层在所述弯折区设置的弯折区第一金属层1040一般用于数据走线，在本发明中，为了克服其易断的问题，本发明采用了换位设计方案，其为所述第一金属层的走线位置变换设置在原第二金属层的走线位置，而原所述第二金属层的走线位置则变换到原第一金属层的走线位置。
具体请参阅图1并结合图2~4所示，其中所述弯折区的所述填充层102的一侧端部1021上设置有弯折区第一金属层（SD1）1050，其还向内侧延伸入所述填充层的上部开口1022内；且，其通过过孔与弯折区第二栅极层1070电性连接，所述弯折区第一金属层1040的外侧设置有弯折区第二金属层1060，所述弯折区第二金属层1060向下通过一转接第一金属层1041与弯折区第一栅极层1050电性连接。进一步的，所述弯折区110内设置的各金属层是沿所述填充层102的两侧成对称分布设置。
通过对比本发明的图1所示的第一金属层（SD1）和第二金属层（SD2）和现有技术中的图5、6所示的第一金属层和第二金属层的位置可知，本发明通过将弯折区的所述第一金属层1040和第二金属层1060间的位置关系转换，使得原为所述第一金属层的走线位置变换设置在原第二金属层的走线位置，而原所述第二金属层的走线位置则变换到原第一金属层的走线位置。如此，由于所述第一金属层和第二金属层为层间上、下间隔设置，而当两者互换位置后，所述第一金属层的走线边上不会再有OILD开孔，也就不会有两孔之间位置偏高的问题，从而有效降低了过刻断线的风险。
进一步的，本发明的又一实施方式提供了一种显示面板，其采用本发明涉及的所述TFT阵列基板。
本发明的技术范围不仅仅局限于上述说明中的内容，本领域技术人员可以在不脱离本发明技术思想的前提下，对上述实施例进行多种变形和修改，而这些变形和修改均应当属于本发明的范围内。

Claims (10)

  1. 一种TFT阵列基板，其定义有显示区和弯折区，其包括衬底层和设置于其上的功能层，其中所述功能层中包括有绝缘层和金属层；
    其中所述弯折区的所述功能层中通过开深孔设置有填充层，其中所述填充层还在其上部开口的侧端部向外延伸出所述深孔边缘的侧端部；
    其中所述金属层在所述弯折区包括第一金属层、第二金属层和第二栅极层，其中所述第二栅极层、第一金属层和第二金属层之间设置有所述功能层中的绝缘层；
    其中所述第一金属层设置在所述填充层的侧端部上，并通过过孔与所述第二栅极层相接；其中所述第二金属层设置在位于所述第一金属层的外侧位置的所述绝缘层上。
  2. 根据权利要求1所述的TFT阵列基板，其中所述金属层在所述弯折区还包括第一栅极层，其中所述第一栅极层和第二栅极层之间设置有栅极绝缘层，所述第二栅极层与所述第一金属层之间设置的所述绝缘层为层间电介质层。
  3. 根据权利要求2所述的TFT阵列基板，其中所述第一金属层和第二金属层之间设置的绝缘层为第一平坦层，其中所述填充层侧端部下方覆盖所述层间电介质层的局部。
  4. 根据权利要求2所述的TFT阵列基板，其中所述第二金属层通过过孔与所述第一栅极层连接。
  5. 根据权利要求4所述的TFT阵列基板，其中所述第二金属层和所述第一栅极层之间还设置有转接金属层，所述第二金属层通过过孔与所述转接金属层相接，所述转接金属层在通过过孔与所述第一栅极层连接。
  6. 根据权利要求1所述的TFT阵列基板，其中所述弯折区的功能层还包括有缓冲层，所述缓冲层设置在所述衬底层上，其中所述填充层向下贯穿所述缓冲层进入到所述衬底层中。
  7. 根据权利要求6所述的TFT阵列基板，其中所述衬底层包括PI层和设置于其上的阻隔层，其中所述填充层的底部穿过所述阻隔层直到所述PI层的表面。
  8. 根据权利要求1所述的TFT阵列基板，其中在所述弯折区的所述第一金属层和第二金属层之间的绝缘层为第一平坦层，所述第二金属层上还覆盖有第二平坦层。
  9. 一种显示面板，其包括根据权利要求1所述的TFT阵列基板。
  10. 一种根据权利要求9所述的显示面板，其中所述显示面板为柔性AMOLED显示面板。
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