WO2021027108A1 - 阵列基板以及其制作方法 - Google Patents

阵列基板以及其制作方法 Download PDF

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WO2021027108A1
WO2021027108A1 PCT/CN2019/116120 CN2019116120W WO2021027108A1 WO 2021027108 A1 WO2021027108 A1 WO 2021027108A1 CN 2019116120 W CN2019116120 W CN 2019116120W WO 2021027108 A1 WO2021027108 A1 WO 2021027108A1
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layer
contact hole
metal
electrode
transistor
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PCT/CN2019/116120
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French (fr)
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周星宇
林振国
徐源竣
吕伯彦
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深圳市华星光电半导体显示技术有限公司
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Priority to US16/623,411 priority Critical patent/US20210327920A1/en
Publication of WO2021027108A1 publication Critical patent/WO2021027108A1/zh

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    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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    • H01L27/1259—Multistep manufacturing methods
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
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Definitions

  • the beneficial effects of the present invention are: the transparent conductive layer covers the surface of the copper of the light-shielding layer to protect the copper, prevent copper oxidation, avoid copper diffusion, reduce etching damage to copper, and reduce peeling risk.
  • the first contact hole 181 and the second contact hole 182 are formed by photolithography.
  • the first contact hole 181 is located in the interlayer insulating layer 142, and the first contact hole 181 extends vertically downward to be connected to the N+ semiconductor layer 1612.
  • the second contact hole 182 passes through the interlayer insulating layer 142 and the buffer layer 141, the second contact hole 182 passes through the interlayer insulating layer 142 and the buffer layer 141, and the second contact hole 182 extends vertically downward to the conductive protection layer 132 .
  • the output electrode 164 (ie, the source and drain metal layer) is deposited on the interlayer insulating layer 142, and the output electrode 164 contacts the N+ semiconductor layer 1612 and the conductive protection layer 132 through the first contact hole 181 and the second contact hole 182, respectively.
  • the output electrode 164 is an alloy of one or more of molybdenum, aluminum, copper, and titanium, and the thickness of the output electrode 164 is 200-1000 nm.

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Abstract

一种阵列基板，包含基板、金属遮光层、导电保护层、缓冲层、晶体管和像素电极。所述导电保护层覆盖所述金属遮光层。所述缓冲层位于所述基板上并覆盖所述导电保护层。所述晶体管位于所述缓冲层上，连接所述导电保护层。所述像素电极连接所述晶体管。有效的解决了金属氧化物薄膜晶体管驱动背板铜氧化的问题，透明导电层覆盖在遮光层铜的表面，形成对铜的保护，防止铜氧化，避免铜的扩散，减少蚀刻对铜的伤害，减小遮光层铜剥离的风险。

Description

阵列基板以及其制作方法 技术领域
本发明涉及显示技术领域，尤指一种阵列基板以及其制作方法。
 背景技术
顶栅自对准结构的金属氧化物薄膜晶体管（Oxide TFT）背板，遮光层采用铜（Cu）可以减轻其它金属层的走线风险，但是铜会有氧化问题。
 技术问题
有鉴于此，本发明的目的是提供一种阵列基板以及其制作方法，以解决现有技术的问题。
 技术解决方案
本发明的技术方案提供一种阵列基板以及其制作方法，所述阵列基板包含：基板；金属遮光层，位于所述基板上；导电保护层，覆盖所述金属遮光层；缓冲层，位于所述基板上并覆盖所述导电保护层；晶体管，位于所述缓冲层上，连接所述导电保护层；以及像素电极，连接所述晶体管。
依据本发明的实施例，所述金属遮光层的材质为钼、铝、铜、钛或合金中的至少一种。
依据本发明的实施例，所述金属遮光层的厚度为50-1000nm。
依据本发明的实施例，另包含第一电极，所述第一电极和所述像素电极形成存储电容，所述第一电极、所述像素电极以及所述导电保护层均为透明导电材料。
依据本发明的实施例，所述晶体管包括：有源层，位于所述缓冲层上；N+半导体层，位于所述有源层；所述晶体管的沟道，位于所述有源层；栅极绝缘层，位于所述有源层上；栅极金属层，位于所述栅极绝缘层上；层间绝缘层，位于与所述栅极金属层上；第一接触孔，所述第一接触孔贯穿所述层间绝缘层；第二接触孔，所述第二接触孔贯穿所述层间绝缘层和所述缓冲层；以及输出极，位于层间绝缘层上，所述输出极通过所述第一接触孔连接到所述N+半导体层，所述输出极通过所述第二接触孔连接到所述导电保护层。
本发明还提供了一种阵列基板的制作方法，其包含：在基板上形成金属遮光层；在所述基板上沉积第一透明导电层，并对所述第一透明导电层进行光刻形成第一电极以及导电保护层，所述导电保护层覆盖所述金属遮光层；形成缓冲层于所述基板上并覆盖所述第一电极以及所述保护层；形成晶体管位于所述缓冲层上；以及形成像素电极位于所述晶体管上方，所述像素电极与所述第一电极形成存储电容。
依据本发明的实施例，所述金属遮光层的材质为钼、铝、铜、钛或合金中的至少一种；
依据本发明的实施例，所述金属遮光层的厚度为50-1000nm。
依据本发明的实施例，所述形成晶体管步骤包括：光刻沉积在所述缓冲层上的导电材料层以形成有源层；沉积绝缘材料层和金属材料层于所述缓冲层上；光刻金属材料层以形成栅极金属层；以栅极金属层做为屏蔽，蚀刻所述绝缘材料层以形成栅极绝缘层；对所述有源层进行等离子化制程，以形成N+半导体层以及所述晶体管的沟道；光刻沉积于所述缓冲层上的层间绝缘层和所述缓冲层以形成第一接触孔以及第二接触孔，其中所述第一接触孔贯穿所述层间绝缘层，所述第二接触孔贯穿所述层间绝缘层和所述缓冲层；以及形成所述晶体管的输出极，使得所述输出极通过所述第一接触孔连接到所述N+半导体层，所述输出极通过所述第二接触孔连接到所述导电保护层。
依据本发明的实施例，还包括：光刻沉积于所述层间绝缘层上的平坦化层以形成第三接触孔；以及形成所述像素电极，使得所述像素电极通过所述第三接触孔连接到所述输出极。
 有益效果
相较于现有技术，本发明的有益效果是：透明导电层覆盖在遮光层铜的表面，形成对铜的保护，防止铜氧化，避免铜的扩散，减少蚀刻对铜的伤害，减小剥离风险。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
 附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1绘示本发明阵列基板结构示意图。
图2绘示本发明阵列基板的制作流程图。
图3-图15绘示本发明形成阵列基板方法。
 本发明的实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施之特定实施例。本发明所提到的方向用语，例如“上”、“下”、“前”、“后”、“左”、“右”、“顶”、“底”、“水平”、“垂直”等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
请参阅图1，本发明提供了一种阵列基板10包括基板110、金属遮光层120、第一电极131、导电保护层132、缓冲层141、晶体管160、层间绝缘层142、钝化层143、像素电极170以及平坦化层144。
金属遮光层120材料为钼、铝、铜、钛中的一种或多种的合金，本实施例金属遮光层120采用金属铜做为说明，但非用以限定，金属遮光层120的厚度为50-1000nm。
导电保护层132覆盖金属遮光层120。导电保护层132为透明导电层，组成材料可以为铟锡氧化物、铟锌氧化物或两者组合。用于避免金属铜的氧化以及可能的金属铜扩散或是后续的蚀刻损伤。导电保护层132的厚度为20-200nm。第一电极131位于基板110上，与导电保护层132皆为透明导电层，第一电极131和导电保护层132也可以同时形成。第一电极131的厚度为20-200nm。
缓冲层141位于第一电极131上，缓冲层141一方面作为阻挡层阻挡湿气或杂质，防止湿气或杂质通过基板110、金属遮光层120、第一电极131以及导电保护层132扩散，另一方面缓冲层141可以作为平坦化层，可省掉后续的平坦化制程，节约成本。缓冲层141可以为氧化硅(SiOx)、氮化硅(SiNx)、氮氧化硅(SiOxNy)、氧化铝(AlOx)或氮化铝(AlNx)等无机材料形成的膜层。缓冲层141厚度为100-500nm。
晶体管160包括有源层161、栅极绝缘层162、栅极金属层163以及输出极164，有源层161位于缓冲层141上，有源层161为铟镓锌氧化物、铟锌锡氧化物或铟镓锌锡氧化物中的一种，有源层161的厚度为10-100nm。半导体有源层161可以通过非晶硅的结晶使非晶硅改变为多晶硅而形成。具体的，为了使非晶硅结晶，可以利用快速热退火(RTA)制程、准分子激光退火(ELA)制程、固相结晶(SPC)制程、金属诱导结晶(MIC)制程、金属诱导横向结晶(MILC) 制程或连续横向固化(SLS)制程实现。通过等离子掺杂工艺对有源层161进行离子掺杂，使得有源层161上未被栅极金属层163与栅极绝缘层162覆盖的区域的导电性增强形成N+半导体层1612，被栅极金属层163与栅极绝缘层162覆盖的区域下面的保持半导体性能作为晶体管160的沟道1611。
栅极绝缘层162位于有源层161上，栅极绝缘层162材质由氧化硅、氮化硅或金属氧化物等无机材料形成，并且可以包括单层或多个膜层。栅极绝缘层162厚度为100-300nm；栅极金属层163位于栅极绝缘层162上，栅极金属层163可以包括金(Au)、银(Ag)、铜(Cu)、钼(Mo)、镍(Ni)、铂(Pt)、铝(Al)或铬(Cr)的单层或多层，或者诸如铝(Al):钕(Nd)合金、钼(Mo):钨(W)合金等合金。栅极金属层163厚度为200-1000nm。
层间绝缘层142位于栅极金属层163上，层间绝缘层142可以由氧化硅或氮化硅等的绝缘无机材料形成。层间绝缘层142厚度200-1000nm。输出极164位于层间绝缘层142上。输出极164可以包括金(Au)、银(Ag)、铜(Cu)、钼(Mo)、镍(Ni)、铂(Pt)、铝(Al)或铬(Cr)的单层或多层，或者诸如铝(Al):钕(Nd)合金、钼(Mo):钨(W)合金等合金；输出极164的厚度为200-1000nm。
层间绝缘层142形成貫穿其中的第一接触孔181，第一接触孔181竖直向下延伸至有源层161上，第一接触孔181被源漏极金属层(亦即输出极164)覆盖并填充。第二接触孔182穿过层间绝缘层142以及缓冲层141，第二接触孔182竖直向下延伸至导电保护层132上，第二接触孔182被源漏极金属层(亦即输出极164)覆盖并填充。
钝化层143位于输出极164上，钝化层143为氧化硅层、氮化硅层或两者的组合，钝化层143厚度为100-500nm。第三接触孔183位于钝化层143，第三接触孔183竖直向下延伸至输出极164上。
像素电极170位于钝化层143上，第三接触孔183被像素电极170覆盖并填充，像素电极170组成材料可以为铟锡氧化物、铟锌氧化物或两者组合。平坦化层144位于像素电极170上，平坦化层144可以由诸如聚酰亚胺(PI)、聚酰胺、苯并环丁烯(BCB)、压克力树脂或酚醛树脂等有机材料形成。平坦化层144为一层厚度为0.5-2um。
本发明所提供的阵列基板可应用于驱动LCD、OLED、QLED或者μLED。
请参阅图2，本发明还提供了一种阵列基板的制作方法，包括如下步骤：S10在基板110上形成金属遮光层120；S20在基板110上沉积第一透明导电层130，并对第一透明导电层130进行光刻形成第一电极131以及导电保护层132，导电保护层132覆盖金属遮光层120；S30形成缓冲层141于所述基板120上并覆盖第一电极131以及保护层132；S40形成晶体管160位于缓冲层141上；S50形成像素电极170位于晶体管160上方，像素电极170与第一电极131形成存储电容；S60形成平坦化层144。
请参阅图3及图4，在基板10上沉积一层金属遮光层120并对金属遮光层120光刻做出图形。金属遮光层120材料为钼、铝、铜、钛中的一种或多种的合金，本实施例金属遮光层120是以金属铜作为说明，但并非用以限制。金属遮光层120的厚度为500-10000A，此结构可以减轻其他金属层的走线风险。
请参阅图5，在金属遮光层120上沉积一层第一透明导电层130并对第一透明导电层130光刻做出图形，其中部分第一透明导电层130覆盖在金属遮光层120的表面形成导电保护层132，避免金属铜的氧化以及可能的金属铜扩散或是后续的蚀刻损伤；另一部分第一透明导电层130覆盖在基板120上形成第一电极131。第一电极130的厚度为20-200nm。
请参阅图6，在第一透明导电层130上形成缓冲层141。缓冲层141一方面作为阻挡层阻挡湿气或杂质，防止湿气或杂质通过基板110、金属遮光层120以及第一电极130扩散，另一方面缓冲层141可以作为平坦化层，可省掉后续的平坦化制程，节约成本。缓冲层141可以为氧化硅(SiOx)、氮化硅(SiNx)、氮氧化硅(SiOxNy)、氧化铝(AlOx)或氮化铝(AlNx)等无机材料形成的膜层。缓冲层141厚度为100-500nm。
请参阅图7，在缓冲层141上形成有源层161，半导体有源层161可以通过非晶硅的结晶使非晶硅改变为多晶硅而形成。具体的，为了使非晶硅结晶，可以利用快速热退火(RTA)制程、准分子激光退火(ELA)制程、固相结晶(SPC)制程、金属诱导结晶(MIC)制程、金属诱导横向结晶(MILC) 制程或连续横向固化(SLS)制程实现。
请参阅图8，沉积绝缘材料层和金属材料层于缓冲层141上并光刻金属材料层以形成栅极金属层163。以栅极金属层163做为屏蔽，蚀刻绝缘材料层以形成栅极绝缘层162。
请参阅图9，对有源层161进行等离子化制程，使得有源层161上未被栅极金属层163与栅极绝缘层162覆盖的区域的导电性增强形成N+半导体层1612，被栅极金属层163与栅极绝缘层162覆盖的区域下面的晶体管160的沟道1611保持半导体性能。
请参阅图10，在栅极金属层163上形成层间绝缘层142。
请参阅图11及图12，光刻处理形成第一接触孔181以及第二接触孔182。第一接触孔181位于层间绝缘层142，第一接触孔181竖直向下延伸至连接到N+半导体层1612上。第二接触孔182穿过层间绝缘层142以及缓冲层141，第二接触孔182穿过层间绝缘层142以及缓冲层141，第二接触孔182竖直向下延伸至导电保护层132上。沉积输出极164(亦即源漏极金属层)于层间绝缘层142上，同时输出极164通过第一接触孔181和第二接触孔182分别接触N+半导体层1612和导电保护层132。输出极164为钼、铝、铜、钛中的一种或多种的合金，输出极164的厚度为200-1000nm。
请参阅图13，沉积钝化层143在输出极164之上，钝化层143为氧化硅层、氮化硅层或两者的组合，钝化层143厚度为100-500nm。
请参阅图14，对钝化层143进行光刻处理形成第三接触孔183。第三接触孔183位于钝化层143，第三接觸孔183竖直向下延伸至所述输出极164上表面。
请参阅图3和图15，在所述钝化层143上沉积像素电极170。像素电极170组成材料可以为铟锡氧化物、铟锌氧化物或两者组合。在像素电极220上沉积平坦化层144。平坦化层144位于像素电极170上，平坦化层144可以由诸如聚酰亚胺(PI)、聚酰胺、苯并环丁烯(BCB)、压克力树脂或酚醛树脂等有机材料形成。平坦化层144的厚度为0.5-2um。
综上所述，本领域技术人员容易理解，本申请的有益效果是：本申请的优点在于，所述遮光层金属铜被透明导电层覆盖。有效的解决了金属氧化物薄膜晶体管驱动背板铜氧化的问题，透明导电层覆盖在遮光层铜的表面，形成对铜的保护，防止铜氧化，避免铜的扩散，减少蚀刻对铜的伤害，减小遮光层铜剥离的风险。
以上对本申请实施例所提供的阵列基板以及其制作方法进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。
 工业实用性
本申请的主体可以在工业中制造和使用，具备工业实用性。

Claims (10)

  1.    一种阵列基板，包含：
    基板；
    金属遮光层，位于所述基板上；
    导电保护层，覆盖所述金属遮光层；
    缓冲层，位于所述基板上并覆盖所述导电保护层；
    晶体管，位于所述缓冲层上，连接所述导电保护层；以及
    像素电极，连接所述晶体管。
  2.    根据权利要求1所述的阵列基板，其中所述金属遮光层的材质为钼、铝、铜、钛或合金中的至少一种。
  3.    根据权利要求1所述的阵列基板，其中所述金属遮光层的厚度为50-1000nm。
  4.    根据权利要求1所述的阵列基板，其另包含第一电极，所述第一电极和所述像素电极形成存储电容，所述第一电极、所述像素电极以及所述导电保护层均为透明导电材料。
  5. 根据权利要求1所述的阵列基板，其中所述晶体管包括：
    有源层，位于所述缓冲层上；
    N+半导体层，位于所述有源层；
    所述晶体管的沟道，位于所述有源层；
    栅极绝缘层，位于所述有源层上；
    栅极金属层，位于所述栅极绝缘层上；
    层间绝缘层，位于与所述栅极金属层上；
    第一接触孔，所述第一接触孔贯穿所述层间绝缘层；
    第二接触孔，所述第二接触孔贯穿所述层间绝缘层和所述缓冲层；以及
    输出极，位于层间绝缘层上，所述输出极通过所述第一接触孔连接到所述N+半导体层，所述输出极通过所述第二接触孔连接到所述导电保护层。
  6. 一种阵列基板的制作方法，其包含：
    在基板上形成金属遮光层；
    在所述基板上沉积第一透明导电层，并对所述第一透明导电层进行光刻形成第一电极以及导电保护层，所述导电保护层覆盖所述金属遮光层；
    形成缓冲层于所述基板上并覆盖所述第一电极以及所述导电保护层；
    形成晶体管位于所述缓冲层上；以及
    形成像素电极位于所述晶体管上方，所述像素电极与所述第一电极形成存储电容。
  7.    根据权利要求6所述的制作方法，其中所述金属遮光层的材质为钼、铝、铜、钛或合金中的至少一种。
  8. 根据权利要求6所述的制作方法，其中所述金属遮光层的厚度为50-1000nm。
  9. 根据权利要求6所述的制作方法，其中所述形成晶体管步骤包括：
    光刻沉积在所述缓冲层上的导电材料层以形成有源层；
    沉积绝缘材料层和金属材料层于所述缓冲层上；
    光刻金属材料层以形成栅极金属层；
    以栅极金属层做为屏蔽，蚀刻所述绝缘材料层以形成栅极绝缘层；
    对所述有源层进行等离子化制程，以形成N+半导体层以及所述晶体管的沟道；
    光刻沉积于所述缓冲层上的层间绝缘层和所述缓冲层以形成第一接触孔以及第二接触孔，其中所述第一接触孔贯穿所述层间绝缘层，所述第二接触孔贯穿所述层间绝缘层和所述缓冲层；以及
    形成所述晶体管的输出极，使得所述输出极通过所述第一接触孔连接到所述N+半导体层，所述输出极通过所述第二接触孔连接到所述导电保护层。
  10. 根据权利要求9所述的制作方法，其还包括：
    光刻沉积于所述层间绝缘层上的平坦化层以形成第三接触孔；以及
    形成所述像素电极，使得所述像素电极通过所述第三接触孔连接到所述输出极。
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