WO2021027012A1 - 具有NiO X保护层的MIS-HEMT器件及制备方法 - Google Patents

具有NiO X保护层的MIS-HEMT器件及制备方法 Download PDF

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WO2021027012A1
WO2021027012A1 PCT/CN2019/106549 CN2019106549W WO2021027012A1 WO 2021027012 A1 WO2021027012 A1 WO 2021027012A1 CN 2019106549 W CN2019106549 W CN 2019106549W WO 2021027012 A1 WO2021027012 A1 WO 2021027012A1
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dielectric layer
nio
mis
hemt device
source
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王洪
周泉斌
高升
廖碧艳
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Zhongshan Institute Of Modern Industrial
South China University of Technology SCUT
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Zhongshan Institute Of Modern Industrial
South China University of Technology SCUT
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers

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  • the invention relates to an AlGaN/GaNHEMT device in the semiconductor field, in particular to a MIS-HEMT device with a NiO X protective layer and a preparation method.
  • GaN materials are widely used in high-frequency power amplifiers and high-voltage power switches due to their high electron mobility, low on-resistance, excellent heat dissipation capability, and high breakdown characteristics.
  • the current collapse phenomenon is widespread in the GaN MIS-HEMT device, which causes the performance and reliability of the device to deteriorate.
  • the current popular explanation is that the accumulation of surface states forms a "virtual gate effect", which deteriorates the performance of the device.
  • the traditional solution is to deposit a layer of SiN X on AlGaN to suppress the surface state. Although it plays a certain role, the overall effect is not significant.
  • the surface traps introduced in the process of PECVD film deposition will enhance the electric field on the drain side of the gate edge and bring higher gate leakage current in the HEMT device;
  • Electron beam evaporation equipment deposits metal films at room temperature, and the damage to the AlGaN surface is very small compared to PECVD.
  • the purpose of the present invention is to provide a MIS-HEMT device with a NiO X protective layer and a preparation method, which adopts NiO X /SiN X and other laminated structures as the gate dielectric layer and passivation at the same time
  • the layer reduces surface state traps, and achieves the purpose of reducing device leakage, suppressing current collapse to a great extent, and increasing breakdown voltage.
  • the formation of the NiO X layer includes the deposition of a thin metal Ni layer using electron beam evaporation equipment and the subsequent high-temperature oxidation process; the second dielectric layer is obtained by PECVD deposition.
  • the present invention provides a MIS-HEMT device with a NiO X protective layer.
  • the device includes an AlGaN/GaN epitaxy. Both ends of the upper surface of the AlGaN/GaN epitaxy are connected to source and drain electrodes respectively, and the source and drain electrodes are connected to the AlGaN/GaN epitaxy.
  • the first dielectric layer and the second dielectric layer are deposited sequentially from bottom to top on the upper surface except for the area connected to the source and drain electrodes.
  • the upper surface of the second dielectric layer is connected to the gate electrode, which is located between the source and drain electrodes.
  • the first dielectric layer is NiO X , the first dielectric layer and the second dielectric layer together serve as the passivation layer and the gate dielectric layer of the MIS-HEMT device.
  • the second dielectric layer is SiN X , SiO 2 or SiON.
  • the thickness of the first dielectric layer is 6-18 nm.
  • the thickness of the second dielectric layer is 5-10 nm.
  • the present invention also provides a method for preparing the MIS-HEMT device with the NiO X protective layer, which includes the following steps:
  • a second dielectric layer is deposited on the first dielectric layer NiO X , and finally the gate electrode is deposited.
  • the first dielectric layer is formed by electron beam evaporation of Ni metal, and then high-temperature oxidation treatment in a rapid annealing furnace.
  • the deposition rate of Ni metal in step (1) is 0.02-0.05 nm/s, and the deposition thickness is 3-10 nm.
  • the high temperature oxidation treatment in step (1) is performed in a rapid annealing furnace or furnace tube.
  • the cavity temperature of the rapid annealing furnace or furnace tube is 300-400°C
  • the oxygen flow rate is 50-100 sccm
  • the high-temperature oxidation treatment time is 10-30 min
  • the annealing temperature rise rate is 7-15°C/s.
  • the method for depositing the second dielectric layer in step (2) is a plasma enhanced chemical vapor deposition method, namely PECVD.
  • the invention adopts a NiO X /SiN X laminated structure as the gate dielectric layer and passivation layer of the device at the same time, wherein the NiO X is deposited with the metal Ni layer by the electron beam evaporation equipment, and then the high temperature annealing treatment is performed in the annealing furnace or furnace tube and other equipment obtain.
  • the film directly in contact with the AlGaN barrier layer in the present invention is obtained by electron beam evaporation equipment.
  • PECVD the deposition damage is greatly reduced, and the device leakage and current collapse And the breakdown voltage has been optimized.
  • the present invention has the following beneficial effects and advantages:
  • the invention adopts NiO X /SiN X and other laminated structures as the gate dielectric layer and passivation layer of the device at the same time, and the electron beam evaporation equipment is used to grow the film, which reduces the deposition damage problem compared with the PECVD equipment, and improves the surface state of the device. Leakage, current collapse and breakdown voltage performance have been optimized.
  • FIG. 1 is a schematic diagram of the device structure after completing the ohmic contact of the embodiment
  • FIG. 2 is a schematic diagram of the device structure after forming the first dielectric layer according to the embodiment
  • FIG. 3 is a schematic diagram of the device structure after forming a second dielectric layer in an embodiment
  • FIG. 5 is a schematic diagram of the current collapse of a MIS-HEMT device with a NiO X protective layer and a device prepared with a traditional SiN X dielectric layer provided by the embodiment when the drain bias voltage is 200V;
  • FIG. 6 is a comparison diagram of breakdown voltage between a MIS-HEMT device with a NiO X protective layer provided by the embodiment and a device prepared with a traditional SiN X dielectric layer;
  • 1 is the AlGaN/GaN epitaxy
  • 2 is the source and drain electrodes
  • 3 is the first dielectric layer
  • 4 is the second dielectric layer
  • 5 is the gate electrode.
  • This embodiment provides a MIS-HEMT device with a NiO X protective layer.
  • the device includes an AlGaN/GaN epitaxy 1, and both ends of the upper surface of the AlGaN/GaN epitaxy are connected to source and drain electrodes 2, respectively,
  • the first dielectric layer 3 and the second dielectric layer 4 are sequentially deposited on the source and drain electrodes 2 and the upper surface of the AlGaN/GaN epitaxial surface except for the source and drain electrodes from bottom to top.
  • the upper surface of the second dielectric layer 4 is connected to the gate electrode 5,
  • the gate electrode 5 is located between the source and drain electrodes 2, the first dielectric layer 3 is NiO X , and the first dielectric layer 3 and the second dielectric layer 4 together serve as the passivation layer and the gate dielectric layer of the MIS-HEMT device.
  • the second dielectric layer 4 is SiN X.
  • the thickness of the first dielectric layer 3 is 18 nm.
  • the thickness of the second dielectric layer 4 is 10 nm.
  • This embodiment also provides a method for preparing the MIS-HEMT device with the NiO X protective layer, including the following steps:
  • the deposition temperature is 300 °C
  • the deposition thickness is 10 nm, as shown in Figure 3
  • the gate electrode 5 is deposited, as shown in Figure 4 .
  • FIG. 5 is a schematic diagram of the current collapse of the MIS-HEMT device with the NiO X protective layer and the device prepared by the traditional SiN X dielectric layer provided by the embodiment, and the drain bias voltage is 200V
  • (a) in FIG. 5 is The schematic diagram of the current collapse of the MIS-HEMT device with the NiO X protective layer provided by this embodiment under the drain bias of 200V and no drain bias (Ref).
  • Figure 5 (b) is a traditional SiN The schematic diagram of the current collapse of the device prepared by the X dielectric layer under the drain bias of 200V and no drain bias. The dotted line is the output corresponding to the duration of 10s of the two devices under the drain bias of 200V.
  • the curve, the solid line are the corresponding output curves of the two devices without drain bias, as a reference control group; under the condition that the drain bias is 200V and the bias stress is continuously applied for 10s, from Figure 5 It can be seen that the current collapse of the MIS-HEMT device with the NiO X protective layer of this example is reduced by 90% compared with the traditional device, from 32.7% to 5.4%;
  • FIG. 6 is a comparison diagram of breakdown voltage between a MIS-HEMT device with a NiO X protective layer used in this embodiment and a device prepared with a traditional SiN X dielectric layer.
  • the dashed line is the breakdown curve of the MIS-HEMT device with the NiO X protective layer of this embodiment, and the solid line is the breakdown curve of the device prepared by the traditional SiN X dielectric layer; it can be seen from FIG. 6 that the NiO X Compared with traditional devices, the breakdown voltage of the MIS-HEMT device with the protective layer has increased by 52.2%, from 452V to 688V.
  • This embodiment provides a MIS-HEMT device with a NiO X protective layer.
  • the device includes an AlGaN/GaN epitaxy 1, and both ends of the upper surface of the AlGaN/GaN epitaxy are connected to source and drain electrodes 2, respectively,
  • the first dielectric layer 3 and the second dielectric layer 4 are sequentially deposited on the source and drain electrodes 2 and the upper surface of the AlGaN/GaN epitaxial surface except for the source and drain electrodes from bottom to top.
  • the upper surface of the second dielectric layer 4 is connected to the gate electrode 5,
  • the gate electrode 5 is located between the source and drain electrodes 2, the first dielectric layer 3 is NiO X , and the first dielectric layer 3 and the second dielectric layer 4 together serve as the passivation layer and the gate dielectric layer of the MIS-HEMT device.
  • the second dielectric layer 4 is SiO 2 .
  • the thickness of the first dielectric layer 3 is 15 nm.
  • the thickness of the second dielectric layer 4 is 7 nm.
  • This embodiment also provides a method for preparing the MIS-HEMT device with the NiO X protective layer, including the following steps:
  • the deposition temperature is 300 °C
  • the deposition thickness is 7 nm, as shown in Figure 3
  • the gate electrode 5 is deposited, as shown in Figure 4 .
  • the current collapse characteristics of the MIS-HEMT device with the NiO X protective layer provided in this embodiment are similar to the breakdown characteristics of the first embodiment, and the specific performance can be referred to FIG. 5 and FIG. 6 in the first embodiment.
  • This embodiment provides a MIS-HEMT device with a NiO X protective layer.
  • the device includes an AlGaN/GaN epitaxy 1, and both ends of the upper surface of the AlGaN/GaN epitaxy are connected to source and drain electrodes 2, respectively,
  • the first dielectric layer 3 and the second dielectric layer 4 are sequentially deposited on the source and drain electrodes 2 and the upper surface of the AlGaN/GaN epitaxial surface except for the source and drain electrodes from bottom to top.
  • the upper surface of the second dielectric layer 4 is connected to the gate electrode 5,
  • the gate electrode 5 is located between the source and drain electrodes 2, the first dielectric layer 3 is NiO X , and the first dielectric layer 3 and the second dielectric layer 4 together serve as the passivation layer and the gate dielectric layer of the MIS-HEMT device.
  • the second dielectric layer 4 is SiON.
  • the thickness of the first dielectric layer 3 is 12 nm.
  • the thickness of the second dielectric layer 4 is 10 nm.
  • This embodiment also provides a method for preparing the MIS-HEMT device with the NiO X protective layer, including the following steps:
  • Use electron beam evaporation equipment to connect source and drain electrodes 2 to the upper surface of AlGaN/GaN epitaxy 1 Deposit a layer of Ni metal in the area outside the source and drain electrodes with a thickness of 6nm and a deposition rate of 0.02nm/s, and then perform high-temperature oxidation treatment in a rapid annealing furnace.
  • the cavity temperature is 400°C
  • the oxygen flow rate is 50sccm.
  • the high temperature oxidation treatment time is 30 minutes, and the annealing temperature rise rate is 10°C/s to form the first dielectric layer NiO X.
  • the corresponding structural diagram is shown in Figure 2;
  • the deposition temperature is 300 °C
  • the deposition thickness is 10 nm, as shown in Figure 3
  • the gate electrode 5 is deposited, as shown in Figure 4 .
  • the current collapse characteristics of the MIS-HEMT device with the NiO X protective layer provided in this embodiment are similar to the breakdown characteristics of the first embodiment, and the specific performance can be referred to FIG. 5 and FIG. 6 in the first embodiment.

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Abstract

一种具有NiO X保护层的MIS-HEMT器件及其制备方法，所述器件包括AlGaN/GaN外延（1），AlGaN/GaN外延（1）上表面的两端分别连接源漏电极（2），源漏电极（2）的上表面和AlGaN/GaN外延（1）上表面连接源漏电极（2）以外的区域从下到上依次沉积第一介质层（3）和第二介质层（4），第二介质层（4）的上表面连接栅电极（5），栅电极（5）位于源漏电极（2）之间，第一介质层（3）为NiO X，第一介质层（3）和第二介质层（4）共同作为钝化层和栅介质层。采用NiO X/SiN X叠层结构同时作为器件的栅介质层与钝化层，利用电子束蒸发设备生长薄膜较PECVD设备减小了沉积损伤问题，改善了器件的表面态，器件的漏电、电流崩塌以及击穿电压性能都得到了优化。

Description

具有NiO X保护层的MIS-HEMT器件及制备方法 技术领域
本发明涉及半导体领域AlGaN/GaNHEMT器件，特别涉及一种具有NiO X保护层的MIS-HEMT器件及制备方法。
背景技术
GaN材料因具有高电子迁移率、低导通电阻、优异的散热能力以及高击穿等特性，广泛应用于高频功率放大器与高压功率开关等场合。然而由于势垒层AlGaN上存在较多的表面态缺陷，使得电流崩塌现象普遍存在于GaN MIS-HEMT器件中，致使器件的性能退化，可靠性降低。目前大众比较认可的解释是表面态的累积形成了“虚栅效应”，使得器件的性能得到恶化。传统的解决方法是在AlGaN上沉积一层SiN X来抑制表面态，虽然起到一定作用，但总体上效果不显著。由于采用PECVD沉积SiN X薄膜的沉积过程会对AlGaN表面造成一定的损伤，在一定程度上会引入新的表面态陷阱，因此许多学者倾向于使用低损伤沉积薄膜的设备，例如(cat-)CVD、ICP-CVD和LPCVD；但是普遍存在的问题是需要更高的温度以及更长的时间来制备所得的薄膜，对于工业量产而言是不利的。
PECVD沉积薄膜过程中引入的表面态陷阱会增强栅极边缘漏极侧的电场，并在HEMT器件中带来更高的栅极漏电流；
电子束蒸发设备沉积金属薄膜在常温下进行，对AlGaN表面造成的损伤相对于PECVD而言是非常小的。
发明概述
技术问题
问题的解决方案
技术解决方案
为了解决现有技术中存在的问题，本发明的目的在于提供一种具有NiO X保护层的MIS-HEMT器件及制备方法，采用NiO X/SiN X等叠层结构同时作为栅介质层与钝化层，减小了表面态陷阱，达到了减小器件漏电、极大程度抑制电流崩塌 以及提高击穿电压的目的。
NiO X层的形成包括采用电子束蒸发设备沉积一层薄的金属Ni层以及后续的高温氧化过程；第二介质层采用PECVD沉积获得。
本发明的目的至少通过如下技术方案之一实现的。
本发明提供了一种具有NiO X保护层的MIS-HEMT器件，所述器件包括AlGaN/GaN外延，AlGaN/GaN外延上表面的两端分别连接源漏电极，源漏电极上和AlGaN/GaN外延上表面连接源漏电极以外的区域从下到上依次沉积第一介质层和第二介质层，第二介质层的上表面连接栅电极，栅电极位于源漏电极之间，第一介质层为NiO X，第一介质层和第二介质层共同作为MIS-HEMT器件的钝化层和栅介质层。
优选地，第二介质层为SiN X、SiO 2或者SiON。
优选地，第一介质层的厚度为6-18nm。
优选地，第二介质层的厚度为5-10nm。
本发明还提供了一种制备所述具有NiO X保护层的MIS-HEMT器件的方法，包括以下步骤：
(1)进行台面隔离以及欧姆接触在AlGaN/GaN外延的上表面制备源漏电极，在源漏电极上和AlGaN/GaN外延上表面连接源漏电极以外的区域沉积一层Ni金属，高温氧化处理，形成第一介质层NiO X；
(2)在第一介质层NiO X上沉积第二介质层，最后进行栅电极的沉积。
优选地，步骤(1)中第一介质层由电子束蒸发Ni金属，然后在快速退火炉中高温氧化处理形成。
优选地，步骤(1)中Ni金属的沉积速率为0.02-0.05nm/s，沉积的厚度为3-10nm。
优选地，步骤(1)中高温氧化处理在快速退火炉或炉管中进行。
优选地，步骤(1)中高温氧化处理时快速退火炉或炉管的腔体温度为300-400℃，氧气流量为50-100sccm，高温氧化处理的时间为10-30min，退火的升温速率为7-15℃/s。
优选地，步骤(2)中第二介质层沉积的方法为等离子体增强化学的气相沉积 法即PECVD。
本发明采用NiO X/SiN X叠层结构同时作为器件的栅介质层与钝化层，其中NiO X由电子束蒸发设备沉积金属Ni层，然后在退火炉或者炉管等设备中进行高温退火处理获得。区别于传统的栅介质层与钝化层，本发明中与AlGaN势垒层直接接触的薄膜由电子束蒸发设备获得，相对于PECVD，极大程度减小了沉积损伤，在器件漏电、电流崩塌以及击穿电压方面都得到了优化。
发明的有益效果
有益效果
和现有技术相比，本发明具有以下有益效果和优点：
本发明采用NiO X/SiN X等叠层结构同时作为器件的栅介质层与钝化层，利用电子束蒸发设备生长薄膜较PECVD设备减小了沉积损伤问题，改善了器件的表面态，器件的漏电、电流崩塌以及击穿电压性能都得到了优化。
对附图的简要说明
附图说明
图1为实施例的在完成欧姆接触后的器件结构示意图；
图2为实施例的形成第一介质层后的器件结构示意图；
图3为实施例的形成第二介质层后的器件结构示意图；
图4为实施例的在完成栅电极后的器件结构示意图；
图5为实施例提供的具有NiO X保护层的MIS-HEMT器件与传统的SiN X介质层制备的器件在漏极偏压为200V应力下的电流崩塌示意图；
图6为实施例提供的具有NiO X保护层的MIS-HEMT器件与传统的SiN X介质层制备的器件的击穿电压对比图；
图中，1是AlGaN/GaN外延，2是源漏电极，3是第一介质层，4是第二介质层，5是栅电极。
发明实施例
本发明的实施方式
下面结合实施例，对本发明作进一步地详细说明，但本发明的实施方式不限于 此。
实施例1
本实施例提供了一种具有NiO X保护层的MIS-HEMT器件，如图4所示，所述器件包括AlGaN/GaN外延1，AlGaN/GaN外延上表面的两端分别连接源漏电极2，源漏电极2上和AlGaN/GaN外延上表面连接源漏电极以外的区域从下到上依次沉积第一介质层3和第二介质层4，第二介质层4的上表面连接栅电极5，栅电极5位于源漏电极2之间，第一介质层3为NiO X，第一介质层3和第二介质层4共同作为MIS-HEMT器件的钝化层和栅介质层。第二介质层4为SiN X。第一介质层3的厚度为18nm。第二介质层4的厚度为10nm。
本实施例还提供了一种制备所述具有NiO X保护层的MIS-HEMT器件的方法，包括以下步骤：
(1)进行台面隔离以及欧姆接触在AlGaN/GaN外延1的上表面制备源漏电极2，如图1所示；利用电子束蒸发设备在源漏电极2的上表面和AlGaN/GaN外延1上表面连接源漏电极以外的区域沉积一层Ni金属，厚度为10nm，沉积速率为0.02nm/s，然后在快速退火炉中进行高温氧化处理，腔体温度为400℃，通入的氧气流量为50sccm，高温氧化处理的时间为20min，退火的升温速率为15℃/s，形成第一介质层NiO X，相应的结构示意图如图2所示；
(2)采用PECVD设备在第一介质层3上沉积第二介质层4，沉积温度为300℃，沉积厚度为10nm，如图3所示；最后进行栅电极5的沉积，如图4所示。
图5为本实施例提供的具有NiO X保护层的MIS-HEMT器件与传统的SiN X介质层制备的器件，在漏极偏压为200V下的电流崩塌示意图，其中图5中(a)为本实施例提供的具有NiO X保护层的MIS-HEMT器件在漏极偏压为200V和无漏极偏压(Ref)两种情况下的电流崩塌示意图，图5中(b)为传统的SiN X介质层制备的器件在漏极偏压为200V和无漏极偏压两种情况下的电流崩塌示意图，其中虚线为两种器件在漏极偏压为200V应力下持续时间为10s对应的输出曲线，实线为两种器件在无漏极偏压的情况下对应的输出曲线，作为参考对照组；在漏极偏压为200V，持续施加偏压应力时间为10s的条件下，从图5可知本实例的具有NiO X保护层的MIS-HEMT器件较传统器件，其电流崩塌量减小了90％， 从32.7％减小到了5.4％；
图6为本实施例采用的具有NiO X保护层的MIS-HEMT器件与传统的SiN X介质层制备的器件的击穿电压对比图。其中虚线为本实施例的具有NiO X保护层的MIS-HEMT器件的击穿曲线，实线为传统的SiN X介质层制备的器件的击穿曲线；从图6可知本实例提供的具有NiO X保护层的MIS-HEMT器件较传统器件，其击穿电压提高了52.2％，从452V提高到了688V。
实施例2
本实施例提供了一种具有NiO X保护层的MIS-HEMT器件，如图4所示，所述器件包括AlGaN/GaN外延1，AlGaN/GaN外延上表面的两端分别连接源漏电极2，源漏电极2上和AlGaN/GaN外延上表面连接源漏电极以外的区域从下到上依次沉积第一介质层3和第二介质层4，第二介质层4的上表面连接栅电极5，栅电极5位于源漏电极2之间，第一介质层3为NiO X，第一介质层3和第二介质层4共同作为MIS-HEMT器件的钝化层和栅介质层。第二介质层4为SiO 2。第一介质层3的厚度为15nm。第二介质层4的厚度为7nm。
本实施例还提供了一种制备所述具有NiO X保护层的MIS-HEMT器件的方法，包括以下步骤：
(1)进行台面隔离以及欧姆接触在AlGaN/GaN外延1的上表面制备源漏电极2，如图1所示；利用电子束蒸发设备在源漏电极2上和AlGaN/GaN外延1上表面连接源漏电极以外的区域沉积一层Ni金属，厚度为8nm，沉积速率为0.02nm/s，然后在快速退火炉中进行高温氧化处理，腔体温度为400℃，通入的氧气流量为50sccm，高温氧化处理的时间为25min，退火的升温速率为15℃/s，形成第一介质层NiO X，相应的结构示意图如图2所示；
(2)采用PECVD设备在第一介质层3上沉积第二介质层4，沉积温度为300℃，沉积厚度为7nm，如图3所示；最后进行栅电极5的沉积，如图4所示。
本实施例提供的具有NiO X保护层的MIS-HEMT器件的电流崩塌特性与击穿特性和实施例1类似，具体性能可参照实施例1中的附图5和附图6。
实施例3
本实施例提供了一种具有NiO X保护层的MIS-HEMT器件，如图4所示，所述器件 包括AlGaN/GaN外延1，AlGaN/GaN外延上表面的两端分别连接源漏电极2，源漏电极2上和AlGaN/GaN外延上表面连接源漏电极以外的区域从下到上依次沉积第一介质层3和第二介质层4，第二介质层4的上表面连接栅电极5，栅电极5位于源漏电极2之间，第一介质层3为NiO X，第一介质层3和第二介质层4共同作为MIS-HEMT器件的钝化层和栅介质层。第二介质层4为SiON。第一介质层3的厚度为12nm。第二介质层4的厚度为10nm。
本实施例还提供了一种制备所述具有NiO X保护层的MIS-HEMT器件的方法，包括以下步骤：
(1)进行台面隔离以及欧姆接触在AlGaN/GaN外延1的上表面制备源漏电极2，如图1所示；利用电子束蒸发设备在源漏电极2上和AlGaN/GaN外延1上表面连接源漏电极以外的区域沉积一层Ni金属，厚度为6nm，沉积速率为0.02nm/s，然后在快速退火炉中进行高温氧化处理，腔体温度为400℃，通入的氧气流量为50sccm，高温氧化处理的时间为30min，退火的升温速率为10℃/s，形成第一介质层NiO X，相应的结构示意图如图2所示；
(2)采用PECVD设备在第一介质层3上沉积第二介质层4，沉积温度为300℃，沉积厚度为10nm，如图3所示；最后进行栅电极5的沉积，如图4所示。
本实施例提供的具有NiO X保护层的MIS-HEMT器件的电流崩塌特性与击穿特性和实施例1类似，具体性能可参照实施例1中的附图5和附图6。
上述实施例为本发明较佳的实施方式，但本发明的实施方式并不受所述实施例的限制，其他的任何未背离本发明的精神实质与原理下所作的改变、修饰、替代、组合、简化，均应为等效的置换方式，都包含在本发明的保护范围之内。

Claims (10)

  1. 具有NiO X保护层的MIS-HEMT器件，其特征在于，所述器件包括AlGaN/GaN外延，AlGaN/GaN外延上表面的两端分别连接源漏电极，源漏电极上和AlGaN/GaN外延上表面连接源漏电极以外的区域从下到上依次沉积第一介质层和第二介质层，第二介质层的上表面连接栅电极，栅电极位于源漏电极之间，第一介质层为NiO X，第一介质层和第二介质层共同作为MIS-HEMT器件的钝化层和栅介质层。
  2. 根据权利要求1所述的具有NiO X保护层的MIS-HEMT器件，其特征在于，第二介质层为SiN X、SiO 2或者SiON。
  3. 根据权利要求1所述的具有NiO X保护层的MIS-HEMT器件，其特征在于，第一介质层的厚度为6-18nm。
  4. 根据权利要求1所述的具有NiO X保护层的MIS-HEMT器件，其特征在于，第二介质层的厚度为5-10nm。
  5. 制备如权利要求1至4任一项所述具有NiO X保护层的MIS-HEMT器件的方法，其特征在于，包括以下步骤：
    (1)进行台面隔离以及欧姆接触在AlGaN/GaN外延的上表面制备源漏电极，在源漏电极上和AlGaN/GaN外延上表面连接源漏电极以外的区域沉积一层Ni金属，高温氧化处理，形成第一介质层NiO X；
    (2)在第一介质层NiO X上沉积第二介质层，最后进行栅电极的沉积。
  6. 根据权利要求5所述的制备具有NiO X保护层的MIS-HEMT器件的方法，其特征在于，步骤(1)中第一介质层由电子束蒸发Ni金属，然后在快速退火炉中高温氧化处理形成。
  7. 根据权利要求5所述的制备具有NiO X保护层的MIS-HEMT器件的方法，其特征在于，步骤(1)中Ni金属的沉积速率为0.02-0.05nm/s，沉积的厚度为3-10nm。
  8. 根据权利要求5所述的制备具有NiO X保护层的MIS-HEMT器件的方法，其特征在于，步骤(1)中高温氧化处理在快速退火炉或炉管中进行。
  9. 根据权利要求8所述的制备具有NiO X保护层的MIS-HEMT器件的方法，其特征在于，步骤(1)中高温氧化处理时快速退火炉或炉管的腔体温度为300-400℃，氧气流量为50-100sccm，高温氧化处理的时间为10-30min，退火的升温速率为7-15℃/s。
  10. 根据权利要求5所述的制备具有NiO X保护层的MIS-HEMT器件的方法，其特征在于，步骤(2)中第二介质层沉积的方法为等离子体增强化学的气相沉积法即PECVD。
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