Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B12/00—Dynamic random access memory [DRAM] devices
  • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
  • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D88/00—Three-dimensional [3D] integrated devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
  • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
  • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
  • H10D84/85—Complementary IGFETs, e.g. CMOS
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
  • H10D84/0186—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/02—Manufacture or treatment characterised by using material-based technologies
  • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
  • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
  • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
  • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
  • H10D84/85—Complementary IGFETs, e.g. CMOS
  • H10D84/859—Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
  • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
  • H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays

Definitions

• CMOS complementary metal-oxide-semiconductor
• a semiconductor device can include a substrate having active devices such as transistors, capacitors, inductors and other components.
• active devices such as transistors, capacitors, inductors and other components.
• This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Nevertheless, such scaling down has also increased the complexity of processing and manufacturing of the semiconductor devices. As dimensions of semiconductor devices scale to smaller sub-micron sizes in advanced technology nodes, it becomes more challenging to increase the density of semiconductor devices. Improved structures and methods for manufacturing same are desired.
• the semiconductor apparatus can include a first stack of transistors including a first transistor formed on a substrate and a second transistor stacked on the first transistor along a Z direction substantially perpendicular to a substrate plane of the substrate.
• the semiconductor apparatus can include a second stack of transistors including a third transistor formed on the substrate and a fourth transistor stacked on the third transistor along the Z direction.
• the semiconductor apparatus can include a first routing track and a second routing track electrically isolated from the first routing track where the first and second routing tracks extend in an X direction parallel to the substrate plane.
• the semiconductor apparatus can include a first conductive trace and a fourth conductive trace configured to conductively couple a first gate of the first transistor and a fourth gate of the fourth transistor to the first routing track, respectively.
• the semiconductor apparatus can include a second conductive trace and a third conductive trace configured to conductively couple a second gate of the second transistor and a third gate of the third transistor to the second routing track, respectively.
• the semiconductor apparatus can include a first terminal structure configured to conductively couple four source/drain (S/D) terminals of the first, second, third and fourth transistors, respectively.
• S/D source/drain
• each of the first and second routing tracks is positioned in a plane above the first stack of transistors and the second stack of transistors along the Z direction.
• the semiconductor apparatus can further include a second terminal structure configured to conductively couple remaining S/D terminals of the first and second transistors.
• the semiconductor apparatus can further include a third terminal structure configured to conductively couple remaining S/D terminals of the third and fourth transistors.
• the semiconductor apparatus can further include an inverter circuit configured to invert an input signal of the inverter circuit into an output signal of the inverter circuit where the output signal is an inverted signal of the input signal.
• the inverter circuit can further include a third stack of transistors having a fifth transistor formed on the substrate and a sixth transistor stacked on the fifth transistor along the Z direction.
• the inverter circuit can include a fifth conductive trace configured to conductively couple a common gate to one of: the first and second routing tracks where the common gate includes a fifth gate of the fifth transistor and a sixth gate of the sixth transistor that are conductively coupled to the input signal.
• the semiconductor apparatus can include a conductive trace configured to conductively couple the input signal to the first routing track and a conductive trace configured to conductively couple the output signal to the second routing track.
• the semiconductor apparatus can include a conductive trace configured to conductively couple a first signal to the first routing track and a conductive trace configured to conductively couple a second signal to the second routing track.
• the second signal can be an inverted signal of the first signal.
• the second gate of the second transistor is stacked directly above the first gate of the first transistor along the Z direction
• the fourth gate of the fourth transistor is stacked directly above the third gate of the third transistor along the Z direction.
• the first conductive trace bypasses the second gate of the second transistor and the second transistor
• the third conductive trace bypasses the fourth gate of the fourth transistor and the fourth transistor.
• the first and the second transistors are complementary transistors including an n-type transistor and a p-type transistor
• the third and the fourth transistors are complementary transistors.
• the second gate of the second transistor is stacked on the first gate of the first transistor and the fourth gate of the fourth transistor is stacked on the third gate of the third transistor
• the first and second routing tracks are positioned in one or more planes above the first, second, third, and fourth gates along the Z direction
• the first and second conductive traces are spatially separated
• the first conductive trace bypasses the second gate of the second transistor and the second transistor
• the second conductive trace bypasses the first gate of the first transistor and the first transistor
• the third and fourth conductive trace are spatially separated
• the third conductive trace bypasses the fourth gate of the fourth transistor and the fourth transistor
• the fourth conductive trace bypasses the third gate of the third transistor and the third transistor
• the fifth conductive trace is conductively coupled to the first routing track.
• the semiconductor apparatus further includes a conductive trace configured to couple the output signal to the second routing track.
• a second gate area that is a maximum cross sectional area of the second gate intersecting with a plane substantially perpendicular to the Z direction is equal to or larger than a first gate area that is a maximum cross sectional area of the first gate intersecting with a plane substantially perpendicular to the Z direction, and a fourth gate area that is a maximum cross sectional area of the fourth gate intersecting with a plane substantially perpendicular to the Z direction, is equal to or larger than a third gate area that is a maximum cross sectional area of the third gate intersecting with a plane substantially perpendicular to the Z direction, the second gate is staggered above the first gate, and the fourth gate is staggered above the third gate.
• the second gate area is less than the first gate area
• the fourth gate area is less than the third gate area
• the second gate is staggered above the first gate
• the fourth gate is staggered above the third gate.
• the first transistor further includes a first set of semiconductor bars stacked along the Z direction in which the first gate surrounds and is attached to the first set of semiconductor bars
• the second transistor further includes a second set of semiconductor bars stacked along the Z direction in which the second gate surrounds and is attached to the second set of semiconductor bars.
• the second set of semiconductor bars is stacked on the first set of semiconductors bars along the Z direction.
• the first gate and the second gate are separated and conductively isolated by a dielectric layer including one or more dielectric materials, and the third gate and the fourth gate are separated and conductively isolated by the dielectric layer.
• Fig. 1A show a circuit schematic of an exemplary multiplexer (MUX) 100 according to an embodiment of the present disclosure
• Fig. IB shows an example of a transmission gate pair 110 according to an embodiment of the present disclosure
• FIG. 2A shows a top view of a 2D semiconductor apparatus 299 according to an embodiment of the present disclosure
• FIGS. 2B-2D show top views of respective portions in the 2D semiconductor apparatus 299 according to embodiments of the present disclosure
• FIGs. 3A-3B show perspective views of a 3D semiconductor apparatus 399 according to embodiments of the present disclosure
• FIG. 3C show atop view of the 3D semiconductor apparatus 399 according to an embodiment of the present disclosure
• Fig. 3D shows a cross sectional view of the 3D semiconductor apparatus 399 sectioned along DD’ of Fig. 3C according to an embodiment of the present disclosure
• Fig. 3E shows a cross sectional view of the 3D semiconductor apparatus 399 sectioned along EE’ of Fig. 3C according to an embodiment of the present disclosure
• Fig. 3F shows a cross sectional view of the 3D semiconductor apparatus 399 sectioned along FF’ of Fig. 3C according to an embodiment of the present disclosure
• Fig. 3G shows a top view of a first portion of the 3D semiconductor apparatus 399 according to an embodiment of the present disclosure
• Fig. 3H shows a top view of a second portion of the 3D semiconductor apparatus 399 according to an embodiment of the present disclosure
• Fig. 31 shows a combined top view of the first portion and the second portion of the 3D semiconductor apparatus 399 according to an embodiment of the present disclosure
• Fig. 3L shows a perspective view of the 3D semiconductor apparatus 399 including an inverter 320 according to an embodiment of the present disclosure.
• FIG. 4 illustrates atop view of an exemplary 3D semiconductor apparatus 499 according to an embodiment of the disclosure.
• Semiconductor devices such as transistors, can be stacked along a Z direction that is substantially perpendicular to a substrate plane of a semiconductor apparatus to increase a device density (i.e., a number of semiconductor devices per unit area of the substrate plane) of the semiconductor apparatus.
• the substrate plane can be a planar working surface of a substrate of the semiconductor apparatus.
• the semiconductor apparatus can be referred to as a three-dimensional (3D) semiconductor apparatus, and 3D integration can refer to manufacturing processes that can form the 3D semiconductor apparatus.
• Fig. 1 A show a circuit schematic of an exemplary multiplexer (MUX) 100 according to an embodiment of the present disclosure.
• the MUX 100 can include an inverter (or an inverter circuit) 120 and a pair of transmission gates (or a transmission gate pair) 110.
• the MUX 100 can have input signals ‘a’ and ‘b’, an output signal ‘q’, and a control signal ‘self
• the inverter 120 can invert a control signal ‘seF (or shortened as ‘sel’) of an input terminal 185 to generate a signal ‘!sel’ (or shortened as ‘!sel’) that is an inverted signal of ‘sel’.
• ‘!sel’ is an output signal of an output terminal 186 of the inverter 120.
• the output signal ‘q’ of the MUX 100 can be one of: the input signals ‘a’ and ‘b’.
• Fig. IB shows an example of the transmission gate pair 110 according to an embodiment of the present disclosure.
• the transmission gate pair 110 can further include a first transmission gate 181 having two transistors PI and N1 connected in parallel and a second transmission gate 182 having two transistors P2 and N2 connected in parallel.
• the input signals ‘a’ and ‘b’ are also input signals of the transmission gate pair 110.
• the output signal ‘q’ is also an output signal of the transmission gate pair 110.
• Fig. 3 A shows a 3D semiconductor apparatus 399 including a MUX 300 that has a transmission gate pair 310 according to an embodiment of the present disclosure.
• the MUX 300 and the transmission gate pair 310 are 3D implementations of the MUX 100 and the transmission gate pair 110, respectively.
• the transmission gate pair 310 includes a first stack of transistors 381 having PI formed on a substrate 301 of the 3D semiconductor apparatus 399 and N1 stacked on PI along aZ direction substantially perpendicular to a substrate plane 305 of the substrate 301.
• PI is formed on the substrate plane 305, and N1 is formed on a plane 307 that is parallel to the substrate plane 305.
• PI includes a gate Gl
• N1 includes a gate G2.
• the transmission gate pair 310 includes a second stack of transistors 382 having P2 formed on the substrate 301 and N2 stacked on P2 along the Z direction.
• P2 is formed on the substrate plane 305, and N2 is formed on the plane 307.
• P2 includes a gate G3, and N2 includes a gate G4.
• the first stack 381 implements the first transmission gate 181
• the second stack 382 implements the second transmission gate 182. Since the gates G1-G2 of the first stack 381 are controlled by different signals (e.g.,
• the gates G1-G2 can be split gates.
• the gates G3-G4 can be split gates.
• Split gates can refer to a stack of gates separated physically and electrically, and can be conductively connected to separate routing tracks via separate conductive traces. The split gates can have independent connections, for example, to be connected to different electrical signals.
• a first conductive trace 353 and a fourth conductive trace 323 can be configured to conductively couple the gates Gl and G4 to a first routing track 324, respectively.
• a second conductive trace 363 and a third conductive trace 313 can be configured to conductively couple the gates G2 and G3 to a second routing track 314, respectively.
• the first routing track 324 and the second routing track 314 that is electrically isolated from the first routing track 324 can be formed to provide different signals ‘seF and ‘!sel’, respectively.
• the split gates G1-G2 are coupled to ‘seF and ‘!sel’, via the first and second conductive traces 353 and 363, respectively, and G3-G4 are coupled to ‘ ! sel’ and ‘sel’ via the third and fourth conductive traces 313 and 323, respectively.
• PI and P2 are p-type transistors, such as p-type field effect transistors (pFETs), and N1 and N2 are n-type transistors, such as n-type FETs (nFETs).
• pFETs p-type field effect transistors
• nFETs n-type FETs
• Gates (e.g., G1 and G4) of a pFET (e.g., PI) and an nFET (e.g., N2) can be formed in different planes (e.g., G1 on the substrate plane 305 and G4 on the plane 307), and share or access a same routing track (e.g., the first routing track 324), and thus alleviating the need for additional metallization, such as nFET to pFET crossing required in some planar complementary FETs (CFETs) and reducing routing congestion.
• CFETs planar complementary FETs
• the first and second routing tracks 324 and 314 are substantially parallel along an X direction (or extend in the X direction) that is perpendicular to the Z direction, and thus the first and second routing tracks 324 and 314 have a unidirectional shape (e.g., a shape formed along a single direction, such as the X direction).
• the X direction is parallel to the substrate plane 305.
• the nFET to pFET crossing shown in Fig. 3A can be created efficiently with a single level of unidirectional metallization.
• the first and second routing tracks 324 and 314 can be conductively coupled to ‘sel’ and ‘!sel’, respectively ‘sel’ and ‘ ! sel’ can be at an opposite logic-level to each other.
• the first and second routing tracks 324 and 314 can be positioned on any suitable routing plane(s). In an example, the first and second routing tracks 324 and 314 can be positioned in a plane 309 that is stacked above the first stack 381 and the second stack 382 along the Z direction.
• a first terminal structure 391 can conductively couple four source/drain (S/D) terminals T2, T4, T6, and T8 of the transistors PI, Nl, P2, and N2, respectively to provide the output signal ‘q’.
• a second terminal structure 392 can conductively couple remaining S/D terminals T1 and T3 of PI and Nl, respectively.
• a third terminal structure 393 can conductively couple remaining S/D terminals T5 and T7 of P2 and N2, respectively.
• the first, second, and third terminal structures 391-393 can include any suitable conductive materials.
• the 3D semiconductor apparatus 399 can further include additional components, such as conductive traces to couple the first, second, and third terminal structures 391-393 to the signals ‘q’, ‘a’, and ‘b’, respectively.
• the present disclosure relates to the design and micro-fabrication of semiconductor devices and apparatuses.
• various fabrication processes can be implemented.
• the fabrication processes can include film-forming depositions, etch mask creation, patterning, material etching and removal, doping treatments, and/or the like.
• the fabrication processes can be performed repeatedly to form desired semiconductor device elements or components on a substrate of the semiconductor apparatus.
• semiconductor device e.g., transistors
• one plane e.g., an active device plane
• wiring/metallization formed above the active device plane can be characterized as two-dimensional (2D) circuits or 2D semiconductor apparatuses fabricated with 2D fabrication (or 2D integration).
• Scaling efforts can increase a device density (e.g., a number of transistors per unit area in 2D circuits), yet scaling efforts face challenges as scaling enters single digit nanometer semiconductor device fabrication nodes.
• 3D semiconductor circuits in which transistors are stacked on top of each other are used to increase a device density.
• 3D integration e.g., vertically stacking multiple semiconductor devices can overcome certain scaling limitations experienced in planar devices by increasing a device density (e.g., a transistor density when multiple transistors are stacked vertically) in volume rather than area of a semiconductor apparatus.
• a device density e.g., a transistor density when multiple transistors are stacked vertically
• Vertically stacking multiple semiconductor devices has been successfully demonstrated and implemented by the flash memory industry with the adoption of 3D NAND.
• implementing 3D integration in random logic designs can be challenging.
• Embodiments in the present disclosure can provide a 3D semiconductor apparatus (e.g., the 3D semiconductor apparatus 399) for a compact transmission gate pair (e.g., the transmission gate pair 310) for dense CFET logic layouts.
• the compact transmission gate pair can include split gates (e.g., G1-G2) and can be manufactured by a split-gate process flow.
• CMOS complementary metal-oxide semiconductor
• CMOS complementary metal-oxide semiconductor
• a transmission gate pair for example, formed by a pair of cross-coupled inverters, is a valuable design construct used to efficiently render logic cells such as a MUX, exclusive or (XOR), a latch, and the like.
• split gates are used instead of a common gate in a transmission gate pair.
• the MUX 100 can be based on a CMOS design and can include the transmission gate pair 110.
• the inverter 120 can include transistors P3 (e.g., a pFET) and N3 (e.g., an nFET).
• P3 includes a gate G5, a source terminal T9, and a drain terminal T10.
• N3 includes a gate G6, a source terminal Til, and a drain terminal T12.
• the gates G5 and G6 can be connected to ‘seF.
• the terminals T10 and T11 can be coupled together and ouput ‘!sel’.
• the transmission gate pair 110 can be formed by a pair of cross-coupled inverters, and thus the transmission gate pair 110 can be referred to as a cross-couple (XC).
• FIG. IB shows an enlarged view of the transmission gate pair 110 (or the XC 110).
• the XC 110 includes the first transmission gate 181 (also referred to as the first pass gate) and the second transmission gate 182 (also referred to as the second pass gate).
• PI and N1 in the first pass gate 181 can be a pair of CFETs
• P2 and N2 in the second pass gate 182 can be a pair of CFETs.
• a pair of CFETs e.g., PI and N2
• another pair of CFETs e.g., P2 and Nl
• PI is a pFET including G1 and the S/D terminals T1-T2; Nl is an nFET including G2 and the S/D terminals T3-T4; P2 is a pFET including G3 and the S/D terminals T5-T6; and N2 is an nFET including G4 and the S/D terminals T7-T8.
• Each of the S/D terminals T1-T8 can be a source terminal or a drain terminal.
• T1 when a voltage at T1 is higher than that of T2, T1 is a source terminal of PI and T2 is a drain terminal of PI.
• T1 is a drain terminal of PI and T2 is a source terminal of PI.
• Similar description can be applied to T3- T8.
• ‘seF when ‘seF is a logic 1, ‘!sel’ is a logic 0.
• PI and Nl can function as ‘open switches’, and thus the first pass gate 181 functions as an ‘open switch’. Accordingly, the first pass gate 181 does not pass the input signal ‘a’ to the output signal ‘q ⁇
• P2 and N2 can function as ‘closed switches’, and thus the second pass gate 182 functions as a ‘closed switch’. Accordingly, the second pass gate 182 can pass the input signal ‘b’ to the output signal ‘q’.
• the output signal ‘q’ can have a same logic-level as that of the input signal ‘b’.
• the XC 110 can have two signal paths, i.e., a first signal path and a second signal path corresponding to the first and second pass gates 181-182, respectively.
• ‘seT also referred to as a gate input
• can control e.g., switch
• the gate G1 in the first signal path while simultaneously controlling (e.g., switching) the gate G4 in the second signal path.
• switching e.g., switching
• ‘ ! sel’ can control (e.g., switch) the gate G2 in the first signal path while simultaneously controlling (e.g., switching) the gate G3 in the second signal path.
• the gate G1 controls a pFET (e.g., PI)
• the gate G4 controls an nFET (e.g., N2) that is complementary to PI.
• the gate G2 controls an nFET (e.g., Nl)
• the gate G3 controls a pFET (e.g., P2) that is complementary to Nl.
• the XC 110 can be formed using any suitable manufacturing processes and/or designs, such as in a 2D semiconductor apparatus 299 in Figs. 2A-2D using 2D manufacturing processes or 2D fabrication or in the 3D semiconductor apparatus 399 in Figs. 3A-3I using 3D manufacturing processes or 3D integration.
• Fig. 2A shows a top view of the 2D semiconductor apparatus 299 that can be used in certain technology nodes.
• the 2D semiconductor apparatus 299 includes a MUX 200 having a XC 210 where the MUX 200 and the XC 210 are 2D implementations of the MUX 100 and XC 110, respectively.
• the MUX 200 can further include an inverter (e.g., a 2D implementation of the inverter 120).
• PI includes G1 and the terminals T1-T2
• Nl includes G2 and the terminals T3-T4
• P2 includes G3 and the terminals T5-T6
• N2 includes G4 and the terminals T7-T8.
• PI and P2 are positioned in a row 251 of a substrate plane 201 of the 2D semiconductor apparatus 299, and the S/D terminals Tl, T2, T5 and T6 for PI and P2 can be formed in a region 231.
• the region 231 can be doped by a diffusion process, an implantation process, and/or the like.
• the terminals T2 and T6 are adjacent to each other and conductively coupled.
• Nl and N2 are positioned in a row 252 of the substrate plane 201, and the S/D terminals T3, T4, T7 and T8 for N1 and N2 can be formed by diffusion into a region 232.
• the region 232 can be doped by a diffusion process, an implantation process, and/or the like.
• the terminals T4 and T8 are adjacent to each other and conductively coupled.
• Each of the gates G1-G4 can include one or more structures, such as a dielectric structure and a conductive structure.
• the conductive structure can include one or more conductive materials, such as polysilicon, copper (Cu), ruthenium (Ru), and/or the like.
• Figs. 2B-2D show exemplary layouts of the gates G1-G4 and additional metallization (e.g., conductive structures 214-215) coupling the gates G1-G4 to signals, such as ‘seF and ‘!sel’ according to embodiments of the present disclosure.
• Fig. 2B shows a top view of the gates G1-G4 according to an embodiment of the present disclosure.
• FIG. 2C shows a top view of the conductive structures 214-215 according to an embodiment of the present disclosure.
• Fig. 2D shows a top view of the gates G1-G4 and the conductive structures 214-215 according to an embodiment of the present disclosure.
• the gate G1 includes a conductive structure 211
• the gate G2 includes a portion 213(1) of a conductive structure 213
• the gate G3 includes a portion 213(2) of the conductive structure 213
• the gate G4 includes a conductive structure 212.
• the conductive structures 211-213 can be formed using polysilicon.
• a unidirectional structure refers to a structure that is formed substantially along a single direction (e.g., the X direction, the Y direction, or the like) in a plane parallel to a substrate plane (e.g., the substrate plane 201).
• a bidirectional structure can refer to a structure where one portion and another portion of the structure are formed along two different directions (e.g., the X and Y directions) in a plane parallel to the substrate plane (e.g., the substrate plane 201).
• a unidirectional structure can have a unidirectional shape, and a bidirectional structure can have a bidirectional shape.
• an nFET to pFET crossing is implemented using a bidirectional structure (e.g., the conductive structure 214 including portions 214(l)-(2) along the X direction and a portion 214(3) along the Y direction).
• the conductive structure 214 can also be referred to as the bidirectional structure 214.
• the bidirectional structure 214 is used because G1 and G4 are positioned in different rows (e.g., the rows 251-252) and different columns 255-256 of the substrate plane 201, respectively. Referring to Fig. 3A, the nFET to pFET crossing can be created efficiently with the first routing track 324 having the unidirectional shape, and thus alleviating the need for the bidirectional structure 214.
• the portion 214(1) can conductively couple G1 (e.g., using the conductive structure 211) via a conductive trace 221.
• the portion 214(2) can conductively couple G4 (e.g., using the conductive structure 212) via a conductive trace 222.
• the portion 214(3) along the X direction connects the portions 214(l)-(2) along the Y direction. Further, the conductive structure 214 can be conductively coupled to ‘seT.
• an nFET to pFET crossing is implemented using a bidirectional structure (e.g., the conductive structure 213).
• the conductive structure 213 can also be referred to as the bidirectional structure 213.
• the conductive structure 213 can be coupled to the conductive structure 215 via a conductive trace 223. Further, the conductive structure 215 can be conductively coupled to ‘!sel’.
• the conductive structures 214-215 can be formed using one or more conductive materials, such as Cu, Ru, and/or the like.
• the conductive structures 214-215 can be formed on one or more planes that are different from a plane (e.g., the substrate plane 201) where the conductive structures 211-213 are formed.
• the XC 210 includes 4 transistors positioned on a same plane (e.g., the substrate plane 201).
• the layout used in the XC 210 can be rather complex, for example, the XC 210 includes the bidirectional structures 213-214.
• a dimension ‘dh’ along the Y direction needs to be large in order to have enough spacing between adjacent structures, and to accommodate tip-to-tip (e.g., a distance dhO between adjacent cells along the Y direction), tip-to-side (e.g., atip-to-side distance tsl), contact enclosure, and/or the like design rules needed for forming the XC 210.
• dh determines a smallest cell height of a cell where XC 210 can be placed.
• the cell is positioned between a first cell boundary 202 and a second cell boundary 203.
• dh includes three sections (e.g., dhA, dhB, and dhC) where dhA along the column 255 and dhC along the column 256 can traverse symmetrical structures and can be equal.
• dhA and dhB can traverse symmetrical structures and can be equal.
• dhA includes 0.5 dhO (i.e., half of the tip-to-tip distance dhO), a gate-past-active channel extension (also referred to as ‘endcap’) dhl, a gate width of the gate Gl, a contact to active channel space dh2, a contact width of the conductive structure 211, a poly past contact extension dh3 (also referred to as an enclosure), the tip-to-side distance tsl (e.g., a distance between the conductive structure 211 and the bidirectional structure 214).
• dhB corresponds to a width of the bidirectional structure 214.
• the adjacent structures include the conductive structures 214-215.
• the adjacent structures can also include the region 231 and the conductive structure 215.
• the bidirectional structure 213 e.g., a horizontal jog structure formed with polysilicon
• the bidirectional structure 214 e.g., a complemented jogged metal line
• the second set of transistors e.g., PI and N2
• certain design can have restrictions for a layout to use unidirectional shapes and/or a space is constrained along the Y direction where a dimension of a logic cell along the Y direction is constrained to be small, and thus the XC 210 shown in Figs. 2A-2D can be difficult to form or the XC 210 can result in density and performance loss for the 2D semiconductor apparatus 299.
• Embodiments, such as designs and methods, in the present disclosure can provide benefits to dense layouts in advanced technology nodes.
• an area of a cell or a device such as a logic cell, a MUX, a XC, or the like, can be represented by a number of tracks (or metal tracks) in the cell or the device, referred to as a cell height along the Y direction.
• the embodiments in the present disclosure can provide a structure for a XC, such as the XC 310, formed with a CFET technology that can be rendered in cells (e.g., logic cells) as small as 5 tracks (5T).
• the XC 310 has a width of 2 pitches and can optimally utilize “split gate” technology to design the XC, for example, using only two routing tracks (e.g., the first routing track 324 and the second routing track 314) and leaving space for other connections in the cell. Referring to Fig.
• one pitch can refer to a distance from a first center (e.g., marked by DD’) of a conductive structure (e.g., Gl) to a second center (e.g., marked by EE’) of an adjacent conductive structure (e.g., G3).
• the conductive structure and the adjacent conductive structure are formed using polysilicon, and thus the distance or the pitch can be referred to as ‘a poly pitch’. . .
• Additional contacts e.g., a source/drain contact for the first terminal structure 391) can be included in the XC 310, such as between the poly pitch.
• the poly pitch (e.g., between DD’ and EE’) is wide enough to accommodate the gates (e.g., Gl and G4) and the source/drain contact for the first terminal structure 391.
• the poly pitch can also be referred to as a ‘contacted poly pitch (or cpp).
• the XC can have the width of 2 cpp.
• the embodiments include a compact and resource efficient XC, such as the XC 310, for CFET-based logic designs.
• Figs. 3A-3C show two perspective views and atop view of the 3D semiconductor apparatus 399, respectively, according to embodiments of the present disclosure.
• Fig. 3D shows a cross sectional view of the 3D semiconductor apparatus 399 sectioned along DD’ of Fig. 3C.
• Fig. 3E shows a cross sectional view of the 3D semiconductor apparatus 399 sectioned along EE’ of Fig. 3C.
• Fig. 3F shows a cross sectional view of the 3D semiconductor apparatus 399 sectioned along FF’ of Fig. 3C.
• a semiconductor apparatus such as the 3D semiconductor apparatus 399, can include transistors (e.g., field-effect transistors and floating-gate transistors), integrated circuits, a semiconductor chip (e.g., memory chip including a 3D NAND memory device, a logic chip on a semiconductor die), a stack of semiconductor chips, a semiconductor package, a semiconductor wafer, and/or the like.
• transistors e.g., field-effect transistors and floating-gate transistors
• integrated circuits e.g., integrated circuits, a semiconductor chip (e.g., memory chip including a 3D NAND memory device, a logic chip on a semiconductor die), a stack of semiconductor chips, a semiconductor package, a semiconductor wafer, and/or the like.
• n- type or p-type transistors in split-gate CFET devices take advantage of the ability of either n- type or p-type transistors in split-gate CFET devices to be extended “north” (e.g. towards a VDD power rail that can supply a positive voltage to the 3D semiconductor apparatus 399) or “south” (e.g., towards a VSS power rail) along the Y direction.
• power rail(s) can be formed along the X direction.
• the power rail(s) can be formed on any suitable planes.
• the power rail(s) can be above or below the first and second stacks 381-382.
• the XC 310 includes the first stack of transistors 381 (e.g., PI and Nl).
• PI is a pFET and N1 is an nFET
• G1 of PI and G2 of Nl are split gates.
• PI is the lower transistor and Nl is the upper transistor, and a portion 397 at a first end of G1 is exposed (e.g., not covered by Nl and G2) such that the first routing track 324 can be connected to G1 via the first conductive trace 353 at the portion 397.
• a portion 398 at a second end of G3 of the lower-transistor (P2) is exposed (e.g., not covered by N2 and G4) such that the second routing track 314 can be connected to G3 via the third conductive trace 313 at the portion 398.
• the exposure of the lower gates (e.g., G1 and G3) can be achieved by any suitable manufacturing processes such as a variety of line-end cut approaches or different direct patterning solutions.
• the XC 310 can include the first and second routing tracks 324 and 314 (e.g., a pair of unidirectional conductive wires) with one delivering the control signal (in anon-limiting example, ‘sel’) and the other delivering the inverted signal (e.g., ‘!sel’) to the respective sets of neighboring transistor pairs.
• the control signal in anon-limiting example, ‘sel’
• the inverted signal e.g., ‘!sel’
• the split gates G1-G2 can be separated and conductively isolated by a dielectric layer 371 including one or more dielectric materials, and the split gates G3-G4 can be separated and conductively isolated by the dielectric layer 371. Alternatively, the split gates G3-G4 can be separated and conductively isolated by a dielectric layer that is different from the dielectric layer 371.
• split gate approaches can selectively expose and contact a bottom transistor (e.g., PI or P2) or a bottom gate (e.g., G1 or G3), and thus can allow a single unidirectional metal line (e.g., the first routing track 324) to conductively couple with the gate G1 of a p-type transistor (i.e., PI) via the first conductive trace 353 while conductively coupling with the gate G4 of an n-type transistor (i.e., N2) of the neighboring second stack 382 via the fourth conductive trace 323.
• a bottom transistor e.g., PI or P2
• a bottom gate e.g., G1 or G3
• a single unidirectional metal line e.g., the first routing track 324
• Fig. 3A shows the XC 310 using CFETs and occupying 2 cpp width along the X direction and compact enough to fit into a 5T cell height along the Y direction.
• the first conductive trace 353 and the fourth conductive trace 323 can be configured to conductively couple the gates G1 and G4 to the first routing track 324, respectively.
• the second conductive trace 363 and the third conductive trace 313 can be configured to conductively couple the gates G2 and G3 to the second routing track 314, respectively.
• the split gates G1 and G2 can be staggered or shifted, for example, along the Y direction.
• the portion 397 (e.g., at the first end of Gl) of the lower gate Gl can be exposed so that the first conductive trace 353 can access Gl and bypass the upper gate G2 and the upper transistor N1.
• a location of the portion 397 can be at any suitable location of Gl where the suitable location allows the first conductive trace 353 to bypass N1 and G2.
• a location of the portion 398 can be at any suitable location of G3 where the suitable location allows the third conductive trace 313 to bypass N2 and G4.
• a cross sectional area of a gate can be a largest cross sectional area (or a maximum cross sectional area) when the gate is sliced with planes parallel to the substrate plane 305.
• the cross sectional area of the gate refers to a maximum cross sectional area of the gate intersecting with a plane substantially perpendicular to the Z direction.
• cross sectional areas of the pair of split gates G1-G2 can have any suitable relationship. In an example, such as shown in Figs. 3A, 3C, and 3D, the cross sectional area of Gl is larger than that of G2.
• the cross sectional area of Gl can also be equal to or small than that of G2, and the split gates G1-G2 can be staggered.
• Cross sectional areas of the split gates G3-G4 can have any suitable relationship.
• the cross sectional area of G3 is larger than that of G4.
• the cross sectional area of G3 can also be equal to or small than that of G4.
• the split gates G3-G4 can be staggered. [0068] In an example, such as shown in Fig.
• the first and second conductive traces 353 and 363 are spatially separated, the first conductive trace 353 bypasses G2 and Nl, and the second conductive trace 363 bypasses G1 and PI, the third and fourth conductive trace 313 and 323 are spatially separated, the third conductive trace 313 bypasses G4 and N2, the fourth conductive trace 323 bypasses G3 and P2.
• the dielectric layer 371 can be sandwiched between the split gates G1-G2, and the dielectric layer 371 can also be sandwiched between the split gates G3-G4.
• the split gates G1-G2 can have any suitable spatial relationship within a plane that is parallel to the substrate plane 305.
• G2 can be shifted from G1 along the X direction, the Y direction, and/or any direction that is parallel to the substrate plane 305.
• the above description is also applicable to the split gates G3-G4.
• G2 can be stacked directly above G1 along the Z direction, for example, to maximize an overlapped area between the split gates G1-G2.
• G4 can be stacked directly above G3 along the Z direction.
• the XC 310 can further include a first channel structure 373 and a second channel structure 375.
• the first and second channel structures 373 and 375 can be surrounded by the first, second, and third terminal structures 391-393.
• the first channel structure 373 can include a portion 373(1) and a portion 373(2), for example, surrounded by the gates G1 and G3, respectively.
• the second channel structure 375 can include a portion 375(1) and a portion 375(2), for example, surrounded by the gates G2 and G4, respectively.
• the first channel structure 373 and the second channel structure 375 can have any suitable structure (including shapes and dimensions) and material systems such that the portion 373(1) can provide a semiconductor channel, such as a p-channel, when PI is in operation; the portion 373(2) can provide a semiconductor channel, such as a p-channel, when P2 is in operation; the portion 375(1) can provide a semiconductor channel, such as an n-channel, when Nl is in operation; and the portion 375(2) can provide a semiconductor channel, such as an n-channel, when N2 is in operation.
• the first channel structure 373 includes a first set of semiconductor bars (e.g., 2 semiconductor bars) stacked along the Z direction
• the second channel structure 375 includes a second set of semiconductor bars (e.g., 2 semiconductor bars) stacked along the Z direction.
• PI can include the portion 373(1) (also a portion of the first set of semiconductor bars) that is surrounded by and attached to Gl
• N1 can include the portion 375(1) (also a portion of the second set of semiconductor bars) that is surrounded by and attached to G2.
• P2 can include the portion 373(2) (also a portion of the first set of semiconductor bars) that is surrounded by and attached to G3
• N2 can include the portion 375(2) (also a portion of the second set of semiconductor bars) that is surrounded by and attached to G4.
• the second channel structure 375 is stacked above the first channel structure 373 along the Z direction and the second set of semiconductor bars is stacked on the first set of semiconductors bars along the Z direction.
• the portion 375(1) is stacked over the portion 373(1) along the Z direction
• the portion 375(2) is stacked over the portion 375(2) along the Z direction.
• a gate e.g., Gl, G2, G3, or G4
• a respective channel structure e.g., a portion of 373 or a portion of 375
• Gate materials can surround the respective channel structures on all sides in the GAA configuration.
• the first channel structure 373 can include portions 373(3)-(5) that can be covered or surrounded by the first, second, and third terminal structures 391-393, respectively.
• the second channel structure 375 can include portions 375(3)-(5) that can be covered or surrounded by the first, second, and third terminal structures 391-393, respectively.
• one or more of the portions 373(3)-(5) and 375(3)-(5) are removed from the 3D semiconductor apparatus 399.
• Fig. 3G shows a top view of a first portion of the 3D semiconductor apparatus 399 according to embodiments of the present disclosure.
• G2 is stacked over Gl, and the split gates G1-G2 are staggered.
• the first conductive trace 353 is connected to Gl at the portion 397 that is exposed (e.g., not covered by the upper gate G2). In an example, the first conductive trace 353 bypasses G2 and Nl.
• the second conductive trace 363 is connected to G2.
• G4 is stacked over G3, and the split gates G3-G4 are staggered.
• the third conductive trace 313 is connected to G3 at the portion 398 that is exposed (e.g., not covered by the upper gate G4). In an example, the third conductive trace 313 bypasses N2 and G4.
• the fourth conductive trace 323 is connected to G4.
• Fig. 3H shows a top view of a second portion of the 3D semiconductor apparatus 399 where the first routing track 324 is conductively connected to the first conductive trace 353 and the fourth conductive trace 323, and the second routing track 314 is conductively connected to the second conductive trace 363 and the third conductive trace 313.
• Fig. 31 shows a combined top view of the first portion and the second portion, and thus detailed descriptions are omitted for purposes of brevity.
• the first and second routing tracks 324 and 314 can be formed above the gates G1-G4.
• a bidirectional structure e.g., the conductive structure 214
• the first conductive trace 353 and the fourth conductive trace 323 can be configured to conductively couple the gates G1 and G4 to the first routing track 324, respectively, where the first routing track 324 is a unidirectional structure (e.g., parallel to the X direction).
• the gates G1 and G4 of a pFET (e.g., PI) and an nFET (e.g., N2) are formed in different planes (e.g., the substrate plane 305 and the plane 307), respectively, the gates G1 and G4 can share or access a same routing track (e.g., the first routing track 341) that has a unidirectional shape, and thus alleviating the need for additional metallization, such as nFET to pFET crossing implemented by the conductive structure 214. Accordingly, usage of bidirectional structures can be eliminated or reduced in the 3D semiconductor apparatus 399 and routing congestion can be reduced since forming a unidirectional structure can be easier than forming a bidirectional structure.
• a pFET e.g., PI
• nFET e.g., N2
• the gates G1 and G4 can share or access a same routing track (e.g., the first routing track 341) that has a unidirectional shape, and thus alleviating the
• Using bidirectional structures can increase an area of a semiconductor apparatus, and thus eliminating or reducing the bidirectional structures can reduce an area of the semiconductor apparatus. Further, stacking multiple transistors vertically along the Z direction (e.g., stacking PI and N1 vertically and stacking P2 and N2 vertically as shown in Figs. 3A, 3B, 3D, and 3E) can reduce an area of a semiconductor apparatus. Comparing Figs. 2A and 3C, a 2D area of the XC 210 in Fig. 2A covers a width of 2 poly pitch (e.g., 2 cpp) along the X direction and a - height of at least 8T along the Y direction. The height can be dh as described above.
• 2 poly pitch e.g., 2 cpp
• a 3D area of the XC 310 in Fig. 3C covers a width of 2 poly pitch (e.g., 2 cpp) along the X direction and a height of 5T along the Y direction.
• a transistor density in the 3D semiconductor apparatus 399 can be higher than a transistor density in the 2D semiconductor apparatus 299.
• a linear dimension (e.g., a sum of dl-d3) of the conductive structure 213 along the X and Y directions and a linear dimension (e.g., a sum of d4-d6) of the conductive structure 214 can be longer than a linear dimension d7 of the first and second routing tracks 324 and 314 along the X direction, and thus parasitic capacitances and/or resistances of each of the conductive structures 213-214 can be larger than those of each of the first and second routing tracks 324 and 314. Accordingly, performance of the XC 310 can be better than that of the XC 210.
• Fig. 3L shows the 3D semiconductor apparatus 399 where the MUX 300 further includes an inverter 320 that implements the inverter 120.
• the inverter 320 can include a third stack of transistors 383 having a transistor P3 formed on the substrate 301, such as on the substrate plane 305, and a transistor N3 stacked on P3 along the Z direction. N3 can be formed on a plane 308. Referring to Figs.
• P3 includes the gate G5, the terminal T9, and the terminal T10, and N3 includes the gate G6, the terminal Til, and the terminal T12 where the gates G5-G6 can be conductively coupled to form a common gate 395.
• the gates G5-G6 are physically connected.
• a fifth conductive trace 343 can be configured to conductively couple the common gate 395 to one of: the first and second routing tracks 324 and 314.
• the fifth conductive trace 343 is configured to couple the common gate 395 to the first routing track 324, and thus the common gate 395 can be coupled to ‘seF.
• P3 can further include a portion of the first channel structure 373.
• the portion of first channel structure 373 can provide a semiconductor channel, such as a p-channel, for P3.
• N3 can further include a portion of the second channel structure 375.
• the portion of the second channel structure 375 can provide a semiconductor channel, such as an n-channel, for N3.
• the third stack 383 can be positioned in any suitable location in the 3D semiconductor apparatus 399 with respect to the XC 310.
• the third stack 383 can be located outside the XC 310 and are parallel to the first stack 381 and the second stack 382. Alternately, the third stack 383 can be located inside the XC 310.
• the terminals T10-T11 can be coupled together as a terminal structure 303 and a conductive trace 333 can be configured to conductively couple the terminals T10-T11 or the terminal structure 303 to the second routing track 314 where the terminals T10-T11 can output the output signal (e.g., ‘ !sel’) of the inverter 320.
• the 3D semiconductor apparatus 399 can include one or more cells, such as logic cells that can implement one or more logic functions, memory cells, and/or the like.
• the 3D semiconductor apparatus 399 includes a cell where the XC 310 is in the cell. Further, the cell can include the inverter 320, and thus the MUX 300 is in the cell.
• Fig. 4 illustrates a top view of an exemplary 3D semiconductor apparatus 499 using the disclosed XC 310 for a CFET-based logic design according to an embodiment of the disclosure.
• the 3D semiconductor apparatus 499 can include a MUX 400 that further has a XC 410 and an inverter 420.
• the MUX 400 can include identical or similar components as those of the MUX 300
• the XC 410 can include identical or similar components as those of the XC 310
• the inverter 420 can include identical or similar components as those of the inverter 320, and thus detailed descriptions of the MUX 400, the XC 410, and the inverter 420 are omitted for purposes of brevity.
• the signal ‘a’ becomes a first input into the XC 410.
• the MUX 400 includes an inverter 440 that is configured to invert the signal ‘a’ into the signal ‘b’ which becomes a second input into the XC 410 where the signals ‘a’ and ‘b’ are inverted from each other, effectively making the signal ‘b’ a double inversion of the original input signal T.
• the MUX 400 can also include dummy gates 451-452 that, for example, can electrically isolate the MUX 400 from adjacent cells or multiplexers.
• the embodiments in the present disclosure are described with certain details, such as a particular geometry, a circuit schematic, and/or the like. It should be understood, however, that techniques herein may be practiced in other embodiments that depart from these specific details, and that such details are for purposes of explanation and not limitation.
• the embodiments can be applicable in forming a transmission gate pair including a first transmission gate and a second transmission gate.
• the first transmission gate can be controlled by a pair of signals (e.g., a pair of inverted signals) that are inverted from each other.
• the second transmission gate can also be controlled by the pair of inverted signals.
• each one of the pair of inverted signals can control two transistors where one of the two transistors is in the first transmission gate (corresponding to a first signal path) and another one of the two transistors is in the second transmission gate (corresponding to a second signal path).
• split gate structures and manufacturing processes can be used to form a first pair of split gates in the first transmission gate.
• a second pair of split gates can be formed in the second transmission gate.
• a transistor density and the performance of the transmission gate pair can be improved.
• the complexity of forming bidirectional structures can be reduced or eliminated by using split gates structures, and a layout or design for the transmission gate pair can be simplified.
• Each of the first transmission gate and the second transmission gate can include complementary transistors.
• the complementary transistors can have any suitable arrangement.
• an n-type transistor can be stacked above a p-type transistor.
• the p-type transistor can be stacked above the n-type transistor.
• the complementary transistors are CFETs.
• the CFETs can have any suitable arrangement.
• an nFET can be stacked above a pFET.
• the pFET can be stacked above the nFET.
• the embodiments described above can be suitably adapted to the above situations.
• multiple p-type transistors can be stacked.
• multiple n-type transistors can be stacked.
• multiple pFETs can be stacked, and multiple nFETs can be stacked.
• the embodiments described above can be suitably adapted to the above situations.
• the 3D semiconductor apparatuses 399 and 499, the MUX 300 and 400, and the XCs 310 and 410 in the present disclosure can be manufactured using any suitable structures, components, material systems, dimensions, and manufacturing processes, such as disclosed in U.S. Patent Application 16/206,513 filed on November 30, 2018 and titled “Semiconductor apparatus having stacked gates and method of manufacture thereof’ which is incorporated herein by reference in its entirety.
• the first stack 381 including the split gates G1-G2 and the dielectric layer 371) and the second stack 382 (including the split gates G3-G4 and the dielectric layer 371) can have similar or identical structure and material systems as those in U.S. Patent Application 16/206,513.
• the embodiments can be suitably adapted to a 3D semiconductor apparatus that can include additional 3D devices, such as a stacked SRAM as well as for other transistor types.
• substrate or “target substrate” as used herein generically refers to an object being processed in accordance with the invention.
• the substrate may include any material portion or structure of a device, particularly a semiconductor or other electronics device, and may, for example, be a base substrate structure, such as a semiconductor wafer, reticle, or a layer on or overlying a base substrate structure such as a thin film.
• substrate is not limited to any particular base structure, underlying layer or overlying layer, patterned or un- pattemed, but rather, is contemplated to include any such layer or base structure, and any combination of layers and/or base structures.
• the description may reference particular types of substrates, but this is for illustrative purposes only.

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