WO2021024810A1 - Dispositif à semi-conducteur au carbure de silicium et son procédé de fabrication - Google Patents

Dispositif à semi-conducteur au carbure de silicium et son procédé de fabrication Download PDF

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WO2021024810A1
WO2021024810A1 PCT/JP2020/028479 JP2020028479W WO2021024810A1 WO 2021024810 A1 WO2021024810 A1 WO 2021024810A1 JP 2020028479 W JP2020028479 W JP 2020028479W WO 2021024810 A1 WO2021024810 A1 WO 2021024810A1
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insulating film
silicon carbide
gate
width
gate insulating
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PCT/JP2020/028479
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English (en)
Japanese (ja)
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康太郎 田中
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住友電気工業株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present disclosure relates to a silicon carbide semiconductor device and a method for manufacturing the same.
  • a gate trench is formed on one main surface of the silicon carbide substrate, a gate electrode is provided so as to extend from the inside of the gate trench to the upper side of the main surface, and a gate insulating film is provided between the silicon carbide substrate and the gate electrode.
  • Known silicon carbide semiconductor devices for example, Patent Document 1.
  • the silicon carbide semiconductor device of the present disclosure includes a silicon carbide substrate having a main surface provided with a gate trench, a gate insulating film on the silicon carbide substrate, and a gate electrode on the gate insulating film.
  • the gate trench has an inner surface connected to the main surface
  • the gate insulating film includes a first portion provided on the inner surface and a second portion provided on the main surface and connected to the first portion.
  • the gate electrode has a base portion provided in the gate trench via the first portion, and an umbrella portion provided on the base portion and the second portion and in contact with the second portion.
  • the maximum width of the umbrella portion is larger than the width at the opening end of the gate trench, and the width of the umbrella portion is the width of the umbrella portion in a cross-sectional view from a direction perpendicular to the longitudinal direction of the gate trench. It is smaller than the maximum width on the main surface side of the position where the width is maximum.
  • FIG. 1 is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to the first embodiment.
  • FIG. 2 is a cross-sectional view (No. 1) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 3 is a cross-sectional view (No. 2) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 4 is a cross-sectional view (No. 3) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 5 is a cross-sectional view (No. 4) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 6 is a cross-sectional view (No.
  • FIG. 7 is a cross-sectional view showing the configuration of the silicon carbide semiconductor device according to the modified example of the first embodiment.
  • FIG. 8 is a cross-sectional view (No. 1) showing a method of manufacturing the silicon carbide semiconductor device according to the second embodiment.
  • FIG. 9 is a cross-sectional view (No. 2) showing a method of manufacturing the silicon carbide semiconductor device according to the second embodiment.
  • FIG. 10 is a cross-sectional view (No. 3) showing a method of manufacturing the silicon carbide semiconductor device according to the second embodiment.
  • an object of the present disclosure is to provide a silicon carbide semiconductor device capable of improving the dielectric strength of the gate insulating film and a method for manufacturing the same.
  • the dielectric strength of the gate insulating film can be improved.
  • the silicon carbide semiconductor device includes a silicon carbide substrate having a main surface provided with a gate trench, a gate insulating film on the silicon carbide substrate, and a gate electrode on the gate insulating film.
  • the gate trench has an inner surface connected to the main surface, and the gate insulating film is provided on the first portion provided on the inner surface and the first portion provided on the main surface.
  • the gate electrode has a second portion connected to the portion, and the gate electrode is provided on the base portion and the second portion provided in the gate trench via the first portion, and the second portion is provided.
  • the maximum width of the umbrella portion is larger than the width at the opening end of the gate trench in a cross-sectional view from a direction perpendicular to the longitudinal direction of the gate trench, which has an umbrella portion in contact with the portion.
  • the width is smaller than the maximum width on the main surface side of the position where the width of the umbrella portion is maximum.
  • one of the causes of dielectric breakdown of the gate insulating film is that the distance between the side surface of the gate electrode and the upper end of the trench may be smaller than the design value due to the misalignment of the gate electrode. It became clear.
  • the width of the gate electrode is maximized at the portion of the gate electrode in contact with the gate insulating film, the electric field tends to concentrate on the lower end of the side surface of the gate electrode. Therefore, when the distance between the side surface of the gate electrode and the upper end of the gate trench becomes smaller than the design value, an excessive electric field is applied to the gate insulating film between the vicinity of the corner of the opening end of the gate trench, which is sufficient.
  • Insulation withstand voltage may not be obtained.
  • the width of the umbrella portion of the gate electrode is smaller than the maximum width on the main surface side of the position where the width of the umbrella portion is maximum, so that the side surface of the gate electrode is included.
  • the electric field concentration at the lower end of the can be relaxed. Therefore, even if the distance between the side surface of the gate electrode and the open end of the gate trench becomes smaller than the design value due to misalignment during the manufacturing process, dielectric breakdown is suppressed by relaxing the electric field concentration, and the insulation of the gate insulating film is insulated.
  • the withstand voltage can be improved.
  • the side surface of the umbrella portion is convex toward the main surface between the position where the umbrella portion contacts the gate insulating film and the position where the width of the gate electrode is maximized. It may be a curved surface.
  • the width of the gate electrode is maximized when the side surface of the second portion is a curved surface that is convex toward the main surface between the position where the umbrella portion is in contact with the gate insulating film and the position where the width of the gate electrode is maximized.
  • the change in inclination becomes gentle toward the portion above the portion, and the electric field concentration is likely to be relaxed.
  • the radius of curvature of the curved surface may be 10% or more and 20% or less of the thickness of the gate insulating film.
  • the electric field concentration is moderately relaxed.
  • the gate insulating film may contain carbon.
  • a carbon-containing gate insulating film can be formed by thermal oxidation of the silicon carbide substrate.
  • an insulating film that is in contact with the side surface and the upper surface of the umbrella portion and has a composition different from that of the gate insulating film may be provided.
  • An insulating film having a composition different from that of the gate insulating film can be formed by thermal oxidation of the gate electrode.
  • the gate trench may include a trench side surface having a plane orientation ⁇ 0-33-8 ⁇ .
  • the gate trench includes a trench side surface having a plane orientation ⁇ 0-33-8 ⁇ , good mobility can be obtained on the side surface of the gate trench and channel resistance can be reduced.
  • the distance between the position where the width of the gate electrode on the side surface of the umbrella portion is maximized and the main surface may be 5 nm or more and 15 nm or less.
  • this distance is 5 nm or more and 15 nm or less, an excellent dielectric strength can be obtained by a simple process.
  • the method for manufacturing a silicon carbide semiconductor device includes a step of preparing a silicon carbide substrate having a main surface and a gate trench having an inner surface connected to the main surface on the main surface.
  • a gate insulating film having a step of forming, a first portion provided on the inner surface of the silicon carbide substrate, and a second portion provided on the main surface and connected to the first portion is formed.
  • the pseudo-gate electrode By performing the step of forming the pseudo-gate electrode having the above and the thermal oxidation of the pseudo-capsular portion, the pseudo-gate electrode is provided on the base portion, the base portion and the second portion, and the second portion is provided.
  • the maximum width of the umbrella portion is, in cross-sectional view from a direction perpendicular to the longitudinal direction of the gate trench, after the thermal oxidation, which comprises a step of forming a gate electrode having an umbrella portion in contact with the gate trench. It is larger than the width at the open end of the gate trench, and the width of the umbrella portion is smaller than the maximum width on the main surface side of the position where the width of the umbrella portion is maximum.
  • the oxidation proceeds preferentially in the vicinity of the portion of the pseudo-umbrella portion in contact with the gate insulating film, and the width of the portion of the pseudo-umbrella portion in contact with the gate insulating film becomes smaller than the maximum width. Therefore, the electric field concentration at the lower end of the side surface of the gate electrode can be relaxed. Therefore, even if the distance between the side surface of the gate electrode and the upper end of the trench becomes smaller than the design value due to misalignment during the manufacturing process, dielectric breakdown is suppressed by relaxing the electric field concentration, and the withstand voltage of the gate insulating film is reduced. Can be improved.
  • FIG. 1 is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to the first embodiment.
  • the silicon carbide semiconductor device 100 includes a silicon carbide substrate 1, a source electrode 16, a drain electrode 30, a source wiring 19, a gate insulating film 40, and a gate electrode. It mainly has 50 and an interlayer insulating film 45.
  • the silicon carbide substrate 1 includes a silicon carbide single crystal substrate 11 and a silicon carbide epitaxial layer 2.
  • the silicon carbide epitaxial layer 2 is provided on the silicon carbide single crystal substrate 11.
  • the silicon carbide substrate 1 has a first main surface 10 and a second main surface 20.
  • the second main surface 20 is on the opposite side of the first main surface 10.
  • the silicon carbide epitaxial layer 2 constitutes the first main surface 10.
  • the silicon carbide single crystal substrate 11 constitutes the second main surface 20.
  • the first main surface 10 is, for example, a surface inclined at an off angle of less than 8 ° with respect to the (000-1) surface or the (000-1) surface.
  • the off angle may be 6 ° or less, or 4 ° or less.
  • the off angle may be 2 ° or more.
  • the silicon carbide single crystal substrate 11 and the silicon carbide epitaxial layer 2 are, for example, polytype 4H hexagonal silicon carbide.
  • the silicon carbide single crystal substrate 11 contains an n-type impurity such as nitrogen (N) and has an n-type conductive type.
  • the drain electrode 30 is provided on the second main surface 20.
  • the drain electrode 30 is made of a material containing, for example, nickel silicide (NiSi) in the case of n-type and titanium aluminum (TiAl) in the case of p-type, depending on the conductive type of the silicon carbide single crystal substrate 11.
  • the drain electrode 30 may be made of a material containing, for example, titanium aluminum silicon (TiAlSi) regardless of whether it is n-type or p-type.
  • the silicon carbide substrate 1 mainly includes a drift region 12, a body region 13, a source region 14, and a contact region 18.
  • the drift region 12 contains an n-type impurity such as nitrogen and has an n-type conductive type (first conductive type).
  • the concentration of n-type impurities in the drift region 12 is, for example, about 7 ⁇ 10 15 cm -3 .
  • the concentration of n-type impurities in the silicon carbide single crystal substrate 11 may be higher than the concentration of n-type impurities in the drift region 12.
  • the body area 13 is on the drift area 12.
  • the body region 13 is in contact with the drift region 12.
  • the body region 13 contains a p-type impurity such as aluminum (Al) and has a p-type conductive type (second conductive type). Channels can be formed in the region of the body region 13 facing the gate insulating film 40.
  • the source area 14 is on the body area 13.
  • the source region 14 is in contact with the body region 13.
  • the source region 14 is separated from the drift region 12 by the body region 13.
  • the source region 14 contains an n-type impurity such as nitrogen or phosphorus (P) and has an n-type conductive type.
  • the source region 14 constitutes a part of the first main surface 10.
  • the concentration of the n-type impurity in the source region 14 may be higher than the concentration of the n-type impurity in the drift region 12.
  • the contact area 18 is in contact with, for example, the body area 13 and the source area 14.
  • the contact region 18 contains a p-type impurity such as aluminum and has a p-type conductive type.
  • the concentration of p-type impurities contained in the contact region 18 may be higher than the concentration of p-type impurities contained in the body region 13.
  • the contact region 18 connects the body region 13 and the first main surface 10.
  • the contact region 18 may form a part of the first main surface 10.
  • the concentration of the n-type impurity or the p-type impurity in each of the impurity regions can be measured by, for example, a secondary ion mass spectrometry (SIMS) method.
  • SIMS secondary ion mass spectrometry
  • a gate trench 6 is provided on the first main surface 10.
  • the first main surface 10 has a flat portion 5
  • the gate trench 6 has an inner surface 6A having a trench side surface 3 and a bottom surface 4.
  • the gate trench 6 is defined by a trench side surface 3 and a bottom surface 4.
  • the trench side surface 3 is connected to the flat portion 5. That is, the inner surface 6A is connected to the first main surface 10.
  • the trench side surface 3 penetrates the body region 13 and the source region 14 to reach the drift region 12.
  • the bottom surface 4 is connected to the trench side surface 3.
  • the bottom surface 4 is located in the drift region 12.
  • the gate trench 6 has, for example, a U-shape. That is, in a cross-sectional view, the trench side surface 3 is substantially perpendicular to the flat portion 5, and the bottom surface 4 is substantially parallel to the flat portion 5.
  • the source region 14, the body region 13, and the drift region 12 form a trench side surface 3 of the gate trench 6.
  • the drift region 12 constitutes the bottom surface 4 of the gate trench 6.
  • the gate insulating film 40 is provided on the inner surface 6A and the first main surface 10.
  • the gate insulating film 40 separates the gate electrode 50 and the silicon carbide substrate 1.
  • the gate insulating film 40 is, for example, a thermal oxide film of silicon carbide.
  • the gate insulating film 40 is made of, for example, a material containing silicon dioxide (SiO 2 ) and carbon (C).
  • the proportion of carbon in the gate insulating film 40 is, for example, 10% by mass or more and 90% by mass or less.
  • the ratio of carbon referred to here can be measured by, for example, the SIMS method.
  • the thickness of the gate insulating film 40 is, for example, about 20 nm or more and 80 nm or less.
  • the gate insulating film 40 is in contact with the source region 14, the body region 13, and the drift region 12 on the trench side surface 3.
  • the gate insulating film 40 is in contact with the drift region 12 on the bottom surface 4.
  • the gate insulating film 40 has a first portion 41 provided on the inner surface 6A and a second portion (flange portion) 42 provided on the first main surface 10 and connected to the first portion 41.
  • the gate electrode 50 is made of polysilicon containing impurities such as phosphorus, for example. Impurities such as phosphorus are included, for example, to adjust the threshold voltage.
  • the gate electrode 50 has a T-shaped cross-sectional shape in cross-sectional view. That is, the gate electrode 50 has a base portion 51 in the gate trench 6 and an umbrella portion 52 on the base portion 51.
  • the umbrella portion 52 projects on both sides of the gate trench 6 in the in-plane direction and covers the second portion 42 of the gate insulating film 40.
  • the in-plane direction is an in-plane direction perpendicular to the thickness direction of the silicon carbide substrate 1.
  • the lower end of the side surface 53 of the umbrella portion 52 is in contact with the second portion 42.
  • the side surface 53 is in-plane as it goes upward from the contact portion 57 between the upper inclined portion 54 that separates from the base 51 in the in-plane direction toward the lower end of the umbrella portion 52 and the second portion 42 of the gate insulating film 40. It has a lower inclined portion 55 that is separated from the base portion 51 in the direction.
  • the width of the gate electrode 50 is maximized at the height of the boundary 56 between the upper inclined portion 54 and the lower inclined portion 55. That is, the gate electrode 50 has the maximum width WG 1 of the gate electrode 50 at the height of the boundary 56. Further, the width WG 1 at the height of the boundary 56 is larger than the opening width WT at the upper end of the gate trench 6.
  • the side surface 53 is separated from the base portion 51 in the in-plane direction toward the upper side from the contact portion 57 with the second portion 42, so that the width WG 2 at the contact portion 57 of the gate electrode 50 is the width WG. Less than 1 .
  • the width of the umbrella portion 52 is smaller than the maximum width WG 1 on the first main surface 10 side of the position where the width of the umbrella portion 52 is maximum.
  • the upper inclined portion 54 and the lower inclined portion 55 may be formed by thermal oxidation of the gate electrode 50, and the lower inclined portion 55 is, for example, a first main element between the contact portion 57 and the boundary 56. It has a curved surface that is convex toward the surface 10. The radius of curvature of this convex curved surface is preferably 10% or more and 20% or less of the thickness of the gate insulating film 40.
  • the boundary 56 having the maximum width WG 1 of the gate electrode 50 may be too close to the gate insulating film 40, making it difficult to obtain an excellent dielectric strength.
  • the thermal oxidation of the gate electrode 50 occurs when the upper inclined portion 54 and the lower inclined portion 55 are formed by thermal oxidation of the gate electrode 50. It may be excessive. For example, during thermal oxidation of the gate electrode 50, oxygen atoms may newly reach the interface between the gate insulating film 40 and the body region 13 to further oxidize the body region 13, and the characteristics of this interface may deteriorate. is there.
  • the radius of curvature of the convex curved surface of the lower inclined portion 55 is 15% or more and 20% or less of the thickness of the gate insulating film 40.
  • the radius of curvature of the convex curved surface of the lower inclined portion 55 is, for example, 5 nm or more and 15 nm or less, preferably 10 nm or more and 15 nm or less.
  • the side surface 53 is preferably a gently convex curved surface. This is because when the inclination of the side surface 53 changes abruptly in the vicinity of the boundary 56, the electric field tends to concentrate in the vicinity of the boundary 56.
  • the base 51 is an example of the first part
  • the umbrella part 52 is an example of the second part.
  • the thickness of the portion located on the bottom side of the gate trench 6 from the first main surface 10 of the gate electrode 50 is, for example, 60% or more and 90% or less of the thickness of the gate electrode 50. is there.
  • a covering insulating film 60 is formed in contact with the side surface 53 and the upper surface 58 of the umbrella portion 52.
  • the coating insulating film 60 is a thermoplastic thermal oxide film containing impurities such as phosphorus.
  • the coating insulating film 60 is made of a material containing impurities such as silicon dioxide and phosphorus.
  • the coating insulating film 60 has a bird's beak shape between the umbrella portion 52 and the flat portion 5.
  • a coating insulating film 60 and a gate insulating film 40 are present between the boundary 56 and the flat portion 5, and the distance L between the boundary 56 and the flat portion 5 is preferably 5 nm or more and 15 nm or less, more preferably. Is 10 nm or more and 15 nm or less.
  • the boundary 56 having the maximum width WG 1 of the gate electrode 50 may be too close to the gate insulating film 40, and it may be difficult to obtain an excellent dielectric strength. In order to make the distance L more than 15 nm, complicated processing may be required.
  • the interlayer insulating film 45 is provided in contact with the covering insulating film 60 and the gate insulating film 40.
  • the interlayer insulating film 45 is made of, for example, a material containing silicon dioxide.
  • the interlayer insulating film 45 and the coating insulating film 60 electrically insulate the gate electrode 50 and the source electrode 16.
  • the source electrode 16 is in contact with the first main surface 10. Specifically, the source electrode 16 is in contact with the source region 14 on the first main surface 10. The source electrode 16 may be in contact with the contact region 18.
  • the source electrode 16 is made of a material containing, for example, titanium (Ti), aluminum, and silicon (Si).
  • the source electrode 16 is ohmic-bonded to, for example, the source region 14.
  • the source wiring 19 is in contact with the source electrode 16.
  • the source wiring 19 is made of a material containing, for example, aluminum.
  • 2 to 6 are cross-sectional views showing a method of manufacturing the silicon carbide semiconductor device 100 according to the first embodiment.
  • the silicon carbide substrate 1 is prepared.
  • the silicon carbide single crystal substrate 11 is prepared by using a sublimation method.
  • the maximum diameter of the silicon carbide single crystal substrate 11 is, for example, 100 mm or more, preferably 150 mm or more.
  • an epitaxial layer is formed on the silicon carbide single crystal substrate 11.
  • chemical vapor deposition using a mixed gas of silane (SiH 4 ) and propane (C 3 H 8 ) as a raw material gas, hydrogen gas (H 2 ) as a carrier gas, and ammonia (NH 3 ) as a dopant gas.
  • a phase growth Chemical Vapor Deposition: CVD
  • a drift region is formed by epitaxial growth on the silicon carbide single crystal substrate 11.
  • ion implantation is performed.
  • P-type impurities such as aluminum are ion-implanted into the surface of the drift region 12.
  • the body region 13 in contact with the drift region 12 is formed.
  • n-type impurities such as phosphorus are ion-implanted into the body region 13.
  • the source region 14 having an n-type conductive type is formed.
  • the source region 14 constitutes the first main surface 10.
  • the concentration of n-type impurities contained in the source region 14 is higher than the concentration of p-type impurities contained in the body region 13.
  • the contact region 18 is formed by ion-implanting a p-type impurity such as aluminum into the source region 14.
  • activation annealing is performed to activate the impurities ion-implanted into the silicon carbide substrate 1.
  • the temperature of activation annealing is preferably 1500 ° C. or higher and 1900 ° C. or lower.
  • the activation annealing time is, for example, about 30 minutes.
  • the atmosphere of the activating annealing is preferably an inert gas atmosphere, for example an argon (Ar) atmosphere.
  • the gate trench 6 is formed.
  • a mask having an opening is formed at a position where the gate trench 6 is formed.
  • a part of the source region 14, a part of the body region 13, and a part of the drift region are removed by etching.
  • etching method for example, Reactive Ion Etching (RIE), particularly Inductively Coupled Plasma Reactive Ion Etching (ICP-RIE) can be used.
  • RIE Reactive Ion Etching
  • ICP-RIE Inductively Coupled Plasma Reactive Ion Etching
  • inductively coupled plasma reactive ion etching using sulfur hexafluoride (SF 6 ) or a mixed gas of SF 6 and oxygen (O 2 ) as the reaction gas can be used.
  • the gate insulating film 40 is formed.
  • the silicon carbide substrate 1 is heated in an atmosphere containing oxygen, for example, at a temperature of 1300 ° C. or higher and 1400 ° C. or lower.
  • the gate insulating film 40 including the first portion 41 and the second portion 42 is formed.
  • the first portion 41 is in contact with the drift region 12 on the bottom surface 4 and is in contact with the drift region 12, the body region 13 and the source region 14 on the trench side surface 3.
  • the gate insulating film 40 formed by thermal oxidation of the silicon carbide substrate 1 contains, for example, silicon dioxide and carbon.
  • the gate insulating film 40 may be formed by another method such as a CVD method.
  • the gate insulating film 40 When the gate insulating film 40 is formed by thermal oxidation, a part of the silicon carbide substrate 1 is incorporated into the gate insulating film 40. Therefore, in the subsequent treatment, it is assumed that the first main surface 10 and the inner surface 6A are slightly moved to the interface between the gate insulating film 40 after thermal oxidation and the silicon carbide substrate 1. On the other hand, when the gate insulating film 40 is formed by a deposition method such as a CVD method, the silicon carbide substrate 1 is not incorporated into the gate insulating film 40, so that the positions of the first main surface 10 and the inner surface 6A do not move.
  • a deposition method such as a CVD method
  • the silicon carbide substrate 1 may be heat-treated (NO annealed) in a nitric oxide (NO) gas atmosphere.
  • NO nitric oxide
  • the silicon carbide substrate 1 is held for about 1 hour under the conditions of, for example, 1100 ° C. or higher and 1300 ° C. or lower.
  • nitrogen atoms are introduced into the interface region between the gate insulating film 40 and the body region 13.
  • introduction of a nitrogen atom if, NO gas other than the gas (e.g., N 2 O) may be used as the atmospheric gas.
  • Ar annealing using argon (Ar) as an atmospheric gas may be further performed.
  • the heating temperature of Ar annealing is, for example, higher than the heating temperature of NO annealing.
  • the Ar annealing time is, for example, about 1 hour.
  • the pseudo gate electrode 50X is formed.
  • the polysilicon film is deposited by the Low Pressure Chemical Vapor Deposition (LPCVD) method, and then the polysilicon film is dry-etched.
  • the pseudo gate electrode 50X has a base portion 51 and a pseudo umbrella portion 52X, and the side surface 53X of the pseudo umbrella portion 52X is inclined so as to move downward from the upper end of the pseudo umbrella portion 52X so as to be separated from the base portion 51 in the in-plane direction. It is a face.
  • the covering insulating film 60 is formed.
  • the pseudo gate electrode 50X is heated in an oxygen-containing atmosphere at, for example, a temperature of 850 ° C. or higher and 950 ° C. or lower.
  • the proportion of oxygen in the atmosphere is, for example, 10% by volume or more and 100% by volume or less, and preferably 80% by volume or more and 90% by volume or less.
  • the gate electrode 50 having the base portion 51 and the umbrella portion 52 is formed from the pseudo gate electrode 50X, and the covering insulating film 60 in contact with the side surface 53 and the upper surface 58 of the umbrella portion 52 is formed.
  • the progress of oxidation of the side surface 53X is not uniform, and the oxidation proceeds preferentially in the vicinity of the contact portion 57 with the second portion 42. As a result, a lower inclined portion 55 is formed on the side surface 53 so as to move upward from the contact portion 57 and away from the base portion 51 in the in-plane direction. Further, in the portion not affected by the preferential oxidation, the oxidation proceeds almost uniformly, and an upper inclined portion 54 is formed which is separated from the base portion 51 in the in-plane direction from the upper end of the umbrella portion 52 toward the lower side.
  • the coating insulating film 60 formed by thermal oxidation of the pseudo gate electrode 50X contains impurities such as silicon dioxide and phosphorus.
  • the width of the gate electrode 50 is maximized at the height of the boundary 56 between the upper inclined portion 54 and the lower inclined portion 55. That is, the umbrella portion 52 has the maximum width WG 1 of the gate electrode 50 at the height of the boundary 56. Further, the width WG 1 at the height of the boundary 56 is larger than the opening width WT at the upper end of the gate trench 6.
  • the side surface 53 is separated from the base portion 51 in the in-plane direction toward the upper side from the contact portion 57, so that the width WG 2 at the contact portion 57 of the gate electrode 50 is smaller than the width WG 1 . That is, the width of the umbrella portion 52 is smaller than the maximum width WG 1 on the first main surface 10 side of the position where the width of the umbrella portion 52 is maximum.
  • the degree of oxidation progress of the side surface 53X changes continuously, and the lower inclined portion 55 of the side surface 53 is a curved surface that is convex toward the first main surface 10 between the contact portion 57 and the boundary 56, for example. It becomes.
  • the coating insulating film 60 has a bird's beak shape between the umbrella portion 52 and the flat portion 5. Further, even at the boundary 56, the side surface 53 has a convex curved surface.
  • the interlayer insulating film 45 is formed.
  • the interlayer insulating film 45 is formed so as to cover the gate electrode 50 and the covering insulating film 60 and to be in contact with the gate insulating film 40.
  • the interlayer insulating film 45 is formed by, for example, a CVD method.
  • the interlayer insulating film 45 is made of, for example, a material containing silicon dioxide.
  • a part of the interlayer insulating film 45 and the gate insulating film 40 is etched so that an opening is formed on the source region 14 and the contact region 18. As a result, the contact region 18 and the source region 14 are exposed from the gate insulating film 40.
  • the source electrode 16 and the source wiring 19 are formed. Specifically, the source electrode 16 in contact with the source region 14 and the contact region 18 is formed on the first main surface 10.
  • the source electrode 16 is formed by, for example, a sputtering method.
  • the source electrode 16 is made of a material containing, for example, Ti, Al and Si.
  • alloying annealing is performed. Specifically, the source electrode 16 in contact with the source region 14 and the contact region 18 is held at a temperature of 900 ° C. or higher and 1100 ° C. or lower for about 5 minutes. As a result, at least a part of the source electrode 16 reacts with the silicon contained in the silicon carbide substrate 1 to silicide. As a result, the source electrode 16 that ohmic contacts with the source region 14 is formed.
  • the source wiring 19 that is electrically connected to the source electrode 16 is formed.
  • the source wiring 19 is formed on the source electrode 16 and the interlayer insulating film 45.
  • the drain electrode 30 is formed on the second main surface 20.
  • the drain electrode 30 is made of, for example, a material containing NiSi.
  • the material constituting the drain electrode 30 is formed by, for example, sputtering.
  • laser annealing is performed on the material formed by sputtering.
  • the material constituting the drain electrode 30 is alloyed.
  • alloying by heat treatment for example, rapid thermal Annealing (RTA) may be performed.
  • RTA rapid thermal Annealing
  • the back surface of the silicon carbide substrate 1 may be polished before the drain electrode 30 is formed.
  • the silicon carbide semiconductor device 100 according to the first embodiment can be manufactured.
  • the width WG 2 at the contact portion 57 of the gate electrode 50 is the width WG 1 at the height of the boundary 56 between the upper inclined portion 54 and the lower inclined portion 55. Smaller. Therefore, the electric field concentration at the lower end of the side surface 53 of the umbrella portion 52 can be relaxed. Therefore, even if the distance between the side surface 53 of the gate electrode 50 and the upper end of the gate trench 6 becomes smaller than the design value due to the misalignment of the gate electrode 50 during the manufacturing process, an excellent dielectric strength can be obtained.
  • the lower inclined portion 55 can be easily made into a convex curved surface by thermal oxidation of the gate electrode 50.
  • the inclination of the side surface 53 changes gently, and the electric field concentration can be further relaxed.
  • the coating insulating film 60 formed by thermal oxidation of the gate electrode 50 exists between the gate insulating film 40 and the umbrella portion 52, the electric field applied to the gate insulating film 40 can be further relaxed.
  • the gate electrode 50 even if the gate electrode 50 is misaligned, the gate electrode 50 having an appropriate width and capable of suppressing electric field concentration and the coating insulating film 60 can be easily formed.
  • FIG. 7 is a cross-sectional view showing the configuration of the silicon carbide semiconductor device according to the modified example of the first embodiment.
  • the gate trench 6 has a U-shape in cross-sectional view, whereas in the silicon carbide semiconductor device 101 according to the modified example, the gate trench 6 has a cross-sectional view.
  • the gate trench 6 has a V-shaped shape. That is, in the silicon carbide semiconductor device 101, the trench side surface 3 is inclined so that the width of the gate trench 6 tapers toward the bottom surface 4 in a cross-sectional view.
  • the trench side surface 3 is inclined at 52 ° or more and 72 ° or less with respect to the (000-1) surface, for example.
  • the trench side surface 3 includes, for example, a ⁇ 0-33-8 ⁇ surface.
  • the bottom surface 4 is substantially parallel to the flat portion 5.
  • the same effect as that of the silicon carbide semiconductor device 100 can be obtained by the silicon carbide semiconductor device 101 according to the modified example. Further, since the trench side surface 3 is inclined with respect to the (000-1) surface in an appropriate range, good mobility can be obtained on the trench side surface 3 and the channel resistance can be reduced.
  • the second embodiment is different from the first embodiment in terms of the manufacturing method. Further, based on the difference in the manufacturing method, the second embodiment is also different from the first embodiment in the configuration of the gate electrode 50 and the coating insulating film 60.
  • the configuration of the silicon carbide semiconductor device according to the second embodiment will also be described. 8 to 10 are cross-sectional views showing a method of manufacturing the silicon carbide semiconductor device according to the second embodiment.
  • the process up to the formation of the pseudo gate electrode 50X is performed (see FIG. 3).
  • a part of the gate insulating film 40 on the flat portion 5 is removed.
  • the pseudo umbrella portion 52X is between the portion exposed from the pseudo gate electrode 50X and the pseudo umbrella portion 52X and the flat portion 5 of the pseudo gate electrode 50X.
  • the portions near both side portions of the above are removed, and a part of the gate insulating film 40 is left between the pseudo umbrella portion 52X and the flat portion 5. That is, the edge of the gate insulating film 40 recedes inward from the edge of the pseudo umbrella portion 52X.
  • the ratio of the portion removed between the pseudo umbrella portion 52X and the flat portion 5 of the gate insulating film 40 is, for example, about 1% to 5%.
  • a part of the gate insulating film 40 is removed by, for example, wet etching.
  • wet etching For example, hydrofluoric acid (HF) is used as the etching solution for wet etching.
  • the covering insulating film 60 is formed.
  • the pseudo gate electrode 50X is heated in an oxygen-containing atmosphere at, for example, a temperature of 850 ° C. or higher and 950 ° C. or lower.
  • the proportion of oxygen in the atmosphere is, for example, 10% by volume or more and 100% by volume or less, and preferably 80% by volume or more and 90% by volume or less.
  • the progress of oxidation of the side surface 53X is not uniform, and the oxidation proceeds preferentially in the vicinity of the contact portion 57 with the second portion 42. As a result, a lower inclined portion 55 is formed on the side surface 53 so as to move upward from the contact portion 57 and away from the base portion 51 in the in-plane direction. Further, in the portion not affected by the preferential oxidation, the oxidation proceeds almost uniformly, and an upper inclined portion 54 is formed which is separated from the base portion 51 in the in-plane direction from the upper end of the umbrella portion 52 toward the lower side. To. As a result, the upper inclined portion 54 and the lower inclined portion 55 are formed on the side surface 53. Further, since the flat portion 5 is also oxidized, the gate insulating film 40 includes the portion in contact with the source region 14 and the contact region 18 again.
  • the coating insulating film 60 penetrates closer to the base 51 as compared with the first embodiment. That is, the coating insulating film 60 has the shape of a bird's beak having a deeper tip as compared with the first embodiment.
  • the processing after the formation of the interlayer insulating film 45 is performed in the same manner as in the first embodiment.
  • the silicon carbide semiconductor device 200 according to the second embodiment can be manufactured.
  • the coating insulating film 60 can be formed over a wider range between the umbrella portion 52 and the flat portion 5 in the thickness direction of the silicon carbide substrate 1, the withstand voltage is increased. Can be further improved.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

L'invention concerne un dispositif à semi-conducteur au carbure de silicium qui comporte un substrat en carbure de silicium ayant une surface principale sur laquelle est disposée une tranchée de grille, un film d'isolation de grille sur le substrat de carbure de silicium, et une électrode de grille sur le film d'isolation de grille. La tranchée de grille a une surface interne reliée à la surface principale. Le film d'isolation de grille a une première partie disposée sur la surface interne, et une seconde partie qui est disposée sur la surface principale et est reliée à la première partie. L'électrode de grille a une base disposée à l'intérieur de la tranchée de grille, la première partie étant interposée entre celles-ci, et une partie de parapluie qui est disposée sur la base et la seconde partie et qui est en contact avec la seconde partie. Dans la vue en coupe transversale à partir d'une direction perpendiculaire à la direction longitudinale de la tranchée de grille, la largeur maximale de la partie de parapluie est supérieure à la largeur de l'extrémité d'ouverture de la tranchée de grille, et la largeur de la partie de parapluie est inférieure à la largeur maximale plus loin du côté de la surface principale que la position à laquelle la largeur de la partie de parapluie est au maximum.
PCT/JP2020/028479 2019-08-05 2020-07-22 Dispositif à semi-conducteur au carbure de silicium et son procédé de fabrication WO2021024810A1 (fr)

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WO2013114477A1 (fr) * 2012-01-31 2013-08-08 パナソニック株式会社 Dispositif à semi-conducteur et son procédé de fabrication
JP2014222734A (ja) * 2013-05-14 2014-11-27 パナソニック株式会社 半導体装置及びその製造方法
JP2015082632A (ja) * 2013-10-24 2015-04-27 住友電気工業株式会社 炭化珪素半導体装置およびその製造方法
JP2016012677A (ja) * 2014-06-30 2016-01-21 住友電気工業株式会社 炭化珪素半導体装置の製造方法および炭化珪素半導体装置
JP2016018860A (ja) * 2014-07-07 2016-02-01 株式会社東芝 半導体装置およびその製造方法
WO2018135147A1 (fr) * 2017-01-17 2018-07-26 富士電機株式会社 Dispositif à semiconducteur et procédé de fabrication d'un dispositif à semiconducteur
JP2018182032A (ja) * 2017-04-11 2018-11-15 富士電機株式会社 炭化珪素半導体装置および炭化珪素半導体装置の製造方法
JP2019096794A (ja) * 2017-11-24 2019-06-20 国立研究開発法人産業技術総合研究所 半導体装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013114477A1 (fr) * 2012-01-31 2013-08-08 パナソニック株式会社 Dispositif à semi-conducteur et son procédé de fabrication
JP2014222734A (ja) * 2013-05-14 2014-11-27 パナソニック株式会社 半導体装置及びその製造方法
JP2015082632A (ja) * 2013-10-24 2015-04-27 住友電気工業株式会社 炭化珪素半導体装置およびその製造方法
JP2016012677A (ja) * 2014-06-30 2016-01-21 住友電気工業株式会社 炭化珪素半導体装置の製造方法および炭化珪素半導体装置
JP2016018860A (ja) * 2014-07-07 2016-02-01 株式会社東芝 半導体装置およびその製造方法
WO2018135147A1 (fr) * 2017-01-17 2018-07-26 富士電機株式会社 Dispositif à semiconducteur et procédé de fabrication d'un dispositif à semiconducteur
JP2018182032A (ja) * 2017-04-11 2018-11-15 富士電機株式会社 炭化珪素半導体装置および炭化珪素半導体装置の製造方法
JP2019096794A (ja) * 2017-11-24 2019-06-20 国立研究開発法人産業技術総合研究所 半導体装置

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