WO2021012161A1 - 阵列基板及其制备方法、显示装置 - Google Patents

阵列基板及其制备方法、显示装置 Download PDF

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Publication number
WO2021012161A1
WO2021012161A1 PCT/CN2019/097141 CN2019097141W WO2021012161A1 WO 2021012161 A1 WO2021012161 A1 WO 2021012161A1 CN 2019097141 W CN2019097141 W CN 2019097141W WO 2021012161 A1 WO2021012161 A1 WO 2021012161A1
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Prior art keywords
thin film
film transistor
sub
coupled
active layer
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PCT/CN2019/097141
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English (en)
French (fr)
Inventor
许晨
程鸿飞
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京东方科技集团股份有限公司
北京京东方技术开发有限公司
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Priority to CN201980001115.3A priority Critical patent/CN112544002A/zh
Priority to PCT/CN2019/097141 priority patent/WO2021012161A1/zh
Priority to US16/768,413 priority patent/US11488983B2/en
Publication of WO2021012161A1 publication Critical patent/WO2021012161A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1229—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with different crystal properties within a device or between different devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the embodiments of the present disclosure relate to the field of display technology, and in particular, to an array substrate, a preparation method thereof, and a display device.
  • the manufacturing of array substrates of existing display panels mainly includes low-temperature polysilicon (LTPS) technology, oxide technology, amorphous silicon technology and organic thin film transistor technology.
  • LTPS technology has been widely used in the manufacturing process of display panels, but due to technical limitations, LTPS technology can not be used in the manufacturing of high-generation line (greater than G6) panels; although the oxide has a higher mobility, it is stable Due to poor performance and uniformity, the current mass production process is difficult; amorphous silicon thin film transistors have low mobility and poor driving ability, which cannot meet the needs of large-size, high-resolution, and high-refresh display panels.
  • the embodiments of the present disclosure provide an array substrate, a preparation method thereof, and a display device.
  • an array substrate includes a substrate having a display area and a peripheral area surrounding the display area, the display area including sub-pixels arranged in an array; and a plurality of thin film transistors located on the substrate, including the peripheral area
  • the first active layer of the first thin film transistor and the second active layer of the nearest second thin film transistor have a first distance in the row and/or column direction, and the adjacent second active layer There is a second distance in the row and/or column direction between the layers, and the first distance is equal to the second distance.
  • the first active layer and the second active layer have the same shape.
  • the first active layer and the second active layer have the same size.
  • At least one of the first active layers includes a polycrystalline semiconductor material.
  • the second active layer includes an amorphous semiconductor material.
  • the second active layer includes a polycrystalline semiconductor material.
  • At least the second active layer adjacent to the peripheral region includes a polycrystalline semiconductor material.
  • At least one of the first active layer and/or the second active layer includes a stacked layer structure, and the stacked layer structure includes sequentially arranged in a direction perpendicular to the substrate and away from the gate of the thin film transistor.
  • the gate of the thin film transistor is located between the active layer of the thin film transistor and the substrate
  • the peripheral area includes at least one driving circuit.
  • the driving circuit includes a first sub-thin film transistor, the gate and first source/drain of the first sub-thin film transistor are coupled to the data input terminal, and the second source/drain of the first sub-thin film transistor is connected to the first Node coupling; a second sub-thin film transistor, the gate of the second sub-thin film transistor is coupled to the reset terminal, the first source/drain of the second sub-thin film transistor is coupled to the first node, the second sub-thin film The second source/drain of the transistor is coupled to the first voltage terminal; the third sub thin film transistor, the gate of the third sub thin film transistor is coupled to the first node, and the first source/drain of the third sub thin film transistor The electrode is coupled to the first clock signal terminal, the second source/drain of the third sub thin film transistor is coupled to the data output end; the fourth sub thin film transistor, the gate of the fourth sub thin film transistor is coupled to the second node Connected,
  • the aspect ratio of the active layer of the seventh sub thin film transistor is configured to be smaller than the active layer of the eighth sub thin film transistor.
  • At least one of the first active layers includes active layers of the first to eleventh sub-thin film transistors.
  • the active layer of the third sub-thin film transistor has a stacked structure.
  • the sub-thin film transistor includes a first semiconductor layer including a polycrystalline semiconductor material, a second semiconductor layer including an amorphous semiconductor material, and a second semiconductor layer located in the direction perpendicular to the substrate and away from the gate of the sub-thin film transistor.
  • a manufacturing method of an array substrate includes: providing a substrate having a display area and a peripheral area surrounding the display area, the display area including sub-pixels arranged in an array; and forming a plurality of thin film transistors on the substrate,
  • the thin film transistor includes a first thin film transistor located in the peripheral area and a second thin film transistor in each sub-pixel of the display area. Further, there is a first distance in the row and/or column direction between the first active layer of the first thin film transistor and the second active layer of the nearest second thin film transistor, and the adjacent second active layer There is a second distance in the row and/or column direction between the active layers, and the first distance is equal to the second distance.
  • forming the thin film transistor includes: forming a semiconductor layer including an amorphous semiconductor material on a substrate; the semiconductor layer includes a first portion corresponding to the first active layer and a second portion corresponding to the first active layer.
  • the source layer corresponds to the second part one-to-one; and the amorphous semiconductor material contained in at least one of the first parts is converted into a polycrystalline semiconductor material.
  • the method further includes converting the amorphous semiconductor material contained in at least the second portion adjacent to the peripheral region into a polycrystalline semiconductor material.
  • the conversion includes laser annealing.
  • the conversion includes laser annealing the semiconductor layer using a mask.
  • the mask has openings arranged in an array and corresponding to the sub-pixels one-to-one, and microlenses corresponding to the openings one-to-one and aligned with the openings along the light transmission direction.
  • the semiconductor layer is patterned to remove parts of the semiconductor layer other than the first part and the second part and the first part and the second part are shaped to form the first active layer and the second active layer. In the embodiment of the present disclosure, shaping is performed so that the first active layer and the second active layer have the same shape, or have the same shape and size.
  • a display device includes the array substrate according to the first aspect of the present disclosure.
  • Fig. 1 is a top view of an array substrate according to an embodiment of the present disclosure
  • FIG. 2 is a side view of the array substrate along the AA′ axis in FIG. 1 according to an embodiment of the present disclosure
  • FIG. 3 is a side view of the array substrate along the AA′ axis in FIG. 1 according to an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of a driving circuit located in a peripheral area according to an embodiment of the present disclosure
  • FIG. 5 is a timing diagram of each signal of the driving circuit shown in FIG. 4;
  • FIG. 6 is a flowchart of a method for preparing an array substrate according to an embodiment of the present disclosure
  • FIG. 7 is a flowchart of a method of forming a thin film transistor according to an embodiment of the present disclosure
  • FIG. 8 is a schematic diagram of a mask according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of forming an active layer by patterning according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • the terms “upper”, “lower”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom” and the directions indicated in the drawings The derivative word should involve public.
  • the terms “overlying”, “on top of”, “positioned on top” or “positioned on top” mean that a first element such as a first structure is present on a second element such as a second structure Above, where there may be an intermediate element such as an interface structure between the first element and the second element.
  • the term “contact” means to connect a first element such as a first structure and a second element such as a second structure, and there may or may not be other elements at the interface of the two elements.
  • the source and drain (emitter and collector) of the transistor are symmetrical, and the source and drain (emitter and collector) of the N-type transistor and the P-type transistor are different The direction of the conduction current is opposite. Therefore, in the embodiments of the present disclosure, the controlled middle terminal of the transistor is collectively called the gate, and the signal input terminal and the signal output terminal can be collectively called the source/drain.
  • terms such as “first” and “second” are only used to distinguish one component (or a part of a component) from another component (or another part of a component).
  • Microlens array (MAL) technology can also be used to manufacture array substrates, but MLA has many problems to be solved urgently.
  • MLA is a regionalized crystallization technology, which requires a specific mask and microlens to heat and melt the amorphous silicon in a specific area to crystallize.
  • the mask and the microlens need to be combined and used in the manufacturing process, and the size of the mask is smaller than the size of the substrate, so multiple irradiations are required to complete the processing of all areas.
  • this process can be achieved by moving the substrate or mask.
  • the active layer has various shapes and positions.
  • the active layer spacing or the shape of the active layer in the peripheral area and the pixel area are different, and the corresponding mask and microlens are different. This makes it difficult to perform crystallization processing by moving the mask and microlenses in steps of the relative pitch.
  • the use of a variety of masks and microlenses will result in an increase in the basic manufacturing cost and a long manufacturing process.
  • the present disclosure provides an array substrate on which thin film transistors can use a single combined mask and microlenses to complete the conversion of an active layer at a desired position on the array substrate. Thus, the manufacturing cost and time of the array substrate are reduced.
  • FIG. 1 schematically shows a top view of an array substrate 100 according to an embodiment of the present disclosure.
  • the array substrate 100 includes a substrate 101.
  • the substrate 101 includes a display area AA and peripheral areas BB located on the left and right sides of the display area AA.
  • the peripheral area BB may also be on the upper and lower sides or four sides of the display area AA.
  • the peripheral area B may include a GOA (Gate driver on Array, array substrate row driving circuit) area.
  • the array substrate further includes a thin film transistor located on the substrate 101.
  • the thin film transistor includes a first thin film transistor M 1 located in the peripheral area BB and a second thin film transistor M 2 located in the display area AA.
  • the first distance L 1 between the first active layer of the first thin film transistor M 1 and the second active layer closest to the second thin film transistor M 2 and the adjacent second active layer is the same.
  • the distance refers to the minimum distance between two components.
  • the peripheral area BB is located on the upper and lower sides or four sides of the display area AA.
  • the first distance between the first active layer and the closest second active layer may be the same as the second distance between the adjacent second active layers.
  • the peripheral area BB is located on four sides of the display area AA. In the row and column directions, the first distance between the first active layer and the nearest second active layer is the same as the second distance between the adjacent second active layers, respectively.
  • the first active layer may have the same shape as the second active layer, for example, a rectangle. Further, in an embodiment, the first active layer may have the same shape and size as the second active layer. In the embodiment, the size refers to the size in the plane where the active layer is located, such as length and width.
  • the first thin film transistor and the second thin film transistor M 1 M of the active layer 2 may be rectangular.
  • FIG. 2 schematically shows a side view of the array substrate 100 along the AA′ axis in FIG. 1 according to an embodiment of the present disclosure.
  • the first thin film transistor M 1 2 comprises: a first gate electrode 102 on the substrate 101; the gate insulating layer 102 is disposed on the first gate electrode 103; a first insulating layer on the gate 103 active layer 104; and a first thin film transistor is located on the first active layer 104 is M 1 a first source / drain electrode 105 and a second source / drain electrode 106.
  • M 2 second thin film transistor comprising: a second gate electrode 102 '; 102 in the second gate' 103 on the gate insulating layer; and a second active layer 104 on the gate insulating layer 103 '; and a second the active layer 104 'on the second thin film transistor T 2, a first source / drain electrode 105' and a second source / drain electrode 106 '.
  • the active layer of the thin film transistor of the array substrate is formed of an amorphous semiconductor material such as amorphous silicon, but the polycrystalline semiconductor material has a higher electron mobility so that the thin film transistor has a stronger driving ability.
  • the amorphous semiconductor material can be crystallized through a single combined mask and microlens to convert a required part of the amorphous semiconductor material into a polycrystalline semiconductor material. This not only reduces the types and quantities of masks and microlenses, but also reduces manufacturing time.
  • At least one of the first active layers 104 includes a polycrystalline semiconductor material (for example, polycrystalline silicon).
  • the second active layer 104' includes an amorphous semiconductor material (for example, amorphous silicon).
  • the display area can be reserved by crystallizing only the peripheral area AA amorphous active layer to significantly improve the driving capability of the display panel.
  • At least one of the first active layer 104 and at least one of the second active layer 104' may include a polycrystalline semiconductor material.
  • the second active layer 104' adjacent to the peripheral region BB may include a polycrystalline semiconductor material.
  • FIG. 3 schematically shows a side view of the array substrate along the AA' axis in FIG. 1 according to other embodiments of the present disclosure.
  • some thin film transistors for example, driving transistors
  • an array substrate is provided on the array substrate.
  • the active layer of the thin film transistor has a stacked structure.
  • the laminated structure can have a small leakage current while satisfying the driving capability.
  • the difference between FIG. 3 and FIG. 2 is that the first active layer 104 or the second active layer 104' comprising polycrystalline semiconductor material as shown in FIG. 2 has a laminated structure.
  • the stacked structure of the active layer sequentially includes: a first semiconductor layer 1041 on the gate insulating layer 103, the first semiconductor layer 1041 may include a polycrystalline semiconductor material (for example, polysilicon); on the first semiconductor layer 1041
  • the second semiconductor layer 1042, the second semiconductor layer 1042 may include an amorphous semiconductor material, for example, amorphous silicon; and a third semiconductor layer 1043 located at the opposite end of the second semiconductor layer 1042, the third semiconductor layer 1043
  • An amorphous semiconductor material may be included, for example, amorphous silicon.
  • the third semiconductor layer has a higher carrier concentration than the second semiconductor layer. The desired carrier concentration can be achieved by appropriate doping.
  • the thin film transistor is a bottom gate type thin film transistor. However, this is not intended to be limiting. In the embodiments of the present disclosure, the thin film transistor may also be a top-gate thin film transistor.
  • the active layer is located under the gate insulating layer.
  • the stacked structure of the active layer sequentially includes: a first semiconductor layer 1041 located under the gate insulating layer 103, a second semiconductor layer 1042 located under the first semiconductor layer 1041, and opposite ends located under the second semiconductor layer 1042 The third semiconductor layer 1043.
  • FIG. 4 shows a schematic diagram of a driving circuit 400 located in the peripheral area BB according to an embodiment of the present disclosure.
  • the peripheral area BB includes at least one driving circuit 400.
  • the driving circuit 400 will be described in detail below with reference to the drawings.
  • the driving circuit 400 includes: a first sub-thin film transistor T 1 , the gate and first source/drain of the first sub-thin film transistor T 1 are coupled to the data input terminal INPUT, the first sub-thin film The second source/drain of the transistor T 1 is coupled to the first node Q 1 ; the second sub-thin film transistor T 2 , the gate electrode of the second sub-thin film transistor T 2 is coupled to the reset terminal RESET, the second sub The first source/drain of the thin film transistor T 2 is coupled to the first node Q 1 , the second source/drain of the second sub thin film transistor T 2 is coupled to the first voltage terminal VSS; the third sub thin film transistor T 3 , the gate electrode of the third sub thin film transistor is coupled to the first node Q 1 , the first source/drain of the third sub thin film transistor T 3 is coupled to the first clock signal terminal CLK, and the third sub thin film transistor a second thin film transistor T 3 of the source / drain and the output terminal o
  • the fourth sub-gate thin film transistor T and the source node. 4 Q 2 coupled to the first
  • the first source/drain of the four sub-thin film transistor T 4 is coupled to the third node Q 3
  • the second source/drain of the fourth sub-thin film transistor T 4 is coupled to the second clock signal terminal CLKB
  • the thin film transistor T 5 , the gate electrode of the fifth sub thin film transistor T 5 is coupled to the first node Q 1
  • the first source/drain of the fifth sub thin film transistor T 5 is coupled to the third node Q 3
  • the second source/drain of the fifth sub thin film transistor T 5 is coupled to the first voltage terminal VSS
  • the sixth sub thin film transistor T 6 , the gate electrode of the sixth sub thin film transistor T 6 and the second clock signal terminal CLKB is coupled, the first source/drain of the sixth sub thin film transistor T 6 is coupled to the data input terminal INPUT, and the second source/drain of the sixth sub thin film transistor T 6 is coupled to the first node Q 1 ;
  • the active layer of the first sub-thin film transistor drive circuit 400 to the T 1 of the eleventh of the thin film transistor T 11 are a first active layer, and includes a polycrystalline semiconductor material.
  • the third sub-thin film transistor T 3 having the active layer of the laminated structure of FIG. 3, not described herein again.
  • the driving circuit provided by the embodiment of the present disclosure has a strong driving capability and can simultaneously meet the requirement of low leakage current.
  • FIG. 5 schematically shows a timing diagram of various signals of the driving circuit 400 shown in FIG. 4.
  • the working process of the driving circuit 400 shown in FIG. 4 will be described in detail below in conjunction with the timing diagram shown in FIG. 5.
  • all transistors are N-type transistors, and the first voltage signal terminal VSS outputs a low voltage signal VGL.
  • the first clock signal CLK1 is input to the first clock signal terminal CLK.
  • the second clock signal CLK2 is input to the second clock signal terminal CLKB.
  • the first clock signal CLK1 and the second clock signal CLK2 have the same clock cycle and amplitude, and have opposite phases.
  • the data signal STV is input to the data input terminal INPUT.
  • the reset terminal RESET inputs the RST reset signal.
  • "0" means low voltage
  • "1" means high voltage
  • the first sub thin film transistor T 1 and the sixth sub thin film transistor T 6 are turned on, the second sub thin film transistor T 2 is turned off, and the high voltage of the input signal STV is output to the first node Q 1 .
  • An eleventh sub-thin film transistor T 11 is opened, and under the control of a high voltage node Q 1, the third sub-thin film transistor T 3 is opened, so that a low voltage and a low voltage signal VGL first clock signal CLK1 are Output to the data output terminal OUTPUT, so that OUT is a low voltage. There is a voltage difference across the capacitor C, so that the capacitor C is charged.
  • Eighth sub thin film transistor T 8 is opened, and under the control of a high voltage node Q 1, the fifth sub-thin film transistor T 5 and a seventh sub-thin film transistor T 7 is opened.
  • the seventh thin film transistor T sub. 7 and eighth sub aspect ratio of the thin film transistor T 8 arranged to seventh sub-thin film transistor T of the thin film transistor of the eighth. 7 T-resistance ratio of 8, so that The second node Q 2 has a low voltage.
  • the aspect ratio of the active layer of the seventh sub thin film transistor T 7 is configured to be greater than the active layer of the eighth sub thin film transistor T 8 , that is, the resistance of the seventh sub thin film transistor T 7 is smaller than that of the eighth sub thin film transistor T 8 .
  • the fourth sub thin film transistor T 4 is turned off. Based on the turned off fourth sub thin film transistor T 4 and the turned on fifth sub thin film transistor T 5 , the voltage of the third node Q 3 is low. Under the control of a third point Q 3 of the low voltage, the ninth sub-tenth the thin film transistor T 9 and T 10 of the thin film transistor is turned off.
  • the difference between the working process of the driving circuit is that the first sub thin film transistor T 1 and the sixth sub thin film transistor T 6 are turned off, and the first node Q 1 maintains a high voltage.
  • the third sub-thin film transistor T 3 is opened, the high voltage of the first clock signal CLK1 is output to the data output terminal OUTPUT. Further, the eleventh of the thin film transistor T 11 is closed so that the output signal OUT to a high voltage. Due to the bootstrap effect of the capacitor C, the voltage of the first node Q1 is further increased.
  • the difference between the working process of the driving circuit is that the first sub-thin film transistor T 1 is turned off.
  • the first node Q 1 still maintains a high voltage.
  • the third sub-thin film transistor T 3 is opened, the first clock signal CLK1 of a low voltage output as an output signal OUT, i.e., a low voltage output signal OUT.
  • the first sub thin film transistor T 1 and the sixth sub thin film transistor T 6 are turned off.
  • the reset terminal RESET of the driving circuit is coupled to the output terminal of the next-level driving circuit.
  • the output signal of the next-stage drive circuit is high voltage, so the reset signal RST of the drive circuit is high voltage.
  • the second sub thin film transistor T 2 is turned on. Therefore, the low voltage VGL is output to the first node Q 1 , so that the voltage of the first node Q 1 is a low voltage.
  • the eighth sub thin film transistor T 8 is turned off, and the second node Q 2 maintains a low voltage. Under the control of the low voltage node Q 2, the fourth sub-thin film transistor T 4 closed so that the third node Q 3 maintains a low voltage. Under the control of a third point Q 3 of the low voltage, the ninth sub-tenth the thin film transistor T 9 and T 10 of the thin film transistor is turned off. In addition, the eleventh sub-thin film transistor T 11 is turned off, so the data output terminal OUTPUT is in a floating state. The load coupled to the data output terminal OUTPUT is relatively large, so the OUT data is low. Both ends of the capacitor C are low voltage, so the capacitor C is discharged.
  • FIG. 6 schematically shows a flowchart of a method for preparing an array substrate according to an embodiment of the present disclosure. The preparation method will be described in detail below with reference to the drawings.
  • a substrate 101 is provided.
  • the substrate 101 has a display area AA and a peripheral area BB surrounding the display area AA.
  • the display area AA includes sub-pixels arranged in an array.
  • a thin film transistor formed on the substrate 101, the thin film transistor comprises a plurality of BB in the peripheral region of the first TFT M 1 and M second thin film transistors in the display region AA 2. Further, in the present embodiment, between the first thin film transistor having a first active layer 104.
  • the method of preparing an array substrate further includes forming a passivation layer and a pixel electrode on the thin film transistor.
  • the material for forming the passivation layer may be SiO 2 , SiO 2 /SiN laminate, SiN, SiON.
  • the material forming the pixel electrode may be ITO, IZO, or a stack of ITO-Ag-ITO.
  • a via hole is formed in the passivation layer to couple the electrode of the thin film transistor with the pixel electrode.
  • FIG. 7 schematically shows a flowchart of a method of forming a thin film transistor according to an embodiment of the present disclosure.
  • a gate is formed.
  • a metal layer such as Mo, Al, Cu, and Ti, is deposited on the substrate 101.
  • a first gate 102 is formed on the BB area and a second gate 102' is formed on the AA area through a patterning process.
  • a gate insulating layer is formed.
  • An insulating material for example, SiO 2 , SiO 2 /SiN stack, SiN, SiON
  • SiO 2 , SiO 2 /SiN stack, SiN, SiON is deposited on the first gate 102, the second gate 102 ′, and the substrate 101 to form a gate insulating layer 103.
  • an active layer is formed.
  • a semiconductor layer containing an amorphous semiconductor material is formed on a substrate.
  • an amorphous semiconductor material may be deposited on the gate insulating layer 103 to form a semiconductor layer.
  • the formed semiconductor layer includes a first part corresponding to the first active layer 104 one-to-one and a second part corresponding to the second active layer 104' one-to-one.
  • the amorphous semiconductor material contained in at least one of the first parts may be converted into a polycrystalline semiconductor material. Specifically, only the first part of the semiconductor layer used to form the at least one first active layer 104 may be annealed to form a polycrystalline semiconductor layer.
  • the amorphous semiconductor material contained in at least the second portion adjacent to the peripheral region BB is converted into a polycrystalline semiconductor material.
  • the first part of the semiconductor layer and the second part adjacent to the peripheral area BB may be subjected to laser annealing treatment, for example, using a single mask.
  • the mask 100 has openings G corresponding to the sub-pixels SP one-to-one and arranged in an array, and microlenses ML corresponding to the openings G and aligned along the light transmission direction. .
  • FIG. 9 (a) by patterning, to remove portions of the semiconductor layer other than the SD of the SD of the second semiconductor layer except a first portion P 1 and second part P, and the to shape of the first portion P 1 and Two parts P 1 to form the first active layer 104 and the second active layer 104' shown in FIG. 9(b).
  • FIG. 9 there are four active layers on a portion of the substrate 101, and it should be understood that the present disclosure is not limited thereto.
  • source/drain electrodes are formed.
  • a metal layer is deposited on the first active layer 104, the second active layer 104' and the gate insulating layer 103.
  • the material forming the metal layer may be the same as the material forming the gate.
  • a first source / drain electrode 105 and a second source / drain of the first thin film transistor 106 is formed through a patterning process M, a first and a second thin film transistor M 2 source / drain electrode 105 'and a second source / Drain 106'.
  • the active layer when the active layer is formed in step 730, first, the first active layer 104 and/or the second active layer 104' is converted into polycrystalline semiconductor material.
  • a second semiconductor layer including an amorphous semiconductor material is formed on the first semiconductor layer.
  • a polycrystalline semiconductor layer formed by annealing the semiconductor layer SD is used as the first semiconductor layer 1041.
  • An amorphous semiconductor material having a first carrier concentration, such as amorphous silicon is deposited on the first semiconductor layer 1041, and then patterned to form a second semiconductor layer 1042.
  • a third semiconductor layer 1043 containing an amorphous semiconductor material is formed on opposite ends of the second semiconductor layer 1042.
  • an amorphous semiconductor material having a second carrier concentration such as amorphous silicon, is deposited on the second semiconductor layer 1042 to form the third semiconductor layer 1043.
  • the first carrier concentration is greater than the second carrier concentration.
  • FIG. 10 shows a schematic diagram of a display device 1000 according to an embodiment of the present disclosure.
  • the display device 1000 may include the aforementioned array substrate 100 as shown in FIGS. 1 to 3.
  • the display panel according to the embodiment of the present disclosure can be used for any product or part having a display function.
  • Such products or components include but are not limited to display devices, wearable devices, mobile phones, tablet computers, televisions, notebook computers, digital photo frames, navigators, etc.

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Abstract

本公开涉及一种阵列基板及其制备方法。该阵列基板包括：衬底，具有显示区域和围绕所述显示区域的周边区域，该显示区域包括呈阵列排布的子像素；以及多个薄膜晶体管，位于衬底上，包括位于周边区域内的多个第一薄膜晶体管和位于显示区域的每个子像素内的第二薄膜晶体管，其中，第一薄膜晶体管的第一有源层与最邻近的第二薄膜晶体管的第二有源层之间具有行和/或列方向上的第一距离，且相邻的第二有源层之间具有行和/或列方向上的第二距离，第一距离等于第二距离。

Description

阵列基板及其制备方法、显示装置 技术领域
本公开的实施例涉及显示技术领域，尤其涉及一种阵列基板及其制备方法以及显示装置。
背景技术
现有显示面板的阵列基板的制造主要包括低温多晶硅(LTPS)技术、氧化物技术、非晶硅技术和有机薄膜晶体管技术。其中，LTPS技术已广泛应用到显示面板的制造工艺中，但因技术限制，LTPS技术尚不能应用于高世代线(大于G6)面板制造中；氧化物虽然有较高的迁移率，但是其稳定性和均匀性差，目前量产工艺难度高；非晶硅薄膜晶体管的迁移率低，驱动能力差，不能满足大尺寸、高分辨率、高刷新率显示面板的需要。
发明内容
本公开的实施例提供了一种阵列基板及其制备方法、显示装置。
根据本公开的一方面，提供了一种阵列基板。该阵列基板包括衬底，该衬底具有显示区域和围绕所述显示区域的周边区域，该显示区域包括呈阵列排布的子像素；以及多个薄膜晶体管，位于衬底上，包括位于周边区域内的第一薄膜晶体管和位于显示区域的每个子像素内的第二薄膜晶体管。进一步地，第一薄膜晶体管的第一有源层与最邻近的第二薄膜晶体管的第二有源层之间具有行和/或列方向上的第一距离，且相邻的第二有源层之间具有行和/或列方向上的第二距离，第一距离等于第二距离。
在本公开的实施例中，第一有源层与第二有源层具有相同的形状。
在本公开的实施例中，第一有源层与第二有源层具有相同的尺寸。
在本公开的实施例中，第一有源层中的至少一个包括多晶半导体材料。
在本公开的实施例中，第二有源层包括非晶半导体材料。
在本公开的实施例中，第二有源层包括多晶半导体材料。
在本公开的实施例中，至少邻近周边区域的第二有源层包括多晶半导体材料。
在本公开的实施例中，第一有源层中的至少一个和/或第二有源层包括叠层结构，叠层结构包括沿垂直于基板且远离薄膜晶体管的栅极的方向依次设置的包含多晶半导体材料的第一半导体层、包含非晶半导体材料的第二半导体层以及包含非晶半导体材料的位于该第二半导体层的相对端部的第三半导体层。进一步地，第三半导体层具有比第二半导体层高的载流子浓度。
在本公开的实施例中，薄膜晶体管的所述栅极位于薄膜晶体管的有源层与所述衬底之间
在本公开的实施例中，周边区域包括至少一个驱动电路。该驱动电路包括：第一子薄膜晶体管，该第一子薄膜晶体管的栅极和第一源/漏极与数据输入端耦接，该第一子薄膜晶体管的第二源/漏极与第一节点耦接；第二子薄膜晶体管，该第二子薄膜晶体管的栅极与复位端耦接，该第二子薄膜晶体管的第一源/漏极与第一节点耦接，该第二子薄膜晶体管的第二源/漏极与第一电压端耦接；第三子薄膜晶体管，该第三子薄膜晶体管的栅极与第一节点耦接，该第三子薄膜晶体管的第一源/漏极与第一时钟信号端耦接，该第三子薄膜晶体管的第二源/漏极与数据输出端耦接；第四子薄膜晶体管，该第四子薄膜晶体管的栅极与第二节点耦接，该第四子薄膜晶体管的第一源/漏极与第三节点耦接，该第四子薄膜晶体管的第二源/漏极与第二时钟信号端耦接；第五子薄膜晶体管，该第五子薄膜晶体管的栅极与第一节点耦接，该第五子薄膜晶体管的第一源/漏极与第三节点耦接，该第五子薄膜晶体管的第二源/漏极与第一电压端耦接；第六子薄膜晶体管，该第六子薄膜晶体管的栅极与所述第二时钟信号端耦接，该第六子薄膜晶体管的第一源/漏极与所述数据输入端耦接，该第六子薄膜晶体管的第二源/漏极与所述第一节点耦接；第七子薄膜晶体管，该第七子薄膜晶体管的栅极与第一节点耦接，该第七子薄膜晶体管的第一源/漏极与第二节点耦接，该第七子薄膜晶体管的第二源/漏极与第一电压端耦接；第八子薄膜晶体管，该第八 子薄膜晶体管的栅极和第一源/漏极与第二时钟信号端耦接，该第八子薄膜晶体管的第二源/漏极与第二节点耦接；第九子薄膜晶体管，该第九子薄膜晶体管的栅极与第三节点耦接，该第九子薄膜晶体管的第一源/漏极与第一节点耦接，该第九子薄膜晶体管的第二源/漏极与第一电压端耦接；第十子薄膜晶体管，该第十子薄膜晶体管的栅极与第三节点耦接，该第十子薄膜晶体管的第一源/漏极与数据输出端耦接，该第十子薄膜晶体管的第二源/漏极与第一电压端耦接；第十一子薄膜晶体管，该第十一子薄膜晶体管的栅极与第二时钟信号端耦接，该第十一子薄膜晶体管的第一源/漏极与数据输出端耦接，该第十一子薄膜晶体管的第二源/漏极与第一电压端耦接；电容，该电容的第一端与第一节点耦接，该电容的第二端与数据输出端耦接。
在本公开的实施例中，第七子薄膜晶体管的有源层的宽长比被配置为小于第八子薄膜晶体管的有源层。
在本公开的实施例中，第一有源层的至少一个包括第一到第十一子薄膜晶体管的有源层。
在本公开的实施例中，第三子薄膜晶体管的有源层具有叠层结构。该子薄膜晶体管包括沿垂直于基板且远离该子薄膜晶体管的栅极的方向依次设置的包含多晶半导体材料的第一半导体层、包含非晶半导体材料的第二半导体层以及位于该第二半导体层的相对端部的包含非晶半导体材料的第三半导体层，其中，该第三半导体层具有比该第二半导体层高的载流子浓度。
根据本公开的第二方面，提供了一种阵列基板的制造方法。该方法包括：提供衬底，该衬底具有显示区域和围绕所述显示区域的周边区域，该显示区域包括呈阵列排布的子像素；以及在该衬底上形成多个薄膜晶体管，多个薄膜晶体管包括位于周边区域内的第一薄膜晶体管和在显示区域的每个子像素内的第二薄膜晶体管。进一步地，第一薄膜晶体管的第一有源层与最邻近的第二薄膜晶体管的第二有源层的之间具有行和/或列方向上的的第一距离，且相邻的第二有源层之间具有行和/或列方向上的第二距离，第一距离等于第二距离。
在本公开的实施例中，形成所述薄膜晶体管包括：在衬底上形成包含非晶半导体材料的半导体层；该半导体层包括与第一有源层一一对应的第一部分和与第二有源层一一对应的第二部分；以及将第一部分中的至少一个中所包含的非晶半导体材料转化为多晶半导体材料。
在本公开的实施例中，该方法还包括，将至少邻近周边区域的第二部分中所包含的非晶半导体材料转化为多晶半导体材料。
在本公开的实施例中，转化包括激光退火。
在本公开的实施例中，转化包括使用掩模对半导体层进行激光退火处理。进一步地，掩模具有呈阵列排布的与子像素一一对应的开口和与开口一一对应且与开口沿透光方向对准的微透镜。在本公开的实施例中，构图半导体层以去除该半导体层的除第一部分和第二部分之外的部分并整形第一部分和第二部分以形成第一有源层和第二有源层。在本公开的实施例中，进行整形以使第一有源层与第二有源层具有相同的形状，或者具有相同的形状和尺寸。
根据本公开的第三方面，提供了一种显示装置。该显示装置包括根据本公开的第一方面所述的阵列基板。
适应性的进一步的方面和范围从本文中提供的描述变得明显。应当理解，本申请的各个方面可以单独或者与一个或多个其他方面组合实施。还应当理解，本文中的描述和特定实施例旨在仅说明的目的并不旨在限制本申请的范围。
附图说明
为了更清楚地说明本公开的实施例的技术方案，下面将对实施例的附图进行简要说明，应当知道，以下描述的附图仅仅涉及本公开的一些实施例，而非对本公开的限制，其中，贯穿这些附图的各个视图，相应的参考编号指示相应的部件或特征：
图1是根据本公开的实施例的一种阵列基板的俯视图；
图2是根据本公开的实施例的沿图1中的AA'轴的阵列基板的侧视图；
图3是根据本公开的实施例的沿图1中的AA'轴的阵列基板的侧视图；
图4是根据本公开的实施例的位于周边区域的驱动电路的示意图；
图5是如图4所示的驱动电路的各信号的时序图；
图6是根据本公开的实施例的制备阵列基板的方法的流程图；
图7是根据本公开的实施例的形成薄膜晶体管的方法的流程图；
图8是根据本公开的实施例的掩模示意图；
图9是根据本公开的实施例的通过构图来形成有源层的示意图；以及
图10是根据本公开的实施例的显示装置示意图。
具体实施方式
为了使本公开的实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本公开的实施例的技术方案进行清楚、完整的描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域技术人员在无需创造性劳动的前提下所获得的所有其他实施例，也都属于本公开保护的范围。
当介绍本公开的元素及其实施例时，冠词“一”、“一个”、“该”和“所述”旨在表示存在一个或者多个要素。用语“包含”、“包括”、“含有”和“具有”旨在包括性的并且表示可以存在除所列要素之外的另外的要素。
出于下文表面描述的目的，如其在附图中被标定方向那样，术语“上”、“下”、“左”、“右”“垂直”、“水平”、“顶”、“底”及其派生词应涉及公开。术语“上覆”、“在……顶上”、“定位在……上”或者“定位在……顶上”意味着诸如第一结构的第一要素存在于诸如第二结构的第二要素上，其中，在第一要素和第二要素之间可存在诸如界面结构的中间要素。术语“接触”意味着连接诸如第一结构的第一要素和诸如第二结构的第二要素，而在两个要素的界面处可以有或者没有其它要素。
除非另外定义，否则在此使用的所有术语(包括技术和科学术语)具有与本公开主题所属领域的技术人员所通常理解的相同含义。进一步将理解的是，诸如在通常使用的词典中定义的那些的术语应解释为具有与说明 书上下文和相关技术中它们的含义一致的含义，并且将不以理想化或过于正式的形式来解释，除非在此另外明确定义。如在此所使用的，将两个或更多部分“连接”或“耦接”到一起的陈述应指这些部分直接结合到一起或通过一个或多个中间部件结合。
在本公开的所有实施例中，由于晶体管的源极和漏极(发射极和集电极)是对称的，并且N型晶体管和P型晶体管的源极和漏极(发射极和集电极)之间的导通电流方向相反，因此在本公开的实施例中，统一将晶体管的受控中间端称为栅极，信号输入端和信号输出端可以统称为源/漏极。另外，诸如“第一”和“第二”的术语仅用于将一个部件(或部件的一部分)与另一个部件(或部件的另一部分)区分开。
微透镜阵列(MAL)技术同样可以用于制造阵列基板，但MLA存在诸多问题亟待解决。MLA属于区域化结晶技术，需要特定的掩模板和微透镜配合才能将特定区域的非晶硅加热熔融后结晶。然而，掩模板和微透镜在制作过程中需要组合在一起使用，且掩模板的尺寸小于基板尺寸，因此需要多次照射才能完成对所有区域的处理。通常这一过程可以通过移动基板或者掩模板实现。但对应于特定的基板，其有源层的形状和位置多样，如周边区域和像素区域中的有源层间距或有源层的形状不同，对应的掩模板和微透镜不同。这造成难以通过以相对间距为步长移动掩模板和微透镜进行结晶处理。然而，采用多种掩膜版和微透镜，则会导致基本的制作成本增加和制程太长。
本公开提供了一种阵列基板，该阵列基板上的薄膜晶体管能够使用单一组合的掩模板和微透镜来完成阵列基板上的希望的位置的有源层的转化。从而，减少了阵列基板的制造成本和时间。
图1示意性示出了根据本公开的实施例的阵列基板100的俯视图。如图1所示，阵列基板100包括衬底101。衬底101包括显示区域AA以及位于显示区域AA的左右两侧的周边区域BB。另外，在实施例中，周边区域BB也可以在显示区域AA上下两侧或四边。根据本公开的实施例，周边区域B可以包括GOA(Gate driver on Array，阵列基板行驱动电路)区 域。该阵列基板还包括位于衬底101上的薄膜晶体管，该薄膜晶体管包括位于周边区域BB的第一薄膜晶体管M 1，以及位于显示区域AA内的第二薄膜晶体管M 2。在行方向上，第一薄膜晶体管M 1的第一有源层与最邻近第二薄膜晶体管M 2的第二有源层之间的第一距离L 1与相邻的第二有源层之间的第二距离L 2相同。在实施例中，距离指的是两个部件之间的最小距离。
在本公开的另一些实施例中，周边区域BB位于显示区域AA上下两侧或四边。在列方向上，第一有源层与最邻近的第二有源层之间的第一距离可以与相邻的第二有源层之间的第二距离相同。
在本公开的另一些实施例中，周边区域BB位于显示区域AA四边。在行和列方向上，第一有源层与最邻近的第二有源层之间的第一距离与相邻的第二有源层之间的第二距离分别相同。
进一步地，在实施例中，第一有源层可以与第二有源层具有相同的形状，例如，矩形。进一步地，在实施例中，第一有源层可以与第二有源层具有相同的形状和尺寸。在实施例中，尺寸是指有源层所在平面中的尺寸，例如长和宽。
在本公开的实施例中，第一薄膜晶体管M 1与第二薄膜晶体管M 2的有源层可以为矩形。
图2示意性示出了根据本公开的实施例的沿图1中的AA'轴的阵列基板100的侧视图。如图2所示，第一薄膜晶体管M 1包括：位于衬底101上的第一栅极102；位于第一栅极102上的栅极绝缘层103；位于栅极绝缘层103上的第一有源层104；以及位于第一有源层104上的第一薄膜晶体管M 1的第一源/漏极105和第二源/漏极106。第二薄膜晶体管M 2包括：第二栅极102'；位于第二栅极102'上的栅极绝缘层103；位于栅极绝缘层103上的第二有源层104'；以及位于第二有源层104'上的第二薄膜晶体管T 2的第一源/漏极105'和第二源/漏极106'。
通常，阵列基板的薄膜晶体管的有源层由诸如非晶硅的非晶半导体材料形成，但多晶半导体材料具有更高的电子迁移率使薄膜晶体管具有更强 的驱动能力。根据本公开，可以通过单一组合的掩模板和微透镜对非晶半导体材料进行结晶处理以将需要部分的非晶半导体材料转化为多晶半导体材料。这不但能够减少掩模板和微透镜的种类和数量，而且还能够减少制造时间。
在本公开的实施例中，第一有源层104中的至少一个包括多晶半导体材料(例如，多晶硅)。第二有源层104'包括非晶半导体材料(例如，非晶硅)。根据本实施例，考虑到对驱动能力影响的关键因素和量产的限制，以及位于周边区域的GOA电路对驱动能力具有更大的影响，因此可以通过仅对周边区域进行结晶处理而保留显示区域AA的非晶有源层，来显著提高显示面板的驱动能力。
在本公开的另一些实施例中，第一有源层104中的至少一个和第二有源层104'中的至少一个可以包括多晶半导体材料。进一步地，在本公开的实施例中，邻近周边区域BB的第二有源层104'可以包括多晶半导体材料。
图3示意性示出了根据本公开的另一些实施例的沿图1中的AA’轴的阵列基板的侧视图。目前，阵列基板上的一些薄膜晶体管(例如，驱动晶体管)既要求较强的驱动能力，还要求在关闭状态时具有较小的漏电流。因此，在本公开的实施例中，提供了一种阵列基板。在该阵列基板上，薄膜晶体管的有源层具有叠层结构。该叠层结构能够在满足驱动能力的情况下具有较小的漏电流。
如图3所示，图3与图2的区别在于：如图2所示的包括多晶半导体材料的第一有源层104或第二有源层104'具有叠层结构。该有源层的叠层结构依次包括：位于栅极绝缘层103上的第一半导体层1041，该第一半导体层1041可以包含多晶半导体材料(例如，多晶硅)；位于第一半导体层1041上的第二半导体层1042，该第二半导体层1042可以包含非晶半导体材料，例如，非晶硅；以及位于第二半导体层1042的相对端部的第三半导体层1043，该第三半导体层1043可以包含非晶半导体材料，例如，非晶硅。进一步地，在本公开的实施例中，第三半导体层具有比第二半导体层高的载流子浓度。希望的载流子浓度可以通过适宜地掺杂来实现。
在图2和图3所示的实施例中，薄膜晶体管是底栅型的薄膜晶体管。但这不旨在限制，本公开的实施例中，薄膜晶体管也可以是顶栅型的薄膜晶体管。此时，有源层位于栅极绝缘层的下方。有源层的叠层结构依次包括：位于栅极绝缘层103下的第一半导体层1041，位于第一半导体层1041下的第二半导体层1042，位于第二半导体层1042下的相对端部的第三半导体层1043。
图4示出了根据本公开的实施例的位于周边区域BB的驱动电路400的示意图。周边区域BB包括至少一个驱动电路400。下面将参照附图，对驱动电路400进行详细的说明。
如图4所示，驱动电路400包括：第一子薄膜晶体管T 1，该第一子薄膜晶体管T 1的栅极和第一源/漏极与数据输入端INPUT耦接，该第一子薄膜晶体管T 1的第二源/漏极与第一节点Q 1耦接；第二子薄膜晶体管T 2，该第二子薄膜晶体管T 2的栅极极与复位端RESET耦接，该第二子薄膜晶体管T 2的第一源/漏极与第一节点Q 1耦接，该第二子薄膜晶体管T 2的第二源/漏极与第一电压端VSS耦接；第三子薄膜晶体管T 3，该第三子薄膜晶体管的栅极极与第一节点Q 1耦接，该第三子薄膜晶体管T 3的第一源/漏极与第一时钟信号端CLK耦接，该第三子薄膜晶体管T 3的第二源/漏极与数据输出端OUTPUT耦接；第四子薄膜晶体管T 4，该第四子薄膜晶体管T 4的栅极极与第二节点Q 2耦接，该第四子薄膜晶体管T 4的第一源/漏极与第三节点Q 3耦接，该第四子薄膜晶体管T 4的第二源/漏极与第二时钟信号端CLKB耦接；第五子薄膜晶体管T 5，该第五子薄膜晶体管T 5的栅极极与第一节点Q 1耦接，该第五子薄膜晶体管T 5的第一源/漏极与第三节点Q 3耦接，该第五子薄膜晶体管T 5的第二源/漏极与第一电压端VSS耦接；第六子薄膜晶体管T 6，该第六子薄膜晶体管T 6的栅极极与第二时钟信号端CLKB耦接，该第六子薄膜晶体管T 6的第一源/漏极与数据输入端INPUT耦接，该第六子薄膜晶体管T 6的第二源/漏极与第一节点Q 1耦接；第七子薄膜晶体管T 7，该第七子薄膜晶体管T 7的栅极极与第一节点Q 1耦接，第七子薄膜晶体管T 7的第一源/漏极与第二节点Q 2耦接，该第七子薄膜晶体管T 7 的第二源/漏极与第一电压端VSS耦接；第八子薄膜晶体管T 8，该第八子薄膜晶体管T 8的栅极和第一源/漏极与第二时钟信号端CLKB耦接，该第八子薄膜晶体管T 8的第二源/漏极与第二节点Q 2耦接；第九子薄膜晶体管T 9，该第九子薄膜晶体管T 9的栅极与第三节点Q 3耦接，该第九子薄膜晶体管T 9的第一源/漏极与第一节点Q 1耦接，该第九子薄膜晶体管T 9的第二源/漏极与第一电压端VSS耦接；第十子薄膜晶体管T 10，该第十子薄膜晶体管T 10的栅极与第三节点Q 3耦接，该第十子薄膜晶体管T 10的第一源/漏极与数据输出端OUTPUT耦接，该第十子薄膜晶体管T 10的第二源/漏极与第一电压端VSS耦接；第十一子薄膜晶体管T 11，该第十一子薄膜晶体管T 11的栅极与第二时钟信号端CLKB耦接，该第十一子薄膜晶体管T 11的第一源/漏极与数据输出端OUTPUT耦接，该第十一子薄膜晶体管T 11的第二源/漏极与第一电压端VSS耦接；以及电容C，该电容C的第一源/漏极与第一节点Q 1耦接，该电容C的第二端与数据输出端OUTPUT耦接。
在本公开的实施例中，驱动电路400的第一子薄膜晶体管T 1到第十一子薄膜晶体管T 11的有源层均为第一有源层，且均包括多晶半导体材料。
进一步地，在本公开的实施例中，第三子薄膜晶体管T 3的有源层具有如图3所述的叠层结构，在此不再赘述。
因此，本公开的实施例提供的驱动电路具有较强的驱动能力，并且能够同时满足低漏电流的要求。
图5示意性示出了如图4所示的驱动电路400的各信号的时序图。下面结合图5所示的时序图，对如图4所示的驱动电路400的工作过程进行详细描述。在以下的描述中，假定所有晶体管都是N型晶体管，第一电压信号端VSS输出低电压信号VGL。向第一时钟信号端CLK输入第一时钟信号CLK1。向第二时钟信号端CLKB输入第二时钟信号CLK2。第一时钟信号CLK1和第二时钟信号CLK2具有相同的时钟周期和振幅且相位相反。向数据输入端INPUT输入数据信号STV。复位端RESET输入RST复位信号。在下面的实施例中，“0”表示低电压；“1”表示高电压
在第一阶段t 1，STV＝1，CLK1＝0，CLK2＝1，RST＝0。
第一子薄膜晶体管T 1和第六子薄膜晶体管T 6打开，第二子薄膜晶体管T 2关闭，输入信号STV的高电压被输出至第一节点Q 1。第十一子薄膜晶体管T 11打开，并且在第一节点Q 1的高电压的控制下，第三子薄膜晶体管T 3打开，从而使低电压信号VGL和第一时钟信号CLK1的低电压均被输出至数据输出端OUTPUT，从而使得OUT为低电压。电容C的两端存在电压差，从而对电容C进行充电。第八子薄膜晶体管T 8打开，并且在第一节点Q 1的高电压的控制下，第五子薄膜晶体管T 5以及第七子薄膜晶体管T 7打开。在实施例中，通过配置第七子薄膜晶体管T 7与第八子薄膜晶体管T 8的宽长比，来配置第七子薄膜晶体管T 7与第八子薄膜晶体管T 8的电阻比值，从而使第二节点Q 2为低电压。例如，将第七子薄膜晶体管T 7的有源层的宽长比配置为大于第八子薄膜晶体管T 8的有源层，即第七子薄膜晶体管T 7的电阻小于第八子薄膜晶体管T 8。并且在第二节点Q 2的低电压的控制下，第四子薄膜晶体管T 4关闭。基于关闭的第四子薄膜晶体管T 4和打开的第五子薄膜晶体管T 5，使得第三节点Q 3的电压为低电压。在第三节点Q 3的低电压的控制下，第九子薄膜晶体管T 9和第十子薄膜晶体管T 10关闭。
在第二阶段t 2，STV＝0，CLK1＝1，CLK2＝0，RST＝0。
在第二阶段t 2与第一阶段t 1，驱动电路的工作过程的区别在于：第一子薄膜晶体管T 1和第六子薄膜晶体管T 6关闭，第一节点Q 1保持高电压。在第一节点Q 1的高电压的控制下，第三子薄膜晶体管T 3打开，将第一时钟信号CLK1的高电压输出至数据输出端OUTPUT。并且，第十一子薄膜晶体管T 11关闭，从而使输出信号OUT为高电压。由于电容C的自举效应，第一节点Q1的电压被进一步抬高。
在第三阶段t 3，STV＝0，CLK1＝0，CLK2＝1，RST＝0。
在第三阶段t 3与第一阶段t 1，驱动电路的工作过程的区别在于：第一子薄膜晶体管T 1关断。第一节点Q 1仍然保持高电压。在高电压的第一节点Q 1的控制下，第三子薄膜晶体管T 3打开，将低电压的第一时钟信号CLK1输出作为输出信号OUT，即输出信号OUT为低电压。在第四阶段t 4， STV＝0，CLK1＝1，CLK2＝0，RST＝1。
在第四阶段t 4，第一子薄膜晶体管T 1和第六子薄膜晶体管T 6关闭。该驱动电路的复位端RESET与下一级驱动电路的输出端耦接。在此阶段，下一级驱动电路的输出信号为高电压，因此，该驱动电路的复位信号RST为高电压。在高电压的复位信号RST的控制下，第二子薄膜晶体管T 2打开。从而将低电压VGL输出至第一节点Q 1，使得第一节点Q 1的电压为低电压。在第一节点Q 1的低电压的控制下，第三子薄膜晶体管T 3、第五子薄膜晶体管T 5和第七子薄膜晶体管T 7关闭。第八子薄膜晶体管T 8关闭，第二节点Q 2保持低电压。在第二节点Q 2的低电压的控制下，第四子薄膜晶体管T 4关闭，从而第三节点Q 3保持低电压。在第三节点Q 3的低电压的控制下，第九子薄膜晶体管T 9和第十子薄膜晶体管T 10关闭。并且第十一子薄膜晶体管T 11关闭，因此数据输出端OUTPUT处于悬空状态。数据输出端OUTPUT耦接的负载较大，因此OUT数据为低。电容C的两端均为低电压，因此电容C被放电。
图6示意性示出了根据本公开的实施例的制备阵列基板的方法的流程图。以下参照附图，对该制备方法进行详细的描述。
如图6所示，在步骤610，提供衬底101，该衬底101具有显示区域AA和围绕该显示区域AA的周边区域BB，该显示区域AA包括呈阵列排布的子像素。在步骤620，在衬底101上形成薄膜晶体管，该薄膜晶体管包括在周边区域BB内的多个第一薄膜晶体管M 1和在显示区域AA内的第二薄膜晶体管M 2。进一步地，在本实施例中，第一薄膜晶体管M 1的第一有源层104与最邻近的第二薄膜晶体管M 2的第二有源层104'之间具有行和/或列方向上的第一距离，邻近的第二有源层104'之间具有行和/或列方向上的第二距离，第一距离等于第二距离。形成薄膜晶体管的方法将在下面参照图7进行描述。
在本公开的实施例中，制备阵列基板的方法还包括在薄膜晶体管上形成钝化层和像素电极。形成钝化层的材料可以是SiO 2、SiO 2/SiN叠层、SiN、SiON。形成像素电极的材料可以是ITO、IZO或者ITO-Ag-ITO的叠层。 并且在钝化层中形成过孔，以使薄膜晶体管的电极与像素电极耦接。
图7示意性示出了根据本公开的实施例的形成薄膜晶体管的方法的流程图。如图7所示，在步骤710，形成栅极。在衬底101上沉积金属层，例如Mo、Al、Cu和Ti。然后，通过构图工艺在BB区域上形成第一栅极102，在AA区域上形成第二栅极102'。
在步骤720，形成栅极绝缘层。在第一栅极102、第二栅极102'和衬底101上沉积绝缘材料(例如由SiO 2、SiO 2/SiN叠层、SiN、SiON)以形成栅极绝缘层103。
在步骤730，形成有源层。首先，在衬底上形成包含非晶半导体材料的半导体层。根据本公开的实施例，可以在栅极绝缘层103上沉积非晶半导体材料，以形成半导体层。进一步地，所形成的半导体层包括与第一有源层104一一对应的第一部分和与第二有源层104'一一对应的第二部分。然后，在本公开的实施例中，可以将第一部分中的至少一个中所包含的非晶半导体材料转化为多晶半导体材料。具体地，可以仅对用于形成至少一个第一有源层104的半导体层中的第一部分进行退火，以形成多晶半导体层。
附加地，在实施例中，将至少邻近周边区域BB的第二部分中所包含的非晶半导体材料转化为多晶半导体材料。
具体地，可以例如使用单一掩模对半导体层的第一部分和邻近周边区域BB的第二部分进行激光退火处理。在实施例中，如图8所示，掩模100具有呈阵列排布的与子像素SP一一对应的开口G和与开口G一一对应且与开口沿透光方向对准的微透镜ML。
然后，如图9(a)所示，通过构图，来去除半导体层SD的除半导体层SD的除第一部分P 1和第二部分P 2之外的部分，并且来整形第一部分P 1和第二部分P 1，以形成图9(b)中所示的第一有源层104和第二有源层104'。在图9的示例中，衬底101的部分上具有四个有源层，应理解，本公开并不限于此。
在步骤740，形成源/漏极。在第一有源层104、第二有源层104'和栅 极绝缘层103上沉积金属层。形成该金属层的材料可以与形成栅极的材料相同。然后，通过构图工艺形成第一薄膜晶体管M 1的第一源/漏极105和第二源/漏极106，以及第二薄膜晶体管M 2的第一源/漏极105'和第二源/漏极106'。
替换地，在本公开的实施例中，在步骤730形成有源层时，首先，在第一有源层104和/或所述第二有源层104'中的转化为多晶半导体材料的第一半导体层上形成包含非晶半导体材料的第二半导体层。具体地，将退火半导体层SD形成的多晶半导体层作为第一半导体层1041。在该第一半导体层1041上沉积具有第一载流子浓度的非晶半导体材料，例如非晶硅，然后构图以形成第二半导体层1042。在第二半导体层1042的相对端部上形成包含非晶半导体材料的第三半导体层1043。具体地，在该第二半导体层1042上沉积具有第二载流子浓度的非晶半导体材料，例如非晶硅，以形成第三半导体层1043。在本实施例中，第一载流子浓度大于第二载流子浓度。
图10示出了根据本公开的实施例的显示装置1000的示意图。如图10所示，显示装置1000可包括上述的如图1至图3所示的阵列基板100。根据本公开的实施例的显示面板可以用于任何具有显示功能的产品或部件。这样的产品或部件包括但不限于显示装置、可穿戴设备、移动电话、平板电脑、电视机、笔记本电脑、数码相框、导航仪等。
以上已经描述了根据本公开的若干实施例，这些实施例仅通过举例的方式展现，而且不旨在限制本公开的范围。事实上，本文所描述的新颖实施例也可以以各种其它形式来实施。此外，在不脱离本公开的精神下，可以对本文所描述的实施例的形式进行各种省略、替代和改变。所附权利要求以及它们的等价物旨在覆盖落在本公开范围和精神内的此类形式或者修改。

Claims (20)

  1. 一种阵列基板，包括：
    衬底，具有显示区域和围绕所述显示区域的周边区域，所述显示区域包括呈阵列排布的子像素；以及
    多个薄膜晶体管，位于所述衬底上，包括位于所述周边区域内的多个第一薄膜晶体管和位于所述显示区域的每个子像素内的第二薄膜晶体管，其中，所述第一薄膜晶体管的第一有源层与最邻近的所述第二薄膜晶体管的第二有源层之间具有行和/或列方向上的第一距离，且相邻的所述第二有源层之间具有行和/或列方向上的第二距离，所述第一距离等于所述第二距离。
  2. 根据权利要求1所述阵列基板，其中，所述第一有源层与所述第二有源层具有相同的形状。
  3. 根据权利要求2所述阵列基板，其中，所述第一有源层与所述第二有源层具有相同的尺寸。
  4. 根据权利要求1所述阵列基板，其中，所述第一有源层中的至少一个包括多晶半导体材料。
  5. 根据权利要求4所述阵列基板，其中，所述第二有源层包括非晶半导体材料。
  6. 根据权利要求4所述阵列基板，其中，所述第二有源层包括多晶半导体材料。
  7. 根据权利要求6所述阵列基板，其中，至少邻近所述周边区域的所述第二有源层包括多晶半导体材料。
  8. 根据权利要求6所述阵列基板，其中，所述第一有源层中的所述至少一个和/或所述第二有源层包括叠层结构，所述叠层结构包括沿垂直于所述基板且远离所述薄膜晶体管的栅极的方向依次设置的包含多晶半导体材料的第一半导体层、包含非晶半导体材料的第二半导体层以及包含非晶半导体材料的位于所述第二半导体层的相对端部的第三半导体层，其中，所述第三半导体层具有比所述第二半导体层高的载流子浓度。
  9. 根据权利要求8所述阵列基板，其中，所述薄膜晶体管的所述栅极位于所述薄膜晶体管的有源层与所述衬底之间
  10. 根据权利要求4所述阵列基板，其中，所述周边区域包括至少一个驱动电路，
    所述驱动电路包括：
    第一子薄膜晶体管，所述第一子薄膜晶体管的栅极和第一源/漏极与数据输入端耦接，所述第一子薄膜晶体管的第二源/漏极与第一节点耦接；
    第二子薄膜晶体管，所述第二子薄膜晶体管的栅极与复位端耦接，所述第二子薄膜晶体管的第一源/漏极与所述第一节点耦接，所述第二子薄膜晶体管的第二源/漏极与第一电压端耦接；
    第三子薄膜晶体管，所述第三子薄膜晶体管的栅极与所述第一节点耦接，所述第三子薄膜晶体管的第一源/漏极与第一时钟信号端耦接，所述第三子薄膜晶体管的第二源/漏极与数据输出端耦接；
    第四子薄膜晶体管，所述第四子薄膜晶体管的栅极与第二节点耦接，所述第四子薄膜晶体管的第一源/漏极与第三节点耦接，所述第四子薄膜晶体管的第二源/漏极与第二时钟信号端耦接；
    第五子薄膜晶体管，所述第五子薄膜晶体管的栅极与所述第一节点耦接，所述第五子薄膜晶体管的第一源/漏极与所述第三节点耦接，所述第五子薄膜晶体管的第二源/漏极与所述第一电压端耦接；
    第六子薄膜晶体管，所述第六子薄膜晶体管的栅极与所述第二时钟信号端耦接，所述第六子薄膜晶体管的第一源/漏极与所述数据输入端耦接，所述第六子薄膜晶体管的第二源/漏极与所述第一节点耦接；
    第七子薄膜晶体管，所述第七子薄膜晶体管的栅极与所述第一节点耦接，所述第七子薄膜晶体管的第一源/漏极与所述第二节点耦接，所述第七子薄膜晶体管的第二源/漏极与所述第一电压端耦接；
    第八子薄膜晶体管，所述第八子薄膜晶体管的栅极和第一源/漏极与所述第二时钟信号端耦接，所述第八子薄膜晶体管的第二源/漏极与所述第二节点耦接；
    第九子薄膜晶体管，所述第九子薄膜晶体管的栅极与所述第三节点耦接，所述第九子薄膜晶体管的第一源/漏极与所述第一节点耦接，所述第九子薄膜晶体管的第二源/漏极与所述第一电压端耦接；
    第十子薄膜晶体管，所述第十子薄膜晶体管的控制极与所述第三节点耦接，所述第十子薄膜晶体管的第一源/漏极与所述数据输出端耦接，所述第十子薄膜晶体管的第二源/漏极与所述第一电压端耦接；
    第十一子薄膜晶体管，所述第十一子薄膜晶体管的栅极与所述第二时钟信号端耦接，所述第十一子薄膜晶体管的第一源/漏极与所述数据输出端耦接，所述第十一子薄膜晶体管的第二源/漏极与所述第一电压端耦接；
    电容，所述电容的第一端与所述第一节点耦接，所述电容的第二端与所述数据输出端耦接。
  11. 根据权利要求10所述的阵列基板，其中，所述第七子薄膜晶体管的有源层的宽长比被配置为大于所述第八子薄膜晶体管的有源层。
  12. 根据权利要求11所述的阵列基板，其中，所述第一有源层的所述至少一个包括所述第一到第十一子薄膜晶体管的有源层。
  13. 根据权利要求10所述阵列基板，其中，所述第三子薄膜晶体管的有源层具有叠层结构，其包括沿垂直于所述基板且远离所述薄膜晶体管的栅极的方向依次设置的包含多晶半导体材料的第一半导体层、包含非晶半导体材料的第二半导体层以及位于所述第二半导体层的相对端部的包含非晶半导体材料的第三半导体层，其中，所述第三半导体层具有比所述第二半导体层高的载流子浓度。
  14. 一种用于制造阵列基板的方法，包括：
    提供衬底，所述衬底具有显示区域和围绕所述显示区域的周边区域，所述显示区域包括呈阵列排布的子像素；以及
    在所述衬底上形成多个薄膜晶体管，所述多个薄膜晶体管包括位于所述周边区域内的多个第一薄膜晶体管和在所述显示区域的每个子像素内的第二薄膜晶体管，
    其中，所述第一薄膜晶体管的第一有源层与最邻近的第二薄膜晶体管 的第二有源层的之间具有行和/或列方向上的第一距离，且相邻的所述第二有源层之间具有行和/或列方向上的第二距离，所述第一距离等于所述第二距离。
  15. 根据权利要求14所述的方法，形成所述多个薄膜晶体管包括：
    在所述衬底上形成包含非晶半导体材料的半导体层，所述半导体层包括与所述第一有源层一一对应的第一部分和与所述第二有源层一一对应的第二部分；以及
    将所述第一部分中的至少一个中所包含的非晶半导体材料转化为多晶半导体材料。
  16. 根据权利要求15所述的方法，还包括，将至少邻近所述周边区域的所述第二部分中所包含的所述非晶半导体材料转化为多晶半导体材料。
  17. 根据权利要求16所述的方法，其中，所述转化包括使用掩模对所述半导体层进行激光退火处理，其中所述掩模具有呈阵列排布的与所述子像素一一对应的开口和与所述开口一一对应且与所述开口沿透光方向对准的微透镜。
  18. 根据权利要求16所述的方法，还包括，构图所述半导体层以去除所述半导体层的除所述第一部分和所述第二部分之外的部分并整形所述第一部分和所述第二部分以形成所述第一有源层和所述第二有源层。
  19. 根据权利要求18所述的方法，其中，进行所述整形以使所述第一有源层与所述第二有源层具有相同的形状和尺寸。
  20. 一种显示装置，包括根据权利要求1至13中任一项所述的阵列基板。
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