WO2021007774A1 - 阵列基板、显示面板、显示装置和阵列基板的制作方法 - Google Patents

阵列基板、显示面板、显示装置和阵列基板的制作方法 Download PDF

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Publication number
WO2021007774A1
WO2021007774A1 PCT/CN2019/096151 CN2019096151W WO2021007774A1 WO 2021007774 A1 WO2021007774 A1 WO 2021007774A1 CN 2019096151 W CN2019096151 W CN 2019096151W WO 2021007774 A1 WO2021007774 A1 WO 2021007774A1
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WIPO (PCT)
Prior art keywords
pixel
source
gate line
array substrate
pixel electrode
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Application number
PCT/CN2019/096151
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English (en)
French (fr)
Inventor
李宗祥
王文超
颜京龙
吴洪江
王宝强
刘文瑞
陈曦
刘耀
林鸿涛
陶文昌
Original Assignee
京东方科技集团股份有限公司
福州京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 福州京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to JP2019567555A priority Critical patent/JP7456773B2/ja
Priority to PCT/CN2019/096151 priority patent/WO2021007774A1/zh
Priority to CN201980001044.7A priority patent/CN112513725B/zh
Priority to EP19932281.9A priority patent/EP4002004B1/en
Priority to US16/959,234 priority patent/US11402711B2/en
Publication of WO2021007774A1 publication Critical patent/WO2021007774A1/zh
Priority to JP2024032841A priority patent/JP2024063174A/ja

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134336—Matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0465—Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness

Definitions

  • the embodiments of the present disclosure relate to a manufacturing method of an array substrate, a display panel, a display device, and an array substrate.
  • TFT-LCDs thin film transistor liquid crystal display devices
  • LCDs thin film transistor liquid crystal display devices
  • people have also put forward higher and higher requirements for the display performance of display devices. For example, display devices are required to have high resolution, high contrast, and high response speed. Wait.
  • people have put forward higher requirements on parameters that characterize the picture quality of the display device (for example, after-image, mura, light leakage, etc.).
  • display devices adopt a dual-gate design.
  • At least one embodiment of the present disclosure provides an array substrate including: a pixel unit group.
  • the pixel unit group includes a first pixel and a second pixel arranged next to each other in a first direction; the first pixel includes a first pixel electrode, a first switching element, and a first pixel electrode extending and protruding from the first pixel electrode.
  • a connecting portion, the second pixel includes a second pixel electrode, a second switching element, and a second connecting portion extending and protruding from the second pixel electrode; the first pixel electrode and the first switching element pass through the The first connection portion is electrically connected to each other, the second pixel electrode and the second switching element are electrically connected to each other via the second connection portion; and the extension length of the first connection portion is not equal to the second connection The length of the extension.
  • the pixel unit group includes a first edge and a second edge opposite to each other in the first direction, and with respect to the second edge, the first switch Both the element and the second switching element are closer to the first edge of the pixel unit group in the first direction.
  • the first pixel electrode in a second direction crossing the first direction, is located between the first switching element and the second switching element.
  • the first switching element and the second switching element extend in the second direction and along the first direction with respect to the first pixel electrode.
  • the center line is set symmetrically.
  • the extending and protruding direction of the first connecting portion is the second direction
  • the extending and protruding direction of the second connecting portion is the first direction
  • the The one direction and the second direction cross each other.
  • the second connection portion in a second direction crossing the first direction, the second connection portion at least partially overlaps the first pixel electrode.
  • the first connection portion and the first pixel electrode are integrally formed using the same material, and the second connection portion and the second pixel electrode are formed of the same material Formed in one body.
  • the first switching element includes a first source-drain layer, and the first source-drain layer includes two first source and drain electrodes that are opposite to each other and are arranged at intervals;
  • the second switching element includes a second source-drain layer, and the second source-drain layer includes two second source and drain electrodes opposite to each other and spaced apart;
  • the first connecting portion is directly electrically connected to the first pixel electrode ,
  • the first connecting portion is electrically connected to one of the two first source and drain electrodes via a first via;
  • the second connecting portion is directly electrically connected to the second pixel electrode, the second The connecting portion is electrically connected to one of the two second source and drain electrodes through a second via hole.
  • one of the two first source and drain electrodes covers a part of the opening area of the first via, and the other part of the opening area of the first via is located A side of one of the first source and drain electrodes close to the first pixel electrode; and one of the two second source and drain electrodes covers a part of the opening area of the second via, the second Another part of the opening area of the via hole is located on one side of the second source and drain electrodes close to the first pixel electrode.
  • the array substrate further includes a first gate line and a second gate line extending along the first direction; the first gate line and the second gate line Located on both sides of the pixel unit group in a second direction crossing the first direction; the orthographic projection of the first gate line on the first source-drain layer and the two first source-drain One of the poles overlaps at at least two different positions.
  • the first gate line includes a first gate part, a first line part, and a first line connection part that are sequentially connected; the first gate part is configured Is the gate of the first switching element; the orthographic projection of the first gate line on the first source-drain layer and the difference between one of the two first source and drain electrodes in the first direction The sides overlap at least partially.
  • the orthographic projection of the first line connecting portion of the first gate line on one of the two first source and drain electrodes is One of the poles overlaps at least partially.
  • the first line connecting portion includes a first protrusion protruding toward the first gate portion; and the first protrusion is positioned between the two second The orthographic projection on one of the source and drain at least partially overlaps with one of the two first source and drain.
  • the orthographic projection of the first protrusion on one of the two first source and drain electrodes overlaps with one of the two first source and drain electrodes
  • the area is a first overlapping area, and the first overlapping area has a first overlapping edge in a second direction that crosses the first direction; the first gate portion is in the two second
  • the overlap area between the orthographic projection on one of the source and drain electrodes and one of the two first source and drain electrodes is a second overlap area, and the second overlap area has a second overlap area in the second direction.
  • Two overlapping edges; the length of the first overlapping edge and the length of the second overlapping edge are equal.
  • the orthographic projection of the second gate line on the second source and drain layer is at least two different positions from one of the two second source and drain electrodes. Overlapped.
  • the second gate line includes a second gate part, a second line part, and a second line connection part that are sequentially connected; the second gate part is configured to The gate of the second switching element; the orthographic projection of the second gate line on the second source and drain layer is at least on both sides of one of the two second source and drain electrodes in the first direction Partially overlapped.
  • the orthographic projection of the second line connecting portion of the second gate line on one of the two second source and drain electrodes is consistent with the two second source and drain electrodes.
  • the second wire connection portion includes a second protrusion protruding toward the second gate portion; the second protrusion is located between the two second sources
  • the orthographic projection on one of the drains at least partially overlaps with one of the two second source and drains.
  • the orthographic projection of the second protrusion on one of the two second source and drain electrodes overlaps with one of the two second source and drain electrodes
  • the area is a third overlapping area, and the third overlapping area has a third overlapping edge in the second direction; the second gate portion is located between one of the two second source and drain electrodes.
  • the overlap area between the orthographic projection and one of the two second source and drain electrodes is a fourth overlap area, and the fourth overlap area has a fourth overlap edge in the second direction; and
  • the length of the third overlapping edge is equal to the length of the fourth overlapping edge.
  • the overlap area between the orthographic projection of the first gate line on the first source and drain layer and one of the two first source and drain electrodes is the first Value;
  • the overlapping area between the orthographic projection of the second gate line on the second source and drain layer and one of the two second source and drain electrodes is a second value; and the first value is equal to the The second value.
  • the first connection portion and the second connection portion are respectively located on both sides of the first pixel electrode in a second direction perpendicular to the first direction
  • the first connecting portion and the second connecting portion are located between the first gate line and the second gate line in the second direction; and the first gate line and the second gate line
  • the gate lines are arranged symmetrically with respect to the center line of the pixel unit group extending along the first direction in the second direction.
  • the array substrate includes a plurality of the pixel unit groups arranged in an array; and a first gate line for driving each of the pixel unit groups and a The second gate lines of the pixel unit groups adjacent to each pixel unit group in the second direction partially overlap in the first direction.
  • the array substrate includes a plurality of the pixel unit groups arranged in an array and data lines arranged between adjacent pixel unit groups; and each The first switching element and the second switching element of the pixel unit group are both connected to the same data line.
  • the array substrate further includes a plurality of common electrode patterns arranged in an array; the plurality of common electrode patterns correspond to the plurality of pixel unit groups one to one; The plurality of common electrode patterns of the row are located between the first gate line and the second gate line of the pixel unit group corresponding to the plurality of common electrode patterns of the same row; the adjacent ones in the first direction
  • the common electrode patterns are electrically connected to each other through a first common electrode connecting portion, the first common electrode connecting portion and the common electrode pattern are in the same layer; and the common electrode patterns adjacent in the second direction pass through
  • the second common electrode connection portions are electrically connected to each other, the second common electrode connection portion is in the same layer as the first connection portion, and the second common electrode connection portion is electrically connected to the corresponding common electrode pattern through a third via hole.
  • each of the common electrode patterns includes a main body part and a first protruding part protruding from a first side of the main body part; the first protruding part Extending along the second direction; the common electrode patterns adjacent in the second direction are electrically connected through the first protrusions of the adjacent common electrode patterns and the third via.
  • the lateral distance between the first pixel electrode and the gate line driving the first pixel is greater than five micrometers; the second pixel electrode and the gate line driving the second pixel
  • the lateral spacing of the grid lines is greater than five microns.
  • the extension length of the first connection portion is smaller than the extension length of the second connection portion; and the second pixel electrode is close to the gate driving the second pixel.
  • the first pixel electrode and the gate line driving the first pixel overlap each other in a second direction crossing the first direction, and the second The pixel electrode and the gate line driving the second pixel overlap each other in a second direction crossing the first direction; and the combination structure of the first pixel electrode and the first connecting portion and the driving
  • the effective overlapping length of the gate line of the first pixel is equal to the effective overlapping length of the combination structure of the second pixel electrode and the second connecting portion and the gate line driving the second pixel.
  • At least one embodiment of the present disclosure also provides a display panel, which includes any array substrate provided by the embodiments of the present disclosure.
  • At least one embodiment of the present disclosure further provides a display device, which includes any array substrate provided by an embodiment of the present disclosure or any display panel provided by an embodiment of the present disclosure.
  • At least one embodiment of the present disclosure also provides a manufacturing method of an array substrate, which includes forming a pixel unit group.
  • the pixel unit group includes a first pixel and a second pixel arranged side by side in a first direction; the first pixel includes a first pixel electrode, a first switching element, and a first pixel electrode extending and protruding from the first pixel electrode.
  • the second pixel includes a second pixel electrode, a second switching element, and a second connecting portion extending and protruding from the second pixel electrode; the first pixel electrode and the first switching element pass through the The first connection portion is electrically connected to each other, the second pixel electrode and the second switching element are electrically connected to each other via the second connection portion; and the length of the first connection portion is not equal to that of the second connection portion length.
  • the forming the pixel unit group includes: using the same patterning process to pattern the same film layer to form the first connecting portion, the first pixel electrode, and the second The connection part and the second pixel electrode.
  • Figure 1 is a schematic plan view of an array substrate
  • FIG. 2A is a schematic plan view of an array substrate provided by at least one embodiment of the present disclosure.
  • FIG. 2B is a schematic plan view of the pixel unit group of the array substrate shown in FIG. 2A;
  • FIG. 2C is a schematic diagram of an image observed by a user of the display panel without shaking his head or shaking his head;
  • Fig. 2D is a schematic diagram of an exemplary calculation method of spatial frequency
  • FIG. 2E is a schematic diagram of the best observation distance of the moving head pattern of different types of display panels
  • Figure 2F is a schematic diagram of the causes of bad head wrinkles
  • 2G is a schematic diagram of charging and discharging pixels of a display panel
  • 2H is a schematic diagram of a pixel-related capacitance of a display panel
  • FIG. 3A is a schematic diagram of the array substrate shown in FIG. 2A;
  • FIG. 3B is an enlarged view of the area RC1 of the array substrate shown in FIG. 2A;
  • 3C is an enlarged view of the area RC2 of the array substrate shown in FIG. 2A;
  • 3D is a schematic diagram of pixel voltages of pixels in pixel unit groups in odd columns of the array substrate shown in FIG. 2A when the source and drain metal layers are not shifted or shifted;
  • 3E is a schematic diagram of pixel voltages of pixels in pixel unit groups located in even-numbered columns of the array substrate shown in FIG. 2A when the source and drain metal layers are not shifted or shifted;
  • 3F is a schematic diagram of the effective overlap length and lateral spacing between the combined structure of the pixel electrode and the connecting portion of the pixel of the array substrate shown in FIG. 2A and the gate line driving the pixel;
  • 3G is a schematic diagram of the comparison of the pixel voltages of the short-connected pixels and the long-connected pixels of the array substrate shown in FIG. 2A in a positive display frame and a negative display frame;
  • FIG. 3H is a schematic diagram of the area RC1 of the array substrate shown in FIG. 2A;
  • FIG. 3I is a schematic diagram of the area RC3 of the array substrate shown in FIG. 2A;
  • 3J is a schematic diagram of the influence of the capacitance Cpg' of the pixel of the array substrate shown in FIG. 2A on the pixel voltage of the pixel;
  • 4A is a schematic plan view of another array substrate provided by at least one embodiment of the present disclosure.
  • FIG. 4B is a schematic plan view of the pixel unit group of the array substrate shown in FIG. 4A;
  • 4C is a schematic plan view of the first electrode layer of the array substrate shown in FIG. 4A;
  • 4D is a schematic plan view of the first gate line and the second gate line of the array substrate shown in FIG. 4A;
  • 4E is a schematic plan view of a portion of the first gate line and the second gate line of the array substrate shown in FIG. 4A corresponding to one pixel unit group;
  • 5A is a schematic plan view of the semiconductor layer and the second electrode layer of the array substrate shown in FIG. 4A;
  • 5B is a schematic plan view of the first switching element of the array substrate shown in FIG. 4A;
  • 5C is a schematic cross-sectional view taken along the line AA' shown in FIG. 5B;
  • 5D is a schematic plan view of a second switching element of the array substrate shown in FIG. 4A;
  • 5E is a schematic plan view of a partial area of the array substrate shown in FIG. 2A;
  • 5F is a schematic plan view of the area RC4 of the array substrate shown in FIG. 5E;
  • 5G is a first schematic diagram of the overlap area between the electrode layer where the gate line is located and the electrode layer where the source and drain are located in the orthographic projection of the electrode layer where the gate line is located on the array substrate shown in FIG. 4A;
  • 5H is a second schematic diagram of the overlap area between the electrode layer where the gate line is located and the electrode layer where the source and drain are located in the orthographic projection of the electrode layer where the gate line is located on the array substrate shown in FIG. 4A;
  • FIG. 6 is a schematic plan view of a third electrode layer of the array substrate shown in FIG. 4A;
  • FIG. 7 is a schematic plan view of the first electrode layer, the semiconductor layer and the second electrode layer of the array substrate shown in FIG. 4A;
  • FIG. 8 is a schematic plan view of the first via hole, the second via hole and the third via hole of the array substrate shown in FIG. 4A;
  • FIG. 9 is a schematic diagram of the pitch and overlap length between the pixel electrode of the array substrate shown in FIG. 4A and the gate line of the pixel driving the pixel electrode;
  • FIG. 10 is a schematic plan view of a plurality of common electrode patterns of the array substrate shown in FIG. 4A;
  • FIG. 11 is a schematic plan view of one of a plurality of common electrode patterns of the array substrate shown in FIG. 4A.
  • FIG. 12 is an exemplary block diagram of a display panel and a display device provided by at least one embodiment of the present disclosure.
  • the inventors of the present disclosure have noticed in their research that some display panels adopting a dual-grid design have bad head patterns and/or low aperture ratio, especially for TN (Twist Nematic) display panels
  • TN Transist Nematic
  • FIG. 1 is a schematic plan view of an array substrate 500.
  • the array substrate 500 includes a plurality of pixel unit groups 510 arranged in an array, gate lines 542 extending along a first direction D1, and a second direction D2 that crosses (for example, perpendicular) to the first direction D1.
  • Two gate lines 542; each row of pixel unit group 510 consists of two gate lines 542 (a gate line 542 located above the row of pixel unit group 510 and the row of pixel unit A gate line 542) under the group 510 is driven.
  • each pixel unit group 510 includes a first pixel and a second pixel arranged next to each other in a first direction D1;
  • the first pixel includes a first pixel electrode 521, a first switching element 523, and a first pixel electrode.
  • Line 522, the first wiring 522 is used to connect the first switching element 523 and the data line 561 for driving the first pixel;
  • the second pixel includes the second pixel electrode 531, the second switching element 533, and the second wiring 532.
  • the second wiring 532 is used to connect the second switching element 533 and the data line 561 for driving the second pixel.
  • the first pixel electrode 521 and the first switching element 523 are electrically connected through a first via 524
  • the second pixel electrode 531 and the second switching element 533 are electrically connected through a second via 534; the first via The orthographic projection of 524 on the first pixel electrode 521 and the first pixel electrode 521 at least partially overlap; the orthographic projection of the second via 534 on the second pixel electrode 531 and the second pixel electrode 531 at least partially overlap.
  • the first switching element 523 and the second switching element 533 for driving the same pixel unit group 510 are arranged side by side in the second direction D2, and the first switching element 523 and the second switching element 533 are arranged in the second direction D2.
  • the direction D2 at least partially overlaps, that is, the orthographic projections of the first switching element 523 and the second switching element 533 on a plane perpendicular to the second direction D2 at least partially overlap; the first trace 522 and the second trace
  • the line 532 is arranged between two gate lines 542 between two adjacent pixel unit groups 510 in the second direction D2.
  • the display panel including the array substrate 500 includes a black matrix (not shown in the figure), and the orthographic projection of the black matrix on the array substrate 500 covers the gate lines 542, the data lines 561, the first wiring 522, and the second wiring.
  • the first wiring 522, the second wiring 532, and the data line 561 are made of the same material.
  • the inventor of the present disclosure has noticed in research that the display panel including the array substrate shown in FIG. 1 has a small aperture ratio. Also, although the aperture ratio of the display panel including the array substrate shown in FIG. 1 can be slightly increased by reducing the width of the first wiring and the second wiring in the second direction, the first wiring and the second wiring are reduced. The width in the second direction can increase the risk of disconnection of the first trace and the second trace. In addition, the signals on the first trace and the second trace may interfere with signals on other traces of the array substrate.
  • the array substrate includes a pixel unit group.
  • the pixel unit group includes a first pixel and a second pixel arranged next to each other in a first direction; the first pixel includes a first pixel electrode, a first switching element, and a first connection portion extending and protruding from the first pixel electrode;
  • the pixel includes a second pixel electrode, a second switching element, and a second connection portion extending and protruding from the second pixel electrode; the first pixel electrode and the first switching element are electrically connected to each other via the first connection portion, and the second pixel electrode and the second The switching elements are electrically connected to each other via the second connection part; and the extension length of the first connection part is not equal to the extension length of the second connection part.
  • the array substrate and the array substrate including the array substrate have the ability to increase the aperture ratio or the basis for increasing the aperture ratio.
  • the array substrate including the ability to increase the aperture ratio or the basis for increasing the aperture ratio may have uneven display.
  • Phenomenon for example, shaking head pattern phenomenon, bad shaking head pattern.
  • Moving head pattern is a kind of stripes that the user of the display panel may observe when shaking his head.
  • the moving head pattern is related to the pixel voltage jump variable ⁇ p of different pixels.
  • the factors that affect the pixel voltage jump variable ⁇ p of the pixel include :
  • the lateral capacitance of the pixel includes the capacitance Cgs formed by the gate line and the source and drain layers, the capacitance Cpg formed by the pixel electrode and the gate line corresponding to the pixel electrode, the pixel electrode and the gate line adjacent to the pixel electrode (but not used for The capacitor Cpg′ formed by driving the pixel where the pixel electrode is located).
  • the pixel voltage of the long-connected pixel jumps.
  • ⁇ p is closer to the pixel voltage jump ⁇ p of the short-connected pixels, which can reduce the head wobble phenomenon.
  • the orthographic projection of the portion of the gate line (the first gate line and the second gate line) corresponding to each pixel (the first pixel and the second pixel) on the source and drain layer is the same as that of the pixel.
  • One of the source and drain overlaps at least two different positions, which can reduce the variation range (deviation from the design value) of the capacitance Cgs formed by the gate line and the source and drain layer, thereby suppressing display unevenness (such as , Shaking head pattern phenomenon, bad shaking head pattern).
  • the orthographic projection of the second gate line on the source and drain layer is equal to two
  • the overlapping area of one of the second source and drain electrodes can make the capacitance Cgs of the long-connected pixel equal to the capacitance Cgs of the short-connected pixel, which can further suppress (for example, the phenomenon of shaking head patterns, bad shaking head patterns).
  • the influence of the following factors on the capacitance Cpg of the first pixel can be reduced: The change in the horizontal spacing of the lines (for example, the change caused by the manufacturing process); the change in the effective overlap length of the combination structure of the first pixel electrode and the first connection part and the gate line driving the first pixel; by making the second pixel
  • the lateral distance between the electrode and the gate line driving the second pixel is greater than five microns, which can reduce the influence of the following factors on the capacitance Cpg of the second pixel: the change in the lateral distance between the second pixel electrode and the gate line driving the second pixel;
  • the combination structure of the pixel electrode and the second connection part and the effective overlap length of the gate line driving the second pixel vary; therefore, the requirements on the manufacturing process can be reduced without degrading the display uniformity.
  • the side of the pixel electrode of the long-connected pixel close to the gate line driving the long-connected pixel have a recess, it is possible to shorten the effective intersection between the pixel electrode of the long-connected pixel and the connection structure of the connecting part and the gate line.
  • Overlapping length lpg in this case, the effective overlapping length of the combined structure of the pixel electrode and the connecting portion of the long-connected pixel and the gate line is shorter than the effective overlapping length of the combined structure of the pixel electrode and the connecting portion of the connected pixel and the gate line Therefore, the capacitance Cpg of the long-connected pixel can be made closer to the capacitance Cpg of the short-connected pixel, thereby further suppressing the wobble defect.
  • the array substrate 100 includes a plurality of pixel unit groups 110 and a plurality of first gate lines 141 arranged in an array.
  • the plurality of second gate lines 142 and the plurality of data lines 161; the plurality of first gate lines 141 and the plurality of second gate lines 142 respectively extend substantially along the first direction D1, and the plurality of data lines 161 substantially extend along the first direction
  • Each row of pixel unit group 110 is driven by two gate lines, and the above two gate lines (one first gate line 141 and one second gate line 142) are located on both sides of the row of pixel unit group 110 in the second direction D2 And it is adjacent to the row of pixel unit group 110.
  • the gate line is adjacent to the pixel unit group 110 means that no other gate lines are included between the pixel unit group 110 and the aforementioned gate line.
  • Two gate lines are arranged between two adjacent pixel unit groups 110 in the second direction D2, and a data line is arranged between two adjacent pixel unit groups 110 in the first direction D1.
  • FIG. 2B is a schematic plan view of the pixel unit group 110 of the array substrate 100 shown in FIG. 2A.
  • FIG. 2B also shows the first gate line 141, the second gate line 142, and the data line 161.
  • Part or all of the pixel unit groups 110 of the array substrate 100 shown in FIG. 2A may be implemented as the pixel unit groups 110 shown in FIG. 2B.
  • the pixel unit group 110 includes a first pixel and a second pixel that are arranged next to each other in the first direction D1. It should be noted that the first pixel and the second pixel that are arranged next to each other in parallel means that no other pixels are included between the first pixel and the second pixel.
  • the first pixel includes a first pixel electrode 121, a first switching element 123, and a first connecting portion 122 extending and protruding from the first pixel electrode 121
  • the second pixel includes a second pixel electrode 131, a second switch
  • the element 133 and the second connection portion 132 extending and protruding from the second pixel electrode 131; the first pixel electrode 121 and the first switching element 123 are electrically connected to each other via the first connection portion 122, and the second pixel electrode 131 and the second switching element 133
  • the second connecting portion 132 is electrically connected to each other; the extension length of the first connecting portion 122 is not equal to (for example, less than) the extension length of the second connecting portion 132.
  • the first pixel may also be called a short connection pixel
  • the second pixel may also be called a long connection pixel
  • the pixel with the smaller extension length of the connecting portion included in each pixel unit group is called a short-connected pixel
  • the pixel with the longer extension length of the connecting portion included in each pixel unit group is called Long connected pixels.
  • all the short-connected pixels on the array substrate are called first pixels
  • all the long-connected pixels on the array substrate are called second pixels.
  • both the first switching element 123 and the second switching element 133 can be arranged in the pixel unit group 110.
  • the edge in the first direction D1 will be exemplified below with reference to FIG. 2B.
  • the pixel unit group 110 includes a first edge 111 and a second edge 112 opposite to each other in the first direction D1.
  • the first switching element 123 and the second switching element 133 Both are closer to the first edge 111 of the pixel unit group 110 in the first direction D1.
  • the first switching element 123 and the second switching element 133 of each pixel unit group 110 are both connected to the same data line 161.
  • the distances between the first switching element 123 and the second switching element 133 of each pixel unit group 110 and the same data line 161 are the same.
  • the switching elements connected to the same data line 161 include the switching element located on the first side (for example, the left side) of the same data line 161 and the second switching element located on the same data line 161.
  • the switching elements partially overlap in the first direction D1.
  • the A structure and the B structure overlap (or partially overlap) in the C direction refers to the orthographic projection of the A structure on the D plane perpendicular to the C direction and the B structure on the D plane
  • the orthographic projections overlap (or partially overlap).
  • the switching elements located on the first side (for example, the left side) of the same data line 161 and the switching elements located on the second side (for example, the right side) of the same data line 161 move in the first direction D1
  • the size on D2 improves the aperture ratio of the array substrate 100 and the display panel and the display device including the array substrate 100.
  • the first connection portion 122 and the second connection portion 132 of the pixel unit group 110 are respectively located on both sides of the first pixel electrode 121 in the second direction D2; the first connection portion 122 and the second connection portion The portions 132 are located between the first gate line 141 and the second gate line 142 in the second direction D2.
  • the extending and protruding direction of the first connecting portion 122 is the second direction D2
  • the extending and protruding direction of the second connecting portion 132 is the first direction D1.
  • the extension length of the first connection portion 122 refers to the length of the first connection portion 122 in the second direction D2
  • the extension length of the second connection portion 132 refers to the length of the second connection portion 132 in the first direction D1
  • the extension length of the connecting portion refers to the length of the connecting portion in its extension direction.
  • the extension length of the connecting portion may also be the overall length or physical length of the connecting portion.
  • the second connecting portion 132 at least partially overlaps the first pixel electrode 121; in the second direction D2, the first pixel electrode 121 is located between the first switching element 123 and the second switching element 133 .
  • first connecting portion 122 and the first pixel electrode 121 are integrally formed using the same material
  • second connecting portion 132 and the second pixel electrode 131 are integrally formed using the same material.
  • the first switching element 123 and the second switching element 133 are integrally formed using the same edge (for example, the first edge 111) of the pixel unit group 110 in the first direction D1
  • the first connecting portion 122 and the first pixel electrode 121 are integrally formed using the same material
  • the second connection portion 132 and the second pixel electrode 131 are integrally formed using the same material, so that the first connection portion 122 (the first end 1221 of the first connection portion 122 6) is directly electrically connected to the first pixel electrode 121, and makes the second connecting portion 132 (the first end 1321 of the second connecting portion 132, also see FIG. 6 below) and the second The pixel electrode 131 is directly electrically connected.
  • the first via 1223 and the second via 1323 shown in FIG. 2B are not The aperture ratio of the pixel unit group 110 and the array substrate 100 will be reduced.
  • both the first pixel electrode 121 and the second pixel electrode 131 may be formed of a transparent conductive material.
  • the transparent conductive material is indium tin oxide (ITO) or indium zinc oxide (IZO).
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • the first connection portion 122 and the second connection portion 132 can also be formed using a transparent conductive material (for example, ITO).
  • the processing accuracy of the transparent conductive material is higher than the processing accuracy of the metal material, that is, the line width of the transparent conductive material trace can be smaller than the line width of the metal material trace; in this case, the first connection
  • the size of the area occupied by the portion 122 and the second connecting portion 132 can be reduced, and the size of the area occupied by the first pixel electrode 121 and the second pixel electrode 131 can be increased correspondingly, thereby further improving the pixel unit group 110 and the array substrate
  • the aperture ratio of 100 is higher than the processing accuracy of the metal material, that is, the line width of the transparent conductive material trace can be smaller than the line width of the metal material trace; in this case, the first connection
  • the size of the area occupied by the portion 122 and the second connecting portion 132 can be reduced, and the size of the area occupied by the first pixel electrode 121 and the second pixel electrode 131 can be increased correspondingly, thereby further improving the pixel unit group 110 and the array substrate
  • the aperture ratio of 100 is
  • the first switching element 123 and the second switching element 133 are both U-shaped TFTs.
  • the opening directions of the U-shaped TFTs of the pixel unit groups located in adjacent rows are opposite.
  • the opening direction of the U-shaped TFT of the pixel unit group located in the first row (odd row) is to the right, and the opening direction of the U-shaped TFT of the pixel unit group located in the second row (even-numbered row) To the left.
  • the U-shaped TFT of the pixel unit group located in the first row is arranged on the right side of the data line
  • the U-shaped TFT of the pixel unit group located in the second row is arranged on the left side of the data line .
  • the inventor of the present disclosure has noticed in research that although the aperture ratio of the array substrate may be increased by making the pixel unit group of the array substrate shown in FIG. 2A include long-connected pixels and short-connected pixels, it may also result in the The array substrate has uneven brightness (for example, the phenomenon of head shaking, bad head shaking).
  • the following is a detailed description of the related problems of bad head wrinkles in conjunction with Figure 2C- Figure 2H.
  • the head-shaking pattern is a stripe of alternating light and dark that the user of the display panel may observe when shaking his head.
  • the left image of FIG. 2C is the image observed when the user of the display panel does not shake his head, and the right image of FIG. 2C is the image observed when the user of the display panel shakes his head (that is, an image with bad head shaking).
  • the display panel is configured to display an image with a grayscale of 127 (that is, the grayscale of each pixel of the image is 127).
  • the bright stripes and dark stripes of the moving head pattern respectively extend in the column direction of the display panel, and the bright stripes and dark stripes of the moving head pattern are alternately arranged in the row direction of the display panel.
  • the shaking head pattern can be described using the spatial frequency fs, which will be exemplified below in conjunction with FIG. 2D.
  • Fig. 2D shows a schematic diagram of an exemplary calculation method of the spatial frequency.
  • the spatial frequency fs refers to the number of cycles of the grating that is sinusoidally modulated by the brightness of the image (or stimulus pattern) per degree of view, or the number of periods of the image’s brightness and darkness distribution per degree of view; the unit of spatial frequency fs It is a week/degree, the spatial frequency fs can be expressed by formula (1), and the best observation distance of the head wobble phenomenon can be expressed by formula (2).
  • r is the observation distance, that is, the distance from the user's eyes 611 to the display panel 612; l is the sub-pixel width (width in the row direction) of the display panel; n is the number of pixels in a light-dark period, ⁇ Is the viewing angle, and d ⁇ is the viewing angle per degree.
  • FIG. 2E shows the best observation distance of the moving head pattern of different types of display panels. As shown in FIG. 2E, the best viewing distance of the moving head pattern of most display panels is between 0.2 m and 0.5 m. It should be noted that the "r/m” shown in Figure 2E means that the ordinate in Figure 2E represents the observation distance r, and the unit of the observation distance r is “meters"; “HD”, “FHD” and “UHD” respectively indicate “HD”, “Full HD” and "Ultra HD”.
  • Figure 2F shows the cause of the bad head wobble.
  • the display panel displays the first frame image F1, the second frame image F2, the third frame image F3, the fourth frame image F4, the fifth frame image F5, and the Six frames of image F6, seventh frame of image F7, and eighth frame of image F8. Since the image seen by the human eye is an image obtained by superimposing and averaging multiple images that are adjacent in time, the user cannot observe the phenomenon of head shaking when the user's head remains stationary.
  • the user's head moves (for example, shaking his head), because the user may not observe part of the image of the frame (for example, the user does not observe the fourth frame image F4-sixth frame image F6), the user's eyes It may not be possible to average the observed images well. In this case, the user may observe head shaking. For example, the user's eyes cannot eliminate the brightness difference between different pixels in the same frame of display image by averaging the observed third frame image F3 and seventh frame image F7.
  • the first pixel voltage applied to the pixel electrode is greater than the common voltage Vcom
  • the second pixel voltage is less than the common voltage Vcom
  • the difference between the first pixel voltage and the common voltage Vcom The voltage difference is smaller than the voltage difference between the common voltage Vcom and the second pixel voltage, that is, the brightness of the second frame image F2, the fourth frame image F4, the sixth frame image F6, and the eighth frame image F8 is greater than that of the first frame image F1, the brightness of the third frame image F3, the fifth frame image F5, and the seventh frame image F7.
  • each display period of pixels may include adjacent first display frame F1 and second display frame F2.
  • the second display frame F2 is, for example, a reverse display frame.
  • the array The polarity of the voltage on the pixel electrode of each pixel of the substrate is opposite to the first display frame F1; both the first display frame F1 and the second display frame F2 include a voltage writing phase Tw and a voltage holding phase Th.
  • the inventors of the present disclosure noticed in their research that, without considering the voltage holding rate (VHR), the jump amount of pixel voltage ⁇ Vp has an effect on the brightness difference of adjacent display frames and the difference in the same display frame.
  • the uniformity of brightness (for example, the phenomenon of shaking head patterns) has a greater impact, especially for the display panel adopting the double-gate structure. This is because the structure of the adjacent sub-pixels of the display panel adopting the double-gate structure may be different.
  • An exemplary description is given below in conjunction with FIG. 2H.
  • FIG. 2H shows a schematic diagram of capacitances related to pixels of the display panel.
  • the capacitances related to the pixel include capacitance Cgs, capacitance Cpg, capacitance Cpg', capacitance Cpd, capacitance Cpd', capacitance Cst, and capacitance Clc.
  • the jump variable ⁇ Vp of the pixel voltage can use the following formula (3) To show.
  • the capacitance Cgs is the capacitance formed between one of the source and drain of the switching element and the gate line (and/or the gate) used to drive the switching element;
  • the capacitance Cpg is the pixel electrode and the pixel electrode used to drive the The lateral capacitance formed between the gate lines (and/or gates) of the pixel;
  • the capacitance Cpg' is formed between the pixel electrode and the gate line adjacent to the pixel electrode (not used to drive the pixel where the pixel electrode is located) Lateral capacitance;
  • capacitance Cpd is the lateral capacitance formed between the pixel electrode and the data line used to drive the pixel where the pixel electrode is located;
  • capacitance Cpd' is the pixel electrode and the data line adjacent to the pixel electrode (not used to drive the pixel
  • the capacitance Cst and the capacitance Clc are the storage capacitance of the pixel, and the
  • the inventors of the present disclosure have noticed in research that poor head wrinkles are related to the brightness difference of different sub-pixels of the same frame of image (the theoretical gray scale of different sub-pixels is the same), and the brightness difference of different sub-pixels of the same frame of image is different.
  • the jump variable ⁇ Vp of the pixel voltage of the sub-pixels is differently correlated.
  • the inventors of the present disclosure have noticed in their research that the array substrate shown in FIG. 2A may have a problem of uneven brightness (for example, the problem of moving head patterns) due to at least one of the following reasons: (1) Source and drain metal layers of the array substrate There is an offset relative to the gate metal layer; (2) the capacitance Cpg of the long-connected pixels of the array substrate is not equal to the capacitance Cpg of the short-connected pixels; (3) the capacitance Cpg' of the long-connected pixels of the array substrate is not equal to that of the short-connected pixels Capacitance Cpg'.
  • FIG. 3A is a schematic diagram of the array substrate shown in FIG. 2A;
  • FIG. 3B is an enlarged view of the area RC1 of the array substrate shown in FIG. 2A, and
  • FIG. 3C is an enlarged view of the area RC2 of the array substrate shown in FIG. 2A.
  • FIG. 3A shows a plurality of first gate lines, a plurality of second gate lines, a plurality of data lines, and a pixel unit group arranged in an array.
  • the plurality of first gate lines include gate line GL1_1, gate line GL2_1, gate line GL3_1, and gate line GL4_1
  • the plurality of second gate lines include gate line GL1_2, gate line GL2_2, gate line GL3_2, and gate line GL4_2
  • the multiple data lines include data lines DL1-DL7
  • the pixel unit group arranged in an array includes, for example, the pixel P11_1, the pixel P11_2, the pixel P12_1, the pixel P12_2, the pixel P21_1, the pixel P21_2, the pixel P22_1, and the pixel P22_2.
  • FIG. 3B is an enlarged view of the region RC1 of the array substrate shown in FIG. 2A, that is, FIG. 3B shows one of the source and drain of the switching element of the pixel P11_2 and the gate line (and/or 3C is an enlarged view of the region RC2 of the array substrate shown in FIG. 2A, that is, FIG. 3C shows one of the source and drain electrodes of the switching element of the pixel P11_1 and The overlap region 202 between the gate lines (and/or gates) of the switching element is driven.
  • the opening direction of the U-shaped electrode of the switching element of the pixel P12_1 and the pixel P12_2 (that is, the other of the source and drain of the switching element) is different from the U of the switching element of the pixel P11_1 and the pixel P11_2.
  • the opening directions of the type electrodes are the same. Therefore, when the source and drain of the switching element move to the right relative to the gate of the switching element, the capacitance Cgs of the pixel P12_2 and the pixel P12_1 and the jump amount ⁇ Vp of the pixel voltage also decrease.
  • the opening direction of the U-shaped electrode of the switching element of the pixel P21_1, the pixel P21_2, the pixel P22_1, and the pixel P22_2 is opposite to the opening direction of the U-shaped electrode of the switching element of the pixel P11_1 and the pixel P11_2,
  • the capacitance Cgs of the pixel P21_1, the pixel P21_2, the pixel P22_1, and the pixel P22_2 and the pixel voltage jump ⁇ Vp all increase.
  • the pixel P11_1 and the pixel P11_2 are all connected to the data line DL1 located in the first column
  • the pixel P12_1, the pixel P12_2, the pixel P21_1 and the pixel P21_2 are all connected to the data line DL2 located in the second column
  • the pixel P22_1 and the pixel P22_2 are all connected to the data line DL2 located in the third column; the voltages applied on the data line DL1 and the data line DL2 are opposite, and the voltages applied on the data line DL1 and the data line DL3 are the same.
  • the voltages applied to the data line DL1, the data line DL2, and the data line DL3 are positive, negative, and positive, respectively (the pixel P11_1, the pixel P11_2, the pixel P22_1, and the pixel P222 are all in the positive display frame.
  • the pixel P12_1 , Pixel P12_2, pixel P21_1, and pixel P21_2 are all in a negative display frame), and the brightness of the pixel is negatively correlated with the absolute value of the difference between the pixel voltage of the pixel and the common voltage. The brightness is dark, and the brightness of the pixels in the pixel unit group in the even-numbered column is dark.
  • a pixel in a positive display frame means that the voltage on the pixel electrode of the pixel is a positive voltage
  • a pixel in a negative display frame means that the voltage on the pixel electrode of the pixel is a negative voltage.
  • FIG. 3D is a schematic diagram of pixel voltages of pixels in a pixel unit group located in odd-numbered columns when the source and drain metal layers are not shifted (dashed line) and shifted (solid lines) relative to the gate metal layer.
  • FIG. 3E is in even-numbered columns. Schematic diagram of the pixel voltages of pixels in the pixel unit group in the case where the source and drain metal layers are not offset (dashed lines) and offset (solid lines) relative to the gate metal layers.
  • the image displayed by the display panel including the array substrate shown in FIG. 2A may have a display unevenness problem (for example, a wobbler problem).
  • the capacitance Cpg parameters that affect the pixel include the lateral pitch dpg and the effective overlap length lpg.
  • FIG. 3F shows the effective overlap length lpg1 and lateral pitch dpg1 between the combined structure of the pixel electrode and the connection part of the short-connected pixel (the first pixel, P11_1) and the gate line driving the short-connected pixel
  • FIG. 3F also shows The effective overlap length lpg2 and lateral pitch dpg2 of the combined structure of the pixel electrode and the connection part of the long-connected pixel (the second pixel, P11_2) and the gate line driving the long-connected pixel are shown.
  • the lateral pitch dpg of a pixel refers to the pixel electrode (the edge of the pixel electrode close to the gate line used to drive the pixel) and the gate line used to drive the pixel (the edge of the gate line close to the pixel electrode ).
  • the capacitance Cpg of the short-connected pixels is smaller than the capacitance Cpg of the long-connected pixels. Therefore, the jump amount of the pixel voltage of the short-connected pixels is ⁇ Vp is smaller than the jump amount ⁇ Vp of the pixel voltage of the long-connected pixel.
  • the pixel P21_1 is also a long-connected pixel.
  • FIG. 3G shows a schematic diagram of the comparison of the pixel voltages of the short-connected pixel P11_1 and the long-connected pixel P21_1 in a positive display frame and a negative display frame.
  • the short-connected pixel P11_1 in the first image frame F1, the short-connected pixel P11_1 is in the positive display frame, and the long-connected pixel P21_1 is in the negative display frame; in the second image frame F2, the short-connected pixel P11_1 is in the negative display frame, and the long-connected pixel P21_1 is in the display frame.
  • the pixel voltage Vp of the short-connected pixel P11_1 in the positive display frame increases, and the absolute value of the difference between the pixel voltage Vp and the common voltage Vcom
  • the pixel voltage Vp of the long-connected pixel P21_1 in the display frame decreases, and the absolute value
  • the pixel voltage Vp of the short-connected pixel P11_1 in the negative display frame increases, and the absolute value of the difference between the pixel voltage Vp and the common voltage Vcom
  • the pixel voltage Vp of the long-connected pixel P21_1 of the display frame decreases, and the absolute value
  • the common voltage should be increased from Vcom to Vcom_S (the optimal common voltage for the short-connected pixel P11_1); however, when only the long-connected pixel P21_1 is considered In this case, the common voltage should be reduced from Vcom to Vcom_L (the optimal common voltage for the long-connected pixel P21_1); therefore, it is difficult to adjust the common voltage to eliminate the image caused by the difference between the Cpg of the long-connected pixel and the Cpg of the short-connected pixel The phenomenon of uneven brightness (pixels in the same column are all brighter or all darker in the same image frame).
  • the capacitance Cpg' parameters that affect the pixel include the lateral pitch dpg' and the effective overlap length lpg'.
  • FIG. 3H shows a schematic diagram of the area RC1 of the array substrate shown in FIG. 2A (obtained by a scanning electron microscope)
  • FIG. 3I shows a schematic diagram of the area RC3 of the array substrate shown in FIG. 2A (obtained by a scanning electron microscope).
  • the first pixel electrode 121 and the gate line adjacent to the first pixel electrode 121 (but not used to drive the first pixel where the first pixel electrode 121 is located, that is, the second gate line 142)
  • the second direction D2 overlaps each other; as shown in FIG. 3I, the second pixel electrode 131 and the gate line adjacent to the second pixel electrode 131 (but not used to drive the second pixel where the second pixel electrode 131 is located, also That is, the second gate lines 142) overlap each other in the second direction D2.
  • the second pixel electrode 131 shown in FIG. 3I and the first pixel electrode 121 shown in FIG. 3H are located in two different pixel unit groups (in the second direction D2 (2)
  • the second pixel electrode 131 in the same pixel unit group as the first pixel electrode 121 shown in FIG. below the adjacent gate line therefore, before charging the pixel where the second pixel electrode 131 in the same pixel unit group as the first pixel electrode 121 shown in FIG.
  • the scanning of the adjacent gate line has ended. Therefore, the charging process of the second pixel electrode 131 located in the same pixel unit group as the first pixel electrode 121 shown in FIG. 3H is not affected (or greatly affected) by the adjacent gate line. small).
  • the distance between the first pixel electrode 121 and the gate line adjacent to the first pixel electrode 121 (for example, the second gate line 142) in the second direction D2 may be regarded as the lateral pitch dpg1 '
  • the pitch of the second pixel electrode 131 and the gate line adjacent to the second pixel electrode 131 (for example, the second gate line 142) in the second direction D2 may be regarded as the lateral pitch dpg2'.
  • the effective overlap length lpg1' between the first pixel electrode 121 and the gate line adjacent to the first pixel electrode 121 refers to the gate line adjacent to the first pixel electrode 121 Corresponds to the length in the first direction D1 of the region with the lateral pitch less than or equal to the predetermined pitch (for example, less than or equal to the lateral pitch dpg1'); between the second pixel electrode 131 and the gate line adjacent to the second pixel electrode 131
  • the effective overlap length lpg2' means that the region of the gate line adjacent to the second pixel electrode 131 corresponding to the lateral pitch dpg2' is less than or equal to a predetermined pitch (for example, less than or equal to the lateral pitch dpg2') in the first direction D1 length.
  • the array substrate has a pre-charging function, and the capacitance Cpg' will cause pixels (for example, pixels with odd rows of gate lines)
  • the pixel voltage is further reduced, which will be exemplified below in conjunction with FIG. 3J.
  • Fig. 3J is a schematic diagram of the influence of the capacitance Cpg' on the pixel voltage Vp.
  • Vgate1 is the gate line in the odd-numbered row
  • Vgate2 is the gate line in the even-numbered row
  • Vp is the pixel voltage of the pixel in the even-numbered row.
  • the pixel voltage Vp of the pixel has an additional increment due to the influence of the capacitor Cpg', but because the pixel is in the charging stage at this time, Therefore, the above additional increment will be removed.
  • the inventor of the present disclosure has noticed in research that the capacitance Cgs of the long-connected pixel and the capacitance Cgs of the short-connected pixel are closer and/or the capacitance Cpg of the long-connected pixel is closer to the capacitance Cpg of the short-connected pixel.
  • the pixel voltage jump ⁇ Vp of the long-connected pixels is closer to the pixel voltage jump ⁇ Vp of the short-connected pixels, which can reduce the display unevenness (for example, the shaking head phenomenon).
  • FIG. 4A The following is an exemplary description with reference to FIG. 4A.
  • FIG. 4A is a schematic plan view of another array substrate 100 provided by at least one embodiment of the present disclosure.
  • the array substrate 100 shown in FIG. 4A and the array substrate shown in FIG. 2A include the following differences: (1) As shown in FIG. 4A The array substrate 100 has Cgs compensation capability; (2) the pixel electrode of the long-connected pixel of the array substrate 100 shown in FIG. 4A has a recess on the side close to the gate line driving the long-connected pixel; (3) as shown in FIG. 4A The first via hole and the second via hole of the array substrate 100 are different from the first via hole and the second via hole of the array substrate 100 shown in FIG. 2A; (4) the common electrode pattern of the array substrate 100 shown in FIG. 4A It is different from the common electrode pattern of the array substrate 100 shown in FIG. 2A.
  • the difference between the array substrate provided by other embodiments of the present disclosure and the array substrate shown in FIG. 2A may only include the above-mentioned four different parts (for example, any combination of one or more). Repeat.
  • FIG. 4A the array substrate 100 shown in FIG. 4A will be exemplarily described in conjunction with FIGS. 4A to 4E, 5A to 5H, and FIGS. 6 to 11.
  • the array substrate 100 includes a plurality of pixel unit groups 110, a plurality of first gate lines 141, a plurality of second gate lines 142, and a plurality of data lines 161 arranged in an array; a plurality of first gate lines
  • the plurality of second gate lines 141 and the plurality of second gate lines 142 respectively extend substantially along the first direction D1, and the plurality of data lines 161 substantially extend along the second direction D2 that crosses (eg, is perpendicular to) the first direction D1.
  • Each row of pixel unit group 110 is driven by two gate lines, and the above two gate lines (one first gate line 141 and one second gate line 142) are located on both sides of the row of pixel unit group 110 in the second direction D2 And it is adjacent to the row of pixel unit group 110.
  • the gate line is adjacent to the pixel unit group 110 means that no other gate lines are included between the pixel unit group 110 and the aforementioned gate line.
  • Two gate lines are arranged between two adjacent pixel unit groups 110 in the second direction D2, and a data line is arranged between two adjacent pixel unit groups 110 in the first direction D1. The following is an exemplary description with reference to FIG. 4A.
  • each row of the pixel unit group 110 corresponds to one of the plurality of first gate lines 141 and one of the plurality of second gate lines 142, and one of the plurality of first gate lines 141 and a plurality of One of the second gate lines 142 is located on both sides of the row of pixel unit groups 110 in the second direction D2, and is configured to drive the row of pixel unit groups 110.
  • one first gate line 141 and one second gate line 142 are arranged between adjacent pixel unit groups 110 in the column direction (that is, the second direction D2).
  • the gate line 141 and a second gate line 142 are respectively used to drive the pixel unit group 110 in adjacent rows.
  • the plurality of first gate lines 141 and the plurality of second gate lines 142 are configured to drive the pixel unit group 110 adjacent thereto (that is, there is no other pixel unit group 110 between the gate line and the pixel unit group 110 driven by the gate line).
  • Grid line As shown in FIG. 4A, one data line 161 is arranged between adjacent pixel unit groups 110 in the row direction (ie, the first direction D1). As shown in FIG. 4A, the plurality of first gate lines 141 and the plurality of second gate lines 142 are alternately arranged in the second direction D2.
  • the plurality of first gate lines 141 and the plurality of second gate lines 142 respectively extend substantially along the first direction D1 and only define the extension direction of the length of the first gate line 141 and the second gate line 142, and It does not mean that the first gate line 141 and the second gate line 142 are parallel to the first direction D1, that is, according to actual application requirements, the first gate line 141 and the second gate line 142 may be parallel to the first direction D1 or may be The part is not parallel to the first direction D1.
  • the partial areas of the plurality of first gate lines 141 and the plurality of second gate lines 142 may be designed in a bent form.
  • the data line 161 may be parallel to the second direction D2 or partly not parallel to the second direction D2.
  • FIG. 4B is a schematic plan view of the pixel unit group 110 of the array substrate 100 shown in FIG. 4A.
  • FIG. 4B also shows the first gate line 141, the second gate line 142, and the data line 161.
  • Part or all of the pixel unit groups 110 of the array substrate 100 shown in FIG. 4A may be implemented as the pixel unit groups 110 shown in FIG. 4B.
  • the pixel unit group 110 includes a first pixel and a second pixel that are arranged next to each other in the first direction D1. It should be noted that the first pixel and the second pixel that are arranged next to each other in parallel means that no other pixels are included between the first pixel and the second pixel.
  • the first pixel includes a first pixel electrode 121, a first switching element 123, and a first connection portion 122 extending and protruding from the first pixel electrode 121
  • the second pixel includes a second pixel electrode 131, a second switch
  • the element 133 and the second connection portion 132 extending and protruding from the second pixel electrode 131; the first pixel electrode 121 and the first switching element 123 are electrically connected to each other via the first connection portion 122, and the second pixel electrode 131 and the second switching element 133
  • the second connecting portion 132 is electrically connected to each other; the extension length of the first connecting portion 122 is not equal to (for example, less than) the extension length of the second connecting portion 132.
  • both the first switching element 123 and the second switching element 133 can be arranged in the pixel unit group 110.
  • the edge in the first direction D1 will be exemplified below with reference to FIG. 4B.
  • the pixel unit group 110 includes a first edge 111 and a second edge 112 opposite to each other in the first direction D1.
  • the first switching element 123 and the second switching element 133 Both are closer to the first edge 111 of the pixel unit group 110 in the first direction D1.
  • the first switching element 123 and the second switching element 133 of each pixel unit group 110 are both connected to the same data line 161.
  • the distances between the first switching element 123 and the second switching element 133 of each pixel unit group 110 and the same data line 161 are the same.
  • the switching elements connected to the same data line 161 include the switching element located on the first side (for example, the left side) of the same data line 161 and the second switching element located on the same data line 161.
  • the switching elements partially overlap in the first direction D1.
  • the switching elements located on the first side (for example, the left side) of the same data line 161 and the switching elements located on the second side (for example, the right side) of the same data line 161 move in the first direction D1
  • the size of the array substrate 100 increases the aperture ratio of the array substrate 100 and the display panel and the display device including the array substrate 100.
  • the first connection portion 122 and the second connection portion 132 of the pixel unit group 110 are respectively located on both sides of the first pixel electrode 121 in the second direction D2; the first connection portion 122 and the second connection portion The portions 132 are located between the first gate line 141 and the second gate line 142 in the second direction D2.
  • the extending direction of the first connecting portion 122 is the second direction D2
  • the extending direction of the second connecting portion 132 is the first direction D1; in the second direction D2, the second connecting The portion 132 at least partially overlaps the first pixel electrode 121; in the second direction D2, the first pixel electrode 121 is located between the first switching element 123 and the second switching element 133.
  • the first switching element 123 and the second switching element 133 are symmetrical with respect to the first pixel electrode 121 (or of the pixel unit group 110) in the second direction D2 and along the first direction D1.
  • Settings see also Figure 4D below).
  • first connecting portion 122 and the first pixel electrode 121 are integrally formed using the same material
  • second connecting portion 132 and the second pixel electrode 131 are integrally formed using the same material
  • the same film layer may be patterned to form the first connection portion 122, the first pixel electrode 121, the second connection portion 132, and the second pixel electrode 131 using the same patterning process.
  • the first switching element 123 and the second switching element 133 are integrally formed using the same edge (for example, the first edge 111) of the pixel unit group 110 in the first direction D1
  • the first connecting portion 122 and the first pixel electrode 121 are integrally formed using the same material
  • the second connection portion 132 and the second pixel electrode 131 are integrally formed using the same material, so that the first connection portion 122 (the first end 1221 of the first connection portion 122 6) is directly electrically connected to the first pixel electrode 121, and makes the second connecting portion 132 (the first end 1321 of the second connecting portion 132, also see FIG. 6 below) and the second The pixel electrode 131 is directly electrically connected.
  • the first connection portion 122 (the second end 1222 of the first connection portion 122) is electrically connected to the first switching element 123 through the first via 1223
  • the second connection portion 132 (The second end 1322 of the second connecting portion 132) is electrically connected to the second switching element 133 through the second via 1323, but since the first via 1223 is close to the first switching element 123, the second via 1323 is close to the second switch
  • the element 133, and the area close to the first switching element 123 and the second switching element 133 originally corresponds to the area blocked by the black matrix. Therefore, the first via 1223 and the second via 1323 shown in FIG. 4B will not decrease The aperture ratio of the pixel unit group 110 and the array substrate 100.
  • both the first pixel electrode 121 and the second pixel electrode 131 may be formed of a transparent conductive material.
  • the transparent conductive material is indium tin oxide (ITO) or indium zinc oxide (IZO).
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • the first connection portion 122 and the second connection portion 132 can also be formed using a transparent conductive material (for example, ITO).
  • the processing accuracy of the transparent conductive material is higher than the processing accuracy of the metal material, that is, the line width of the transparent conductive material trace can be smaller than the line width of the metal material trace; in this case, the first connection
  • the size of the area occupied by the portion 122 and the second connection portion 132 can be reduced, and the size of the area occupied by the first pixel electrode 121 and the second pixel electrode 131 can be increased correspondingly, thereby improving the pixel unit group 110 and the array substrate 100. Opening rate.
  • the switching elements connected to the same data line and located on the right side of the same data line are all used to drive pixel unit groups in odd rows (or even rows); connected to the same data line , And the switching elements located on the left side of the same data line are all used to drive the pixel unit groups of even rows (or odd rows).
  • the first switching element 123 and the second switching element 133 for driving each pixel unit group are arranged in the first direction on the edge of the pixel unit group where the short-connected pixels are arranged.
  • the first switching element 123 and the second switching element 133 of the pixel unit group located in odd rows (or even rows) are both arranged on the left side of the pixel unit group, located in even rows (or odd rows).
  • the first switching element 123 and the second switching element 133 of the pixel unit group are both arranged on the right side of the pixel unit group.
  • the first switching element 123 and the second switching element 133 are both thin film transistors (TFT).
  • TFT thin film transistors
  • the first switching element 123 and the second switching element 133 are both U-shaped thin film transistors, that is, the source (or drain) of the thin film transistor is a U-shaped electrode, and the thin film transistor At least part of the drain (or source) is arranged in the opening of the U-shaped electrode; the source and drain of the U-shaped thin film transistor at least partially overlap in the second direction D2.
  • the opening directions of the U-shaped TFTs used to drive adjacent rows are opposite.
  • the opening direction of the U-shaped TFT for driving the first row is rightward
  • the opening direction of the U-shaped TFT for driving the second row is leftward.
  • the array substrate 100 may include a first electrode layer 172 (see FIG. 4C), a first insulating layer 173 (see FIG. 5C), a semiconductor layer 174 (see FIG. 5A and FIG. 5C), and a second electrode layer 175 (see FIG. 5C).
  • the second insulating layer 176 (see FIG. 5C) and the third electrode layer 177 (see FIG. 6) the above-mentioned first electrode layer 172, first insulating layer 173, semiconductor layer 174, second electrode layer 175, second The insulating layer 176 and the third electrode layer 177 are sequentially disposed on the base substrate 171, for example.
  • the first electrode layer 172 includes a plurality of first gate lines 141, a plurality of second gate lines 142, and a common electrode pattern 150 arranged in an array; a plurality of first gate lines 141 and a plurality of second gate lines The lines 142 are alternately arranged in the second direction D2; the multiple common electrode patterns 150 correspond to the multiple pixel unit groups 110 one-to-one; the multiple common electrode patterns 150 located in the same row are located for driving multiple common electrode patterns in the same row. Between the first gate line 141 and the second gate line 142 of the pixel unit group 110 corresponding to the electrode pattern 150. It should be noted that, in some examples, the first electrode layer 172 may not include the common electrode pattern.
  • FIG. 4D shows a schematic plan view of the first gate line 141 and the second gate line 142 of the array substrate shown in FIG. 4A.
  • the first gate line 141 used to drive each pixel unit group 110 is used to drive the pixel unit group 110 adjacent to each pixel unit group 110 in the second direction D2.
  • the second gate line 142 partially overlaps in the first direction D1, that is, the first gate line 141 and the second gate line 142 located between the adjacent pixel unit groups 110 in the second direction D2 are in the first direction D1.
  • the direction D1 partially overlaps, thereby reducing the size of the area occupied by the gate line in the second direction D2, thereby increasing the aperture ratio of the array substrate 100 and the aperture ratio of the display panel and the display device including the array substrate 100 .
  • the first gate line 141 and the second gate line 142 are symmetrically arranged with respect to the center line 113 of the pixel unit group 110 in the second direction D2 extending along the first direction D1.
  • FIG. 4E shows a schematic plan view of a portion of the first gate line 141 and the second gate line 142 of the array substrate shown in FIG. 4A corresponding to one pixel unit group 110.
  • the first gate line 141 includes a first gate portion 1411
  • the second gate line 142 includes a second gate portion 1421.
  • the first gate portion 1411 is configured as the gate of the first switching element 123
  • the second gate portion 1421 is configured as the gate of the second switching element 133, that is, the U-shaped electrode of the first switching element 123.
  • the orthographic projection of the (source or drain) on the first electrode layer 172 at least partially overlaps the first gate portion 1411, and the U-shaped electrode (source or drain) of the second switching element 133 is on the first electrode layer 172.
  • the orthographic projection on it at least partially overlaps with the second grid portion 1421.
  • the first gate portion 1411 used to drive the first gate line 141 of each pixel unit group 110 and the first gate portion 1411 used to drive the first gate line 141 adjacent to each pixel unit group 110 in the second direction D2 The second gate portion 1421 of the second gate line 142 of the pixel unit group 110 partially overlaps in the first direction D1, thereby reducing the size of the area occupied by the gate line in the second direction D2, thereby improving the array
  • the aperture ratio of the substrate 100 and the aperture ratio of the display panel and the display device including the array substrate 100 For example, the corresponding gate portions of two gate lines (the first gate line 141 and the second gate line 142) located between adjacent pixel unit groups 110 in the second direction D2 partially overlap in the first direction D1 .
  • the first gate line 141 further includes a first line portion 1412, a first line connection portion 1413, and a third line portion 1414 that are sequentially connected;
  • the second gate line 142 also includes a second line that is sequentially connected A portion 1422, a second wire connecting portion 1423, and a fourth wire portion 1424;
  • the first wire portion 1412 is connected to the first grid portion 1411, and the second wire portion 1422 is connected to the second grid portion 1421.
  • the first wire connecting portion 1413 includes a first protrusion 143 protruding toward the first gate portion 1411
  • the second wire connecting portion 1423 includes a second protrusion protruding toward the second gate portion 1421. From 144.
  • the first line portion 1412, the second line portion 1422, the third line portion 1414, and the fourth line portion 1424 are respectively parallel to the first direction D1.
  • first recessed structure 211 between the gate portions and the line connecting portions that are located on the same gate line and correspond to different pixel unit groups and are adjacent to each other, which is the same as the above
  • the line connecting portions of the gate lines adjacent to the gate lines are arranged in the first recess structure 211 described above.
  • each gate line can simultaneously drive the short-connected pixels and the long-connected pixels. Therefore, each gate line can include the first gate portion 1411, the first line portion 1412, and the first The wire connection portion 1413, the third wire portion 1414, the second gate portion 1421, the second wire portion 1422, the second wire connection portion 1423, and the fourth wire portion 1424.
  • the gate portion and the line connection portion of the gate line corresponding to the same pixel unit group 110 are arranged side by side in the first direction and form a second recess structure 212, which is driven by the gate line
  • the pixel via (for example, the first via or the second via) is located in the second recess structure 212.
  • the array substrate 100 provided by at least one embodiment of the present disclosure is not limited to that each of the plurality of first gate lines 141 and the plurality of second gate lines 142 adopts the structure shown in FIG. 4D, according to actual application requirements. It is also possible to make the parts of the plurality of first gate lines 141 and the plurality of second gate lines 142 adopt the structure shown in FIG. 4D, and the remaining parts of the plurality of first gate lines 141 and the plurality of second gate lines 142 may Other suitable gate line structures (for example, straight gate lines) are used, and the details are not repeated here.
  • suitable gate line structures for example, straight gate lines
  • first wire connection portion 1413 may not include the first protrusion 143 and the second wire connection portion 1423 may not include the second protrusion 144.
  • the second electrode layer 175 includes a plurality of data lines 161, a plurality of first source and drain layers arranged in parallel, and a plurality of second source and drain layers arranged in parallel;
  • the second source and drain layer includes a second switch One of the two second source and drain electrodes 1341 of the element 124 and the other 1343 of the two second source and drain electrodes of the second switching element 124 (for example, U-shaped electrodes).
  • first source-drain layer and the second source-drain layer are located in different regions of the same layer, and the first source-drain layer and the second source-drain layer are spaced apart in a direction perpendicular to the base substrate, and the same patterning can be used
  • the process patterns the same film layer (for example, a single film layer) to form a first source drain layer and a second source drain layer.
  • FIG. 5B is a schematic plan view of the first switching element 123 of the array substrate shown in FIG. 4A (an image obtained by a scanning electron microscope image). For ease of description, FIG. 5B also shows a part of the first gate line 141 and a part of the first pixel The electrode 121 and the first via hole 1223.
  • 5C is a schematic cross-sectional view of the array substrate 100 obtained by cutting along the AA' line shown in FIG. 5B.
  • FIG. 5D is a schematic plan view of the second switching element 133 provided by at least one embodiment of the present disclosure.
  • the first switching element 123 in a direction perpendicular to the base substrate 171, includes a first gate portion 1411 (as the gate of the first switching element 123, the first insulating layer 173 , The semiconductor layer 174 (first semiconductor layer 125) and a first source and drain layer; the first source and drain layer includes two first source and drain electrodes (that is, one of the two first source and drain electrodes 1241) opposite to each other and separately arranged And the other 1243 of the two first source and drain, for example, when the first switching element 123 is in the off state, the two first source and drain are insulated from each other).
  • the semiconductor layer 174 includes a first semiconductor layer 125 (a region of the semiconductor layer 174 corresponding to the first switching element) and a second semiconductor layer (a region of the semiconductor layer 174 corresponding to the second switching element).
  • first semiconductor layer 125 and the second semiconductor layer are located in different regions of the same layer, and the first semiconductor layer 125 and the second semiconductor layer are spaced apart in a direction perpendicular to the base substrate, and the same patterning process can be used to The same film layer (for example, a single film layer) is patterned to form the first semiconductor layer 125 and the second semiconductor layer.
  • the second switching element 133 includes a second gate portion 1421 (as a gate of the second switching element 133, a first insulating layer 173, a semiconductor layer 174 (a second semiconductor layer) ) And a second source-drain layer.
  • the second source-drain layer includes two second source and drain electrodes (that is, one of the two second source and drain electrodes 1341 and two The other 1343 of the two source and drain, for example, when the second switching element 133 is in the off state, the two second source and drain are insulated from each other).
  • the array substrate 100 further includes a second insulating layer 176, a third electrode layer 177, and a first via hole 1223 and a second via hole 1323 provided in the second insulating layer 176.
  • FIG. 6 is a schematic plan view of the third electrode layer 177 of the array substrate 100 shown in FIG. 4A.
  • 7 is a schematic plan view of the first electrode layer 172, the semiconductor layer 174, and the second electrode layer 175 of the array substrate 100 shown in FIG. 4A, and
  • FIG. 8 is the first via hole 1223, the second electrode layer 175 of the array substrate 100 shown in FIG. 4A
  • the third electrode layer 177 includes a first pixel electrode 121, a first connection portion 122, a second pixel electrode 131, a second connection portion 132 and a second common electrode connection portion 152.
  • the first connecting portion 122 includes a first end 1221 and a second end 1222.
  • the first end 1221 of the first connecting portion 122 is directly electrically connected to the first pixel electrode 121.
  • the second end 1222 of a connecting portion 122 is electrically connected to one of the two first source and drain electrodes 1241 through the first via hole 1223.
  • the first via 1223 is a half via, that is, one of the two first source and drain 1241 only covers a part of the opening area of the first via 1223; as shown in FIGS. 5B and As shown in FIG.
  • another part of the opening area of the first via hole 1223 is located on the side of one of the two first source and drain electrodes 1241 close to the first pixel electrode 121, and is directly covered by the first pixel electrode 121, that is, , The bottom of another part of the opening area of the first via hole 1223 directly contacts the first pixel electrode 121.
  • the second connecting portion 132 includes a first end 1321 and a second end 1322.
  • the first end 1321 of the second connecting portion 132 is directly electrically connected to the second pixel electrode 131, and the second connecting portion
  • the second end 1322 of the 132 is electrically connected to one of the second source and drain 1341 through the second via 1323; as shown in FIG. 5D, the one of the second source and drain 1341 covers a portion 1324 of the opening area of the second via 1323.
  • the other part 1325 of the opening area of the second via 1323 is located on one side of the second source and drain 1341 close to the first pixel electrode 121, and is directly covered by the second pixel electrode 131, that is, the second via
  • the bottom of the other part 1325 of the opening area 1323 is in direct contact with the second pixel electrode 131.
  • first via 1223 and the second via 1323 is not limited to the arrangement shown in FIGS. 5B and 5C. According to actual application requirements, the first via 1223 and the second via 1323 can also be selected Other applicable setting methods. An exemplary description will be given below in conjunction with the array substrate 100 shown in FIG. 2A.
  • Fig. 5E shows a schematic plan view of a partial area of the array substrate 100 shown in Fig. 2A
  • Fig. 5F is a schematic plan view of the area RC4 of the array substrate 100 shown in Fig. 5E (obtained by a scanning electron microscope).
  • the first via hole 1223 and the second via hole 1323 of the array substrate 100 shown in FIG. 2A are also half via holes, that is, the two second via holes of the first switching element 123
  • One of the source and drain electrodes 1241 (for example, the first drain) covers only a part 1224 of the opening area of the first via hole 1223; one of the two second source and drain electrodes 1341 (for example, the second The drain) only covers a part 1324 of the opening area of the second via 1323.
  • the other part 1225 of the opening area of the first via hole 1223 is located on the side of one of the two first source and drain electrodes 1241 away from the first pixel electrode 121, and the opening of the second via hole 1323
  • the other part 1325 of the region is located on one side of the second source and drain electrodes 1341 away from the first pixel electrode 121.
  • the first wire connection portion 1413 may also include a first protrusion
  • the second wire connection portion 1423 may also include a second protrusion; however, in this case, If the positions of the first protrusion and the second protrusion are offset, the additional first protrusion may be electrically connected (short-circuited) with the first pixel electrode through the first via hole, and the additional second protrusion may It is electrically connected (short-circuited) with the second pixel electrode through the second via hole. Therefore, compared with the structure of the first via hole 1223 shown in FIGS. 5E and 5F, another part 1225 of the opening area of the first via hole 1223 shown in FIGS. 5B and 5C is provided in the two first sources.
  • the side of one of the drain electrodes 1241 away from the first pixel electrode 121 can reduce the risk of short circuit between the first protrusion 143 of the array substrate shown in FIG. 5B and FIG. 5C and the first connection portion 122, as shown in FIG. 5F
  • the other part 1325 of the opening area of the second via hole 1323 is arranged on the side of the second source and drain electrode 1341 away from the first pixel electrode 121, which can reduce the second protrusion of the array substrate shown in FIGS. 5B and 5C. This raises the risk of short circuit between 144 and the second connecting portion 132.
  • the orthographic projection of the first gate line 141 on the second conductive layer overlaps with one of the two first source and drain electrodes 1241 at least at two different positions; for example, As shown in FIG. 5B, the orthographic projection of the first gate line 141 on the first source/drain layer at least partially overlaps two sides of one of the two first source/drain 1241 in the first direction D1.
  • the first gate line 141 on the first source and drain layer at least partially overlap the two sides of one of the two first source and drain electrodes 1241 in the first direction D1, the first gate line can be reduced.
  • the magnitude of the change in the value of the capacitance formed between the first gate line and the first source-drain layer; since the magnitude of the change in the value of the capacitance formed between the first gate line and the first source-drain layer is positively correlated with the shaking head pattern, by reducing The magnitude of the change in the value of the capacitance formed between the first gate line and the first source-drain layer can suppress and avoid the moving head pattern caused by the offset of the mask used to make the second electrode layer 175 relative to the first electrode layer 172. bad.
  • the following embodiments refer to the first source and drain connected to the data line 161 as the first source and the second source, respectively, and the first source and drain connected to the pixel electrode And the second source and drain are respectively referred to as the first drain and the second drain; however, the embodiment of the present disclosure is not limited to this; in other embodiments, the first source and drain connected to the data line 161
  • the two source and drain electrodes may be called a first drain and a second drain, respectively, and the first source and drain connected to the pixel electrode are called a first source and a second source, respectively.
  • FIG. 5G is the first schematic diagram of the overlap region between the electrode layer where the gate line is located and the electrode layer where the source and drain are located in the orthographic projection of the electrode layer where the gate line is located on the array substrate shown in FIG. 4A (corresponding to the first A switching element);
  • FIG. 5H is the second overlap area between the electrode layer where the gate line of the array substrate is shown in FIG. 4A and the electrode layer where the source and drain are located in the orthographic projection of the electrode layer where the gate line is located Schematic diagram (corresponding to the second switching element).
  • the orthographic projection of the first gate line 141 (the first gate portion 1411 of the first gate line 141) on the first source-drain layer and the first drain near the first source one
  • the orthographic projection of the first gate line 141 (the first line connection portion 1413 of the first gate line 141) on the first source-drain layer is also the same as that of the first drain.
  • the area on the side far from the first source (for example, the right side) overlaps.
  • the orthographic projection of the first bump 143 on one of the two first source and drain electrodes 1241 (e.g., the first drain) and one of the two first source and drain electrodes 1241 (e.g., the The first drain) at least partially overlaps, and the orthographic projection of the first bump 143 on one of the two first source and drain 1241 (for example, the first drain) and one of the two first source and drain 1241 ( For example, the overlapping area of the first drain) is the first overlapping area 145.
  • the overlapping area between the orthographic projection of the first gate portion 1411 on the first drain and the first drain is the second overlapping area 146.
  • the size of the first overlapping area 145 increases, and the second overlapping area
  • the size of 146 is reduced; when the first source-drain layer is shifted to the left relative to the first electrode layer 172 (for example, the first gate portion 1411), the size of the first overlap region 145 is reduced, and the second overlap region 146 Therefore, compared with the example in which the first overlap region 145 is not provided, by providing the first overlap region 145, the value of the capacitance (Cgs1) formed between the gate line and the first source-drain layer can be reduced The amplitude of the change (due to the offset of the first source/drain layer with respect to the first electrode layer 172), which can suppress the wobble defects of the display panel and the display device including the array substrate 100.
  • the first overlap area 145 has a first overlap edge 1451 in a second direction D2 that crosses the first direction D1
  • the second overlap area 146 has a first overlap edge 1451 that crosses the first direction D1.
  • the second overlapping edge 1461 in the two directions D2, and the length of the first overlapping edge 1451 and the length of the second overlapping edge 1461 are equal; in this case, the gate line and the first source drain layer can be further reduced
  • the magnitude of the change in the value of the formed capacitance (Cgs1) (due to the offset of the first source and drain layer relative to the first electrode layer 172) and the magnitude of the change in the pixel voltage jump of the first pixel.
  • the orthographic projection of the second gate line 142 on the second source and drain layer overlaps with one of the two second source and drain electrodes 1341 in at least two different positions; the second gate line 142 The orthographic projection on the second source and drain layer at least partially overlaps the two sides of one of the two second source and drain electrodes 1341 in the first direction D1.
  • the orthographic projection of the second gate line 142 (the second gate portion 1421 of the second gate line 142) on the second source-drain layer and the second drain near the second source one Except for the overlap of the area on the side, the orthographic projection of the second gate line 142 (the second line connecting portion 1423 of the second gate line 142) on the second source-drain layer and the second drain on the side away from the second source Regions overlap.
  • the orthographic projection of the second protrusion 144 on one of the second source and drain electrodes 1341 (for example, the second drain) and one of the second source and drain electrodes 1341 (for example, the second drain ) At least partially overlapped, the orthographic projection of the second protrusion 144 on one of the second source and drain electrodes 1341 (for example, the second drain) and one of the two second source and drain electrodes 1341 (for example, the second drain
  • the overlapping area of) is the third overlapping area 147.
  • the overlapping area between the orthographic projection of the second gate portion 1421 on the second drain and the second drain is the fourth overlapping area 148.
  • the change in the value of the capacitance (Cgs2) formed between the gate line and the second source-drain layer can be reduced (due to The second source/drain layer is shifted relative to the first electrode layer 172 and caused by the amplitude of), which can suppress the wobble defects of the display panel and the display device including the array substrate 100.
  • the third overlap area 147 has a third overlap edge 1471 in a second direction D2 that crosses the first direction D1
  • the fourth overlap area 148 has a second direction D2 that crosses the first direction D1.
  • the length of the fourth overlapping edge 1481, the length of the third overlapping edge 1471 and the length of the fourth overlapping edge 1481 are equal; in this case, the formation between the gate line and the second source-drain layer can be further reduced
  • the magnitude of the change in the value of the capacitance (Cgs2) (due to the offset of the second source and drain layer relative to the first electrode layer 172) and the magnitude of the change in the pixel voltage jump of the second pixel.
  • the planar shape of the first overlapping area 145, the planar shape of the second overlapping area 146, the planar shape of the third overlapping area 147, and the planar shape of the fourth overlapping area 148 are all substantially rectangular.
  • the size of the first overlapping area 145 in the second direction D2 is equal to the size of the second overlapping area 146 in the second direction D2
  • the size of the third overlapping area 147 in the second direction D2 is equal to the fourth overlapping area
  • the first semiconductor layer 125 disposed between the first gate portion 1411 and the first drain may be taken into consideration, that is, The overlapping area between the orthographic projection of the combined structure of the first drain and the first semiconductor layer 125 on the first gate portion 1411 and the first gate portion 1411 serves as the second overlapping area 146; correspondingly, the fourth When the region 148 is overlapped, the orthogonal projection of the combined structure of the second drain electrode and the second semiconductor layer on the second gate portion 1421 and the overlap region of the second gate portion 1421 may be used as the fourth overlap region 148.
  • the overlap area between the orthographic projection of the first gate line 141 on the first source and drain layer and one of the two first source and drain electrodes 1241 is the first value
  • the second gate line 142 is on the second source and drain layer.
  • the overlap area between the orthographic projection and one of the two second source and drain electrodes 1341 is the second value
  • the first value is equal to the second value; in this case, the capacitance formed between the gate line and the first source and drain layer ( Cgs1) and the capacitance (Cgs2) formed between the gate line and the second source-drain layer are equal to each other, and the pixel voltage jump amount of the first pixel and the pixel voltage jump amount of the second pixel are relatively close (for example, equal), by This can further suppress the wobble defects of the display panel and the display device including the array substrate 100.
  • FIG. 9 shows a schematic diagram of the pitch and the overlap length between a pixel electrode and a gate line driving a pixel where the pixel electrode is located according to at least one embodiment of the present disclosure.
  • the lateral distance dpg1 between the first pixel electrode 121 and the gate line for driving the first pixel is the distance between the first pixel electrode 121 and the gate line for driving the first pixel (for example, the first pixel electrode 121 shown in FIG.
  • the pitch dpg2 is the pitch between the edge of the second pixel electrode 131 close to the gate line for driving the second pixel and the gate line for driving the second pixel.
  • the distance between the third electrode layer 177 where the first pixel electrode 121 is located and the first electrode layer 172 where the gate line for driving the first pixel is located is small
  • the distance between the first pixel electrode 121 and the gate line for driving the first pixel (for example, the first gate line 141 shown in FIG. 9) in the second direction D2 may be taken as the lateral pitch dpg1
  • the distance between the second pixel electrode 131 and the gate line for driving the second pixel (for example, the second gate line 142 shown in FIG. 9) in the second direction D2 is taken as the lateral pitch dpg2.
  • the horizontal pitches of other embodiments of the present disclosure have similar definitions, and will not be repeated.
  • the effective overlap length between the combined structure of the first pixel electrode 121 and the first connecting portion 122 and the gate line driving the first pixel means that the horizontal pitch dpg1 of the gate line driving the first pixel is less than or equal to
  • the length of a region with a predetermined pitch (for example, six microns) in the first direction D1; the effective overlapping length of the combination structure of the second pixel electrode 131 and the second connection portion 132 and the gate line for driving the second pixel refers to the driving of the second pixel
  • the length in the first direction D1 of the region of the gate line of the two pixels corresponding to the lateral pitch dpg2 being less than or equal to the predetermined pitch (for example, six microns).
  • the lateral distance between the first pixel electrode 121 and the gate line for driving the first pixel is greater than five microns
  • the lateral distance between the second pixel electrode 131 and the gate line for driving the second pixel is greater than five microns.
  • the inventors of the present disclosure have obtained through many experiments and analyses that by making the lateral distance between the first pixel electrode 121 and the gate line driving the first pixel greater than five microns, the influence of the following factors on the capacitance Cpg of the first pixel can be reduced:
  • the change in the lateral distance between the first pixel electrode 121 and the gate line driving the first pixel for example, the change caused by the manufacturing process
  • Variation of the overlap length by making the lateral distance between the second pixel electrode 131 and the gate line driving the second pixel greater than five microns, the influence of the following factors on the capacitance Cpg of the second pixel can be reduced:
  • the extension length of the first connection portion 122 is smaller than the extension length of the second connection portion 132, and the combination structure of the first pixel electrode and the first connection portion effectively overlaps the first gate line.
  • the length is smaller than the effective overlapping length of the second gate line and the combined structure of the second pixel electrode and the second connection part, and the second pixel electrode 131 has a recessed part on the side close to the gate line for driving the second pixel.
  • the combination structure and the gate of the pixel electrode and the connecting portion of the long-connected pixel can be shortened.
  • the effective overlap length of the line is lpg; in this case, the effective overlap length of the long-connected pixel electrode and the connecting portion of the combined structure and the gate line is the same as the short-connected pixel (for example, the first pixel).
  • the combination structure of, and the effective overlap length of the gate line are closer, therefore, the capacitance Cpg of the long-connected pixel and the capacitance Cpg of the short-connected pixel can be made closer, thereby further suppressing the wobble defect.
  • the effective overlapping length of the combination structure of the first pixel electrode 121 and the first connection portion 122 and the gate line for driving the first pixel is equal to the combination structure of the second pixel electrode 131 and the second connection portion 132 and the drive second
  • the effective overlap length of the gate lines of the two pixels can further suppress the wobble defect.
  • the first pixel electrode 121 and the gate line adjacent to the first pixel electrode 121 overlap each other in the second direction D2
  • the two pixel electrodes 131 and the gate line adjacent to the second pixel electrode 131 overlap each other in the second direction D2.
  • the gate line adjacent to the second pixel electrode 131 when the gate line adjacent to the second pixel electrode 131 is located above the second pixel electrode 131, the gate line adjacent to the second pixel electrode 131 has a greater influence on the charging process of the second pixel electrode 131. There is little or no effect. Therefore, the second pixel electrode 131 of the long-connected pixel described in the following description of the effect of Cpg' on the display uniformity of the display panel is located above the adjacent gate line (but does not drive the pixel). That is, the first pixel electrode 121 and the second pixel electrode 131 involved in the following description of the influence of Cpg′ on the display uniformity of the display panel are not located in the same pixel unit group but in the same column.
  • the lateral pitch dpg1' can be made (for example, the first pixel electrode 121 and the The pitch of the gate line adjacent to the first pixel electrode 121 in the second direction D2) and the lateral pitch dpg2' (for example, the second pixel electrode 131 and the gate line adjacent to the second pixel electrode 131 in the second direction
  • the distance in the direction D2) is as large as possible
  • the effective overlap length lpg1' (for example, the effective overlap length between the first pixel electrode 121 and the gate line adjacent to the first pixel electrode 121) is equal to the effective The overlap length lpg2' (the effective overlap length between the second pixel electrode 131 and the gate line adjacent to the second pixel electrode 131); or the capacitance Cpg of the long-connected pixel and the short-connected pixel can be
  • FIGS. 10 and 11 are schematic plan views of the common electrode patterns 150 arranged in an array of the array substrate 100 provided by at least one embodiment of the present disclosure.
  • FIG. 11 is a schematic plan view of the common electrode patterns 150 of the array substrate 100 provided by at least one embodiment of the present disclosure.
  • the common electrode patterns 150 adjacent to each other in the first direction D1 are electrically connected to each other through the first common electrode connecting portion 151.
  • the first common electrode connecting portion 151 and the common electrode pattern 150 are in the same layer and are located in different rows.
  • the common electrode patterns 150 are spaced apart from each other.
  • the common electrode patterns 150 adjacent to each other in the second direction D2 are electrically connected to each other through the second common electrode connecting portion 152.
  • the second common electrode connecting portion 152 and the first connecting portion 122 are on the same layer.
  • the electrode connection part 152 and the corresponding common electrode pattern 150 are electrically connected through the third via 153.
  • At least one (each) common electrode pattern 150 includes a main body 154, a first protrusion 155 and two second protrusions 156 protruding from a first side of the main body 154
  • the first protrusion 155 and the two second protrusions 156 respectively extend along the second direction D2; the first protrusion 155 is disposed between the two second protrusions 156 in the first direction D1,
  • the first common electrode connecting portion 151 is disposed between the second protrusions 156 of two adjacent common electrode patterns 150 in the first direction D1, and both ends of the first common electrode connecting portion 151 are connected to the first
  • the second protrusions 156 of two adjacent common electrode patterns 150 in the direction D1 are directly and electrically connected.
  • the common electrode patterns 150 adjacent in the second direction D2 are electrically connected through the first protrusion 155 and the third via 153 of the adjacent common electrode pattern 150.
  • the end of the first protrusion 155 that is not connected to the main body 154 includes an enlarged portion 158, and the adjacent common electrode pattern 150 in the second direction D2 passes through the enlarged portion 158 and the third adjacent common electrode pattern 150.
  • the via 153 and the second common electrode connection part 152 are electrically connected.
  • the design freedom of the second common electrode connecting portion 152 can be improved.
  • the second common electrode connection portion 152 shown in FIG. 10 is only used to schematically show the connection manner of the common electrode patterns 150 located in different rows, but the shape and structure of the second common electrode connection portion 152 are different. Limited to this.
  • the second common electrode connecting portion 152 may also adopt the shape and structure of the second common electrode connecting portion 152 as shown in FIG. 6, which will not be repeated.
  • the planar shape of the at least one (each) common electrode pattern 150 may be an "E" type, and the opening direction of the at least one (each) common electrode pattern 150 (that is, the "E" type The opening direction) and the opening directions of the common electrode patterns 150 adjacent in the column direction are both opposite.
  • the main body portion 154 of each common electrode pattern 150 is opposed to the main body portion 154 of one common electrode pattern 150 adjacent to each common electrode pattern 150 described above in the second direction, and the opening of each common electrode pattern 150 Opposite the opening of another common electrode pattern 150 adjacent to each of the above-mentioned common electrode patterns 150 in the second direction.
  • the opening directions of the common electrode patterns 150 located in the odd-numbered columns are the same as each other, and the opening directions of the common electrode patterns 150 located in the even-numbered columns are the same as each other.
  • the opening directions of two common electrode patterns 150 adjacent in two directions are different from each other.
  • the main body portion 154 of at least one (each) common electrode pattern 150 has a concave portion on a side away from the first protrusion 155 of the common electrode pattern 150, and, as shown in FIG. 4B, The depressed portion of the body portion 154 of at least one (each) common electrode pattern 150 corresponds to (eg, at least partially overlaps) the depressed portion of the corresponding common electrode pattern 150.
  • each common electrode pattern 150 is disposed in the second direction at the second connection portion of the pixel unit group 110 corresponding to the common electrode pattern 150.
  • the opening of each common electrode pattern 150 is arranged in the second direction on the side where the first connection portion 122 of the pixel unit group 110 corresponding to the common electrode pattern 150 is provided.
  • the common electrode pattern 150 may also be referred to as a common electrode line or a common data line.
  • the counter substrate of the display panel further includes a common electrode layer (for example, made of a transparent conductive material such as ITO), and the common electrode layer and the common electrode pattern 150 are electrically conductive.
  • the parts for example, conductive gold balls are electrically connected.
  • the array substrate further includes a common electrode layer (for example, a patterned common electrode layer, which is insulated from the gate lines), and the common electrode pattern 150 And the common electrode layer are electrically connected to each other.
  • the common electrode pattern 150 and the common electrode layer may be directly electrically connected or connected through a via hole.
  • the common electrode layer may be located on the side of the common electrode pattern 150 away from the data line.
  • At least one embodiment of the present disclosure also provides an experimental analysis method for shaking head patterns.
  • the analysis of experimental data when the display panel displays an image with a gray level of 127 and the pixels are different by 6 gray levels, you can see To obvious shaking head lines.
  • the following is the experimental analysis method of shaking head lines and the experimental design plan for the research of shaking head lines.
  • the experimental equipment used for the study of shaking head marks includes a lighter, a detector (for example, model CA310) and a DC power supply.
  • the experiment of head wobble research includes the following steps S501 to S505.
  • Step S501 The sample (display panel) to be inspected is processed by externally irrigating the common voltage Vcom, that is, using the DC power supply (DC voltage) outside the display panel to apply the common voltage Vcom to the common electrode or the common electrode pattern in the display panel .
  • DC power supply DC voltage
  • Step S502 Use a lighting machine to edit the graphics, and light up the pixels of the same structure and the same polarity (127 gray levels), while other pixels are off (0 gray levels).
  • Step S503 Place the measuring probe of the detector (for example, model CA310) vertically in the middle of the sample to test its degree of flicker (flicker value).
  • the measuring probe of the detector for example, model CA310
  • Step S504 Adjust the common voltage Vcom until the flicker value is the smallest, then the common voltage Vcom at this time is the best common voltage Vcom for this pixel structure.
  • Step S505 For all sub-pixels in a period, repeat the above steps S501 to S504 until the optimal common voltage Vcom of all sub-pixels (12) in a period is tested.
  • Vcom Vcenter- ⁇ Vp.
  • the common voltage Vcom is inversely proportional to the jump amount ⁇ Vp of the pixel voltage, and the difference in the jump amount ⁇ Vp of the pixel voltage between different pixels can be calculated from the difference in Vcom.
  • Table 1 shows the optimal common voltage Vcom of the pixels (pixels P1-P6) in a period of a 21.5-inch twisted nematic display panel (full HD).
  • the pixels P1-P6 are, for example, red, green, and blue respectively. Color, red, green and blue sub-pixels.
  • Table 1 The best common voltage of the sub-pixels of a 21.5-inch twisted nematic display panel (Full HD)
  • the difference of the best common voltage Vcom of different sub-pixels is 0.05V; when the display panel does not have a bad head pattern, the best common voltage Vcom of different sub-pixels is different The value is 0.02V.
  • the VT curve that is, the curve between the voltage and the transmittance of the display panel
  • the gamma curve it can be obtained that the pixel voltage difference is 0.05 V, when the gray level difference is 6 gray levels, the head shaking pattern is more obvious.
  • At least one embodiment of the present disclosure also provides a display panel, which includes any array substrate provided by the embodiments of the present disclosure. At least one embodiment of the present disclosure further provides a display device, which includes any array substrate provided by an embodiment of the present disclosure or any display panel provided by an embodiment of the present disclosure.
  • FIG. 12 shows an exemplary block diagram of a display panel and an exemplary block diagram of a display device.
  • the display panel 10 includes an array substrate 100, and the display device includes a display panel 10.
  • the display substrate 10 and other components of the display device 20 for example, thin film transistors, control devices, image data encoding/decoding devices, row scan drivers, column scan drivers, clock circuits, etc.
  • the components which should be understood by those of ordinary skill in the art, will not be repeated here, nor should they be used as a limitation to the present disclosure.
  • the display substrate 10 and the display device 20 can specifically improve the ability or foundation of the aperture ratio.
  • At least one embodiment of the present disclosure also provides a manufacturing method of an array substrate, which includes forming a pixel unit group.
  • the pixel unit group includes a first pixel and a second pixel arranged side by side in a first direction; the first pixel includes a first pixel electrode, a first switching element, and a first connection portion extending and protruding from the first pixel electrode, and the second pixel It includes a second pixel electrode, a second switching element, and a second connection portion extending and protruding from the second pixel electrode; the first pixel electrode and the first switching element are electrically connected to each other via the first connection portion, the second pixel electrode and the second switch The elements are electrically connected to each other via the second connection part; and the length of the first connection part is not equal to the length of the second connection part.
  • forming the pixel unit group includes: using the same patterning process to pattern the same film layer to form the first connection portion, the first pixel electrode, the second connection portion and the second pixel electrode.
  • the manufacturing method of the array substrate may include the following steps S101 to S108.
  • Step S101 Provide a base substrate.
  • Step S102 forming a first electrode layer on the base substrate.
  • Step S103 forming a first insulating layer on the base substrate on which the first electrode layer is formed.
  • Step S104 forming a semiconductor layer on the base substrate on which the first insulating layer is formed.
  • Step S105 forming a second electrode layer on the base substrate on which the semiconductor layer is formed.
  • Step S106 forming a second insulating layer on the base substrate on which the second electrode layer is formed.
  • Step S107 forming a first via hole, a second via hole and a third via hole in the second insulating layer.
  • Step S108 forming a third electrode layer on the base substrate on which the first via hole, the second via hole and the third via hole are formed.
  • the base substrate may be a glass substrate, a quartz substrate, a plastic substrate (such as a polyethylene terephthalate (PET) substrate) or a substrate made of other suitable materials.
  • a glass substrate such as a glass substrate, a quartz substrate, a plastic substrate (such as a polyethylene terephthalate (PET) substrate) or a substrate made of other suitable materials.
  • PET polyethylene terephthalate
  • the first electrode layer includes a plurality of first gate lines, a plurality of second gate lines, common electrode patterns arranged in an array, and a plurality of first common electrode connecting portions.
  • step S102 includes: forming a first electrode film on a base substrate; using the same patterning process to pattern the first electrode film to form multiple first gate lines, multiple second gate lines, common electrode patterns arranged in an array, and The plurality of first common electrode connection parts, that is, form the first electrode layer.
  • the first electrode layer may be formed of a metal material (for example, copper, aluminum or aluminum alloy) or other suitable materials.
  • the material of the first insulating layer may be silicon oxide (SiOx), silicon oxynitride (SiNxOy), silicon nitride (SiNx) or other suitable materials.
  • the material of the semiconductor layer may be made of an oxide semiconductor material, but the embodiments of the present disclosure are not limited thereto.
  • the oxide semiconductor material may include ZnO, MgZnO, Zn-Sn-O (ZTO), In-Zn-O (IZO), SnO2, Ga2O3, In-Ga-O (IGO), In2O3, In-Sn -O (ITO), In-Ga-Zn-O (IGZO), In-Zn-Sn-O (IZTO), In-Ga-Zn-Sn-O (IGZTO) and InAlZnO (IAZO), etc., but this disclosure
  • the semiconductor layer of the embodiment is not limited to being made of the above-mentioned specific oxide semiconductor material.
  • the second electrode layer includes multiple data lines, and source and drain electrodes of multiple switching elements.
  • step S105 includes: forming a second electrode film on the semiconductor layer; using the same patterning process to pattern the second electrode film to form a plurality of data lines, the source and drain of the plurality of switching elements, that is, forming a second metal Floor.
  • the second electrode layer may be formed of a metal material (for example, copper, aluminum or aluminum alloy) or other suitable materials.
  • the second insulating layer may be formed using inorganic or organic materials.
  • the second insulating layer may be formed using organic resin, silicon oxide (SiOx), silicon oxynitride (SiNxOy), or silicon nitride (SiNx).
  • step S107 in the second insulating layer corresponding to the end of one of the two first source and drain electrodes away from the U-shaped electrode (the other of the two first source and drain electrodes) is formed.
  • the first via hole is formed in the second insulating layer at a position corresponding to the end of one of the second source and drain electrodes away from the U-shaped electrode (the other of the two second source and drain electrodes)
  • a third via is formed in the second insulating layer at a position corresponding to the first protrusion of the common electrode pattern (for example, the enlarged portion 158 of the first protrusion).
  • the third electrode layer 177 includes a first pixel electrode, a second pixel electrode, a first connection part, a second connection part, and a second common electrode connection part.
  • step S108 includes: forming a third electrode film on the base substrate on which the first via hole, the second via hole and the third via hole are formed; using the same patterning process to pattern the third electrode film to form the first pixel electrode, The second pixel electrode, the first connection part, the second connection part and the second common electrode connection part.
  • the third electrode layer may be formed of a transparent conductive material.
  • the transparent conductive material is indium tin oxide (ITO) or indium zinc oxide (IZO).

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Abstract

一种阵列基板(100)、显示面板(10)、显示装置(20)和阵列基板的制作方法。该阵列基板(100)包括像素单元组(110)。像素单元组(110)包括在第一方向(D1)上并列紧邻布置的第一像素和第二像素；第一像素包括第一像素电极(121)、第一开关元件(123)以及从第一像素电极(121)延伸突出的第一连接部(122)，第二像素包括第二像素电极(131)、第二开关元件(133)以及从第二像素电极(131)延伸突出的第二连接部(132)；第一像素电极(121)和第一开关元件(123)经由第一连接部(122)彼此电连接，第二像素电极(131)和第二开关元件(133)经由第二连接部(132)彼此电连接；以及第一连接部(122)的延伸长度不等于第二连接部(132)的延伸长度。该阵列基板(100)、显示面板(10)、显示装置(20)和阵列基板的制作方法可以提升包括该阵列基板(100)的显示装置(20)的性能。

Description

阵列基板、显示面板、显示装置和阵列基板的制作方法 技术领域
本公开的实施例涉及一种阵列基板、显示面板、显示装置和阵列基板的制作方法。
背景技术
随着显示科技的发展，薄膜晶体管液晶显示器件(TFT-LCD)以其具有的低功耗、轻薄、低辐射等优势而逐渐成为市场主流。随着人们生活水平的提高以及对显示器件认知的不断提升，人们对显示器件的显示性能也提出了越来越高的要求，例如，要求显示器件具有高分辨率、高对比度、高响应速度等。此外，人们对表征显示器件的画面品质(例如，残像、姆拉、漏光等)的参数也提出了更高的要求。例如，为实现低成本、高分辨率的显示器件，诸多显示器件采用了双栅设计方案。
发明内容
本公开的至少一个实施例提供了一种阵列基板，其包括：像素单元组。所述像素单元组包括在第一方向上并列紧邻布置的第一像素和第二像素；所述第一像素包括第一像素电极、第一开关元件以及从所述第一像素电极延伸突出的第一连接部，所述第二像素包括第二像素电极、第二开关元件以及从所述第二像素电极延伸突出的第二连接部；所述第一像素电极和所述第一开关元件经由所述第一连接部彼此电连接，所述第二像素电极和所述第二开关元件经由所述第二连接部彼此电连接；以及所述第一连接部的延伸长度不等于所述第二连接部的延伸长度。
例如，在所述阵列基板的至少一个示例中，所述像素单元组包括在所述第一方向上彼此相对的第一边缘和第二边缘，相对于所述第二边缘，所述第一开关元件和所述第二开关元件在所述第一方向均更靠近所述像素单元组的第一边缘。
例如，在所述阵列基板的至少一个示例中，在与所述第一方向交叉的第二方向上，所述第一像素电极位于所述第一开关元件和所述第二开关元件之 间。
例如，在所述阵列基板的至少一个示例中，所述第一开关元件和所述第二开关元件相对于所述第一像素电极在所述第二方向上且沿所述第一方向延伸的中线对称设置。
例如，在所述阵列基板的至少一个示例中，所述第一连接部的延伸突出的方向为第二方向，所述第二连接部的延伸突出的方向为所述第一方向，所述第一方向和所述第二方向彼此交叉。
例如，在所述阵列基板的至少一个示例中，在与所述第一方向交叉的第二方向上，所述第二连接部与所述第一像素电极至少部分重叠。
例如，在所述阵列基板的至少一个示例中，所述第一连接部与所述第一像素电极使用相同的材料一体形成，所述第二连接部与所述第二像素电极使用相同的材料一体形成。
例如，在所述阵列基板的至少一个示例中，所述第一开关元件包括第一源漏层，所述第一源漏层包括彼此相对且间隔设置的两个第一源漏极；所述第二开关元件包括第二源漏层，所述第二源漏层包括彼此相对且间隔设置的两个第二源漏极；所述第一连接部与所述第一像素电极直接电性连接，所述第一连接部经由第一过孔与所述两个第一源漏极之一电连接；以及所述第二连接部与所述第二像素电极直接电性连接，所述第二连接部经由第二过孔与所述两个第二源漏极之一电连接。
例如，在所述阵列基板的至少一个示例中，所述两个第一源漏极之一覆盖所述第一过孔的开口区域的一部分，所述第一过孔的开口区域的另一部分位于所述第一源漏极之一的靠近所述第一像素电极的一侧；以及所述两个第二源漏极之一覆盖所述第二过孔的开口区域的一部分，所述第二过孔的开口区域的另一部分位于所述第二源漏极之一的靠近所述第一像素电极的一侧。
例如，在所述阵列基板的至少一个示例中，所述阵列基板还包括沿所述第一方向延伸的第一栅线和第二栅线；所述第一栅线和所述第二栅线在与所述第一方向交叉的第二方向上位于所述像素单元组的两侧；所述第一栅线在所述第一源漏层上的正投影与所述两个第一源漏极之一在至少两个不同的位置处交叠。
例如，在所述阵列基板的至少一个示例中，所述第一栅线包括顺次相连的第一栅极部、第一线部、第一线连接部；所述第一栅极部被配置为所述第 一开关元件的栅极；所述第一栅线在所述第一源漏层上的正投影与所述两个第一源漏极之一在所述第一方向上的两侧至少部分交叠。
例如，在所述阵列基板的至少一个示例中，所述第一栅线的第一线连接部在所述两个第一源漏极之一上的正投影与所述两个第一源漏极之一至少部分交叠。
例如，在所述阵列基板的至少一个示例中，所述第一线连接部包括朝向所述第一栅极部凸出的第一凸起；以及所述第一凸起在所述两个第一源漏极之一上的正投影与所述两个第一源漏极之一至少部分交叠。
例如，在所述阵列基板的至少一个示例中，所述第一凸起在所述两个第一源漏极之一上的正投影与所述两个第一源漏极之一的交叠区域为第一交叠区域，且所述第一交叠区域具有在与所述第一方向交叉的第二方向上的第一交叠边缘；所述第一栅极部在所述两个第一源漏极之一上的正投影与所述两个第一源漏极之一的交叠区域为第二交叠区域，所述第二交叠区域具有在所述第二方向上的第二交叠边缘；所述第一交叠边缘的长度和所述第二交叠边缘的长度相等。
例如，在所述阵列基板的至少一个示例中，所述第二栅线在所述第二源漏层上的正投影与所述两个第二源漏极之一在至少两个不同的位置处交叠。
例如，在所述阵列基板的至少一个示例中，所述第二栅线包括顺次相连的第二栅极部、第二线部、第二线连接部；所述第二栅极部被配置为所述第二开关元件的栅极；所述第二栅线在所述第二源漏层上的正投影与所述两个第二源漏极之一在所述第一方向上的两侧至少部分交叠。
例如，在所述阵列基板的至少一个示例中，所述第二栅线的第二线连接部在所述两个第二源漏极之一上的正投影与所述两个第二源漏极之一至少部分交叠。
例如，在所述阵列基板的至少一个示例中，所述第二线连接部包括朝向所述第二栅极部凸出的第二凸起；所述第二凸起在所述两个第二源漏极之一上的正投影与所述两个第二源漏极之一至少部分交叠。
例如，在所述阵列基板的至少一个示例中，所述第二凸起在所述两个第二源漏极之一上的正投影与所述两个第二源漏极之一的交叠区域为第三交叠区域，所述第三交叠区域具有在所述第二方向上的第三交叠边缘；所述第二栅极部在所述两个第二源漏极之一的正投影与所述两个第二源漏极之一的交 叠区域为第四交叠区域，所述第四交叠区域具有在所述第二方向上的第四交叠边缘；以及所述第三交叠边缘的长度和所述第四交叠边缘的长度相等。
例如，在所述阵列基板的至少一个示例中，所述第一栅线在所述第一源漏层上的正投影与所述两个第一源漏极之一的交叠面积为第一值；所述第二栅线在所述第二源漏层上的正投影与所述两个第二源漏极之一的交叠面积为第二值；以及所述第一值等于所述第二值。
例如，在所述阵列基板的至少一个示例中，所述第一连接部和所述第二连接部在与所述第一方向垂直的第二方向上分别位于所述第一像素电极的两侧；所述第一连接部和所第二连接部在所述第二方向上均位于所述第一栅线和所述第二栅线之间；以及所述第一栅线和所述第二栅线相对于所述像素单元组在所述第二方向上的沿所述第一方向延伸的中线对称设置。
例如，在所述阵列基板的至少一个示例中，所述阵列基板包括阵列排布的多个所述像素单元组；以及用于驱动每个所述像素单元组的第一栅线与用于驱动与所述每个像素单元组在所述第二方向上相邻的像素单元组的第二栅线在所述第一方向上部分交叠。
例如，在所述阵列基板的至少一个示例中，所述阵列基板包括阵列排布的多个所述像素单元组以及设置在相邻的所述像素单元组之间的数据线；以及每个所述像素单元组的第一开关元件和第二开关元件均与同一根数据线相连。
例如，在所述阵列基板的至少一个示例中，所述阵列基板还包括阵列排布的多个公共电极图案；所述多个公共电极图案和所述多个像素单元组一一对应；位于同一行的多个公共电极图案位于用于驱动与所述同一行的多个公共电极图案对应的像素单元组的第一栅线和第二栅线之间；在所述第一方向上相邻的所述公共电极图案通过第一公共电极连接部彼此电连接，所述第一公共电极连接部与所述公共电极图案同层；以及在所述第二方向上相邻的所述公共电极图案通过第二公共电极连接部彼此电连接，所述第二公共电极连接部与所述第一连接部同层，所述第二公共电极连接部与对应的公共电极图案通过第三过孔电连接。
例如，在所述阵列基板的至少一个示例中，每个所述公共电极图案包括主体部以及从所述主体部的第一侧伸出的第一凸出部构成；所述第一凸出部沿所述第二方向延伸；在所述第二方向上相邻的所述公共电极图案通过所述 相邻的公共电极图案的第一凸出部和所述第三过孔电连接。
例如，在所述阵列基板的至少一个示例中，所述第一像素电极与驱动所述第一像素的栅线的横向间距大于五微米；所述第二像素电极与驱动所述第二像素的栅线的横向间距大于五微米。
例如，在所述阵列基板的至少一个示例中，所述第一连接部的延伸长度小于所述第二连接部的延伸长度；以及所述第二像素电极的靠近驱动所述第二像素的栅线的一侧具有凹陷部。
例如，在所述阵列基板的至少一个示例中，所述第一像素电极与驱动所述第一像素的栅线在与所述第一方向交叉的第二方向上彼此交叠，所述第二像素电极与驱动所述第二像素的栅线在与所述第一方向交叉的第二方向上彼此交叠；以及所述第一像素电极和所述第一连接部的结合结构与驱动所述第一像素的栅线的有效交叠长度等于所述第二像素电极和所述第二连接部的结合结构与驱动所述第二像素的栅线的有效交叠长度。
本公开的至少一个实施例还提供了一种显示面板，其包括本公开的实施例提供的任一阵列基板。
本公开的至少一个实施例还提供了一种显示装置，其包括本公开的实施例提供的任一阵列基板或本公开的实施例提供的任一显示面板。
本公开的至少一个实施例还提供了一种阵列基板的制作方法，其包括：形成像素单元组。所述像素单元组包括在第一方向上并列布置的第一像素和第二像素；所述第一像素包括第一像素电极、第一开关元件以及从所述第一像素电极延伸突出的第一连接部，所述第二像素包括第二像素电极、第二开关元件以及从所述第二像素电极延伸突出的第二连接部；所述第一像素电极和所述第一开关元件经由所述第一连接部彼此电连接，所述第二像素电极和所述第二开关元件经由所述第二连接部彼此电连接；以及所述第一连接部的长度不等于所述第二连接部的长度。
例如，在所述制作方法的至少一个示例中，所述形成像素单元组包括：使用同一构图工艺对相同的膜层构图形成所述第一连接部、所述第一像素电极、所述第二连接部和所述第二像素电极。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1是一种阵列基板的平面示意图；
图2A是本公开的至少一个实施例提供的一种阵列基板的平面示意图；
图2B是图2A所示的阵列基板的像素单元组的平面示意图；
图2C是显示面板的用户在没有摇头和摇头时观察到的图像的示意图；
图2D是空间频率的一种示例性的计算方法的示意图；
图2E是不同类型的显示面板的摇头纹的最佳观察距离的示意图；
图2F是摇头纹不良产生的原因的示意图；
图2G是一种显示面板的像素的充电和放电的示意图；
图2H是与一种显示面板的与像素相关的电容的示意图；
图3A是图2A所示的阵列基板的示意图；
图3B是图2A所示的阵列基板的区域RC1的放大图；
图3C是图2A所示的阵列基板的区域RC2的放大图；
图3D是图2A所示的阵列基板的位于奇数列的像素单元组的像素在源漏金属层未偏移和偏移情况下的像素电压的示意图；
图3E是图2A所示的阵列基板的位于偶数列的像素单元组的像素在源漏金属层未偏移和偏移情况下的像素电压的示意图；
图3F是图2A所示的阵列基板的像素的像素电极和连接部的结合结构与驱动该像素的栅线之间的有效交叠长度和横向间距的示意图；
图3G是图2A所示的阵列基板的短连接像素和长连接像素在正显示帧和负显示帧下的像素电压的对比的示意图；
图3H是图2A所示的阵列基板的区域RC1的示意图；
图3I是图2A所示的阵列基板的区域RC3的示意图；
图3J是图2A所示的阵列基板的像素的电容Cpg’对该像素的像素电压的影响的示意图；
图4A是本公开的至少一个实施例提供的另一种阵列基板的平面示意图；
图4B是图4A所示的阵列基板的像素单元组的平面示意图；
图4C是图4A所示的阵列基板的第一电极层的平面示意图；
图4D是图4A所示的阵列基板的第一栅线和第二栅线的平面示意图；
图4E是图4A所示的阵列基板的第一栅线和第二栅线的对应于一个像素 单元组的部分的平面示意图；
图5A是图4A所示的阵列基板的半导体层和第二电极层的平面示意图；
图5B是图4A所示的阵列基板的第一开关元件的平面示意图；
图5C是沿图5B所示的AA’线剖切获得的截面示意图；
图5D是图4A所示的阵列基板的第二开关元件的平面示意图；
图5E是图2A所示的阵列基板的部分区域的平面示意图；
图5F是图5E所示的阵列基板的区域RC4的平面示意图；
图5G是图4A所示的阵列基板的栅线所在的电极层与源漏极所在的电极层在栅线所在的电极层的正投影之间的交叠区域的第一个示意图；
图5H是图4A所示的阵列基板的栅线所在的电极层与源漏极所在的电极层在栅线所在的电极层的正投影之间的交叠区域的第二个示意图；
图6是图4A所示的阵列基板的第三电极层的平面示意图；
图7是图4A所示的阵列基板的第一电极层、半导体层和第二电极层的平面示意图；
图8是图4A所示的阵列基板的第一过孔、第二过孔和第三过孔的平面示意图；
图9是图4A所示的阵列基板的像素电极与驱动该像素电极所在的像素的栅线的间距和交叠长度的示意图；
图10是图4A所示的阵列基板的多个公共电极图案的平面示意图；
图11是图4A所示的阵列基板的多个公共电极图案的一个的平面示意图；以及
图12是本公开至少一个实施例提供的显示面板和显示装置的示例性框图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领 域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本公开的发明人在研究中注意到，一些采用了双栅设计方案的显示面板存在摇头纹不良和/或开口率较低，尤其是对于TN(Twist Nematic，扭曲向列型)显示面板而言，下面结合图1对采用了双栅设计方案的显示面板的开口率较低问题进行示例性说明。
图1是一种阵列基板500的平面示意图。如图1所示，该阵列基板500包括阵列排布的多个像素单元组510、沿第一方向D1延伸的栅线542以及沿与第一方向D1交叉(例如，垂直)的第二方向D2延伸的数据线561；在第一方向D1上相邻的两个像素单元组510之间设置了一根数据线561，在第二方向D2上相邻的两个像素单元组510之间设置了两根栅线542；每行像素单元组510由设置在该行像素单元组510两侧的两根栅线542(位于该行像素单元组510上方的一根栅线542以及位于该行像素单元组510下方的一根栅线542)驱动。
如图1所示，每个像素单元组510包括在第一方向D1上并列紧邻布置的第一像素和第二像素；第一像素包括第一像素电极521、第一开关元件523以及第一走线522，该第一走线522用于连接第一开关元件523以及用于驱动该第一像素的数据线561；第二像素包括第二像素电极531、第二开关元件533以及第二走线532，该第二走线532用于连接第二开关元件533以及用于驱动该第二像素的数据线561。
如图1所示，第一像素电极521与第一开关元件523通过第一过孔524电连接，第二像素电极531与第二开关元件533通过第二过孔534电连接；第一过孔524在第一像素电极521上的正投影与第一像素电极521至少部分重叠；第二过孔534在第二像素电极531上的正投影与第二像素电极531至少部分重叠。
如图1所示，用于驱动同一像素单元组510的第一开关元件523和第二开关元件533在第二方向D2上并列布置，且第一开关元件523和第二开关元件533在第二方向D2上至少部分交叠，也即，第一开关元件523和第二开关元件533在垂直于第二方向D2上的平面上的正投影至少部分交叠；第一走线522和第二走线532设置在第二方向D2上相邻的两个像素单元组510之间的两根栅线542之间。
例如，包括该阵列基板500的显示面板包括黑矩阵(图中未示出)，且黑矩阵在阵列基板500上的正投影覆盖栅线542、数据线561、第一走线522、第二走线532、第一开关元件523、第二开关元件533、第一过孔524和第二过孔534。例如，第一走线522、第二走线532以及数据线561使用相同的材料制成。
本公开的发明人在研究中注意到，包括图1所示的阵列基板的显示面板的开口率较小。并且，尽管通过缩小第一走线和第二走线在第二方向上的宽度可以略微提升包括图1所示的阵列基板的显示面板的开口率，但是缩小第一走线和第二走线在第二方向上的宽度可以增加第一走线和第二走线的断路风险。此外，第一走线和第二走线上的信号可能会对阵列基板的其它走线上的信号产生干扰。
本公开的至少一个实施例提供了一种阵列基板、显示面板、显示装置和阵列基板的制作方法。该阵列基板包括像素单元组。像素单元组包括在第一方向上并列紧邻布置的第一像素和第二像素；第一像素包括第一像素电极、第一开关元件以及从第一像素电极延伸突出的第一连接部，第二像素包括第二像素电极、第二开关元件以及从第二像素电极延伸突出的第二连接部；第一像素电极和第一开关元件经由第一连接部彼此电连接，第二像素电极和第二开关元件经由第二连接部彼此电连接；以及第一连接部的延伸长度不等于第二连接部的延伸长度。
在一些示例中，通过使得第一连接部的延伸长度不等于第二连接部的延伸长度(也即，使得阵列基板具有长连接像素和短连接像素)，使得该阵列基板以及包括该阵列基板的显示面板和显示装置具有提升开口率的能力或提升开口率的基础。
在一些示例中，由于长连接像素的侧向电容和短连接像素的相关电容不等，此种情况下，可能导致包括具有提升开口率的能力或提升开口率的基础 的阵列基板具有显示不均匀现象(例如，摇头纹现象，摇头纹不良)。摇头纹是一种显示面板的用户在摇头时才可能会观察到的明暗交替排布的条纹，摇头纹与不同像素的像素电压跳变量Δp不同相关，影响像素的像素电压跳变量Δp的因素包括：像素的侧向电容包括栅线与源漏层形成的电容Cgs，像素电极以及与该像素电极对应的栅线形成的电容Cpg，像素电极以及与该像素电极相邻的栅线(但不用于驱动该像素电极所在的像素)形成的电容Cpg’等。例如，在长连接像素的电容Cgs和短连接像素的电容Cgs更为接近和/或长连接像素的电容Cpg和短连接像素的电容Cpg更为接近的情况下，长连接像素的像素电压跳变量Δp与短连接像素的像素电压跳变量Δp更为接近，由此可以使得摇头纹现象减弱。需要说明的是，为清楚起见，摇头纹的定义、产生原因、相关因素以及观察和研究摇头纹的实验方法将在后面进行详细阐述，在此不再赘述。
在一些示例中，通过使得对应于每个像素(第一像素和第二像素)的栅线(第一栅线和第二栅线)的部分在源漏层上的正投影与该像素的两个源漏极之一在至少两个不同的位置处交叠，可以降低栅线与源漏层形成的电容Cgs的变化幅度(偏离设计值的幅度)，由此可以抑制显示不均匀现象(例如，摇头纹现象，摇头纹不良)。
在一些示例中，通过使得第一栅线在源漏层上的正投影与两个第一源漏极之一的交叠面积等于，第二栅线在源漏层上的正投影与两个第二源漏极之一的交叠面积，可以使得长连接像素的电容Cgs等于短连接像素的电容Cgs，由此可以进一步地抑制(例如，摇头纹现象，摇头纹不良)。
在一些示例中，通过使得第一像素电极与驱动第一像素的栅线的横向间距大于五微米可以降低以下因素对第一像素的电容Cpg的影响：第一像素电极与驱动第一像素的栅线的横向间距(例如，因制造工艺导致的变化)的变化；第一像素电极和第一连接部的结合结构与驱动第一像素的栅线的有效交叠长度的变化；通过使得第二像素电极与驱动第二像素的栅线的横向间距大于五微米，可以降低以下因素对第二像素的电容Cpg的影响：第二像素电极与驱动第二像素的栅线的横向间距的变化；第二像素电极和第二连接部的结合结构与驱动第二像素的栅线的有效交叠长度的变化；因此，可以在不劣化显示均匀性的情况下，可以降低对制造工艺的要求。
在一些示例中，通过使得长连接像素的像素电极的靠近驱动该长连接像 素的栅线的一侧具有凹陷部，可以缩短长连接像素的像素电极和连接部的结合结构与栅线的有效交叠长度lpg；此种情况下，长连接像素的像素电极和连接部的结合结构与栅线的有效交叠长度与短连接像素的像素电极和连接部的结合结构与栅线的有效交叠长度更为接近，因此，可以使得长连接像素的电容Cpg与短连接像素的电容Cpg更为接近，由此可以进一步地抑制摇头纹不良。
下面通过几个示例和实施例对根据本公开实施例提供的阵列基板进行非限制性的说明，如下面所描述的，在不相互抵触的情况下这些具体示例和实施例中不同特征可以相互组合，从而得到新的示例和实施例，这些新的示例和实施例也都属于本公开保护的范围。
图2A是本公开的至少一个实施例提供的一种阵列基板100的平面示意图，如图2A所示，该阵列基板100包括阵列排布的多个像素单元组110、多根第一栅线141、多根第二栅线142和多根数据线161；多根第一栅线141和多根第二栅线142分别大致沿第一方向D1延伸，多根数据线161大致沿与第一方向D1交叉(例如，垂直)的第二方向D2延伸。
每行像素单元组110被两根栅线驱动，上述两根栅线(一根第一栅线141和一根第二栅线142)在第二方向D2上位于该行像素单元组110两侧且与该行像素单元组110紧邻。此处，栅线与像素单元组110紧邻是指像素单元组110与上述栅线之间不包括其它栅线。在第二方向D2上相邻的两个像素单元组110之间设置了两根栅线，在第一方向D1上相邻的两个像素单元组110之间设置了一根数据线。
为清楚起见，下面针对多个像素单元组110中的一个进行示例性说明。
图2B是图2A所示的阵列基板100的像素单元组110的平面示意图，为方便描述，图2B还示出了第一栅线141、第二栅线142和数据线161。图2A所示的阵列基板100的部分或所有像素单元组110可以实现为图2B所示的像素单元组110。
如图2B所示，该像素单元组110包括在第一方向D1上并列紧邻布置的第一像素和第二像素。需要说明的是，并列紧邻布置的第一像素和第二像素是指上述第一像素和第二像素之间不包含其它像素。
如图2B所示，第一像素包括第一像素电极121、第一开关元件123以及从第一像素电极121延伸突出的第一连接部122，第二像素包括第二像素电极 131、第二开关元件133以及从第二像素电极131延伸突出的第二连接部132；第一像素电极121和第一开关元件123经由第一连接部122彼此电连接，第二像素电极131和第二开关元件133经由第二连接部132彼此电连接；第一连接部122的延伸长度不等于(例如，小于)第二连接部132的延伸长度。
例如，对于第一连接部122的延伸长度小于第二连接部132的延伸长度的示例，第一像素也可以被称为短连接像素，第二像素也可以被称为长连接像素。例如，每个像素单元组中所包括的连接部的延伸长度较小的那个像素被称为短连接像素，每个像素单元组中所包括的连接部的延伸长度较长的那个像素被称为长连接像素。在一些示例中，阵列基板的所有的短连接像素均被称为第一像素，阵列基板的所有的长连接像素均被称为第二像素。
例如，通过使得第一连接部122的延伸长度不等于(例如，小于)第二连接部132的延伸长度，可以将第一开关元件123和第二开关元件133均设置在像素单元组110的在第一方向D1上的边缘，下面结合图2B进行示例性说明。
例如，如图2B所示，像素单元组110包括在第一方向D1上彼此相对的第一边缘111和第二边缘112，相对于第二边缘112，第一开关元件123和第二开关元件133在第一方向D1均更靠近像素单元组110的第一边缘111。
例如，如图2B所示，每个像素单元组110的第一开关元件123和第二开关元件133均与同一根数据线161相连。例如，每个像素单元组110的第一开关元件123和第二开关元件133与上述同一根数据线161的距离均相同，此种情况下，每个像素单元组110的第一开关元件123与驱动该像素单元组110的数据线161之间的连接线的长度(在第一方向D1上的长度)可以等于每个像素单元组110的第二开关元件133与驱动该像素单元组110的数据线161之间的连接线的长度(在第一方向D1上的长度)。
例如，如图2A所示，与同一根数据线161相连的开关元件包括位于上述同一根数据线161的第一侧(例如，左侧)的开关元件以及位于上述同一根数据线161的第二侧(例如，右侧)的开关元件，位于上述同一根数据线161的第一侧(例如，左侧)的开关元件以及位于上述同一根数据线161的第二侧(例如，右侧)的开关元件在第一方向D1上部分重叠。
例如，在本公开的至少一些实施例中，A结构与B结构在C方向上重叠(或部分重叠)是指A结构在垂直于C方向上的D平面上正投影与B结构在 D平面上的正投影重叠(或部分重叠)。
例如，通过使得位于上述同一根数据线161的第一侧(例如，左侧)的开关元件以及位于上述同一根数据线161的第二侧(例如，右侧)的开关元件在第一方向D1上部分重叠，可以降低设置了开关元件(第一开关元件123和第二开关元件133)占据的区域在第二方向D2上的尺寸，因此可以降低用于遮挡开关元件的黑矩阵在第二方向D2上的尺寸，提升该阵列基板100以及包括该阵列基板100的显示面板和显示装置的开口率。
例如，如图2B所示，像素单元组110的第一连接部122和第二连接部132在第二方向D2上分别位于第一像素电极121的两侧；第一连接部122和第二连接部132在第二方向D2上均位于第一栅线141和第二栅线142之间。
例如，如图2B所示，第一连接部122的延伸突出的方向为第二方向D2，第二连接部132的延伸突出的方向为第一方向D1。在一个示例中，第一连接部122的延伸长度是指第一连接部122在第二方向D2上长度；第二连接部132的延伸长度是指第二连接部132在第一方向D1上长度，也即，连接部的延伸长度是指该连接部在其延伸方向上的长度。在另一个示例中，连接部的延伸长度还可以是该连接部的总体长度或物理长度。
例如，在第二方向D2上，第二连接部132与第一像素电极121至少部分重叠；在第二方向D2上，第一像素电极121位于第一开关元件123和第二开关元件133之间。
例如，第一连接部122与第一像素电极121使用相同的材料一体形成，第二连接部132与第二像素电极131使用相同的材料一体形成。
例如，如图2B所示，通过使得第一开关元件123和第二开关元件133在第一方向D1均更靠近像素单元组110的同一个边缘(例如，第一边缘111)，第一连接部122与第一像素电极121使用相同的材料一体形成，第二连接部132与第二像素电极131使用相同的材料一体形成，可以使得第一连接部122(第一连接部122的第一端1221，还可参见下方的图6)与第一像素电极121直接电性连接，且使得第二连接部132(第二连接部132的第一端1321，还可参见下方的图6)与第二像素电极131直接电性连接，因此，相比于图1所示的阵列基板，可以避免在靠近第一像素电极121和第二像素电极131的区域设置过孔，由此可以提升第一像素的显示区域和第二像素的显示区域的面积；此外，尽管第一连接部122(第一连接部122的第二端1222)通过第 一过孔1223与第一开关元件123电连接，第二连接部132(第二连接部132的第二端1322)通过第二过孔1323与第二开关元件133电连接，但是由于第一过孔1223靠近第一开关元件123，第二过孔1323靠近第二开关元件133，且靠近第一开关元件123和第二开关元件133的区域原本也对应于被黑矩阵遮挡的区域，因此，图2B所示的第一过孔1223和第二过孔1323不会降低像素单元组110以及阵列基板100的开口率。
例如，第一像素电极121和第二像素电极131均可以采用透明导电材料形成。例如，透明导电材料为氧化铟锡(ITO)或氧化铟锌(IZO)。对于第一连接部122与第一像素电极121使用相同的材料一体形成，且第二连接部132与第二像素电极131使用相同的材料一体形成的示例，第一连接部122和第二连接部132也均可以使用透明导电材料形成(例如，ITO)。例如，透明导电材料(例如，ITO)的加工精度高于金属材料的加工精度，也即，透明导电材料走线的线宽可以小于金属材料走线的线宽；此种情况下，第一连接部122和第二连接部132占据的区域的尺寸可以降低，第一像素电极121和第二像素电极131占据的区域的尺寸可以对应的增加，由此可以进一步地提升像素单元组110以及阵列基板100的开口率。
例如，如图2A和图2B所示，第一开关元件123和第二开关元件133均为U型TFT。例如，如图2A所示，位于相邻行的像素单元组的U型TFT的开口方向相反。例如，如图2A所示，位于第一行(奇数行)的像素单元组的U型TFT的开口方向为向右，位于第二行(偶数行)的像素单元组的U型TFT的开口方向为向左。对应的，位于第一行(奇数行)的像素单元组的U型TFT设置在数据线的右侧，位于第二行(偶数行)的像素单元组的U型TFT设置在数据线的左侧。
本公开的发明人在研究中注意到，虽然通过使得图2A所示的阵列基板的像素单元组包括长连接像素和短连接像素可能提升阵列基板的开口率，但是也可能导致图2A所示的阵列基板的存在亮度不均匀现象(例如，摇头纹现象，摇头纹不良)。下面结合图2C-图2H对摇头纹不良的相关问题进行具体阐述。
摇头纹是一种显示面板的用户在摇头时才可能会观察到的明暗交替排布的条纹。图2C的左图是在显示面板的用户没有摇头时观察到的图像，图2C的右图是在显示面板的用户摇头时观察到的图像(也即，存在摇头纹不良的图像)，此处，显示面板被配置为显示灰度为127的图像(也即，图像的各个 像素的灰度均为127)。
如图2C的右图所示，摇头纹的亮条纹和暗条纹例如分别在显示面板的列方向上延伸，并且摇头纹的亮条纹和暗条纹在显示面板的行方向上交替排布。例如，摇头纹可以使用空间频率fs进行描述，下面结合图2D进行示例性说明。图2D示出了空间频率的一种示例性的计算方法的示意图。
如图2D所示，空间频率fs是指每度视角内图像(或刺激图形)的亮暗作正弦调制的栅条周数，或者每度视角内图像亮暗分布的周期数目；空间频率fs单位为周/度，空间频率fs可由公式(1)进行表示，摇头纹现象的最佳观察距离可由公式(2)进行表示。
Figure PCTCN2019096151-appb-000001
Figure PCTCN2019096151-appb-000002
此处，r是观察距离，也即，用户的眼睛611至显示面板612的距离；l是显示面板的子像素宽度(在行方向上的宽度)；n是一个明暗周期内像素的个数，θ是视角，dθ是每度视角。
研究表明，对于不同的空间频率，不同明暗程度的摇头纹，人眼对空间频率等于8周/度时最敏感。因此，对于一个相关参数确定的显示面板的摇头纹而言，具有一个最佳观察距离。图2E示出了不同类型的显示面板的摇头纹的最佳观察距离，如图2E所示，大多数显示面板的摇头纹的最佳观察距离位于0.2米至0.5米之间。需要说明的是，图2E所示的“r/m”表示图2E的纵坐标代表观察距离r，且观察距离r的单位为“米”；“HD”、“FHD”和“UHD”分别表示“高清”、“全高清”和“超高清”。
下面结合图2F示例性地说明摇头纹不良产生的原因。图2F示出了摇头纹不良产生的原因。如图2F所示，显示面板显示了在时间T上顺次相邻的第一帧图像F1、第二帧图像F2、第三帧图像F3、第四帧图像F4、第五帧图像F5、第六帧图像F6、第七帧图像F7和第八帧图像F8。由于人眼看到的图像是对在时间上相邻的多幅图像叠加和平均后的图像，因此，在用户的头部保持静止时，用户观察不到摇头纹现象。然而，在用户的头部运动(例如，摇头)时，由于用户可能观察不到部分帧的图像(例如，用户未观察到第四帧 图像F4-第六帧图像F6)，因此，用户的眼睛可能无法对观察到的图像进行较好的平均化，此种情况下，用户可能观察到摇头纹现象。例如，用户的眼睛无法通过对观察到第三帧图像F3和第七帧图像F7进行平均化而消除同一帧显示图像中不同像素之间存在的亮度差异。
如图2F所示，在显示第一帧图像F1、第三帧图像F3、第五帧图像F5和第七帧图像F7时，施加在像素电极上第一像素电压大于公共电压Vcom，在显示第二帧图像F2、第四帧图像F4、第六帧图像F6和第八帧图像F8时，施加在像素电极上第二像素电压小于公共电压Vcom，且第一像素电压和公共电压Vcom之间的电压差小于公共电压Vcom和第二像素电压之间的电压差，也即，第二帧图像F2、第四帧图像F4、第六帧图像F6和第八帧图像F8的亮度大于第一帧图像F1、第三帧图像F3、第五帧图像F5和第七帧图像F7的亮度。例如，即使通过调整图2F所示的公共电压Vcom，并使得第一像素电压和公共电压Vcom之间的电压差等于公共电压Vcom和第二像素电压之间的电压差，由于上述未观察到的第四帧图像F4-第六帧图像F6，用户的眼睛也无法对观察到第三帧图像F3和第七帧图像F7进行较好的平均化，此种情况下，用户可能依然可以观察到摇头纹现象。
例如，影响像素在正帧和负帧亮度的主要因素包括公共电极上的电压(VCOM)、像素电压的跳变量(△Vp)以及电压保持率(VHR)。图2G是显示面板的像素的充电和放电的示意图，图2G示出了显示面板的像素的漏极电压Vd、公共电压Vcom、像素电压Vp以及栅极电压Vg随时间变化的曲线。如图2G所示，像素的每个显示周期可以包括相邻的第一显示帧F1和第二显示帧F2，第二显示帧F2例如为反转显示帧，在第二显示帧F2中，阵列基板的各个像素的像素电极上的电压的极性与第一显示帧F1相反；第一显示帧F1和第二显示帧F2均包括电压写入阶段Tw和电压保持阶段Th。
如图2G所示，在电压写入阶段Tw的初期，漏极电压Vd和公共电压Vcom的差值的绝对值发生跳变，△Vp为漏极电压Vd和公共电压Vcom的差值的绝对值的跳变量，△Vp也被称为像素电压的跳变量。如图2G所示，在电压写入阶段Tw，漏极电压Vd和公共电压Vcom的差值的绝对值逐渐降低，Vh为保持电压。
对于同一个像素而言，尽管理论上可以通过调节公共电压Vcom使得正帧亮度等于负帧亮度，但是由于显示面板包括的多个像素的最佳公共电压 Vcom值不同，因此，在实践中，可能难以使用调节公共电压Vcom的方法来完全消除相邻显示帧的亮度差异。
如图2G所示，本公开的发明人在研究中注意到，在不考虑电压保持率(VHR)的情况下，像素电压的跳变量△Vp对相邻显示帧的亮度差异以及同一显示帧的亮度均匀性(例如，摇头纹现象)的影响较大，尤其对于采用了双栅结构的显示面板而言，这是由于采用了双栅结构的显示面板的相邻子像素的结构可能存在差异，下面结合图2H进行示例性说明。
图2H示出了与显示面板的像素相关的电容的示意图。如图2H所示，与像素相关的电容包括电容Cgs、电容Cpg、电容Cpg’、电容Cpd、电容Cpd’、电容Cst和电容Clc，像素电压的跳变量△Vp可以使用以下的公式(3)进行表示。
Figure PCTCN2019096151-appb-000003
此处，电容Cgs是开关元件的源漏极之一与用于驱动该开关元件的栅线(和/或栅极)之间形成的电容；电容Cpg是像素电极与用于驱动该像素电极所在的像素的栅线(和/或栅极)之间形成的横向电容；电容Cpg’是像素电极和与该像素电极相邻的栅线(不用于驱动该像素电极所在的像素)之间形成的横向电容；电容Cpd是像素电极与用于驱动该像素电极所在的像素的数据线之间形成的横向电容；电容Cpd’是像素电极和与该像素电极相邻的数据线(不用于驱动该像素电极所在的像素)之间形成的横向电容；电容Cst和电容Clc是像素的存储电容，COM是公共电极；Vgh和Vgl分别是栅线接收的栅极扫描信号的第一电平和第二电平，第一电平的电压值大于第二电平的电压值；GLn和GLn+1分别是位于n行和n+1行的栅线；DLn和DLn+1分别是位于n列和n+1列的数据线。
本公开的发明人在研究中注意到，摇头纹不良与同一帧图像的不同子像素的亮度差异(不同子像素的理论灰阶相同)相关，并且同一帧图像的不同子像素的亮度差异与不同子像素的像素电压的跳变量△Vp不同相关。
本公开的发明人在研究中注意到，由于以下原因的至少一个，图2A所示的阵列基板可能存在亮度不均匀的问题(例如，摇头纹问题)：(1)阵列基板的源漏金属层相对于栅极金属层存在偏移；(2)阵列基板的长连接像素的电容Cpg不等于短连接像素的电容Cpg；(3)阵列基板的长连接像素的电容Cpg’ 不等于短连接像素的电容Cpg’。
下面结合图3A-图3C对阵列基板的源漏金属层相对于栅极金属层存在偏移可能导致的亮度不均匀问题进行示例性说明。
图3A是图2A所示的阵列基板的示意图；图3B是图2A所示的阵列基板的区域RC1的放大图，图3C是图2A所示的阵列基板的区域RC2的放大图。
图3A示出了多根第一栅线、多根第二栅线、多根数据线以及阵列排布的像素单元组。如图3A所示，多根第一栅线包括栅线GL1_1、栅线GL2_1、栅线GL3_1和栅线GL4_1，多根第二栅线包括栅线GL1_2、栅线GL2_2、栅线GL3_2和栅线GL4_2，多根数据线包括数据线DL1-DL7，阵列排布的像素单元组包括例如像素P11_1、像素P11_2、像素P12_1、像素P12_2、像素P21_1、像素P21_2、像素P22_1和像素P22_2。
图3B是图2A所示的阵列基板的区域RC1的放大图，也即，图3B示出了像素P11_2的开关元件的源漏极之一与用于驱动该开关元件的栅线(和/或栅极)之间的交叠区域201；图3C是图2A所示的阵列基板的区域RC2的放大图，也即，图3C示出了像素P11_1的开关元件的源漏极之一与用于驱动该开关元件的栅线(和/或栅极)之间的交叠区域202。
如图3B和图3C所示，在开关元件的源漏极相对于开关元件的栅极向右移动时(也即阵列基板的源漏金属层相对于栅极金属层向右偏移)，交叠区域201和交叠区域202的面积减小，因此，像素P11_2的电容Cgs和像素P11_1的电容Cgs均减小，像素P11_2的像素电压的跳变量△Vp和像素P11_1的像素电压的跳变量△Vp均减小。
如图2A和图3A所示，由于像素P12_1和像素P12_2的开关元件的U型电极(也即，开关元件的源漏极的另一个)的开口方向与像素P11_1和像素P11_2的开关元件的U型电极的开口方向相同，因此，在开关元件的源漏极相对于开关元件的栅极向右移动时，像素P12_2和像素P12_1的电容Cgs和像素电压的跳变量△Vp也均减小。
如图2A和图3A所示，由于像素P21_1、像素P21_2、像素P22_1和像素P22_2的开关元件的U型电极的开口方向与像素P11_1和像素P11_2的开关元件的U型电极的开口方向相反，因此，在开关元件的源漏极相对于开关元件的栅极向右移动时，像素P21_1、像素P21_2、像素P22_1和像素P22_2 的电容Cgs和像素电压的跳变量△Vp均增加。
如图3A所示，像素P11_1和像素P11_2均与位于第一列的数据线DL1连接，像素P12_1、像素P12_2、像素P21_1和像素P21_2均与位于第二列的数据线DL2连接，像素P22_1和像素P22_2均与位于第三列的数据线DL2连接；数据线DL1和数据线DL2上施加的电压相反，数据线DL1和数据线DL3上施加的电压相同。
如图3A所示，对于数据线DL1、数据线DL2和数据线DL3上施加的电压分别为正电压、负电压和正电压(像素P11_1、像素P11_2、像素P22_1和像素P222均处于正显示帧像素P12_1、像素P12_2、像素P21_1和像素P21_2均处于负显示帧)，且像素的亮度与该像素的像素电压和公共电压的差值的绝对值负相关的示例，位于奇数列的像素单元组的像素的亮度偏暗，位于偶数列的像素单元组的像素的亮度偏暗。像素处于正显示帧是指该像素的像素电极上的电压为正电压，像素处于负显示帧是指该像素的像素电极上的电压为负电压。下面结合图3A、图3D和图3E进行示例性说明。
图3D是位于奇数列的像素单元组的像素在源漏金属层相对于栅极金属层未偏移(虚线)以及偏移(实线)情况下的像素电压的示意图，图3E是位于偶数列的像素单元组的像素在源漏金属层相对于栅极金属层未偏移(虚线)以及偏移(实线)情况下的像素电压的示意图。
如图3A和图3D所示，由于像素P11_1和像素P11_2的像素电压的跳变量△Vp均减小，且像素P11_1和像素P11_2均处于正显示帧，因此，像素P11_1和像素P11_2的像素电压Vp均增加，像素P11_1和像素P11_2的像素电压与公共电压的差值的绝对值|Vp-Vcom|均增加，像素P11_1和像素P11_2均偏暗；由于像素P21_1和像素P21_2的像素电压的跳变量△Vp均增加，且像素P21_1和像素P21_2均处于负显示帧，因此，像素P21_1和像素P21_2的像素电压Vp均降低，像素P21_1和像素P21_2的像素电压与公共电压的差值的绝对值|Vp-Vcom|均增加，像素P21_1和像素P21_2也均偏暗。
如图3A和图3E所示，由于像素P12_1和像素P12_2的像素电压的跳变量△Vp均减小，且像素P12_1和像素P12_2均处于负显示帧，因此，像素P12_1和像素P12_2的像素电压Vp均增加，像素P12_1和像素P12_2的像素电压与公共电压的差值的绝对值|Vp-Vcom|均降低，像素P12_1和像素P12_2均偏亮；由于像素P22_1和像素P22_2的像素电压的跳变量△Vp均增加，且 像素P22_1和像素P22_2均处于正显示帧，因此，像素P22_1和像素P22_2的像素电压Vp均降低，像素P12_1和像素P12_2的像素电压与公共电压的差值的绝对值|Vp-Vcom|均降低，像素P12_1和像素P12_2均偏亮。
因此，在同一图像帧，包括图2A所示的阵列基板的显示面板显示的图像可能存在显示不均匀问题(例如，摇头纹问题)。
下面结合图3F和图3G对阵列基板的长连接像素的电容Cpg不等于(大于)短连接像素的电容Cpg可能导致的亮度不均匀问题进行示例性说明。影响像素的电容Cpg参数包括横向间距dpg和有效交叠长度lpg。
图3F示出了短连接像素(第一像素，P11_1)的像素电极和连接部的结合结构与驱动该短连接像素的栅线之间的有效交叠长度lpg1和横向间距dpg1，图3F还示出了长连接像素(第二像素，P11_2)的像素电极和连接部的结合结构与驱动该长连接像素的栅线的有效交叠长度lpg2和横向间距dpg2。
如图3F所示，像素的横向间距dpg是指像素的像素电极(像素电极靠近用于驱动该像素的栅线的边缘)以及用于驱动该像素的栅线(栅线的靠近像素电极的边缘)之间的间距。
如图3F所示，短连接像素(第一像素)的有效交叠长度lpg1(lpg1＝lpg1_1+lpg1_2)小于长连接像素(第二像素)的有效交叠长度lpg2。例如，在短连接像素的横向间距dpg1与长连接像素的横向间距dpg2相等或接近的情况，短连接像素的电容Cpg小于长连接像素的电容Cpg，因此，短连接像素的像素电压的跳变量△Vp小于长连接像素的像素电压的跳变量△Vp。
如图2A和图3A所示，像素P21_1也是长连接像素。图3G示出了短连接像素P11_1和长连接像素P21_1在正显示帧和负显示帧下的像素电压的对比的示意图。
如图3G所示，在第一图像帧F1，短连接像素P11_1处于正显示帧，长连接像素P21_1处于负显示帧；在第二图像帧F2，短连接像素P11_1处于负显示帧，长连接像素P21_1处于正显示帧。
如图3G所示，由于短连接像素的像素电压的跳变量△Vp小于长连接像素的像素电压的跳变量△Vp，在第一图像帧F1，短连接像素P11_1和长连接像素P21_1均偏暗；在第二图像帧F2，短连接像素P11_1和长连接像素P21_1均偏亮，下面结合图3G进行示例性说明。
如图3G所示，在第一图像帧F1，处于正显示帧的短连接像素P11_1的像素电压Vp增加，像素电压Vp与公共电压Vcom的差值的绝对值|Vp-Vcom|增加；处于负显示帧的长连接像素P21_1的像素电压Vp降低，像素电压Vp与公共电压Vcom的差值的绝对值|Vp-Vcom|增加，因此，在第一图像帧F1，短连接像素P11_1和长连接像素P21_1均偏暗。基于类似的原因，在第一图像帧F1，位于短连接像素P11_1和长连接像素P21_1所在列的其它像素也均偏暗。基于类似的原因，在第一图像帧F1，位于长连接像素P11_2和短连接像素P21_2所在列的所有像素均偏亮。
如图3G所示，在第二图像帧F2，处于负显示帧的短连接像素P11_1的像素电压Vp增加，像素电压Vp与公共电压Vcom的差值的绝对值|Vp-Vcom|降低，处于正显示帧的长连接像素P21_1的像素电压Vp降低，像素电压Vp与公共电压Vcom的差值的绝对值|Vp-Vcom|降低，因此，在第一图像帧F1，短连接像素P11_1和长连接像素P21_1均偏亮。基于类似的原因，在第二图像帧F2，位于短连接像素P11_1和长连接像素P21_1所在列的其它像素也均偏亮。基于类似的原因，在第一图像帧F1，位于长连接像素P11_2和短连接像素P21_2所在列的所有像素均偏暗。
如图3G所示，在仅考虑短连接像素P11_1的情况下，应当将公共电压从Vcom增加至Vcom_S(针对短连接像素P11_1的最优的公共电压)；然而，在仅考虑长连接像素P21_1的情况下，应当将公共电压从Vcom降低至Vcom_L(针对长连接像素P21_1的最优的公共电压)；因此，难以通过调节公共电压消除因长连接像素的Cpg与短连接像素的Cpg不同导致的图像亮度不均匀的现象(位于同一列的像素在同一图像帧均偏亮或均偏暗)。
下面结合图3H-图3J对阵列基板的长连接像素的电容Cpg’不等于(大于)短连接像素的电容Cpg’可能导致的亮度不均匀问题进行示例性说明。例如，影响像素的电容Cpg’参数包括横向间距dpg’和有效交叠长度lpg’。
图3H示出了图2A所示的阵列基板的区域RC1的示意图(由扫描电子显微镜获得)，图3I示出了图2A所示的阵列基板的区域RC3的示意图(由扫描电子显微镜获得)。
如图3H所示，第一像素电极121以及与第一像素电极121相邻的栅线(但不用于驱动该第一像素电极121所在的第一像素，也即，第二栅线142)在第二方向D2上彼此交叠；如图3I所示，第二像素电极131以及与第二像素电 极131相邻的栅线(但不用于驱动该第二像素电极131所在的第二像素，也即，第二栅线142)在第二方向D2上彼此交叠。
有以下两点需要说明。(1)如图2A、图3H和图3I所示，图3I所示的第二像素电极131与图3H所示的第一像素电极121位于两个不同的像素单元组(在第二方向D2上相邻的两个像素单元组)；(2)如图2A、图3H和图3I所示，与图3H所示的第一像素电极121位于同一像素单元组的第二像素电极131位于与其相邻的栅线的下方，因此，在对与图3H所示的第一像素电极121位于同一像素单元组的第二像素电极131所在的像素进行充电之前，对与上述第二像素电极131相邻的栅线的扫描已经结束，因此，与图3H所示的第一像素电极121位于同一像素单元组的第二像素电极131的充电过程不受与其相邻的栅线的影响(或影响很小)。
如图3H和图3I所示，可以将第一像素电极121以及与该第一像素电极121相邻的栅线(例如，第二栅线142)在第二方向D2上的间距作为横向间距dpg1’，可以将第二像素电极131以及与该第二像素电极131相邻的栅线(例如，第二栅线142)在第二方向D2上的间距作为横向间距dpg2’。
如图3H和图3I所示，第一像素电极121以及与该第一像素电极121相邻的栅线之间的有效交叠长度lpg1’是指与该第一像素电极121相邻的栅线的对应于横向间距小于等于预定间距(例如，小于等于横向间距dpg1’)的区域在第一方向D1上的长度；第二像素电极131以及与该第二像素电极131相邻的栅线之间的有效交叠长度lpg2’是指与该第二像素电极131相邻的栅线的对应于横向间距dpg2’小于等于预定间距(例如，小于等于横向间距dpg2’)的区域在第一方向D1上的长度。
例如，在采用GOA(阵列基板上栅驱动集成)对栅线进行驱动的阵列基板的情况下，阵列基板具有预充电功能，电容Cpg’会导致像素(例如，有奇数行栅线驱动的像素)的像素电压进一步地降低，下面将结合图3J进行示例性说明。
图3J是电容Cpg’对像素电压Vp的影响的示意图。如图3J所示，Vgate1是位于奇数行的栅线，Vgate2是位于偶数行的栅线，Vp是位于偶数行的像素的像素电压。如图3J所示，在位于奇数行的栅线的信号处于上升沿时，受到电容Cpg’的影响，该像素的像素电压Vp有一个附加的增量，但由于该像素此时处于充电阶段，因此，上述附加的增量将被去除。如图3J所示，在位于 偶数行的栅线的信号处于下升沿时，受到电容Cpg’的影响，该像素的像素电压Vp有一个附加的降低量ΔVp’，并且由于该像素此时已不处于充电阶段，因此，上述附加的增量将无法被去除。
例如，本公开的发明人在研究中注意到，在长连接像素的电容Cgs和短连接像素的电容Cgs更为接近和/或长连接像素的电容Cpg和短连接像素的电容Cpg更为接近的情况下，长连接像素的像素电压跳变量ΔVp与短连接像素的像素电压跳变量ΔVp更为接近，由此可以使得显示不均匀现象(例如，摇头纹现象)减弱。下面结合图4A进行示例性说明。
图4A是本公开的至少一个实施例提供的另一种阵列基板100的平面示意图，图4A所示的阵列基板100与图2A所示的阵列基板包括以下区别：(1)图4A所示的阵列基板100具有Cgs补偿能力；(2)图4A所示的阵列基板100的长连接像素的像素电极的靠近驱动该长连接像素的栅线的一侧具有凹陷部；(3)图4A所示的阵列基板100的第一过孔和第二过孔与图2A所示的阵列基板100的第一过孔和第二过孔不同；(4)图4A所示的阵列基板100的公共电极图案与图2A所示的阵列基板100的公共电极图案不同。
需要说明的是，本公开的其它实施例提供的阵列基板与图2A所示的阵列基板的不同之处可以仅包括上述四个区别的部分(例如，一个或多个的任意组合)，不再赘述。
下面结合图4A-图4E、图5A-图5H以及图6-图11对图4A所示的阵列基板100进行示例性说明。
如图4A所示，该阵列基板100包括阵列排布的多个像素单元组110、多根第一栅线141、多根第二栅线142和多根数据线161；多根第一栅线141和多根第二栅线142分别大致沿第一方向D1延伸，多根数据线161大致沿与第一方向D1交叉(例如，垂直)的第二方向D2延伸。
每行像素单元组110被两根栅线驱动，上述两根栅线(一根第一栅线141和一根第二栅线142)在第二方向D2上位于该行像素单元组110两侧且与该行像素单元组110紧邻。此处，栅线与像素单元组110紧邻是指像素单元组110与上述栅线之间不包括其它栅线。在第二方向D2上相邻的两个像素单元组110之间设置了两根栅线，在第一方向D1上相邻的两个像素单元组110之间设置了一根数据线。下面结合图4A作示例性说明。
如图4A所示，每行像素单元组110对应于多根第一栅线141的一根和多 根第二栅线142的一根，上述多根第一栅线141的一根和多根第二栅线142的一根在第二方向D2上位于该行像素单元组110的两侧，且被配置为驱动该行像素单元组110。
如图4A所示，一根第一栅线141和一根第二栅线142设置在列方向(也即，第二方向D2)上相邻的像素单元组110之间，上述一根第一栅线141和一根第二栅线142分别用于驱动相邻行的像素单元组110。例如，多根第一栅线141和多根第二栅线142被配置为驱动与其相邻的像素单元组110(也即，栅线与被该栅线驱动的像素单元组110之间无其它栅线)。如图4A所示，一根数据线161设置在行方向(也即，第一方向D1)上相邻的像素单元组110之间。如图4A所示，多根第一栅线141和多根第二栅线142在第二方向D2上交替排布。
需要说明的是，多根第一栅线141和多根第二栅线142分别大致沿第一方向D1延伸仅限定了第一栅线141和第二栅线142的长度的延伸方向，而并不表示第一栅线141和第二栅线142平行于第一方向D1，也即是，根据实际应用需求，第一栅线141和第二栅线142可以平行于第一方向D1或者也可以部分不平行于第一方向D1。例如，为了更好的提升阵列基板100的开口率，多根第一栅线141和多根第二栅线142的部分区域可以设计成弯折的形式。例如，数据线161可以平行于第二方向D2或者也可以部分不平行于第二方向D2。
为清楚起见，下面针对多个像素单元组110中的一个像素单元组110进行示例性说明。
图4B是图4A所示的阵列基板100的像素单元组110的平面示意图，为方便描述，图4B还示出了第一栅线141、第二栅线142和数据线161。图4A所示的阵列基板100的部分或所有像素单元组110可以实现为图4B所示的像素单元组110。
如图4B所示，该像素单元组110包括在第一方向D1上并列紧邻布置的第一像素和第二像素。需要说明的是，并列紧邻布置的第一像素和第二像素是指上述第一像素和第二像素之间不包含其它像素。
如图4B所示，第一像素包括第一像素电极121、第一开关元件123以及从第一像素电极121延伸突出的第一连接部122，第二像素包括第二像素电极131、第二开关元件133以及从第二像素电极131延伸突出的第二连接部132； 第一像素电极121和第一开关元件123经由第一连接部122彼此电连接，第二像素电极131和第二开关元件133经由第二连接部132彼此电连接；第一连接部122的延伸长度不等于(例如，小于)第二连接部132的延伸长度。
例如，通过使得第一连接部122的延伸长度不等于(例如，小于)第二连接部132的延伸长度，可以将第一开关元件123和第二开关元件133均设置在像素单元组110的在第一方向D1上的边缘，下面结合图4B进行示例性说明。
例如，如图4B所示，像素单元组110包括在第一方向D1上彼此相对的第一边缘111和第二边缘112，相对于第二边缘112，第一开关元件123和第二开关元件133在第一方向D1均更靠近像素单元组110的第一边缘111。
例如，如图4B所示，每个像素单元组110的第一开关元件123和第二开关元件133均与同一根数据线161相连。例如，每个像素单元组110的第一开关元件123和第二开关元件133与上述同一根数据线161的距离均相同，此种情况下，每个像素单元组110的第一开关元件123与驱动该像素单元组110的数据线161之间的连接线的长度(在第一方向D1上的长度)可以等于每个像素单元组110的第二开关元件133与驱动该像素单元组110的数据线161之间的连接线的长度(在第一方向D1上的长度)。
例如，如图4A所示，与同一根数据线161相连的开关元件包括位于上述同一根数据线161的第一侧(例如，左侧)的开关元件以及位于上述同一根数据线161的第二侧(例如，右侧)的开关元件，位于上述同一根数据线161的第一侧(例如，左侧)的开关元件以及位于上述同一根数据线161的第二侧(例如，右侧)的开关元件在第一方向D1上部分重叠。
例如，通过使得位于上述同一根数据线161的第一侧(例如，左侧)的开关元件以及位于上述同一根数据线161的第二侧(例如，右侧)的开关元件在第一方向D1上部分重叠，可以降低开关元件(第一开关元件123和第二开关元件133)占据的区域在第二方向D2上的尺寸，因此可以降低用于遮挡开关元件的黑矩阵在第二方向D2上的尺寸，提升该阵列基板100以及包括该阵列基板100的显示面板和显示装置的开口率。
例如，如图4B所示，像素单元组110的第一连接部122和第二连接部132在第二方向D2上分别位于第一像素电极121的两侧；第一连接部122和第二连接部132在第二方向D2上均位于第一栅线141和第二栅线142之间。
例如，如图4B所示，第一连接部122的延伸突出的方向为第二方向D2，第二连接部132的延伸突出的方向为第一方向D1；在第二方向D2上，第二连接部132与第一像素电极121至少部分重叠；在第二方向D2上，第一像素电极121位于第一开关元件123和第二开关元件133之间。
例如，如图4B所示，第一开关元件123和第二开关元件133相对于第一像素电极121(或像素单元组110的)在第二方向D2上且沿第一方向D1延伸的中线对称设置(还可参见下方的图4D)。
例如，第一连接部122与第一像素电极121使用相同的材料一体形成，第二连接部132与第二像素电极131使用相同的材料一体形成。例如，可以使用同一构图工艺对相同的膜层构图形成第一连接部122、第一像素电极121、第二连接部132和第二像素电极131。
例如，如图4B所示，通过使得第一开关元件123和第二开关元件133在第一方向D1均更靠近像素单元组110的同一个边缘(例如，第一边缘111)，第一连接部122与第一像素电极121使用相同的材料一体形成，第二连接部132与第二像素电极131使用相同的材料一体形成，可以使得第一连接部122(第一连接部122的第一端1221，还可参见下方的图6)与第一像素电极121直接电性连接，且使得第二连接部132(第二连接部132的第一端1321，还可参见下方的图6)与第二像素电极131直接电性连接，因此，相比于图1所示的阵列基板，可以避免在靠近第一像素电极121和第二像素电极131的区域设置过孔，由此可以提升第一像素的显示区域和第二像素的显示区域的面积；尽管第一连接部122(第一连接部122的第二端1222)通过第一过孔1223与第一开关元件123电连接，第二连接部132(第二连接部132的第二端1322)通过第二过孔1323与第二开关元件133电连接，但是由于第一过孔1223靠近第一开关元件123，第二过孔1323靠近第二开关元件133，且靠近第一开关元件123和第二开关元件133的区域原本也对应于被黑矩阵遮挡的区域，因此，图4B所示的第一过孔1223和第二过孔1323不会降低像素单元组110以及阵列基板100的开口率。
例如，第一像素电极121和第二像素电极131均可以采用透明导电材料形成。例如，透明导电材料为氧化铟锡(ITO)或氧化铟锌(IZO)。对于第一连接部122与第一像素电极121使用相同的材料一体形成，且第二连接部132与第二像素电极131使用相同的材料一体形成的示例，第一连接部122和第 二连接部132也均可以使用透明导电材料形成(例如，ITO)。例如，透明导电材料(例如，ITO)的加工精度高于金属材料的加工精度，也即，透明导电材料走线的线宽可以小于金属材料走线的线宽；此种情况下，第一连接部122和第二连接部132占据的区域的尺寸可以降低，第一像素电极121和第二像素电极131占据的区域的尺寸可以对应的增加，由此可以提升像素单元组110以及阵列基板100的开口率。
例如，如图4A所示，与同一根数据线相连的，且位于该同一根数据线右侧的开关元件均用于驱动奇数行(或偶数行)的像素单元组；与同一根数据线相连的，且位于该同一根数据线左侧的开关元件均用于驱动偶数行(或奇数行)的像素单元组。
例如，如图4A所示，用于驱动每一像素单元组的第一开关元件123和第二开关元件133均在第一方向上设置在该像素单元组的设置了短连接像素的边缘。例如，如图4A所示，位于奇数行(或偶数行)的像素单元组的第一开关元件123和第二开关元件133均设置在像素单元组的左侧，位于偶数行(或奇数行)的像素单元组的第一开关元件123和第二开关元件133均设置在像素单元组的右侧。
例如，第一开关元件123和第二开关元件133均为薄膜晶体管(TFT)。例如，如图4A和图4B所示，第一开关元件123和第二开关元件133均为U型薄膜晶体管，也即，薄膜晶体管的源极(或漏极)为U型电极，薄膜晶体管的漏极(或源极)的至少部分设置在U型电极的开口中；U型薄膜晶体管的源极和漏极在第二方向D2上至少部分重叠。例如，如图4A所示，用于驱动相邻行的U型TFT的开口方向相反。例如，如图4A所示，用于驱动第一行的U型TFT的开口方向为向右，用于驱动第二行的U型TFT的开口方向为向左。
例如，该阵列基板100可以包括第一电极层172(参见图4C)、第一绝缘层173(参见图5C)、半导体层174(参见图5A和图5C)、第二电极层175(参见图5A)、第二绝缘层176(参见图5C)和第三电极层177(参见图6)，上述第一电极层172、第一绝缘层173、半导体层174、第二电极层175、第二绝缘层176和第三电极层177例如顺次设置在衬底基板171上。
图4C是图4A所示的阵列基板的第一电极层172的平面示意图。如图4C所示，第一电极层172包括多根第一栅线141、多根第二栅线142以及阵列排 布的公共电极图案150；多根第一栅线141和多根第二栅线142在第二方向D2上交替排布；多个公共电极图案150和多个像素单元组110一一对应；位于同一行的多个公共电极图案150位于用于驱动与同一行的多个公共电极图案150对应的像素单元组110的第一栅线141和第二栅线142之间。需要说明的是，在一些示例中，第一电极层172还可以不包括公共电极图案。
为清楚起见，公共电极图案150的具体结构以及公共电极图案150的之间的连接方式将在后面进行具体阐述，下面将结合图4D和图4E阐述第一栅线141和第二栅线142的结构。
图4D示出了图4A所示的阵列基板的第一栅线141和第二栅线142的平面示意图。
例如，如图4A和图4D所示，用于驱动每个像素单元组110的第一栅线141与用于驱动与每个像素单元组110在第二方向D2上相邻的像素单元组110的第二栅线142在第一方向D1上部分交叠，也即，在第二方向D2上位于相邻的像素单元组110之间的第一栅线141和第二栅线142在第一方向D1上部分交叠，由此可以降低栅线所占据区域在第二方向D2上的尺寸，由此可以提升阵列基板100的开口率以及包括该阵列基板100的显示面板和显示装置的开口率。
例如，如图4D所示，第一栅线141和第二栅线142相对于像素单元组110在第二方向D2上的沿第一方向D1延伸的中线113对称设置。
图4E示出了图4A所示的阵列基板的第一栅线141和第二栅线142的对应于一个像素单元组110的部分的平面示意图。例如，如图4E所示，第一栅线141包括第一栅极部1411，第二栅线142包括第二栅极部1421。例如，第一栅极部1411被配置为第一开关元件123的栅极，第二栅极部1421被配置为第二开关元件133的栅极，也即，第一开关元件123的U型电极(源极或漏极)在第一电极层172上的正投影与第一栅极部1411至少部分重叠，第二开关元件133的U型电极(源极或漏极)在第一电极层172上的正投影与第二栅极部1421至少部分重叠。
例如，如图4E所示，用于驱动每个像素单元组110的第一栅线141的第一栅极部1411与用于驱动与每个像素单元组110在第二方向D2上相邻的像素单元组110的第二栅线142的第二栅极部1421在第一方向D1上部分交叠，由此可以降低栅线所占据区域在第二方向D2上的尺寸，由此可以提升阵列基 板100的开口率以及包括该阵列基板100的显示面板和显示装置的开口率。例如，在第二方向D2上位于相邻的像素单元组110之间的两根栅线(第一栅线141和第二栅线142)的对应栅极部在第一方向D1上部分交叠。
例如，如图4E所示，第一栅线141还包括顺次相连的第一线部1412、第一线连接部1413和第三线部1414；第二栅线142还包括顺次相连的第二线部1422、第二线连接部1423和第四线部1424；第一线部1412与第一栅极部1411相连，第二线部1422与第二栅极部1421相连。例如，如图4E所示，第一线连接部1413包括朝向第一栅极部1411凸出的第一凸起143，第二线连接部1423包括朝向第二栅极部1421凸出的第二凸起144。
例如，如图4D和图4E所示，第一线部1412、第二线部1422、第三线部1414、第四线部1424分别平行于第一方向D1。
例如，如图4D和图4E所示，位于同一根栅线上的、对应于不同像素单元组且彼此相邻的栅极部和线连接部之间具有第一凹陷结构211，与上述同一根栅线相邻的栅线的线连接部设置在上述第一凹陷结构211中。
例如，如图4A和图4D所示，每根栅线可以同时驱动短连接像素和长连接像素，因此，每根栅线可以同时包括第一栅极部1411、第一线部1412、第一线连接部1413、第三线部1414、第二栅极部1421、第二线部1422、第二线连接部1423和第四线部1424。
例如，如图4A-图4D所示，栅线的对应于同一个像素单元组110的栅极部和线连接部在第一方向上并列布置并形成第二凹陷结构212，该栅线驱动的像素的过孔(例如，第一过孔或第二过孔)位于该第二凹陷结构212中。
需要说明的是，本公开的至少一个实施例提供的阵列基板100不限于多根第一栅线141和多根第二栅线142的每个均采用图4D所示的结构，根据实际应用需求，还可以使得多根第一栅线141和多根第二栅线142的部分采用采用图4D所示的结构，多根第一栅线141和多根第二栅线142的剩余的部分可以采用其它适用的栅线结构(例如，平直的栅线)，此处不再赘述。
在一些示例中，第一线连接部1413可以不包括第一凸起143，第二线连接部1423可以不包括第二凸起144。
图5A是图4A所示的阵列基板的半导体层174和第二电极层175的平面示意图。如图4B和图5A所示，第二电极层175包括多根数据线161、多个并列布置的第一源漏层以及多个并列布置的第二源漏层；第一源漏层包括第 一开关元件123的两个第一源漏极之一1241以及第一开关元件123的两个第一源漏极的另外一个1243(例如，U型电极)；第二源漏层包括第二开关元件124的两个第二源漏极之一1341以及第二开关元件124的两个第二源漏极的另外一个1343(例如，U型电极)。
需要说明的是，第一源漏层和第二源漏层位于同一层的不同区域，第一源漏层和第二源漏层在垂直于衬底基板的方向上间隔设置，可以使用同一构图工艺对同一膜层(例如，单层膜层)进行构图形成第一源漏层和第二源漏层。
图5B是图4A所示的阵列基板的第一开关元件123的平面示意图(扫描电子显微镜图获取的图像)，为描述方便，图5B还示出了部分第一栅线141、部分第一像素电极121、第一过孔1223。图5C是沿图5B所示的AA’线剖切获得的阵列基板100的截面示意图。图5D是本公开的至少一个实施例提供的第二开关元件133的平面示意图。
例如，如图5B和图5C所示，在垂直于衬底基板171的方向上，第一开关元件123包括第一栅极部1411(作为第一开关元件123的栅极、第一绝缘层173、半导体层174(第一半导体层125)以及第一源漏层；第一源漏层包括彼此相对并分立设置两个第一源漏极(也即，两个第一源漏极之一1241和两个第一源漏极的另外一个1243，例如，在第一开关元件123处于关闭状态时，两个第一源漏极彼此绝缘)。
例如，半导体层174包括第一半导体层125(半导体层174的对应于第一开关元件的区域)和第二半导体层(半导体层174的对应于第二开关元件的区域)。需要说明的是，第一半导体层125和第二半导体层位于同一层的不同区域，第一半导体层125和第二半导体层在垂直于衬底基板的方向上间隔设置，可以使用同一构图工艺对同一膜层(例如，单层膜层)进行构图形成第一半导体层125和第二半导体层。
例如，在垂直于衬底基板171的方向上，第二开关元件133包括第二栅极部1421(作为第二开关元件133的栅极、第一绝缘层173、半导体层174(第二半导体层)以及第二源漏层。如图4B所示，第二源漏层包括彼此相对并分立设置两个第二源漏极(也即，两个第二源漏极之一1341和两个第二源漏极的另外一个1343，例如，在第二开关元件133处于关闭状态时，两个第二源漏极彼此绝缘)。
例如，如图5C所示，阵列基板100还包括第二绝缘层176、第三电极层177以及设置在第二绝缘层176中的第一过孔1223和第二过孔1323。
图6是图4A所示的阵列基板100的第三电极层177的平面示意图。图7是图4A所示的阵列基板100的第一电极层172、半导体层174和第二电极层175的平面示意图，图8是图4A所示的阵列基板100的第一过孔1223、第二过孔1323和第三过孔153的平面示意图。
如图5B、图5C和图6所示，第三电极层177包括第一像素电极121、第一连接部122、第二像素电极131、第二连接部132以及第二公共电极连接部152。
如图5B、图5C和图6所示，第一连接部122包括第一端1221和第二端1222，第一连接部122的第一端1221与第一像素电极121直接电性连接，第一连接部122的第二端1222经由第一过孔1223与两个第一源漏极之一1241电连接。如5B和图5C所示，第一过孔1223是一种半过孔，也即，两个第一源漏极之一1241仅覆盖第一过孔1223的开口区域的一部分；如图5B和图5C所示，第一过孔1223的开口区域的另一部分位于两个第一源漏极之一1241的靠近第一像素电极121的一侧，且被第一像素电极121直接覆盖，也即，第一过孔1223的开口区域的另一部分的底部与第一像素电极121直接接触。
如图6和图4B所示，第二连接部132包括第一端1321和第二端1322，第二连接部132的第一端1321与第二像素电极131直接电性连接，第二连接部132的第二端1322经由第二过孔1323与第二源漏极之一1341电连接；如图5D所示，第二源漏极之一1341覆盖第二过孔1323的开口区域的一部分1324，第二过孔1323的开口区域的另一部分1325位于第二源漏极之一1341的靠近第一像素电极121的一侧，且被第二像素电极131直接覆盖，也即，第二过孔1323的开口区域的另一部分1325的底部与第二像素电极131直接接触。
需要说明的是，第一过孔1223和第二过孔1323的设置方式不限于图5B和图5C所示设置方式，根据实际应用需求，第一过孔1223和第二过孔1323还可以选用其它适用的设置方式。下面结合图2A所示的阵列基板100进行示例性说明。
图5E示出了图2A所示的阵列基板100的部分区域的平面示意图，图5F是图5E所示的阵列基板100的区域RC4的平面示意图(扫描电子显微镜获 取)。
如图5E和图5F所示，图2A所示的阵列基板100的第一过孔1223和第二过孔1323也均是一种半过孔，也即，第一开关元件123的两个第一源漏极之一1241(例如，第一漏极)仅覆盖第一过孔1223的开口区域的一部分1224；第二开关元件133的两个第二源漏极之一1341(例如，第二漏极)仅覆盖第二过孔1323的开口区域的一部分1324。
如图5E和图5F所示，第一过孔1223的开口区域的另一部分1225位于两个第一源漏极之一1241的远离第一像素电极121的一侧，第二过孔1323的开口区域的另一部分1325位于第二源漏极之一1341的远离第一像素电极121的一侧。在一些示例中，图5E和图5F所示的阵列基板，第一线连接部1413也可以包括第一凸起，第二线连接部1423也可以包括第二凸起；然而，此种情况下，如果第一凸起和第二凸起的位置偏移，则该额外增加的第一凸起可能经由第一过孔与第一像素电极电连接(短路)，该额外增加的第二凸起可能经由第二过孔与第二像素电极电连接(短路)。因此，相比于图5E和图5F所示的第一过孔1223的结构，通过将图5B和图5C所示的第一过孔1223的开口区域的另一部分1225设置在两个第一源漏极之一1241的远离第一像素电极121的一侧，可以降低图5B和图5C所示的阵列基板的第一凸起143与第一连接部122短路的风险，通过将图5F所示的第二过孔1323的开口区域的另一部分1325设置在第二源漏极之一1341的远离第一像素电极121的一侧，可以降低图5B和图5C所示的阵列基板的第二凸起144与第二连接部132短路的风险。
以下将结合图4B和图5B阐述图4B所示的阵列基板的Cgs补偿功能以及摇头纹抑制功能。
如图5B所示，第一栅线141在第二导电层(第一源漏层)上的正投影与两个第一源漏极之一1241在至少两个不同的位置处交叠；例如，如图5B所示，第一栅线141在第一源漏层上的正投影与两个第一源漏极之一1241在第一方向D1上的两侧至少部分交叠。
例如，通过使得第一栅线141在第一源漏层上的正投影与两个第一源漏极之一1241在第一方向D1上的两侧至少部分交叠，可以降低第一栅线和第一源漏层之间的形成的电容取值的变化幅度；由于第一栅线和第一源漏层之间的形成的电容取值的变化幅度与摇头纹正相关，因此，通过降低第一栅线 和第一源漏层之间的形成的电容取值的变化幅度，可以抑制避免用于制作第二电极层175的掩膜版相对于第一电极层172偏移导致的摇头纹不良。
例如，为方便描述，以下实施例将与数据线161相连的第一源漏极和第二源漏极分别称为第一源极和第二源极，与像素电极相连的第一源漏极和第二源漏极分别称为第一漏极和第二漏极；然而，本公开的实施例不限于此；在其它一些实施例中，与数据线161相连的第一源漏极和第二源漏极可以分别称为第一漏极和第二漏极，与像素电极相连的第一源漏极和第二源漏极分别称为第一源极和第二源极。
图5G是图4A所示的阵列基板的栅线所在的电极层与源漏极所在的电极层在栅线所在的电极层的正投影之间的交叠区域的第一个示意图(对应于第一开关元件)；图5H是图4A所示的阵列基板的栅线所在的电极层与源漏极所在的电极层在栅线所在的电极层的正投影之间的交叠区域的第二个示意图(对应于第二开关元件)。
例如，如图5G所示，除第一栅线141(第一栅线141的第一栅极部1411)在第一源漏层上的正投影与第一漏极的靠近第一源极一侧的区域(例如，左侧)交叠之外，第一栅线141(第一栅线141的第一线连接部1413)在第一源漏层上的正投影还与第一漏极的远离第一源极一侧的区域(例如，右侧)交叠。
例如，如图5G所示，第一凸起143在两个第一源漏极之一1241(例如，第一漏极)上的正投影与两个第一源漏极之一1241(例如，第一漏极)至少部分交叠，第一凸起143在两个第一源漏极之一1241(例如，第一漏极)上的正投影与两个第一源漏极之一1241(例如，第一漏极)的交叠区域为第一交叠区域145。例如，如图5G所示，第一栅极部1411在第一漏极上的正投影与第一漏极的交叠区域为第二交叠区域146。
如图5G所示，在第一源漏层相对于第一电极层172(例如，第一栅极部1411)向右偏移时，第一交叠区域145的尺寸增加，第二交叠区域146的尺寸降低；在第一源漏层相对于第一电极层172(例如，第一栅极部1411)向左偏移时，第一交叠区域145的尺寸降低，第二交叠区域146的尺寸增加；因此，相比于未设置第一交叠区域145的示例，通过设置第一交叠区域145，可以降低栅线和第一源漏层之间的形成的电容(Cgs1)取值的变化(因第一源漏层相对于第一电极层172偏移而导致)的幅度，由此可以抑制包含该阵 列基板100的显示面板和显示装置的摇头纹不良。
如图5G所示，第一交叠区域145具有在与第一方向D1交叉的第二方向D2上的第一交叠边缘1451，第二交叠区域146具有在与第一方向D1交叉的第二方向D2上的第二交叠边缘1461，且第一交叠边缘1451的长度和第二交叠边缘1461的长度相等；此种情况下，可以进一步地可以降低栅线和第一源漏层之间的形成的电容(Cgs1)的取值的变化(因第一源漏层相对于第一电极层172偏移而导致)的幅度以及第一像素的像素电压跳变量的变化幅度。
例如，如图5H所示，第二栅线142在第二源漏层上的正投影与两个第二源漏极之一1341在至少两个不同的位置处交叠；第二栅线142在第二源漏层上的正投影与两个第二源漏极之一1341在第一方向D1上的两侧至少部分交叠。
例如，如图5H所示，除第二栅线142(第二栅线142的第二栅极部1421)在第二源漏层上的正投影与第二漏极的靠近第二源极一侧的区域交叠之外，第二栅线142(第二栅线142的第二线连接部1423)在第二源漏层上的正投影与第二漏极的远离第二源极一侧的区域交叠。
例如，如图5H所示，第二凸起144在第二源漏极之一1341(例如，第二漏极)上的正投影与第二源漏极之一1341(例如，第二漏极)至少部分交叠，第二凸起144在第二源漏极之一1341(例如，第二漏极)上的正投影与两个第二源漏极之一1341(例如，第二漏极)的交叠区域为第三交叠区域147。例如，如图5H所示，第二栅极部1421在第二漏极上的正投影与第二漏极的交叠区域为第四交叠区域148。例如，相比于未设置第三交叠区域147的示例，通过设置第三交叠区域147，可以降低栅线和第二源漏层之间的形成的电容(Cgs2)取值的变化(因第二源漏层相对于第一电极层172偏移而导致)的幅度，由此可以抑制包含该阵列基板100的显示面板和显示装置的摇头纹不良。
例如，第三交叠区域147具有在与第一方向D1交叉的第二方向D2上的第三交叠边缘1471，第四交叠区域148具有在与第一方向D1交叉的第二方向D2上的第四交叠边缘1481，第三交叠边缘1471的长度和第四交叠边缘1481的长度相等；此种情况下，可以进一步地可以降低栅线和第二源漏层之间的形成的电容(Cgs2)的取值的变化(因第二源漏层相对于第一电极层172偏移而导致)的幅度以及第二像素的像素电压跳变量的变化幅度。
在一些示例中，第一交叠区域145的平面形状、第二交叠区域146的平面形状、第三交叠区域147的平面形状以及第四交叠区域148的平面形状实质上均为矩形，第一交叠区域145在第二方向D2上的尺寸等于第二交叠区域146在第二方向D2上的尺寸，且第三交叠区域147在第二方向D2上的尺寸等于第四交叠区域148在第二方向D2上的尺寸。需要说明的是，在一些示例中，在确定第二交叠区域146时，可以将设置在第一栅极部1411和第一漏极之间的第一半导体层125纳入考虑，也即，将第一漏极和第一半导体层125的结合结构在第一栅极部1411上的正投影与第一栅极部1411的交叠区域作为第二交叠区域146；对应地，在确定第四交叠区域148时，可以将第二漏极和第二半导体层的结合结构在第二栅极部1421上的正投影与第二栅极部1421的交叠区域作为第四交叠区域148。
例如，第一栅线141在第一源漏层上的正投影与两个第一源漏极之一1241的交叠面积为第一值，第二栅线142在第二源漏层上的正投影与两个第二源漏极之一1341的交叠面积为第二值，第一值等于第二值；此种情况下，栅线和第一源漏层之间的形成的电容(Cgs1)以及栅线和第二源漏层之间的形成的电容(Cgs2)彼此相等，以及第一像素的像素电压跳变量以及第二像素的像素电压跳变量比较接近(例如，相等)，由此可以进一步地抑制包含该阵列基板100的显示面板和显示装置的摇头纹不良。
以下结合图9阐述图4A所示的阵列基板的其它用于提升包括该阵列基板的显示面板的显示均匀度的技术方案。
在一个示例中，第一像素电极121与驱动第一像素的栅线在第二方向D2上彼此交叠，第二像素电极131与驱动第二像素的栅线在第二方向D2上彼此交叠。图9示出了本公开至少一个实施例提供的像素电极与驱动该像素电极所在的像素的栅线的间距和交叠长度的示意图。
如图9所示，第一像素电极121与驱动第一像素的栅线的横向间距dpg1是第一像素电极121的靠近用于驱动第一像素的栅线(例如，图9所示的第一栅线141)的边缘与用于驱动第一像素的栅线之间的间距，第二像素电极131与驱动第二像素的栅线(例如，图9所示的第二栅线142)的横向间距dpg2是第二像素电极131的靠近用于驱动第二像素的栅线的边缘与用于驱动第二像素的栅线之间的间距。例如，由于第一像素电极121所在的第三电极层177以及用于驱动第一像素的栅线所在的第一电极层172的间距(在垂直于第一 电极层172方向上的间距)较小，如图9所示，可以将第一像素电极121与用于驱动第一像素的栅线(例如，图9所示的第一栅线141)在第二方向D2上的间距作为横向间距dpg1，将第二像素电极131与用于驱动第二像素的栅线(例如，图9所示的第二栅线142)在第二方向D2上的间距作为横向间距dpg2。本公开的其它实施例的横向间距具有类似的定义，不再赘述。
如图9所示，第一像素电极121和第一连接部122的结合结构与驱动第一像素的栅线的有效交叠长度是指驱动第一像素的栅线的对应于横向间距dpg1小于等于预定间距(例如，六微米)的区域在第一方向D1上的长度；第二像素电极131和第二连接部132的结合结构与驱动第二像素的栅线的有效交叠长度是指驱动第二像素的栅线的对应于横向间距dpg2小于等于预定间距(例如，六微米)的区域在第一方向D1上的长度。
在一个示例中，第一像素电极121与驱动第一像素的栅线的横向间距大于五微米，第二像素电极131与驱动第二像素的栅线的横向间距大于五微米。例如，本公开的发明人通过多次试验和分析得到，通过使得第一像素电极121与驱动第一像素的栅线的横向间距大于五微米可以降低以下因素对第一像素的电容Cpg的影响：第一像素电极121与驱动第一像素的栅线的横向间距(例如，因制造工艺导致的变化)的变化；第一像素电极121和第一连接部122与驱动第一像素的栅线的有效交叠长度的变化；通过使得第二像素电极131与驱动第二像素的栅线的横向间距大于五微米，可以降低降低以下因素对第二像素的电容Cpg的影响：第二像素电极131与驱动第二像素的栅线的横向间距的变化；第二像素电极131和第二连接部132与驱动第二像素的栅线的有效交叠长度的变化；因此，可以在不劣化摇头纹的情况下，可以降低对制造工艺的要求。
在一个示例中，如图9所示，第一连接部122的延伸长度小于第二连接部132的延伸长度，第一像素电极和第一连接部的结合结构与第一栅线的有效交叠长度小于第二像素电极和第二连接部的结合结构与第二栅线的有效交叠长度，第二像素电极131的靠近驱动第二像素的栅线的一侧具有凹陷部。
例如，通过使得长连接像素(例如，第二像素)的像素电极的靠近驱动该长连接像素的栅线的一侧具有凹陷部，可以缩短长连接像素的像素电极和连接部的结合结构与栅线的有效交叠长度lpg；此种情况下，长连接像素的像素电极和连接部的结合结构与栅线的有效交叠长度与短连接像素(例如，第 一像素)的像素电极和连接部的结合结构与栅线的有效交叠长度更为接近，因此，可以使得长连接像素的电容Cpg与短连接像素的电容Cpg更为接近，由此可以进一步地抑制摇头纹不良。
在一个示例中，第一像素电极121和第一连接部122的结合结构与驱动第一像素的栅线的有效交叠长度等于第二像素电极131和第二连接部132的结合结构与驱动第二像素的栅线的有效交叠长度，由此可以进一步地抑制摇头纹不良。
在一个示例中，第一像素电极121以及与第一像素电极121相邻的栅线(但不用于驱动该第一像素电极121所在的第一像素)在第二方向D2上彼此交叠，第二像素电极131以及与第二像素电极131相邻的栅线(但不用于驱动该第二像素电极131所在的第二像素)在第二方向D2上彼此交叠。
需要说明的是，在与第二像素电极131相邻的栅线位于上述第二像素电极131上方时，与第二像素电极131相邻的栅线对上述第二像素电极131充电过程的影响较小或没有影响，因此，在以下描述Cpg’对显示面板显示均匀性的影响时阐述的长连接像素的第二像素电极131位于与其相邻的栅线(但不驱动该像素)的上方，也即，在以下描述Cpg’对显示面板显示均匀性的影响时涉及的第一像素电极121和第二像素电极131不是位于同一像素单元组而是位于同一列。
在一些示例中，为了进一步地降低长连接像素以及短连接像素的电容Cpg’对显示面板显示均匀性的影响，抑制摇头纹不良，可以使得横向间距dpg1’(例如，将第一像素电极121以及与该第一像素电极121相邻的栅线在第二方向D2上的间距)和横向间距dpg2’(例如，第二像素电极131以及与该第二像素电极131相邻的栅线在第二方向D2上的间距)尽可能的大，并使得有效交叠长度lpg1’(例如，第一像素电极121以及与该第一像素电极121相邻的栅线之间的有效交叠长度)等于有效交叠长度lpg2’(第二像素电极131以及与该第二像素电极131相邻的栅线之间的有效交叠长度)；或者可以使得长连接像素以及短连接像素的电容Cpg对显示面板显示均匀性的影响完全相同或相近。
以下将结合图10和图11阐述多个公共电极图案150的结构和彼此之间的连接关系。图10是本公开至少一个实施例提供的阵列基板100的阵列排布的公共电极图案150的平面示意图，图11是本公开至少一个实施例提供的阵 列基板100的公共电极图案150的平面示意图。
如图10所示，在第一方向D1上相邻的公共电极图案150通过第一公共电极连接部151彼此电连接，第一公共电极连接部151与公共电极图案150同层，位于不同行的公共电极图案150彼此间隔设置。
如图10所示，在第二方向D2上相邻的公共电极图案150通过第二公共电极连接部152彼此电连接，第二公共电极连接部152与第一连接部122同层，第二公共电极连接部152与对应的公共电极图案150通过第三过孔153电连接。
如图10和图11所示，至少一个(每个)公共电极图案150包括主体部154以及从主体部154的第一侧伸出的第一凸出部155以及两个第二凸出部156构成；第一凸出部155以及两个第二凸出部156分别沿第二方向D2延伸；第一凸出部155在第一方向D1上设置在两个第二凸出部156之间，第一公共电极连接部151设置在在第一方向D1上相邻的两个公共电极图案150的第二凸出部156之间，且第一公共电极连接部151的两端分别与在第一方向D1上相邻的两个公共电极图案150的第二凸出部156直接电性相连。
如图10所示，在第二方向D2上相邻的公共电极图案150通过相邻的公共电极图案150的第一凸出部155和第三过孔153电连接。例如，第一凸出部155的不与主体部154相连的一端包括扩大部158，在第二方向D2上相邻的公共电极图案150通过相邻的公共电极图案150的扩大部158、第三过孔153和第二公共电极连接部152电连接。例如，通过使得第一凸出部155的不与主体部154相连的一端包括扩大部158，可以提升第二公共电极连接部152的设计自由度。
需要说明的是，图10所示的第二公共电极连接部152仅用于示意性的示出位于不同行的公共电极图案150的连接方式，但第二公共电极连接部152的形状和结构不限于此。例如，第二公共电极连接部152还可以采用如图6所示的第二公共电极连接部152的形状和结构，不再赘述。
如图10所示，至少一个(每个)公共电极图案150的平面形状可以为“E”型，且上述至少一个(每个)公共电极图案150的开口方向(也即，“E”型的开口方)与列方向上相邻的公共电极图案150的开口方向均相反。例如，每个公共电极图案150的主体部154和与上述每个公共电极图案150在第二方向上相邻的一个公共电极图案150的主体部154对置，且每个公共电极图 案150的开口和与上述每个公共电极图案150第二方向上相邻的另一个公共电极图案150的开口对置。
在一个示例中，如图10所示，对于位于同一列的公共电极图案，位于奇数列的公共电极图案150的开口方向彼此相同，位于偶数列的公共电极图案150的开口方向彼此相同，在第二方向上相邻的两个公共电极图案150的开口方向彼此不同。
如图10所示，至少一个(每个)公共电极图案150的主体部154的远离该公共电极图案150的第一凸出部155的一侧具有凹陷部，并且，如图4B所示，上述至少一个(每个)公共电极图案150的主体部154的凹陷部与对应的公共电极图案150的凹陷部对应(例如，至少部分重叠)。
例如，如图4B、图6和图10所示，每个公共电极图案150的主体部154在第二方向上设置在设置了对应于该公共电极图案150的像素单元组110的第二连接部132的一侧，每个公共电极图案150的开口在第二方向上设置在设置了对应于该公共电极图案150的像素单元组110的第一连接部122的一侧。
需要说明的是，在一些示例中，公共电极图案150还可以被称为公共电极线或公共数据线。
在一些示例中(对于TN模式的显示面板)，显示面板的对置基板还包括一层公共电极层(例如，由诸如ITO的透明导电材料制成)，公共电极层与公共电极图案150通过导电部(例如，导电金球)电连接。
在另一些示例中(对于基于高级超维场转换技术的显示面板)，阵列基板还包括一层公共电极层(例如，图案化的公共电极层，其与栅线彼此绝缘)，公共电极图案150与公共电极层彼此电连接。例如，公共电极图案150与公共电极层可以直接电性连接或通过过孔连接。例如，在公共电极图案150与公共电极层直接电性连接时，公共电极层可以位于公共电极图案150的远离数据线的一侧。
本公开的至少一个实施例还提供了一种摇头纹的实验分析方法，通过实验数据分析得出，在显示面板显示灰度为127的图像且像素之间相差6个灰阶时，即可看到明显的摇头纹。下面对摇头纹的实验分析方法以及用于摇头纹研究的实验设计方案。
例如，用于摇头纹研究的实验设备包括点灯机，探测器(例如，型号为 CA310)以及直流电源。
摇头纹研究的实验包括以下的步骤S501-步骤S505。
步骤S501：将待检的样品(显示面板)进行外灌公共电压Vcom处理，也即，使用显示面板外部的直流电源(直流电压)，向显示面板内的公共电极或公共电极图案施加公共电压Vcom。
步骤S502：用点灯机编辑图形，将相同结构、相同极性的像素点亮(127灰阶)，其他像素不亮(0灰阶)。
步骤S503：将探测器(例如，型号为CA310)的测量探头垂直放置于样品中间，用于测试其闪烁程度(闪烁值)。
步骤S504：调节公共电压Vcom，直至闪烁值最小，则此时的公共电压Vcom即为此像素结构的最佳公共电压Vcom。
步骤S505：针对一个周期内所有子像素，重复上述步骤步骤S501-步骤S504，直至测试出一个周期内所有子像素(12个)的最佳公共电压Vcom。
然后基于以上测试结果进行摇头纹分析。
根据闪烁的机理，当闪烁值最小时，可近似认为此时像素的正负帧亮度相同，因此，当闪烁值最小时，公共电压Vcom与像素电压的跳变量△Vp关系如下所示，
Vcom＝Vcenter-△Vp。
因此，当闪烁值最小时，公共电压Vcom与像素电压的跳变量△Vp成反比，由此可通过Vcom的差异推算出不同像素之间的像素电压的跳变量△Vp的差异。
表1示出了一款21.5英寸的扭曲向列型显示面板(全高清)的一个周期内像素(像素P1-P6)的最佳公共电压Vcom，像素P1-P6例如分别为红色、绿色、蓝色、红色、绿色和蓝色子像素。
表1 21.5英寸的扭曲向列型显示面板(全高清)的子像素的最佳公共电压
Figure PCTCN2019096151-appb-000004
如表1所示，当显示面板存在摇头纹不良时，不同子像素的最佳公共电压Vcom差值为0.05V；当显示面板不存在摇头纹不良时，不同子像素的最佳公共电压Vcom差值为0.02V。例如，基于表1中的数据，可以拟合出在127灰阶附近的VT曲线(也即，电压与显示面板透射率之间的曲线)，并结合gamma曲线可以得出，在像素电压差异0.05V，灰阶差异为6个灰阶时，摇头纹比较明显。
本公开的至少一个实施例还提供了一种显示面板，其包括本公开的实施例提供的任一阵列基板。本公开的至少一个实施例还提供了一种显示装置，其包括本公开的实施例提供的任一阵列基板或本公开的实施例提供的任一显示面板。
图12示出了一种显示面板的示例性框图以及一种显示装置的示例性框图。如图12所示，该显示面板10包括阵列基板100，该显示装置包括显示面板10。
需要说明的是，对于该显示基板10和显示装置20的其它组成部分(例如，薄膜晶体管、控制装置、图像数据编码/解码装置、行扫描驱动器、列扫描驱动器、时钟电路等)可以采用适用的部件，这些均是本领域的普通技术人员所应该理解的，在此不做赘述，也不应作为对本公开的限制。该显示基板10和显示装置20具体提升开口率的能力或基础。
本公开的至少一个实施例还提供了一种阵列基板的制作方法，其包括：形成像素单元组。像素单元组包括在第一方向上并列布置的第一像素和第二像素；第一像素包括第一像素电极、第一开关元件以及从第一像素电极延伸突出的第一连接部，第二像素包括第二像素电极、第二开关元件以及从第二像素电极延伸突出的第二连接部；第一像素电极和第一开关元件经由第一连接部彼此电连接，第二像素电极和第二开关元件经由第二连接部彼此电连接；以及第一连接部的长度不等于第二连接部的长度。
例如，形成像素单元组包括：使用同一构图工艺对相同的膜层构图形成第一连接部、第一像素电极、第二连接部和第二像素电极。
例如，该阵列基板的制作方法可以包括以下的步骤S101-步骤S108。
步骤S101：提供衬底基板。
步骤S102：在衬底基板上形成第一电极层。
步骤S103：在形成了第一电极层的衬底基板上形成第一绝缘层。
步骤S104：在形成了第一绝缘层的衬底基板上形成半导体层。
步骤S105：在形成了半导体层的衬底基板上形成第二电极层。
步骤S106：在形成了第二电极层的衬底基板上形成第二绝缘层。
步骤S107：在第二绝缘层中形成第一过孔、第二过孔和第三过孔。
步骤S108：在形成了第一过孔、第二过孔和第三过孔的衬底基板上形成第三电极层。
下面以图4A示出的阵列基板对本公开的至少一个实施例提供的阵列基板的制作方法进行示例性说明。
例如，衬底基板可以是玻璃基板、石英基板、塑料基板(例如聚对苯二甲酸乙二醇酯(PET)基板)或者由其它适合的材料制成的基板。
例如，第一电极层(参见图4C)包括多根第一栅线、多根第二栅线、阵列排布的公共电极图案以及多个第一公共电极连接部。例如，步骤S102包括：在衬底基板上形成第一电极膜；使用同一构图工艺对第一电极膜构图形成多根第一栅线、多根第二栅线、阵列排布的公共电极图案以及多个第一公共电极连接部，也即，形成第一电极层。例如第一电极层可以采用金属材料(例如，铜、铝或者铝合金)或其它适用的材料形成。
例如，第一绝缘层(参见图5C)的材料可以是氧化硅(SiOx)、氧氮化硅(SiNxOy)、氮化硅(SiNx)或者其它适合的材料。
例如，半导体层(参见图5A和图5C)的材料可以由氧化物半导体材料制成，但本公开的实施例不限于此。例如，该氧化物半导体材料例如可以包括ZnO、MgZnO、Zn-Sn-O(ZTO)、In-Zn-O(IZO)、SnO2、Ga2O3、In-Ga-O(IGO)、In2O3、In-Sn-O(ITO)、In-Ga-Zn-O(IGZO)、In-Zn-Sn-O(IZTO)、In-Ga-Zn-Sn-O(IGZTO)和InAlZnO(IAZO)等，但本公开的实施例的半导体层不限于由上述具体的氧化物半导体材料制成。
例如，第二电极层(参见图5A)包括多根数据线、多个开关元件的源极和漏极。例如，步骤S105包括：在半导体层上形成第二电极膜；使用同一构图工艺对第二电极膜构图形成多根数据线、多个开关元件的源极和漏极，也即，形成第二金属层。例如，第二电极层可以采用金属材料(例如，铜、铝或者铝合金)或其它适用的材料形成。
例如，第二绝缘层可以采用无机或有机材料形成。例如，第二绝缘层可以采用有机树脂、氧化硅(SiOx)、氧氮化硅(SiNxOy)或者氮化硅(SiNx) 形成。
例如，在步骤S107中，在第二绝缘层中对应于两个第一源漏极之一的远离U型电极(两个第一源漏极的另一个)一侧的端部的位置处形成第一过孔，在第二绝缘层中对应于第二源漏极之一的远离U型电极(两个第二源漏极的另一个)一侧的端部的位置处形成第二过孔，在第二绝缘层中对应于公共电极图案的第一凸出部(例如，第一凸出部的扩大部158)的位置处形成第三过孔。
例如，第三电极层177(参见图6)包括第一像素电极、第二像素电极、第一连接部、第二连接部和第二公共电极连接部。
例如，步骤S108包括：在形成了第一过孔、第二过孔和第三过孔的衬底基板上形成第三电极膜；使用同一构图工艺对第三电极膜构图形成第一像素电极、第二像素电极、第一连接部、第二连接部和第二公共电极连接部。例如，第三电极层可以采用透明导电材料形成。例如，透明导电材料为氧化铟锡(ITO)或氧化铟锌(IZO)。
虽然上文中已经用一般性说明及具体实施方式，对本公开作了详尽的描述，但在本公开实施例基础上，可以对之作一些修改或改进，这对本领域技术人员而言是显而易见的。因此，在不偏离本公开精神的基础上所做的这些修改或改进，均属于本公开要求保护的范围。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (22)

  1. 一种阵列基板，包括：像素单元组，其中，所述像素单元组包括在第一方向上并列紧邻布置的第一像素和第二像素；
    所述第一像素包括第一像素电极、第一开关元件以及从所述第一像素电极延伸突出的第一连接部，
    所述第二像素包括第二像素电极、第二开关元件以及从所述第二像素电极延伸突出的第二连接部；
    所述第一像素电极和所述第一开关元件经由所述第一连接部彼此电连接，
    所述第二像素电极和所述第二开关元件经由所述第二连接部彼此电连接；以及
    所述第一连接部的延伸长度不等于所述第二连接部的延伸长度。
  2. 根据权利要求1所述的阵列基板，其中，所述像素单元组包括在所述第一方向上彼此相对的第一边缘和第二边缘，
    相对于所述第二边缘，所述第一开关元件和所述第二开关元件在所述第一方向均更靠近所述像素单元组的第一边缘。
  3. 根据权利要求1或2所述的阵列基板，其中，在与所述第一方向交叉的第二方向上，所述第一像素电极位于所述第一开关元件和所述第二开关元件之间；
    所述第一连接部的延伸突出的方向为所述第二方向，所述第二连接部的延伸突出的方向为所述第一方向；
    在所述第二方向上，所述第二连接部与所述第一像素电极至少部分重叠；以及
    所述第一开关元件和所述第二开关元件相对于所述第一像素电极在所述第二方向上且沿所述第一方向延伸的中线对称设置。
  4. 根据权利要求1-3任一所述的阵列基板，其中，所述第一连接部与所述第一像素电极使用相同的材料一体形成，所述第二连接部与所述第二像素电极使用相同的材料一体形成。
  5. 根据权利要求1-4任一所述的阵列基板，其中，所述第一开关元件包括第一源漏层，所述第一源漏层包括彼此相对且间隔设置的两个第一源漏极；
    所述第二开关元件包括第二源漏层，所述第二源漏层包括彼此相对且间隔设置的两个第二源漏极；
    所述第一连接部与所述第一像素电极直接电性连接，所述第一连接部还经由第一过孔与所述两个第一源漏极之一电连接；以及
    所述第二连接部与所述第二像素电极直接电性连接，所述第二连接部还经由第二过孔与所述两个第二源漏极之一电连接。
  6. 根据权利要求5所述的阵列基板，其中，所述两个第一源漏极之一覆盖所述第一过孔的开口区域的一部分，所述第一过孔的开口区域的另一部分位于所述第一源漏极之一的靠近所述第一像素电极的一侧；以及
    所述两个第二源漏极之一覆盖所述第二过孔的开口区域的一部分，所述第二过孔的开口区域的另一部分位于所述第二源漏极之一的靠近所述第一像素电极的一侧。
  7. 根据权利要求5或6所述的阵列基板，其中，所述阵列基板还包括分别沿所述第一方向延伸的第一栅线和第二栅线；
    所述第一栅线和所述第二栅线在与所述第一方向交叉的第二方向上位于所述像素单元组的两侧；以及
    所述第一栅线在所述第一源漏层上的正投影与所述两个第一源漏极之一在至少两个不同的位置处交叠和所述第二栅线在所述第二源漏层上的正投影与所述两个第二源漏极之一在至少两个不同的位置处交叠。
  8. 根据权利要求7所述的阵列基板，其中，所述第一栅线包括顺次相连的第一栅极部、第一线部、第一线连接部；
    所述第二栅线包括顺次相连的第二栅极部、第二线部、第二线连接部；
    所述第一栅极部被配置为所述第一开关元件的栅极，所述第二栅极部被配置为所述第二开关元件的栅极；
    所述第一栅线在所述第一源漏层上的正投影与所述两个第一源漏极之一在所述第一方向上的两侧至少部分交叠；以及
    所述第二栅线在所述第二源漏层上的正投影与所述两个第二源漏极之一在所述第一方向上的两侧至少部分交叠。
  9. 根据权利要求8所述的阵列基板，其中，所述第一栅线的第一线连接部在所述两个第一源漏极之一上的正投影与所述两个第一源漏极之一至少部分交叠，
    所述第二栅线的第二线连接部在所述两个第二源漏极之一上的正投影与所述两个第二源漏极之一至少部分交叠。
  10. 根据权利要求8或9所述的阵列基板，其中，所述第一线连接部包括朝向所述第一栅极部凸出的第一凸起，所述第二线连接部包括朝向所述第二栅极部凸出的第二凸起；以及
    所述第一凸起在所述两个第一源漏极之一上的正投影与所述两个第一源漏极之一至少部分交叠，所述第二凸起在所述两个第二源漏极之一上的正投影与所述两个第二源漏极之一至少部分交叠。
  11. 根据权利要求10所述的阵列基板，其中，所述第一凸起在所述两个第一源漏极之一上的正投影与所述两个第一源漏极之一的交叠区域为第一交叠区域，且所述第一交叠区域具有在与所述第一方向交叉的第二方向上的第一交叠边缘；
    所述第一栅极部在所述两个第一源漏极之一上的正投影与所述两个第一源漏极之一的交叠区域为第二交叠区域，所述第二交叠区域具有在所述第二方向上的第二交叠边缘；
    所述第一交叠边缘的长度和所述第二交叠边缘的长度相等；
    所述第二凸起在所述两个第二源漏极之一上的正投影与所述两个第二源漏极之一的交叠区域为第三交叠区域，所述第三交叠区域具有在所述第二方向上的第三交叠边缘；
    所述第二栅极部在所述两个第二源漏极之一的正投影与所述两个第二源漏极之一的交叠区域为第四交叠区域，所述第四交叠区域具有在所述第二方向上的第四交叠边缘；以及
    所述第三交叠边缘的长度和所述第四交叠边缘的长度相等。
  12. 根据权利要求7-11任一所述的阵列基板，其中，所述第一栅线在所述第一源漏层上的正投影与所述两个第一源漏极之一的交叠面积为第一值；
    所述第二栅线在所述第二源漏层上的正投影与所述两个第二源漏极之一的交叠面积为第二值；以及
    所述第一值等于所述第二值。
  13. 根据权利要求5或6所述的阵列基板，其中，所述阵列基板还包括分别沿所述第一方向延伸的第一栅线和第二栅线；
    所述第一栅线和所述第二栅线在与所述第一方向交叉的第二方向上位于 所述像素单元组的两侧；以及
    所述第一栅线在所述第一源漏层上的正投影与所述两个第一源漏极之一在至少两个不同的位置处交叠或所述第二栅线在所述第二源漏层上的正投影与所述两个第二源漏极之一在至少两个不同的位置处交叠。
  14. 根据权利要求7-13任一所述的阵列基板，其中，所述第一连接部和所述第二连接部在与所述第一方向垂直的第二方向上分别位于所述第一像素电极的两侧；
    所述第一连接部和所第二连接部在所述第二方向上均位于所述第一栅线和所述第二栅线之间；以及
    所述第一栅线和所述第二栅线相对于所述像素单元组在所述第二方向上的沿所述第一方向延伸的中线对称设置。
  15. 根据权利要求7-14任一所述的阵列基板，其中，所述阵列基板包括阵列排布的多个所述像素单元组；
    用于驱动每个所述像素单元组的第一栅线与用于驱动与所述每个像素单元组在所述第二方向上相邻的像素单元组的第二栅线在所述第一方向上部分交叠；
    所述阵列基板还包括设置在相邻的所述像素单元组之间的数据线；以及
    每个所述像素单元组的第一开关元件和第二开关元件均与同一根数据线相连。
  16. 根据权利要求15所述的阵列基板，其中，所述阵列基板还包括阵列排布的多个公共电极图案；
    所述多个公共电极图案和所述多个像素单元组一一对应；
    位于同一行的多个公共电极图案位于用于驱动与所述同一行的多个公共电极图案对应的像素单元组的第一栅线和第二栅线之间；
    在所述第一方向上相邻的所述公共电极图案通过第一公共电极连接部彼此电连接，所述第一公共电极连接部与所述公共电极图案同层；以及
    在所述第二方向上相邻的所述公共电极图案通过第二公共电极连接部彼此电连接，所述第二公共电极连接部与所述第一连接部同层，所述第二公共电极连接部与对应的公共电极图案通过第三过孔电连接。
  17. 根据权利要求16所述的阵列基板，其中，每个所述公共电极图案包括主体部以及从所述主体部的第一侧伸出的第一凸出部构成；
    所述第一凸出部沿所述第二方向延伸；
    在所述第二方向上相邻的所述公共电极图案通过所述相邻的公共电极图案的第一凸出部和所述第三过孔电连接。
  18. 根据权利要求1-14任一所述的阵列基板，其中，所述第一像素电极与驱动所述第一像素的栅线的横向间距大于五微米；所述第二像素电极与驱动所述第二像素的栅线的横向间距大于五微米。
  19. 根据权利要求1-18任一所述的阵列基板，其中，所述第一连接部的延伸长度小于所述第二连接部的延伸长度；
    所述第二像素电极的靠近驱动所述第二像素的栅线的一侧具有凹陷部。
    所述第一像素电极与驱动所述第一像素的栅线在与所述第一方向交叉的第二方向上彼此交叠，所述第二像素电极与驱动所述第二像素的栅线在与所述第一方向交叉的第二方向上彼此交叠；以及
    所述第一像素电极和所述第一连接部的结合结构与驱动所述第一像素的栅线的有效交叠长度等于所述第二像素电极和所述第二连接部的结合结构与驱动所述第二像素的栅线的有效交叠长度。
  20. 一种显示面板，包括如权利要求1-19任一所述的阵列基板。
  21. 一种显示装置，包括如权利要求1-19任一所述的阵列基板或如权利要求20所述的显示面板。
  22. 一种阵列基板的制作方法，包括：形成像素单元组，
    其中，所述像素单元组包括在第一方向上并列布置的第一像素和第二像素；
    所述第一像素包括第一像素电极、第一开关元件以及从所述第一像素电极延伸突出的第一连接部，
    所述第二像素包括第二像素电极、第二开关元件以及从所述第二像素电极延伸突出的第二连接部；
    所述第一像素电极和所述第一开关元件经由所述第一连接部彼此电连接，
    所述第二像素电极和所述第二开关元件经由所述第二连接部彼此电连接；以及
    所述第一连接部的长度不等于所述第二连接部的长度。
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