WO2020258643A1 - 阵列基板及其制作方法 - Google Patents

阵列基板及其制作方法 Download PDF

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Publication number
WO2020258643A1
WO2020258643A1 PCT/CN2019/115927 CN2019115927W WO2020258643A1 WO 2020258643 A1 WO2020258643 A1 WO 2020258643A1 CN 2019115927 W CN2019115927 W CN 2019115927W WO 2020258643 A1 WO2020258643 A1 WO 2020258643A1
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Prior art keywords
layer
insulating layer
metal layer
goa
array substrate
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Ceased
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PCT/CN2019/115927
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English (en)
French (fr)
Inventor
卢延涛
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US16/631,175 priority Critical patent/US11036322B2/en
Publication of WO2020258643A1 publication Critical patent/WO2020258643A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes

Definitions

  • the present invention relates to the field of display technology, in particular to an array substrate and a manufacturing method thereof.
  • the array substrate row drive (GateDriveronArray, GOA) technology is to integrate the gate (Gate) switching circuit on the array substrate to remove the gate drive integrated circuit part, thereby saving materials and reducing process steps.
  • GOA Gate DriveronArray
  • the GOA circuit area is usually arranged in the non-display area of the array substrate, including the GOA signal area and the GOA driving circuit area.
  • the GOA signal area and the GOA driving circuit area are arranged adjacently. Limited by this structure, it is difficult for the GOA circuit area to continue to shrink, which makes it difficult for the non-display area of the display device to continue to shrink, so that the frame of the display device cannot continue to shrink and the screen-to-body ratio cannot continue to increase.
  • the purpose of the present disclosure is to provide an array substrate and a manufacturing method thereof, which can solve the problems in the prior art.
  • the present disclosure provides an array substrate and a manufacturing method thereof, which includes a non-display area in which a GOA drive circuit area is provided, and the GOA drive circuit area includes a GOA signal area
  • the GOA drive circuit area further includes: a substrate; a buffer layer provided on the substrate; an active layer provided on the buffer layer; a gate insulating layer provided on the active layer; first A metal layer is arranged on the gate insulating layer; an interlayer insulating layer is arranged on the first metal layer; a second metal layer is arranged on the interlayer insulating layer; an organic layer is arranged on the On the second metal layer; a touch metal layer, arranged on the organic layer located in the GOA signal area; a first insulating layer, arranged on the organic layer and the touch metal layer; and signal wiring, arranged On the first insulating layer located in the GOA signal area, the signal traces are respectively connected to the touch metal layer through first vias provided in the first insulating layer and through The second via hole of
  • the materials of the first metal layer, the second metal layer and the touch metal layer are all different.
  • the present invention provides an array substrate including a non-display area, a GOA driving circuit area is provided in the non-display area, and the GOA driving circuit area includes a GOA signal area;
  • the GOA driving circuit area further includes: a substrate; a thin film transistor layer disposed on the substrate; an organic layer disposed on the thin film transistor layer; a touch metal layer disposed on the organic layer in the GOA signal area.
  • the first insulating layer is provided on the organic layer and the touch metal layer; and the signal wiring is provided on the first insulating layer in the GOA signal area, wherein the signal wiring passes through A first via provided on the first insulating layer is connected to the touch metal layer and connected to the thin film transistor layer through a second via provided on the first insulating layer and the organic layer.
  • the thin film transistor layer includes: a buffer layer disposed on the substrate; an active layer disposed on the buffer layer; a gate insulating layer disposed on the active layer; a first metal layer , Arranged on the gate insulating layer; an interlayer insulating layer, arranged on the first metal layer; and a second metal layer, arranged on the interlayer insulating layer.
  • the second metal layer is further filled in a third via hole penetrating the interlayer insulating layer and the gate insulating layer and connected to the active layer, and filled in the interlayer insulating layer Inside the fourth via hole and connected to the first metal layer.
  • the buffer layer includes a second insulating layer and a third insulating layer that are stacked.
  • the materials of the first metal layer, the second metal layer and the touch metal layer are all different.
  • the present invention also provides a manufacturing method of an array substrate, which includes the following steps: providing a substrate; forming a thin film transistor layer on the substrate; forming an organic layer on the thin film transistor layer; forming a touch metal layer on the On the organic layer; forming a first insulating layer on the organic layer and the touch metal layer; patterning the first insulating layer to form a first via, patterning the first insulating layer and the organic Layer to form a second via; and forming signal traces on the first insulating layer, and the signal traces are respectively connected to the touch metal layer through the first vias and through the second via The hole is connected to the thin film transistor layer.
  • the step of forming a thin film transistor layer on the substrate further includes the following steps: forming a buffer layer on the substrate; forming an active layer on the buffer layer; forming a gate insulating layer on the active layer Forming a first metal layer on the gate insulating layer; forming an interlayer insulating layer on the first metal layer; patterning the interlayer insulating layer and the gate insulating layer to form a third Via holes, patterning the interlayer insulating layer to form a fourth via hole; and forming a second metal layer on the interlayer insulating layer.
  • the second metal layer is further filled in the third via hole penetrating the interlayer insulating layer and the gate insulating layer and connected to the active layer, and filled in the interlayer
  • the fourth via hole of the insulating layer is connected to the first metal layer.
  • the buffer layer includes a second insulating layer and a third insulating layer that are stacked.
  • the materials of the first metal layer, the second metal layer and the touch metal layer are all different.
  • the array substrate and manufacturing method thereof disclosed in the present disclosure reduces the space occupied by the GOA circuit area by arranging the GOA signal area above the GOA driving circuit area, thereby reducing the frame of the display device.
  • the screen-to-body ratio of the display device is further improved.
  • the materials of the first metal layer, the second metal layer and the touch metal layer are all different, and they are located on different levels, effectively preventing signal transmission quality problems caused by interference between metals.
  • the touch metal layer in the GOA signal area is used to implement the touch function, which does not affect the touch function of the display device while reducing the frame.
  • FIG. 1 is a schematic diagram of the structure of an array substrate in an embodiment of the invention.
  • FIG. 2 is a schematic structural diagram of the array substrate in FIG. 1 from another perspective.
  • FIG. 3 is a schematic structural diagram of a display device in an embodiment of the invention.
  • FIG. 4 is a schematic flowchart of a manufacturing method of an array substrate in an embodiment of the invention.
  • FIG. 5 is a schematic flowchart of the step of forming a thin film transistor layer in FIG. 4.
  • 6 to 18 are schematic diagrams of structures corresponding to the manufacturing method of the array substrate in an embodiment of the present invention.
  • the present invention provides an array substrate 1 whose structure is shown in FIG. 1.
  • the array substrate 1 includes a GOA circuit area 21.
  • the GOA circuit area 21 is divided into a GOA signal area 211 and a GOA drive circuit area 212.
  • the GOA signal area 211 is set in the GOA drive circuit area 212 and is located directly above the GOA drive circuit area 212.
  • the GOA driving circuit area 212 includes a substrate 101, a buffer layer 102, an active layer 103, a gate insulating layer 104, a first metal layer 105, an interlayer insulating layer 106, a second metal layer 107, an organic layer 108, and a touch metal layer 109, the first insulating layer 110, the via 111 and the signal wiring 112.
  • the GOA signal area 211 includes an organic layer 108, a touch metal layer 109, a first insulating layer 110, via holes 111 and signal traces 112.
  • the substrate 101 serves as the bottom of the array substrate 1.
  • the substrate 101 is, for example, but not limited to, a glass substrate.
  • the buffer layer 102 is provided on the substrate 101.
  • the buffer layer 102 includes a second insulating layer 1021 and a third insulating layer 1022 that are stacked.
  • the second insulating layer 1021 is disposed on the substrate 101 and covers the upper surface of the substrate 101.
  • the third insulating layer 1022 is disposed on the second insulating layer 1021 and covers the upper surface of the second insulating layer 1021.
  • the material of the buffer layer 102 is one or a combination of silicon nitride (SiNx) and silicon oxide (SiOx).
  • the material of the second insulating layer 1021 is silicon oxide
  • the material of the third insulating layer 1022 is silicon nitride.
  • the active layer 103 is provided on the buffer layer 102.
  • the active layer is patterned to form the active layer 103 shown in FIG. 1.
  • the active layer 103 is disposed on the upper surface of the buffer layer 102.
  • the gate insulating layer 104 is provided on the active layer 103.
  • the gate insulating layer 104 covers the upper surface of the active layer 103 and the upper surface of the buffer layer 102 that is not covered by the active layer 103.
  • the first metal layer 105 is disposed on the gate insulating layer 104.
  • the first metal layer is patterned to form the first metal layer 105 shown in FIG. 1.
  • the first metal layer 105 is disposed on the upper surface of the gate insulating layer 104.
  • the material of the first metal layer 105 is molybdenum.
  • the material of the first metal layer 105 includes but is not limited to molybdenum.
  • the interlayer insulating layer 106 is provided on the first metal layer 105.
  • the interlayer insulating layer 106 covers the upper surface of the first metal layer 105 and the portion of the upper surface of the gate insulating layer 104 that is not covered by the first metal layer 105.
  • the via 111 includes a first via 1111, a second via 1112, a third via 1113, and a fourth via 1114.
  • the second metal layer 107 is connected to the active layer 103 through a third via 1113 that sequentially penetrates the interlayer insulating layer 106 and the gate insulating layer 104.
  • the second metal layer 107 is connected to the first metal layer 105 through a fourth via 1114 penetrating the interlayer insulating layer 106.
  • the second metal layer 107 is provided on the interlayer insulating layer 106.
  • the second metal layer is filled in the third via hole 1113 that penetrates the interlayer insulating layer 106 and the gate insulating layer 104 and is connected to the active layer 103, and at the same time is filled in the fourth layer of the interlayer insulating layer 106.
  • the via hole 1114 is connected to the first metal layer 105. After that, the second metal layer undergoes a patterning operation to form the second metal layer 107 shown in FIG. 1.
  • the second metal layer 107 may have a laminated structure, such as a three-layer structure, and specifically, include a titanium (Ti) film layer, an aluminum (Al) film layer, and a titanium (Ti) film layer.
  • the film layer serves as the middle layer, sandwiched by the outer titanium film layer.
  • buffer layer 102 active layer 103, gate insulating layer 104, first metal layer 105, interlayer insulating layer 106 and second metal layer 107 together constitute the thin film transistor layer 113 in this embodiment.
  • the organic layer 108 is disposed on the thin film transistor layer 113, that is, on the second metal layer 107.
  • the organic layer 108 covers the upper surface of the second metal layer 107 and the upper surface of the interlayer insulating layer 106 that is not covered by the second metal layer 107.
  • the organic layer 108 serves as a flat layer, which can make the alignment more uniform and reduce the coupling capacitance.
  • the touch metal layer 109 is disposed on the organic layer 108 in the GOA signal area 211.
  • the touch metal layer 109 is arranged on the upper surface of the organic layer 108 at intervals.
  • the touch metal layer 109 integrates a touch function.
  • the touch metal layer 109 has a laminated structure, such as a three-layer structure, including a molybdenum film layer, an aluminum film layer, and a molybdenum film layer.
  • the aluminum film layer serves as an intermediate layer and is sandwiched by the outer molybdenum film layer. in the middle.
  • the materials of the first metal layer 105, the second metal layer 107, and the touch metal layer 109 are all different, and the three are not on the same horizontal plane, thereby effectively preventing signal transmission quality problems caused by interference between metals.
  • the first insulating layer 110 is disposed on the touch metal layer 109.
  • the first insulating layer 110 covers the upper surface of the touch metal layer 109 and the upper surface of the organic layer 108 that is not covered by the touch metal layer 109.
  • the material of the first insulating layer 110 is one or a combination of silicon nitride and silicon oxide.
  • the first insulating layer 110 is silicon nitride, and the first insulating layer 110 is used as a passivation layer to isolate water and oxygen and prolong the working life of the array substrate 1.
  • the signal wiring 112 is arranged on the first insulating layer 110 in the GOA signal area 211 and above the GOA driving circuit area 212.
  • the signal traces 112 are respectively connected to the touch metal layer 109 through the first via hole 1111 provided on the first insulating layer 110, and through the second via provided on the first insulating layer 110 and the organic layer 108.
  • the hole 1112 is connected to the thin film transistor layer 113, specifically, is further connected to the second metal layer 107.
  • Such a structure achieves a successful connection between the GOA signal area 211 and the GOA driving circuit area 212, while reducing the space occupied by the entire GOA circuit area 21.
  • the material of the signal trace 112 includes but is not limited to indium tin oxide (ITO.
  • the GOA signal area 211 is included by the GOA driving circuit area 212.
  • the space occupied by the GOA signal area 211 and the GOA driving circuit area 212 in parallel is reduced, thereby reducing the space occupied by the entire GOA circuit area 21, which is beneficial to further reduce the frame and increase the screen ratio.
  • the array substrate 1 of the present invention can be applied to the display device 4.
  • the display device 4 includes a display area 3 and a non-display area 2.
  • the GOA circuit area 21 in the array substrate 1 is arranged in the non-display area 2.
  • the GOA circuit area 21 includes the above-mentioned GOA signal area 211 and the GOA driving circuit area 212, and the GOA signal area 211 may be arranged in the display area. 3 and the edge of the non-display area 2. Since the GOA signal area 211 is provided with a touch metal layer 109 that integrates a touch function, the display device 4 is further reduced in frame without affecting its touch function.
  • the present invention also provides a manufacturing method of the array substrate 1, as shown in FIG. 4, wherein the specific structure of the array substrate 1 is as described above, and will not be repeated here.
  • the method includes the following steps:
  • Step S1 Provide a substrate 101.
  • a substrate 101 is provided as the bottom of the array substrate 1.
  • the substrate 101 is, for example, but not limited to, a glass substrate.
  • Step S2 forming a thin film transistor layer 113 on the substrate 101.
  • step S2 further includes the following steps:
  • Step S201 forming a buffer layer 102 on the substrate 101.
  • the buffer layer 102 includes a second insulating layer 1021 and a third insulating layer 1022 that are stacked. As shown in FIG. 7 in combination, the second insulating layer 102 is formed on the substrate 101 and covers the upper surface of the substrate 101.
  • the third insulating layer 1022 is formed on the second insulating layer 1021 and covers the upper surface of the second insulating layer 1021.
  • the material of the buffer layer 102 is one or a combination of silicon nitride (SiNx) and silicon oxide (SiOx).
  • the material of the second insulating layer 1021 is silicon oxide
  • the material of the third insulating layer 1022 is silicon nitride.
  • Step S202 forming an active layer 103 on the buffer layer 102.
  • the active layer 103 is formed on the buffer layer 102.
  • the active layer is patterned to form the active layer 103 shown in FIG. 9.
  • the active layer 103 is formed on the upper surface of the buffer layer 102.
  • Step S203 forming a gate insulating layer 104 on the active layer 103.
  • the gate insulating layer 104 is formed on the active layer 103.
  • the gate insulating layer 104 covers the upper surface of the active layer 103 and the upper surface of the buffer layer 102 that is not covered by the active layer 103.
  • Step S204 forming a first metal layer 105 on the gate insulating layer 104.
  • the first metal layer 105 is formed on the gate insulating layer 104.
  • the first metal layer is patterned to form the first metal layer 105 shown in FIG. 11, specifically, the first metal layer 105 is formed on the upper surface of the gate insulating layer 104.
  • Step S205 forming an interlayer insulating layer 106 on the first metal layer 105.
  • the interlayer insulating layer 106 is formed on the first metal layer 105.
  • the interlayer insulating layer 106 covers the upper surface of the first metal layer 105 and the portion of the upper surface of the gate insulating layer 104 that is not covered by the first metal layer 105.
  • Step S206 patterning the interlayer insulating layer 106 and the gate insulating layer 104 to form a third via 1113, and patterning the interlayer insulating layer 106 to form a fourth via 1114.
  • a patterning operation is performed on the interlayer insulating layer 106 and the gate insulating layer 104 to form a third via 1113. Then, the patterning operation on the interlayer insulating layer 106 is continued to form the fourth via 1114.
  • the third via 1113 penetrates the interlayer insulating layer 106 and the gate insulating layer 104 sequentially from top to bottom, and is connected to the upper surface of the active layer 103.
  • the fourth via 1114 penetrates the interlayer insulating layer 106 and is connected to the upper surface of the first metal layer 105.
  • Step S207 forming a second metal layer 107 on the interlayer insulating layer 106.
  • a second metal layer 107 is deposited on the interlayer insulating layer. Since the third via 1113 and the fourth via 1114 have been formed before the operation of depositing the second metal layer, when the second metal layer 107 is deposited, part of the second metal layer 107 will be filled in the third via 1113 And the fourth via 1114. Next, the second metal layer is patterned to form the second metal layer 107 shown in FIG. 14.
  • the second metal layer 107 may have a laminated structure, such as a three-layer structure, and specifically include a titanium (Ti) film layer, an aluminum (Al) film layer, and a titanium (Ti) film layer.
  • the film layer serves as the middle layer, sandwiched by the outer titanium film layer.
  • Step S3 forming an organic layer 108 on the thin film transistor layer 113.
  • the organic layer 108 is formed on the thin film transistor layer 113, specifically, is further provided on the second metal layer 107.
  • the organic layer 108 covers the upper surface of the second metal layer 107 and the upper surface of the interlayer insulating layer 106 that is not covered by the second metal layer 107.
  • the organic layer 108 is used as a flat layer to make the alignment more uniform. At the same time reduce the coupling capacitance.
  • Step S4 forming a touch metal layer 109 on the organic layer 108.
  • the touch metal layer 109 is formed on the organic layer 108 located in the GOA signal area 211.
  • the touch metal layer 109 is arranged on the upper surface of the organic layer 108 at intervals.
  • the touch metal layer 109 integrates a touch function.
  • the touch metal layer 109 has a laminated structure, such as a three-layer structure, including a molybdenum film layer, an aluminum film layer, and a molybdenum film layer.
  • the aluminum film layer serves as an intermediate layer and is sandwiched by the outer molybdenum film layer. in the middle.
  • the materials of the first metal layer 105, the second metal layer 107, and the touch metal layer 109 are all different, and the three are not on the same horizontal plane, thereby effectively preventing signal transmission quality problems caused by interference between metals.
  • Step S5 forming a first insulating layer 110 on the organic layer 108 and the touch metal layer 109.
  • the first insulating layer 110 is formed on the organic layer 108 and the touch metal layer 109.
  • the first insulating layer 110 covers the upper surface of the touch metal layer 109 and the upper surface of the organic layer 108 that is not covered by the touch metal layer 109.
  • the material of the first insulating layer 110 is one or a combination of silicon nitride and silicon oxide.
  • the first insulating layer 110 is silicon nitride, and the first insulating layer 110 is used as a passivation layer to isolate water and oxygen and prolong the working life of the array substrate 1.
  • Step S6 pattern the first insulating layer 110 to form a first via hole 1111, and pattern the first insulating layer 110 and the organic layer 108 to form a second via hole 1112.
  • a patterning operation is performed on the first insulating layer 110 to form a first via hole 1111. Then, the patterning operation is continued on the first insulating layer 110 and the organic layer 108 to form the second via hole 1112.
  • the second via hole 1112 penetrates the first insulating layer 110 and the organic layer 108 sequentially from top to bottom, and is connected to the upper surface of the second metal layer 107.
  • the first via hole 1111 penetrates the first insulating layer 110 and is connected to the upper surface of the touch metal layer 109.
  • Step S7 Form signal traces 112 on the first insulating layer 110.
  • the signal traces 112 are respectively connected to the touch metal layer 109 through the first via hole 1111 and through the second via hole.
  • 1112 is connected to the thin film transistor layer 113.
  • the signal wiring 112 is formed on the first insulating layer 110 located in the GOA signal area 211 and formed above the GOA driving circuit area 212.
  • the signal trace 112 is respectively connected to the touch metal layer 109 through the first via hole 1111 provided in the first insulating layer 110, and through
  • the second via hole 1112 provided in the first insulating layer 110 and the organic layer 108 is connected to the thin film transistor layer 113, specifically, is further connected to the second metal layer 107.
  • the material of the signal trace 112 includes, but is not limited to, indium tin oxide (ITO).
  • the advantage of the present invention is to provide an array substrate 1 and a manufacturing method thereof.
  • the GOA signal area By arranging the GOA signal area above the GOA drive circuit area, the space occupied by the GOA circuit area is reduced, thereby reducing the frame of the display device, and further This greatly improves the screen-to-body ratio of the display device.
  • the materials of the first metal layer, the second metal layer and the touch metal layer are all different, and they are located on different levels, effectively preventing signal transmission quality problems caused by interference between metals.
  • the touch metal layer in the GOA signal area is used to implement the touch function, which does not affect the touch function of the display device while reducing the frame.
  • the subject of this application can be manufactured and used in industry and has industrial applicability.

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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本发明提供一种阵列基板及其制作方法。通过将GOA信号区设在GOA驱动电路区的上方，减小了GOA电路区所占用的空间，从而缩小了显示装置的边框，进一步地提高了显示装置的屏占比。

Description

阵列基板及其制作方法 技术领域
本发明涉及显示技术领域，特别涉及一种阵列基板及其制作方法。
 背景技术
随着薄膜晶体管液晶显示器(Thinfilmtransistorliquidcrystaldisplay，TFT-LCD)的迅速发展，各生产厂家采用新技术提高产品的市场竞争力以及降低产品成本。其中，阵列基板行驱动(GateDriveronArray，GOA)技术作为新技术的代表，是将栅极(Gate)开关电路集成在阵列基板上，以去掉栅极驱动集成电路部分，从而节省材料并且减少工艺步骤，以达到缩小显示装置边框和降低产品成本的目的。
然而，随着目前带触控功能显示屏占比的不断提高，边框也越来越小，GOA也要不断随着边框调整结构而越缩越小，但在现有的结构下，GOA 由于电性稳定性及性能需求不能缩小。GOA电路区通常设置于阵列基板的非显示区域中，包括GOA信号区和GOA驱动电路区。在现有的阵列基板结构中GOA信号区和GOA驱动电路区两者相邻设置。受限于这种结构，GOA电路区很难继续缩小，从而导致显示装置的非显示区难以继续缩小，使得显示装置的边框无法继续缩窄、屏占比难以继续提高。
因此，有必要提供一种新的阵列基板及其制作方法，来解决现有技术所存在的问题。
 技术问题
本揭示的目的在于提供一种阵列基板及其制作方法，其能解决现有技术中的问题。
 技术解决方案
为解决上述问题，本揭示提供的一种阵列基板及其制作方法，其包括一非显示区，在所述非显示区内设有一GOA驱动电路区，所述GOA驱动电路区包括一GOA信号区；所述GOA驱动电路区进一步包括：基板；缓冲层，设置在所述基板上；有源层，设置在所述缓冲层上；栅极绝缘层，设置在所述有源层上；第一金属层，设置在所述栅极绝缘层上；层间绝缘层，设置在所述第一金属层上；第二金属层，设置在所述层间绝缘层上；有机层，设置在所述第二金属层上；触控金属层，设置在位于所述GOA信号区的有机层上；第一绝缘层，设置在所述有机层和所述触控金属层上；以及信号走线，设置在位于所述GOA信号区的第一绝缘层上，其中，所述信号走线分别通过设置于所述第一绝缘层的第一过孔连接至所述触控金属层以及通过设置于所述第一绝缘层和所述有机层的第二过孔连接至所述薄膜晶体管层；所述第二金属层进一步填充在贯穿所述层间绝缘层和所述栅极绝缘层的第三过孔内并连接至所述有源层，以及填充在所述层间绝缘层的第四过孔内并连接至所述第一金属层；以及所述缓冲层包括层叠设置的第二绝缘层和第三绝缘层。
进一步地，所述第一金属层、第二金属层与触控金属层的材料均不相同。
根据本发明的另一方面，本发明提供一种阵列基板，其包括一非显示区，在所述非显示区内设有一GOA驱动电路区，所述GOA驱动电路区包括一GOA信号区；所述GOA驱动电路区进一步包括：基板；薄膜晶体管层，设置在所述基板上；有机层，设置在所述薄膜晶体管层上；触控金属层，设置在位于所述GOA信号区的有机层上；第一绝缘层，设置在所述有机层和所述触控金属层上；以及信号走线，设置在位于所述GOA信号区的第一绝缘层上，其中，所述信号走线分别通过设置于所述第一绝缘层的第一过孔连接至所述触控金属层以及通过设置于所述第一绝缘层和所述有机层的第二过孔连接至所述薄膜晶体管层。
进一步地，所述薄膜晶体管层包括：缓冲层，设置于所述基板上；有源层，设置在所述缓冲层上；栅极绝缘层，设置在所述有源层上；第一金属层，设置在所述栅极绝缘层上；层间绝缘层，设置在所述第一金属层上；以及第二金属层，设置在所述层间绝缘层上。
进一步地，所述第二金属层进一步填充在贯穿所述层间绝缘层和所述栅极绝缘层的第三过孔内并连接至所述有源层，以及填充在所述层间绝缘层的第四过孔内并连接至所述第一金属层。
进一步地，所述缓冲层包括层叠设置的第二绝缘层和第三绝缘层。
进一步地，所述第一金属层、第二金属层与触控金属层的材料均不相同。
本发明还提供一种阵列基板的制作方法，其包括如下步骤：提供一基板；形成薄膜晶体管层于所述基板上；形成有机层于所述薄膜晶体管层上；形成触控金属层于所述有机层上；形成第一绝缘层于所述有机层和所述触控金属层上；图形化所述第一绝缘层以形成第一过孔，图形化所述第一绝缘层和所述有机层以形成第二过孔；以及形成信号走线于所述第一绝缘层上，所述信号走线分别通过所述第一过孔连接至所述触控金属层以及通过所述第二过孔连接至所述薄膜晶体管层。
进一步地，所述形成薄膜晶体管层于所述基板上步骤还包括如下步骤：形成缓冲层于所述基板上；形成有源层于所述缓冲层上；形成栅极绝缘层于所述有源层上；形成第一金属层于所述栅极绝缘层上；形成层间绝缘层于所述第一金属层上；图形化所述层间绝缘层和所述栅极绝缘层以形成第三过孔，图形化所述层间绝缘层以形成第四过孔；以及形成第二金属层于所述层间绝缘层上。
进一步地，所述第二金属层进一步填充在贯穿所述层间绝缘层和所述栅极绝缘层的所述第三过孔内并连接至所述有源层，以及填充在所述层间绝缘层的所述第四过孔内并连接至所述第一金属层。
进一步地，所述缓冲层包括层叠设置的第二绝缘层和第三绝缘层。
进一步地，所述第一金属层、第二金属层与触控金属层的材料均不相同。
 有益效果
相较于现有技术，本揭示的一种阵列基板及其制作方法，通过将GOA信号区设在GOA驱动电路区的上方，缩小了GOA电路区占用的空间，从而缩小了显示装置的边框，进一步地提高了显示装置的屏占比。另外，第一金属层、第二金属层与触控金属层的材料均不相同，并且位于不同的水平面上，有效防止金属间的干扰而引起的信号传输质量问题。再者，GOA信号区中的触控金属层用于实现触控功能，在缩小边框的同时，不影响显示装置的触控功能。
 附图说明
图1所示为本发明一实施例中阵列基板的结构示意图。
图2所示为图1中的阵列基板的另一视角的结构示意图。
图3所示为本发明一实施例中显示装置的结构示意图。
图4所示为本发明一实施例中阵列基板的制作方法的流程示意图。
图5所示为图4中的形成薄膜晶体管层步骤的流程示意图。
图6至图18为本发明一实施例中阵列基板的制作方法对应的结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图式，用以例示本揭示可用以实施的特定实施例。
下面参考图1至图5描述本发明一实施例中阵列基板1及其制作方法。
本发明提供了一种阵列基板1，其结构如图1所示，阵列基板1包括GOA电路区21，GOA电路区21分为GOA信号区211和GOA驱动电路区212。其中，GOA信号区211设于GOA驱动电路区212内，位于GOA驱动电路区212的正上方。GOA驱动电路区212包括基板101、缓冲层102、有源层103、栅极绝缘层104、第一金属层105、层间绝缘层106、第二金属层107、有机层108、触控金属层109、第一绝缘层110、过孔111和信号走线112。GOA信号区211包括有机层108、触控金属层109、第一绝缘层110、过孔111和信号走线112。
基板101作为阵列基板1的底部。基板101例如但不限于为玻璃基板。
缓冲层102设置在基板101上。缓冲层102包括层叠设置的第二绝缘层1021和第三绝缘层1022，在本实施例中，第二绝缘层1021设置在基板101上，覆盖基板101的上表面。第三绝缘层1022设置在第二绝缘层1021上，覆盖第二绝缘层1021的上表面。缓冲层102的材料为氮化硅(SiNx)、氧化硅(SiOx)中的一种或两种的组合。在本实施例中，第二绝缘层1021的材料为氧化硅，第三绝缘层1022的材料为氮化硅。
有源层103设置在缓冲层102上。在本实施例中，有源层被图形化后形成图1所示的有源层103，具体地，有源层103设置在缓冲层102的上表面。
栅极绝缘层104设置在有源层103上。在本实施例中，栅极绝缘层104覆盖有源层103的上表面，以及缓冲层102上表面中未被有源层103覆盖的部分。
第一金属层105设置在栅极绝缘层104上。在本实施例中，第一金属层被图形化后形成图1所示的第一金属层105，具体地，第一金属层105设置在栅极绝缘层104上表面。在本实施例中，第一金属层105的材料为钼。当然，在其他部分实施例中，第一金属层105的材料包括但不限于钼。
层间绝缘层106设置在第一金属层105上。在本实施例中，层间绝缘层106覆盖第一金属层105的上表面，以及栅极绝缘层104上表面中未被第一金属层105覆盖的部分。
过孔111包括第一过孔1111、第二过孔1112、第三过孔1113和第四过孔1114。第二金属层107通过依次贯穿层间绝缘层106和栅极绝缘层104的第三过孔1113而连接至有源层103。第二金属层107通过贯穿层间绝缘层106的第四过孔1114而连接至第一金属层105。
第二金属层107设置在层间绝缘层106上。在本实施例中，第二金属层填充在贯穿层间绝缘层106和栅极绝缘层104的第三过孔内1113并连接至有源层103，同时填充在层间绝缘层106的第四过孔1114内并连接至第一金属层105。之后，第二金属层经过图形化操作形成图1所示的第二金属层107。在本实施例中，第二金属层107可以为层叠结构，例如为三层结构，具体地，包括钛(Ti）膜层、铝(Al）膜层和钛(Ti）膜层，其中，铝膜层作为中间层，被外侧的钛膜层夹在中间。
上述的缓冲层102、有源层103、栅极绝缘层104、第一金属层105、层间绝缘层106和第二金属层107共同构成本实施例中的薄膜晶体管层113。
有机层108设置在薄膜晶体管层113上，即设置在第二金属层107上。在本实施例中，有机层108覆盖第二金属层107的上表面，以及层间绝缘层106上表面中未被第二金属层107覆盖的部分。在本实施例中，有机层108作为平坦层，可使配向更加均匀，同时减小耦合电容。
触控金属层109设置在位于GOA信号区211的有机层108上。在本实施例中，触控金属层109间隔设置于有机层108的上表面。触控金属层109集成触控功能。在本实施例中，触控金属层109为层叠结构，例如为三层结构，包括钼膜层、铝膜层和钼膜层，其中，铝膜层作为中间层，被外侧的钼膜层夹在中间。第一金属层105、第二金属层107和触控金属层109三者的材料均不相同，并且三者不位于同一水平面上，从而有效防止金属间的干扰而引起的信号传输质量问题。
第一绝缘层110设置在触控金属层109上。在本实施例中，第一绝缘层110覆盖触控金属层109的上表面，以及有机层108上表面中未被触控金属层109覆盖的部分。第一绝缘层110的材料为氮化硅、氧化硅中的一种或两种的组合。在本实施例中，第一绝缘层110为氮化硅，第一绝缘层110作为钝化层，用于隔绝水氧，延长阵列基板1的工作寿命。
信号走线112设置在位于GOA信号区211的第一绝缘层110上，且位于GOA驱动电路区212的上方。在本实施例中，信号走线112分别通过设置于第一绝缘层110的第一过孔1111连接至触控金属层109，以及通过设置于第一绝缘层110和有机层108的第二过孔1112连接至薄膜晶体管层113，具体地，进一步连接至第二金属层107。这样的结构在实现成功连接GOA信号区211和GOA驱动电路区212的同时，缩小了整个GOA电路区21所占的空间。信号走线112的材料包括但不限于氧化铟锡（ITO。
如图2所示，在这一视角下，GOA信号区211 被GOA驱动电路区212所包含。减小了GOA信号区211与GOA驱动电路区212并列时所占的空间，进而减小了整个GOA电路区21所占的空间，利于进一步缩小边框以及提升屏占比。
本发明的阵列基板1可以应用于显示装置4。具体如图3所示，显示装置4包括显示区3和非显示区2。在本实施例中，阵列基板1中的GOA电路区21设置在非显示区2中，GOA电路区21包括上述的GOA信号区211 和GOA驱动电路区212，GOA信号区211可以设置在显示区3和非显示区2相接的边缘处。由于GOA信号区211设有集成了触控功能的触控金属层109，因此，在进一步缩小显示装置4边框的同时，不影响其触控功能。
本发明还提供了一种阵列基板1的制作方法，如图4，其中所述阵列基板1的具体结构如上文所述，在此不再赘述。
所述方法包括如下步骤：
步骤S1、提供一基板101。
结合参阅图6所示，提供一基板101作为阵列基板1的底部。基板101例如但不限于为玻璃基板。
步骤S2、形成薄膜晶体管层113于所述基板101上。
在本实施例中，步骤S2还包括以下步骤：
步骤S201、形成缓冲层102于所述基板101上。
缓冲层102包括层叠设置的第二绝缘层1021和第三绝缘层1022。结合参阅图7所示，第二绝缘层102形成于基板101上，覆盖基板101的上表面。
结合参阅图8所示，第三绝缘层1022形成于第二绝缘层1021上，覆盖第二绝缘层1021的上表面。缓冲层102的材料为氮化硅(SiNx)、氧化硅(SiOx)中的一种或两种的组合。在本实施例中，第二绝缘层1021的材料为氧化硅，第三绝缘层1022的材料为氮化硅。
步骤S202、形成有源层103于所述缓冲层102上。
结合参阅图9所示，有源层103形成于缓冲层102上。在本实施例中，有源层被图形化后形成图9所示的有源层103，具体地，有源层103形成于缓冲层102的上表面。
步骤S203、形成栅极绝缘层104于所述有源层103上。
结合参阅图10所示，栅极绝缘层104形成于有源层103上。在本实施例中，栅极绝缘层104覆盖有源层103的上表面，以及缓冲层102上表面中未被有源层103覆盖的部分。
步骤S204、形成第一金属层105于所述栅极绝缘层104上。
结合参阅图11所示，第一金属层105形成于栅极绝缘层104上。在本实施例中，第一金属层被图形化后形成图11所示的第一金属层105，具体地，第一金属层105形成于栅极绝缘层104上表面。
步骤S205、形成层间绝缘层106于所述第一金属层105上。
结合参阅图12所示，层间绝缘层106形成于第一金属层105上。在本实施例中，层间绝缘层106覆盖第一金属层105的上表面，以及栅极绝缘层104上表面中未被第一金属层105覆盖的部分。
步骤S206、图形化所述层间绝缘层106和所述栅极绝缘层104以形成第三过孔1113，图形化所述层间绝缘层106以形成第四过孔1114。
对层间绝缘层106和栅极绝缘层104进行图形化操作，以形成第三过孔1113。接着继续对层间绝缘层106进行图形化操作，以形成第四过孔1114。结合参阅图13所示，第三过孔1113从上到下依次贯穿层间绝缘层106和栅极绝缘层104，并连接至有源层103的上表面。第四过孔1114贯穿层间绝缘层106，并连接至第一金属层105的上表面。
步骤S207、形成第二金属层107于所述层间绝缘层106上。
结合参阅图14所示，进一步在此步骤中，在所述层间绝缘层上沉积第二金属层107。由于在沉积第二金属层的操作之前，已形成第三过孔1113和第四过孔1114，因此，在沉积第二金属层107时，部分第二金属层107会填充于第三过孔1113和第四过孔1114。接着，对第二金属层进行图形化，形成图14所示的第二金属层107。
在本实施例中，第二金属层107可以为层叠结构，例如为三层结构，具体地，包括钛(Ti)膜层、铝(Al) 膜层和钛(Ti) 膜层，其中，铝膜层作为中间层，被外侧的钛膜层夹在中间。
步骤S3、形成有机层108于所述薄膜晶体管层113上。
结合参阅图15所示，有机层108形成于薄膜晶体管层113上，具体地，进一步设置在第二金属层107上。在本实施例中，有机层108覆盖第二金属层107的上表面，以及层间绝缘层106上表面中未被第二金属层107覆盖的部分。在本实施例中，有机层108作为平坦层，可使配向更加均匀。同时减小耦合电容。
步骤S4、形成触控金属层109于所述有机层108上。
结合参阅图16所示，触控金属层109形成于位于GOA信号区211的有机层108上。在本实施例中，触控金属层109间隔设置于有机层108的上表面。触控金属层109集成触控功能。在本实施例中，触控金属层109为层叠结构，例如为三层结构，包括钼膜层、铝膜层和钼膜层，其中，铝膜层作为中间层，被外侧的钼膜层夹在中间。第一金属层105、第二金属层107和触控金属层109三者的材料均不相同，并且三者不位于同一水平面上，从而有效防止金属间的干扰而引起的信号传输质量问题。
步骤S5、形成第一绝缘层110于所述有机层108和所述触控金属层109上。
结合参阅图17所示，第一绝缘层110形成于有机层108和触控金属层109上。在本实施例中，第一绝缘层110覆盖触控金属层109的上表面，以及有机层108上表面中未被触控金属层109覆盖的部分。第一绝缘层110的材料为氮化硅、氧化硅中的一种或两种的组合。在本实施例中，第一绝缘层110为氮化硅，第一绝缘层110作为钝化层，用于隔绝水氧，延长阵列基板1的工作寿命。
步骤S6、图形化所述第一绝缘层110以形成第一过孔1111，图形化所述第一绝缘层110和所述有机层108以形成第二过孔1112。
对第一绝缘层110进行图形化操作，以形成第一过孔1111。接着继续对第一绝缘层110和有机层108进行图形化操作，以形成第二过孔1112。结合参阅图18所示，第二过孔1112从上到下依次贯穿第一绝缘层110和有机层108，并连接至第二金属层107的上表面。第一过孔1111贯穿第一绝缘层110，并连接至触控金属层109的上表面。
步骤S7、形成信号走线112于所述第一绝缘层110上，所述信号走线112分别通过所述第一过孔1111连接至所述触控金属层109以及通过所述第二过孔1112连接至所述薄膜晶体管层113。
结合参阅图1所示，信号走线112形成于位于GOA信号区211的第一绝缘层110上，形成于GOA驱动电路区212的上方。在本实施例中，在第一过孔1111和第二过孔1112形成后，信号走线112分别通过设置于第一绝缘层110的第一过孔1111连接至触控金属层109，以及通过设置于第一绝缘层110和有机层108的第二过孔1112连接至薄膜晶体管层113，具体地，进一步连接至第二金属层107。这样的结构在实现成功连接GOA信号区211和GOA驱动电路区212的同时，缩小了整个GOA电路区21所占的空间。信号走线112的材料包括但不限于氧化铟锡(ITO)。
本发明的优点在于，提供了一种阵列基板1及其制作方法，通过将GOA信号区设在GOA驱动电路区的上方，缩小了GOA电路区占用的空间，从而缩小了显示装置的边框，进一步地提高了显示装置的屏占比。另外，第一金属层、第二金属层与触控金属层的材料均不相同，并且位于不同的水平面上，有效防止金属间的干扰而引起的信号传输质量问题。再者，GOA信号区中的触控金属层用于实现触控功能，在缩小边框的同时，不影响显示装置的触控功能。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。
 工业实用性
本申请的主题可以在工业中制造和使用，具备工业实用性。

Claims (12)

  1. 一种阵列基板，其包括一非显示区，在所述非显示区内设有一GOA驱动电路区，所述GOA驱动电路区包括一GOA信号区；所述GOA驱动电路区进一步包括：
    基板；
    缓冲层，设置在所述基板上；
    有源层，设置在所述缓冲层上；
    栅极绝缘层，设置在所述有源层上；
    第一金属层，设置在所述栅极绝缘层上；
    层间绝缘层，设置在所述第一金属层上；
    第二金属层，设置在所述层间绝缘层上；
    有机层，设置在所述第二金属层上；
    触控金属层，设置在位于所述GOA信号区的有机层上；
    第一绝缘层，设置在所述有机层和所述触控金属层上；以及
    信号走线，设置在位于所述GOA信号区的第一绝缘层上，其中，所述信号走线分别通过设置于所述第一绝缘层的第一过孔连接至所述触控金属层以及通过设置于所述第一绝缘层和所述有机层的第二过孔连接至所述薄膜晶体管层；所述第二金属层进一步填充在贯穿所述层间绝缘层和所述栅极绝缘层的第三过孔内并连接至所述有源层，以及填充在所述层间绝缘层的第四过孔内并连接至所述第一金属层；以及所述缓冲层包括层叠设置的第二绝缘层和第三绝缘层。
  2. 根据权利要求1所述的阵列基板，其中所述第一金属层、第二金属层与触控金属层的材料均不相同。
  3. 一种阵列基板，其包括一非显示区，在所述非显示区内设有一GOA驱动电路区，所述GOA驱动电路区包括一GOA信号区；所述GOA驱动电路区进一步包括：
    基板；
    薄膜晶体管层，设置在所述基板上；
    有机层，设置在所述薄膜晶体管层上；
    触控金属层，设置在位于所述GOA信号区的有机层上；
    第一绝缘层，设置在所述有机层和所述触控金属层上；以及
    信号走线，设置在位于所述GOA信号区的第一绝缘层上，其中，所述信号走线分别通过设置于所述第一绝缘层的第一过孔连接至所述触控金属层以及通过设置于所述第一绝缘层和所述有机层的第二过孔连接至所述薄膜晶体管层。
  4. 根据权利要求3所述的阵列基板，其中所述薄膜晶体管层包括：
    缓冲层，设置于所述基板上；
    有源层，设置在所述缓冲层上；
    栅极绝缘层，设置在所述有源层上；
    第一金属层，设置在所述栅极绝缘层上；
    层间绝缘层，设置在所述第一金属层上；以及
    第二金属层，设置在所述层间绝缘层上。
  5. 根据权利要求4所述的阵列基板，其中所述第二金属层进一步填充在贯穿所述层间绝缘层和所述栅极绝缘层的第三过孔内并连接至所述有源层，以及填充在所述层间绝缘层的第四过孔内并连接至所述第一金属层。
  6. 根据权利要求4所述的阵列基板，其中所述缓冲层包括层叠设置的第二绝缘层和第三绝缘层。
  7. 根据权利要求4所述的阵列基板，其中所述第一金属层、第二金属层与触控金属层的材料均不相同。
  8. 一种阵列基板的制作方法，其包括如下步骤：
    提供一基板；
    形成薄膜晶体管层于所述基板上；
    形成有机层于所述薄膜晶体管层上；
    形成触控金属层于所述有机层上；
    形成第一绝缘层于所述有机层和所述触控金属层上；
    图形化所述第一绝缘层以形成第一过孔，图形化所述第一绝缘层和所述有机层以形成第二过孔；以及
    形成信号走线于所述第一绝缘层上，所述信号走线分别通过所述第一过孔连接至所述触控金属层以及通过所述第二过孔连接至所述薄膜晶体管层。
  9. 根据权利要求8所述的阵列基板的制作方法，其中所述形成薄膜晶体管层于所述基板上步骤还包括如下步骤：
    形成缓冲层于所述基板上；
    形成有源层于所述缓冲层上；
    形成栅极绝缘层于所述有源层上；
    形成第一金属层于所述栅极绝缘层上；
    形成层间绝缘层于所述第一金属层上；
    图形化所述层间绝缘层和所述栅极绝缘层以形成第三过孔，图形化所述层间绝缘层以形成第四过孔；以及
    形成第二金属层于所述层间绝缘层上。
  10. 根据权利要求9所述的阵列基板的制作方法，其中所述第二金属层进一步填充在贯穿所述层间绝缘层和所述栅极绝缘层的所述第三过孔内并连接至所述有源层，以及填充在所述层间绝缘层的所述第四过孔内并连接至所述第一金属层。
  11. 根据权利要求9所述的阵列基板，其中所述缓冲层包括层叠设置的第二绝缘层和第三绝缘层。
  12. 根据权利要求9所述的阵列基板，其中所述第一金属层、第二金属层与触控金属层的材料均不相同。
PCT/CN2019/115927 2019-06-24 2019-11-06 阵列基板及其制作方法 Ceased WO2020258643A1 (zh)

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CN111223439A (zh) * 2020-03-12 2020-06-02 深圳市华星光电半导体显示技术有限公司 应用于阵列基板的goa电路、阵列基板及goa电路的制作方法
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