WO2020258478A1 - 像素电极、阵列基板及显示装置 - Google Patents

像素电极、阵列基板及显示装置 Download PDF

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Publication number
WO2020258478A1
WO2020258478A1 PCT/CN2019/101901 CN2019101901W WO2020258478A1 WO 2020258478 A1 WO2020258478 A1 WO 2020258478A1 CN 2019101901 W CN2019101901 W CN 2019101901W WO 2020258478 A1 WO2020258478 A1 WO 2020258478A1
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Prior art keywords
layer
pixel electrode
array substrate
main body
electrode
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PCT/CN2019/101901
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English (en)
French (fr)
Inventor
肖诗笛
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武汉华星光电技术有限公司
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Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US16/607,254 priority Critical patent/US11366362B2/en
Publication of WO2020258478A1 publication Critical patent/WO2020258478A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the invention relates to the field of display, in particular to a pixel electrode, an array substrate and a display device.
  • the two ends of the actual hollow area of the pixel electrode show smaller openings, which causes the two ends of the hollow area of the pixel electrode to occupy the original pixel. Spacer area in the electrode. Therefore, the effective electric field will be reduced, and the effective arrangement of the liquid crystal molecules in the pixel will be affected, thereby reducing the transmittance effect of the entire panel.
  • the purpose of the present invention is to provide a pixel electrode, an array substrate, and a display device to solve the problem that the effective electric field of the pixel electrode in the prior art is small, thereby affecting the effective arrangement of liquid crystal molecules in the pixel, and further reducing the overall panel Penetration effect.
  • the present invention provides a pixel electrode, which includes an electrode area and a hollow area.
  • the hollow areas are distributed between the electrode areas.
  • the hollow area has a main body and ends located at two ends of the main body, wherein the main body has a width.
  • At least one end portion is an expansion body, which also has a width, and the width of the main body portion is smaller than the width of the expansion body.
  • the expansion body has a superior arc shape.
  • ends located at the two ends of the main body are all expansion bodies.
  • one end of the ends located at both ends of the main body portion is an expanded body, and the other end extends to the electrode area and forms a hollow gap.
  • the electrode area is formed with a corner, and the edge of the corner is an arc-shaped edge.
  • the present invention also provides an array substrate, which includes the above-mentioned pixel electrode.
  • the array substrate further includes a thin film transistor structure layer, a flat layer and a passivation layer.
  • the flat layer is arranged on the thin film transistor structure layer.
  • the passivation layer is provided on the flat layer.
  • the pixel electrode is arranged on the passivation layer.
  • the thin film transistor structure layer has a source and drain layer.
  • the planarization layer has a first via hole
  • the passivation layer has a second via hole
  • the first via hole corresponds to the second via hole
  • the pixel electrode passes through the first via hole
  • the second via hole is connected to the source drain layer.
  • the aperture of the first via hole is less than 7 microns, and the aperture of the second via hole is less than 5 microns.
  • the present invention also provides a display device, including the above-mentioned pixel electrode.
  • the advantage of the present invention is that the pixel electrode of the present invention is redesigned at both ends to make the rest of the liquid crystal molecules on the edge closer to the liquid crystal molecules in the effective display area, thereby increasing the transmission of the backlight light source effect. Thereby improving the penetration rate level of the existing panel, achieving the purpose of enhancing the contrast and enhancing the endurance.
  • the holes in each film layer are adjusted according to the increase of the two ends of the hollow area of the pixel electrode, which can further eliminate dark lines and improve backlight transmission. rate.
  • FIG. 1 is a schematic diagram of the structure of a pixel electrode in Embodiment 1 of the present invention.
  • FIG. 2 is a schematic diagram of the structure of a pixel electrode in Embodiment 2 of the present invention.
  • FIG. 3 is a schematic diagram of the structure of a pixel electrode in Embodiment 3 of the present invention.
  • FIG. 4 is a schematic diagram of the layered structure of the array substrate in the embodiment 1-3 of the present invention.
  • Thin film transistor structure layer 200
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of the features. In the description of this application, “multiple” means two or more than two, unless otherwise specifically defined.
  • connection should be interpreted broadly unless otherwise clearly specified and limited.
  • it can be a fixed connection or a detachable connection.
  • Connected or integrally connected it can be mechanically connected, or electrically connected or can communicate with each other; it can be directly connected, or indirectly connected through an intermediate medium, it can be the internal communication of two components or the interaction of two components relationship.
  • connection should be interpreted broadly unless otherwise clearly specified and limited.
  • it can be a fixed connection or a detachable connection.
  • Connected or integrally connected it can be mechanically connected, or electrically connected or can communicate with each other; it can be directly connected, or indirectly connected through an intermediate medium, it can be the internal communication of two components or the interaction of two components relationship.
  • a pixel electrode 100 is provided, and the pixel electrode is elongated.
  • the pixel electrode 100 includes an electrode area 110 and a hollow area 120.
  • the pixel electrode 100 has two hollow areas 120 and one electrode area 110.
  • the hollow area 120 is evenly distributed on the electrode area 110, and the electrode area 110 surrounds the hollow area 120.
  • the electrode area 110 includes a first contact portion 111, a second contact portion 112 and three connecting portions 113.
  • the connecting portion 113 is elongated, and every two connecting portions 113 are parallel to each other, and the connecting portion 113 and the hollow area 120 are arranged to overlap each other.
  • the first contact portion 111 and the second contact portion 112 are respectively provided at two ends of the connecting portion 113.
  • the first contact portion 111 and the second contact portion 112 are used for contact connection with the structure layer in the array substrate, and the connection portion 113 is used for transmitting current.
  • the hollow areas 120 are evenly distributed on the pixel electrode 100, and the hollow areas 120 are parallel to each other.
  • Each hollow area 120 has a main body 121 and end 122 and end 123 located at two ends of the main body 121.
  • the main body 121 is a long strip with a width.
  • the end 122 and the end 123 at the two ends of the hollow area 120 are both expansion bodies.
  • the expansion body also has a width.
  • the width of the main body 121 is smaller than that of the end 122 and the end 123. width.
  • the expansion body has a superior arc shape.
  • the hollow area is used to pass through the backlight and provide light for the display panel.
  • the material of the pixel electrode 100 is indium tin oxide (ITO).
  • ITO indium tin oxide
  • the pixel electrode 100 improves the arrangement of the liquid crystal molecules by enlarging the end 122 and the end 123 at the two ends of the hollow area 120, and eliminates or reduces the dark lines in the pixel display area, thereby increasing the transmittance of the panel. the goal of.
  • the pixel electrode 100 has a single-pixel dual-domain structure, but in other embodiments, the pixel electrode 100 may also have other structures, such as a dual-pixel dual-domain structure and other pixel structures, which are hollowed out.
  • the design of the area 120 and the electrode area 110 is similar to the pixel electrode 100 of the single-pixel and double-domain structure in the embodiment of the present invention, so it is not repeated here. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of this application.
  • an embodiment of the present invention also provides an array substrate 1000.
  • the array substrate 1000 includes a thin film transistor structure layer 200, a planarization layer 300, a passivation layer 400, and the above-mentioned pixel electrode 100. .
  • the thin film transistor structure layer 200 includes a base layer 210, an active layer 220, a first insulating layer 230, a gate layer 240, a second insulating layer 250, and a source and drain layer 260.
  • the substrate is an insulating substrate, and the material of the insulating substrate may be an insulating material such as glass or quartz, which is used to protect the overall structure of the array substrate 1000.
  • the active layer 220 is disposed on the base layer 210.
  • the doped regions 221 at the ends are doped with N-type ions of the same type, or the doped regions 221 at both ends of the active layer 220 are doped with P-type ions of the same type through a heavy P-type doping process.
  • the doping after the doping process can reduce the contact resistance between the source and drain layer 260 and the active layer 220, reduce the leakage current of the array substrate 1000, and improve the performance of the array substrate 1000. Electrical performance.
  • the first insulating layer 230 is disposed on the base layer 210 and covers the active layer 220.
  • the first insulating layer 230 may be deposited from an insulating material, and the insulating material may be one of silicon oxide, silicon nitride, or silicon oxynitride.
  • the first insulating layer 230 is used to protect and isolate the active layer 220.
  • the gate layer 240 is disposed on the first insulating layer 230 and corresponds to the active layer.
  • the gate layer 240 is made of conductive material, and the conductive material may be tungsten, chromium, aluminum, copper, or the like.
  • the gate layer 240 is used to generate an electric field through voltage, thereby changing the thickness of the conductive channel, so as to achieve the purpose of controlling the current of the source and drain layer 260.
  • the second insulating layer 250 is disposed on the first insulating layer 230 and covers the gate layer 240.
  • the second insulating layer 250 may be deposited by a chemical vapor deposition method.
  • the second insulating layer 250 may also adopt a dielectric isolation technology and be made of an insulating dielectric material.
  • the insulating dielectric material may be one of silicon oxide, silicon nitride, or silicon oxynitride.
  • the second insulating layer 250 is used to isolate metal traces, such as the gate layer 240 and the source-drain layer 260, to prevent the gate layer 240 from the source-drain layer 260 has a short circuit.
  • the thin film transistor structure layer 200 further includes a contact hole 270 that penetrates from the second insulating layer 250 to the first insulating layer 230 and extends to the active layer 220.
  • the contact holes 270 respectively correspond to the doped regions 221 at both ends of the active layer 220.
  • the hole diameter of the contact hole 270 is less than 5 microns.
  • the source and drain layers 260 are disposed on the second insulating layer 250.
  • the source and drain layer 260 may be formed by patterning metal.
  • the source and drain layers 260 are respectively connected to the doped regions 221 of the active layer 220 through a contact hole 270.
  • the flat layer 300 is disposed on the second insulating layer 250 of the thin film transistor structure layer 200 and covers the source and drain layers 260.
  • the flattening layer 300 is generally made of an organic material, which is used to flatten the thin film transistor structure layer 200 and protect the source and drain layer 260 to prevent short circuit and corrosion of the source and drain.
  • the passivation layer 400 is disposed on the planarization layer 300, a common electrode 500 is provided between the passivation layer 400 and the planarization layer 300, and the passivation layer 400 is used to passivate the common electrode 500 , To prevent the common electrode 500 layer from corroding and causing short circuits.
  • first via 310 on the planarization layer 300 and a second via 410 on the passivation layer 400, and the first via 310 and the second via 410 correspond to each other.
  • the aperture of the first via hole 310 is less than 7 microns, and the aperture of the second via hole 410 is less than 5 microns.
  • the pixel electrode 100 is disposed on the passivation layer 400, and the pixel electrode 100 passes through the first via hole 310 and the second via hole 410 and is connected to the source and drain layer 260.
  • both ends of the pixel electrode 100 adopt an enlarged design, but because the two ends of the pixel electrode 100 are covered by the cutout of the common electrode 500 in the prior art, the The effect of the enlarged design of the pixel electrode 100 is limited.
  • the common electrode 500 may be digged and reduced to further eliminate dark lines, and at the same time, other film layers in the array substrate 1000 need to be further adjusted.
  • the hole diameter of the common electrode 500 is less than 13 microns
  • the trace width of the source and drain layer 260 is less than 10 microns
  • the aperture of the first via 310 on the flat layer 300 is less than 7 microns.
  • the aperture of the second via 410 on the passivation layer 400 is less than 5 microns
  • the aperture of the contact hole 270 on the second insulating layer 250 is less than 5 microns.
  • the array substrate 1000 has a back-channel etching structure of 10 times photolithography, but in other embodiments, the array substrate 1000 may also have other structures, such as a 12-time photolithography back trench.
  • the array substrate 1000 of the trench-etched structure is similar, so it will not be repeated here. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of this application.
  • An embodiment of the present invention also provides a display device (not shown), which includes the above-mentioned pixel electrode 100 and the array substrate 1000.
  • the display device may be a liquid crystal display, a mobile phone, a tablet computer, a notebook computer, a digital camera, Any product or component with display function such as navigator.
  • the end 122 and the end 123 at the two ends of the hollow area 120 are designed with an expanded body, so that the rest of the liquid crystal molecules at the edge are arranged closer to the liquid crystal molecules in the effective display area. Cloth, increase the transmission effect of the backlight light source, thereby improving the penetration rate of the existing panel, achieving the purpose of enhancing the contrast and enhancing the endurance.
  • the holes in each film layer are adjusted according to the increase of the two ends of the hollow area 120 of the pixel electrode 100, which can further eliminate dark lines and improve Backlight transmittance.
  • a pixel electrode 100 is provided, and the pixel electrode is elongated.
  • the pixel electrode 100 includes an electrode area 110 and a hollow area 120.
  • the pixel electrode 100 has two hollow areas 120 and one electrode area 110.
  • the hollow area 120 is evenly distributed on the electrode area 110.
  • the electrode region 110 includes a first contact part 111, three second contact parts 112 and three connection parts 113.
  • the connecting portion 113 is elongated, and every two connecting portions 113 are parallel to each other, and the connecting portion 113 and the hollow area 120 are arranged to overlap each other.
  • the first contact portion 111 and the second contact portion 112 are respectively provided at two ends of the connecting portion 113.
  • the second contact portion 112 is a corner shape, the edge of the corner is an arc-shaped edge, the second contact portion 112 is respectively provided at one end of the connecting portion 113, and the second contact portion of the corner shape
  • the orientations of the two contact portions 112 are the same.
  • the first contact portion 111 and the second contact portion 112 are used for contact connection with the structure layer in the array substrate, and the connection portion 113 is used for transmitting current.
  • the hollow areas 120 are evenly distributed on the pixel electrode 100, and the hollow areas 120 are parallel to each other.
  • Each hollow area 120 has a main body 121 and end 122 and end 123 located at two ends of the main body 121.
  • the main body 121 is a long strip with a width.
  • the end 122 of the hollow area 120 close to the first contact portion 111 is an expanded body, and the end 123 of the hollow area 120 close to the second contact portion 112 extends to the second contact portion 112 and forms a hollow The indentation of, urges the second contact portion 112 to form the corner.
  • the expansion body also has a width, and the width of the main body 121 is smaller than the width of the end 122. In addition, the expansion body has a superior arc shape.
  • the hollow area is used to pass through the backlight and provide light for the display panel.
  • the material of the pixel electrode 100 is indium tin oxide (ITO).
  • ITO indium tin oxide
  • the pixel electrode 100 improves the arrangement of the liquid crystal molecules by enlarging the end 122 and the end 123 at the two ends of the hollow area 120, and eliminates or reduces the dark lines in the pixel display area, thereby increasing the transmittance of the panel. the goal of.
  • the pixel electrode 100 has a single-pixel dual-domain structure, but in other embodiments, the pixel electrode 100 may also have other structures, such as a dual-pixel dual-domain structure and other pixel structures, which are hollowed out.
  • the design of the area 120 and the electrode area 110 is similar to the pixel electrode 100 of the single-pixel and double-domain structure in the embodiment of the present invention, so it is not repeated here. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of this application.
  • an embodiment of the present invention also provides an array substrate 1000.
  • the array substrate 1000 includes a thin film transistor structure layer 200, a planarization layer 300, a passivation layer 400, and the above-mentioned pixel electrode 100. .
  • the thin film transistor structure layer 200 includes a base layer 210, an active layer 220, a first insulating layer 230, a gate layer 240, a second insulating layer 250, and a source and drain layer 260.
  • the substrate is an insulating substrate, and the material of the insulating substrate may be an insulating material such as glass or quartz, which is used to protect the overall structure of the array substrate 1000.
  • the active layer 220 is disposed on the base layer 210.
  • the doped regions 221 at the ends are doped with N-type ions of the same type, or the doped regions 221 at both ends of the active layer 220 are doped with P-type ions of the same type through a heavy P-type doping process.
  • the doping after the doping process can reduce the contact resistance between the source and drain layer 260 and the active layer 220, reduce the leakage current of the array substrate 1000, and improve the performance of the array substrate 1000. Electrical performance.
  • the first insulating layer 230 is disposed on the base layer 210 and covers the active layer 220.
  • the first insulating layer 230 may be deposited from an insulating material, and the insulating material may be one of silicon oxide, silicon nitride, or silicon oxynitride.
  • the first insulating layer 230 is used to protect and isolate the active layer 220.
  • the gate layer 240 is disposed on the first insulating layer 230 and corresponds to the active layer.
  • the gate layer 240 is made of conductive material, and the conductive material may be tungsten, chromium, aluminum, copper, or the like.
  • the gate layer 240 is used to generate an electric field through voltage, thereby changing the thickness of the conductive channel, so as to achieve the purpose of controlling the current of the source and drain layer 260.
  • the second insulating layer 250 is disposed on the first insulating layer 230 and covers the gate layer 240.
  • the second insulating layer 250 may be deposited by a chemical vapor deposition method.
  • the second insulating layer 250 may also adopt a dielectric isolation technology and be made of an insulating dielectric material.
  • the insulating dielectric material may be one of silicon oxide, silicon nitride, or silicon oxynitride.
  • the second insulating layer 250 is used to isolate metal traces, such as the gate layer 240 and the source-drain layer 260, to prevent the gate layer 240 from the source-drain layer 260 has a short circuit.
  • the thin film transistor structure layer 200 further includes a contact hole 270 that penetrates from the second insulating layer 250 to the first insulating layer 230 and extends to the active layer 220.
  • the contact holes 270 respectively correspond to the doped regions 221 at both ends of the active layer 220.
  • the hole diameter of the contact hole 270 is less than 5 microns.
  • the source and drain layers 260 are disposed on the second insulating layer 250.
  • the source and drain layer 260 may be formed by patterning metal.
  • the source and drain layers 260 are respectively connected to the doped regions 221 of the active layer 220 through a contact hole 270.
  • the flat layer 300 is disposed on the second insulating layer 250 of the thin film transistor structure layer 200 and covers the source and drain layers 260.
  • the flattening layer 300 is generally made of an organic material, which is used to flatten the thin film transistor structure layer 200 and protect the source and drain layer 260 to prevent short circuit and corrosion of the source and drain.
  • the passivation layer 400 is disposed on the planarization layer 300, a common electrode 500 is provided between the passivation layer 400 and the planarization layer 300, and the passivation layer 400 is used to passivate the common electrode 500 , To prevent the common electrode 500 layer from corroding and causing short circuits.
  • first via 310 on the planarization layer 300 and a second via 410 on the passivation layer 400, and the first via 310 and the second via 410 correspond to each other.
  • the aperture of the first via hole 310 is less than 7 microns, and the aperture of the second via hole 410 is less than 5 microns.
  • the pixel electrode 100 is disposed on the passivation layer 400, and the pixel electrode 100 passes through the first via hole 310 and the second via hole 410 and is connected to the source and drain layer 260.
  • one end of the two ends of the pixel electrode 100 adopts an enlarged design, and the other end adopts a notch design.
  • the two ends of the pixel electrode 100 are covered by the common electrode 500.
  • the common electrode 500 may be digged and reduced to further eliminate dark lines, and at the same time, other film layers in the array substrate 1000 need to be further adjusted.
  • the hole diameter of the common electrode 500 is less than 13 microns
  • the trace width of the source and drain layer 260 is less than 10 microns
  • the aperture of the first via 310 on the flat layer 300 is less than 7 microns.
  • the aperture of the second via 410 on the passivation layer 400 is less than 5 microns
  • the aperture of the contact hole 270 on the second insulating layer 250 is less than 5 microns.
  • the array substrate 1000 has a 10PEP structure, but in other embodiments, the array substrate 1000 may also have other structures, such as 12PEP structure, 9PEP structure, 8PEP structure and other structures.
  • the pixel electrode The design of 100 is similar to that of the array substrate 1000 with the 10PEP structure in the embodiment of the present invention, so it will not be repeated here. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of this application.
  • An embodiment of the present invention also provides a display device (not shown), which includes the above-mentioned pixel electrode 100 and the array substrate 1000.
  • the display device may be a liquid crystal display, a mobile phone, a tablet computer, a notebook computer, a digital camera, Any product or component with display function such as navigator.
  • the ends 122 at both ends of the hollow area 120 are set as expanded bodies, and the end portions 123 are set to extend to the second contact portion 112 and form a hollow gap, and The second contact portion 112 forms a corner.
  • This design makes the arrangement of the rest of the liquid crystal molecules at the edge closer to the arrangement of the liquid crystal molecules in the effective display area, increasing the transmission effect of the backlight light source, thereby improving the transmittance of the existing panel Level, achieve the purpose of improving contrast and enhancing endurance.
  • the holes in each film layer are adjusted according to the increase of the two ends of the hollow area 120 of the pixel electrode 100, which can further eliminate dark lines and improve Backlight transmittance.
  • a pixel electrode 100 is provided, and the pixel electrode has a " ⁇ " shape.
  • the pixel electrode 100 includes an electrode area 110 and a hollow area 120.
  • the pixel electrode 100 has two hollow areas 120 and one electrode area 110.
  • the hollow area 120 is evenly distributed on the electrode area 110.
  • the electrode region 110 includes a first contact part 111, three second contact parts 112 and three connection parts 113.
  • the connecting portion 113 is in the shape of " ⁇ ", every two connecting portions 113 are parallel to each other, and the connecting portion 113 and the hollow area 120 are arranged to overlap each other.
  • the first contact portion 111 and the second contact portion 112 are respectively provided at two ends of the connecting portion 113.
  • the second contact portion 112 is a corner shape, the edge of the corner is an arc-shaped edge, the second contact portion 112 is respectively provided at one end of the connecting portion 113, and the second contact portion of the corner shape
  • the orientations of the two contact portions 112 are the same.
  • the first contact portion 111 and the second contact portion 112 are used for contact connection with the structure layer in the array substrate, and the connection portion 113 is used for transmitting current.
  • the hollow areas 120 are evenly distributed on the pixel electrode 100, and the hollow areas 120 are parallel to each other.
  • Each hollow area 120 has a main body 121 and end 122 and end 123 located at two ends of the main body 121.
  • the main body 121 has a " ⁇ " shape with a width.
  • the end 122 of the hollow area 120 close to the first contact portion 111 is an expanded body, and the end 123 of the hollow area 120 close to the second contact portion 112 extends to the second contact portion 112 and forms a hollow The indentation of, urges the second contact portion 112 to form the corner.
  • the expansion body also has a width, and the width of the main body 121 is smaller than the width of the end 122.
  • the expansion body has a superior arc shape.
  • the hollow area is used to pass through the backlight and provide light for the display panel.
  • the material of the pixel electrode 100 is indium tin oxide (ITO).
  • ITO indium tin oxide
  • the pixel electrode 100 improves the arrangement of the liquid crystal molecules by enlarging the end 122 and the end 123 at the two ends of the hollow area 120, and eliminates or reduces the dark lines in the pixel display area, thereby increasing the transmittance of the panel. the goal of.
  • the pixel electrode 100 has a single-pixel dual-domain structure, but in other embodiments, the pixel electrode 100 may also have other structures, such as a dual-pixel dual-domain structure and other pixel structures, which are hollowed out.
  • the design of the area 120 and the electrode area 110 is similar to the pixel electrode 100 of the single-pixel and double-domain structure in the embodiment of the present invention, so it is not repeated here. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of this application.
  • an embodiment of the present invention also provides an array substrate 1000.
  • the array substrate 1000 includes a thin film transistor structure layer 200, a planarization layer 300, a passivation layer 400, and the above-mentioned pixel electrode 100. .
  • the thin film transistor structure layer 200 includes a base layer 210, an active layer 220, a first insulating layer 230, a gate layer 240, a second insulating layer 250, and a source and drain layer 260.
  • the substrate is an insulating substrate, and the material of the insulating substrate may be an insulating material such as glass or quartz, which is used to protect the overall structure of the array substrate 1000.
  • the active layer 220 is disposed on the base layer 210.
  • the doped regions 221 at the ends are doped with N-type ions of the same type, or the doped regions 221 at both ends of the active layer 220 are doped with P-type ions of the same type through a heavy P-type doping process.
  • the doping after the doping process can reduce the contact resistance between the source and drain layer 260 and the active layer 220, reduce the leakage current of the array substrate 1000, and improve the performance of the array substrate 1000. Electrical performance.
  • the first insulating layer 230 is disposed on the base layer 210 and covers the active layer 220.
  • the first insulating layer 230 may be deposited from an insulating material, and the insulating material may be one of silicon oxide, silicon nitride, or silicon oxynitride.
  • the first insulating layer 230 is used to protect and isolate the active layer 220.
  • the gate layer 240 is disposed on the first insulating layer 230 and corresponds to the active layer.
  • the gate layer 240 is made of conductive material, and the conductive material may be tungsten, chromium, aluminum, copper, or the like.
  • the gate layer 240 is used to generate an electric field through voltage, thereby changing the thickness of the conductive channel, so as to achieve the purpose of controlling the current of the source and drain layer 260.
  • the second insulating layer 250 is disposed on the first insulating layer 230 and covers the gate layer 240.
  • the second insulating layer 250 may be deposited by a chemical vapor deposition method.
  • the second insulating layer 250 may also adopt a dielectric isolation technology and be made of an insulating dielectric material.
  • the insulating dielectric material may be one of silicon oxide, silicon nitride, or silicon oxynitride.
  • the second insulating layer 250 is used to isolate metal traces, such as the gate layer 240 and the source-drain layer 260, to prevent the gate layer 240 from the source-drain layer 260 has a short circuit.
  • the thin film transistor structure layer 200 further includes a contact hole 270 that penetrates from the second insulating layer 250 to the first insulating layer 230 and extends to the active layer 220.
  • the contact holes 270 respectively correspond to the doped regions 221 at both ends of the active layer 220.
  • the hole diameter of the contact hole 270 is less than 5 microns.
  • the source and drain layers 260 are disposed on the second insulating layer 250.
  • the source and drain layer 260 may be formed by patterning metal.
  • the source and drain layers 260 are respectively connected to the doped regions 221 of the active layer 220 through a contact hole 270.
  • the flat layer 300 is disposed on the second insulating layer 250 of the thin film transistor structure layer 200 and covers the source and drain layers 260.
  • the flattening layer 300 is generally made of an organic material, which is used to flatten the thin film transistor structure layer 200 and protect the source and drain layer 260 to prevent short circuit and corrosion of the source and drain.
  • the passivation layer 400 is disposed on the planarization layer 300, a common electrode 500 is provided between the passivation layer 400 and the planarization layer 300, and the passivation layer 400 is used to passivate the common electrode 500 , To prevent the common electrode 500 layer from corroding and causing short circuits.
  • first via 310 on the planarization layer 300 and a second via 410 on the passivation layer 400, and the first via 310 and the second via 410 correspond to each other.
  • the aperture of the first via hole 310 is less than 7 microns, and the aperture of the second via hole 410 is less than 5 microns.
  • the pixel electrode 100 is disposed on the passivation layer 400, and the pixel electrode 100 passes through the first via hole 310 and the second via hole 410 and is connected to the source and drain layer 260.
  • both ends of the pixel electrode 100 adopt an enlarged design, but because the two ends of the pixel electrode 100 are covered by the cutout of the common electrode 500 in the prior art, the The effect of the enlarged design of the pixel electrode 100 is limited.
  • the common electrode 500 may be digged and reduced to further eliminate dark lines, and at the same time, other film layers in the array substrate 1000 need to be further adjusted.
  • the hole diameter of the common electrode 500 is less than 13 microns
  • the trace width of the source and drain layer 260 is less than 10 microns
  • the aperture of the first via 310 on the flat layer 300 is less than 7 microns.
  • the aperture of the second via 410 on the passivation layer 400 is less than 5 microns
  • the aperture of the contact hole 270 on the second insulating layer 250 is less than 5 microns.
  • the array substrate 1000 has a back-channel etching structure of 10 times photolithography, but in other embodiments, the array substrate 1000 may also have other structures, such as a 12-time photolithography back trench.
  • the array substrate 1000 of the trench-etched structure is similar, so it will not be repeated here. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of this application.
  • An embodiment of the present invention also provides a display device (not shown), which includes the above-mentioned pixel electrode 100 and the array substrate 1000.
  • the display device may be a liquid crystal display, a mobile phone, a tablet computer, a notebook computer, a digital camera, Any product or component with display function such as navigator.
  • the ends 122 at both ends of the hollow area 120 are set as expanded bodies, and the end portions 123 are set to extend to the second contact portion 112 and form a hollow gap, and The second contact portion 112 forms a corner.
  • This design makes the arrangement of the rest of the liquid crystal molecules at the edge closer to the arrangement of the liquid crystal molecules in the effective display area, increasing the transmission effect of the backlight light source, thereby improving the transmittance of the existing panel Level, achieve the purpose of improving contrast and enhancing endurance.
  • the holes in each film layer are adjusted according to the increase of the two ends of the hollow area 120 of the pixel electrode 100, which can further eliminate dark lines and improve Backlight transmittance.

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Abstract

一种像素电极（100）、阵列基板及显示装置。像素电极（100）包括电极区（110）以及镂空区（120）。镂空区（120）分布于电极区（110）之间。其中，镂空区（120）具有主体部（121）和位于主体部（121）两端的端部（122），其中主体部（121）具有一宽度。至少一端部（122）为膨胀体，其也具有一宽度，主体部（121）的宽度小于膨胀体的宽度。通过此设计增加背光光源的透过效果，从而改善现有面板的穿透率水准，达到提升对比度和增强续航能力的目的。

Description

像素电极、阵列基板及显示装置 技术领域
本发明涉及显示领域，特别是一种像素电极、阵列基板及显示装置。
 背景技术
在现如今产品像素电极设计中，由于原设计和制造能力的限制，使得实际像素电极的镂空区的两端部中所示为开口较小，导致像素电极的镂空区的两端部会占有原像素电极中的间隔区域。因此，会降低有效电场作用范围，影响像素内液晶分子的有效排布，从而降低整个面板的穿透率效果。
 技术问题
本发明的目的是提供一种像素电极、阵列基板及显示装置，以解决现有技术中像素电极的有效电场作用范围小，从而影响了像素内液晶分子的有效排布，进一步降低了整个面板的穿透率效果。
 技术解决方案
为实现上述目的，本发明提供一种像素电极，所述像素电极包括电极区以及镂空区。所述镂空区分布于所述电极区之间。其中，所述镂空区具有主体部和位于主体部两端的端部，其中所述主体部具有一宽度。至少一端部为膨胀体，其也具有一宽度，所述主体部的宽度小于所述膨胀体的宽度。
进一步地，所述膨胀体为优弧形。
进一步地，位于所述主体部的两端的端部均为膨胀体。
进一步地，位于所述主体部的两端的端部其中一端为膨胀体，另一端延伸至所述电极区并形成镂空的缺口。
进一步地，在所述缺口处，所述电极区形成有拐角，所述拐角的边缘为弧形边缘。
本发明中还提供一种阵列基板，所述阵列基板包括如上所述的像素电极。
进一步地，所述阵列基板还包括薄膜晶体管结构层、平坦层以及钝化层。所述平坦层设于所述薄膜晶体管结构层上。所述钝化层设于所述平坦层上。所述像素电极设于所述钝化层上。
进一步地，所述薄膜晶体管结构层中具有源漏极层。所述平坦层上具有一第一过孔，钝化层上具有一第二过孔，所述第一过孔对应于所述第二过孔，所述像素电极穿过所述第一过孔和所述第二过孔与所述源漏极层连接。
进一步地，所述第一过孔的孔径小于7微米，所述第二过孔的孔径小于5微米。
本发明中还提供一种显示装置，包括如上所述的像素电极。
 有益效果
本发明的优点是：本发明的一种像素电极，通过对其两端部的重新设计，使其边缘其余的液晶分子排布更加接近有效显示区域的液晶分子排布，增加背光光源的透过效果。从而改善现有面板的穿透率水准，达到提升对比度和增强续航能力的目的。并且本发明中的一种阵列基板，其个膜层中的挖孔根据所述像素电极的镂空区的两端部的增大而做出相应的调整，可以进一步消除暗纹，提高背光透过率。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例1中像素电极的结构示意图；
图2为本发明实施例2中像素电极的结构示意图；
图3为本发明实施例3中像素电极的结构示意图；
图4为本发明实施例1-3中阵列基板的层状结构示意图。
图中部件表示如下：
像素电极100；
电极区110；第一接触部111；
第二接触部112；连接部113；
镂空区120；主体部121；
端部122、123；
阵列基板1000；
薄膜晶体管结构层200；
基层210；有源层220；
掺杂区221；第一绝缘层230；
栅极层240；第二绝缘层250；
源漏极层260；接触孔270；
平坦层300；第一过孔310；
钝化层400；第二过孔410；
公共电极500。
 本发明的实施方式
下面详细描述本申请的实施方式，所述实施方式的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本申请，而不能理解为对本申请的限制。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
实施例1
本发明实施例中提供一种像素电极100，所述像素电极为长条形。
如图1所示，所述像素电极100包括电极区110和镂空区120，在本发明实施例中，所述像素电极100具有两个镂空区120以及一个电极区110。所述镂空区120均匀分布于所述电极区110上，所述电极区110将所述镂空区120包围。
所述电极区110包括第一接触部111、第二接触部112和三个连接部113。所述连接部113为长条形，每两个连接部113之间相互平行，并且所述连接部113与所述镂空区120相互交叠设置。所述第一接触部111和所述第二接触部112分别设于所述连接部113的两端。所述第一接触部111和所述第二接触部112用于与阵列基板中的结构层进行接触连接，所述连接部113用于传输电流。
所述镂空区120平均分布在所述像素电极100上，并且所述镂空区120之间互相平行。每一镂空区120具有一主体部121和位于主体部121两端的端部122和端部123。其中，所述主体部121为长条形，其具有一宽度。位于所述镂空区120的两端的端部122和端部123均为膨胀体，所述膨胀体也具有一宽度，所述主体部121的宽度小于所述端部122和所述端部123的宽度。并且，所述膨胀体为优弧形。所述镂空区用于透过所述背光，为所述显示面板提供光线。
所述像素电极100的材料为氧化铟锡（ITO）。所述像素电极100通过加大所述镂空区120两端的端部122和端部123的设计，改善了液晶分子排布，消除或减弱了像素显示区域的暗纹，从而达到增加面板穿透率的目的。
在本发明实施例中，所述像素电极100为单像素双畴结构，但是在其他实施例中，所述像素电极100还可以为其他结构，例如双像素双畴结构等其他像素结构，其镂空区120以及电极区110的设计与本发明实施例中单像素双畴结构的像素电极100相似，因此不在此做过多赘述。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其它实施例，都属于本申请保护的范围。
如图4所示，本发明实施例中还提供一种阵列基板1000，所述阵列基板1000包括一薄膜晶体管结构层200、一平坦层300、一钝化层400以及如上所述的像素电极100。
所述薄膜晶体管结构层200中包括基层210、有源层220、第一绝缘层230、栅极层240、第二绝缘层250以及源漏极层260。
所述基板为绝缘基板，所述绝缘基板的材料可以为玻璃或石英等绝缘材料，用于保护所述阵列基板1000的整体结构。
所述有源层220设于所述基层210上。在所述有源层220的两端分别具一掺杂区221，所述掺杂区221可以通过离子掺杂技术制备而成，如通过N型重掺杂工艺将所述有源层220两端的掺杂区221掺杂相同类型的离子N型离子，或通过P型重掺杂工艺将所述有源层220两端的掺杂区221掺杂相同类型的离子P型离子。进行掺杂工艺后的所述掺杂可以减少所述源漏极层260与所述有源层220之间的接触电阻，降低所述阵列基板1000的泄露电流，并提升所述阵列基板1000的电性能。
所述第一绝缘层230设于所述基层210上，并覆盖所述有源层220。所述第一绝缘层230可以由绝缘材料沉积而成，所述绝缘材料可为氧化硅、氮化硅或氮氧化硅中的一种。所述第一绝缘层230用于保护以及隔绝所述有源层220。
所述栅极层240设于所述第一绝缘层230上，并与所述有源层相互对应。所述栅极层240由导电材料制备而成，所述导电材料可以为钨、铬、铝、铜等。所述栅极层240用于通过电压产生电场，从而改变导电沟道的厚度，以达到控制所述源漏极层260的电流的目的。
所述第二绝缘层250设于所述第一绝缘层230上，并覆盖所述栅极层240。所述第二绝缘层250可以通过化学气相沉积法沉积而成。所述第二绝缘层250还可以采用介质隔离技术，由绝缘电介质材料制成，所述绝缘电介质材料可以为氧化硅、氮化硅或氮氧化硅中的一种。所述第二绝缘层250用于隔离金属走线，所述金属走线为如所述栅极层240和所述源漏极层260，防止所述栅极层240和所述源漏极层260发生短路。
所述薄膜晶体管结构层200中还包括接触孔270，所述接触孔270从所述第二绝缘层250贯穿至所述第一绝缘层230，并延伸至所述有源层220上。其中，所述接触孔270分别对应于所述有源层220的两端的掺杂区221。所述接触孔270的孔径小于5微米。
所述源漏极层260设于所述第二绝缘层250上。所述源漏极层260可以通过将金属图案化而形成。所述源漏极层260分别通过一所述接触孔270对应连接至所述有源层220的掺杂区221。
所述平坦层300设于所述薄膜晶体管结构层200的第二绝缘层250上，并覆盖所述源漏极层260。所述平坦层300一般采用有机材料制成，其用于将所述薄膜晶体管结构层200平坦化，并保护所述源漏极层260，防止所述源漏极发生短路及腐蚀。
所述钝化层400设于所述平坦层300上，在所述钝化层400与所述平坦层300之间有公共电极500，所述钝化层400用于钝化所述公共电极500，防止所述公共电极500层发生腐蚀从而出现短路等现象。
在所述平坦层300上具有一第一过孔310，在所述钝化层400上具有一第二过孔410，所述第一过孔310与所述第二过孔410相互对应。所述第一过孔310的孔径小于7微米，所述第二过孔410的孔径小于5微米。
所述像素电极100设于所述钝化层400上，并且所述像素电极100穿过所述第一过孔310和所述第二过孔410与所述源漏极层260连接。
在本发明实施例中，所述像素电极100的两端均采用膨大体设计，但由于在现有技术中所述像素电极100的两端被所述公共电极500的挖孔所覆盖，故而所述像素电极100的膨大体设计的作用效果有限。在本发明实施例中可以将所述公共电极500挖孔缩小来进一步消除暗纹，同时需将所述阵列基板1000中的其他膜层做进一步调整。其中，所述公共电极500的挖孔孔径小于13微米，所述源漏极层260的走线宽度范围小于10微米，所述平坦层300上的第一过孔310的孔径小于7微米，所述钝化层400上的第二过孔410的孔径小于5微米，所述第二绝缘层250上的接触孔270的孔径小于5微米。
在本发明实施例中，所述阵列基板1000为10次光刻背沟道刻蚀型结构，但是在其他实施例中，所述阵列基板1000还可以为其他结构，例如12次光刻背沟道刻蚀型结构、9次光刻背沟道刻蚀型结构、8次光刻背沟道刻蚀型结构等其他结构，其像素电极100的设计与本发明实施例中10次光刻背沟道刻蚀型结构的阵列基板1000相似，因此不在此做过多赘述。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其它实施例，都属于本申请保护的范围。
本发明实施例还提供一种显示装置（图未示），包括以上所述像素电极100以及所述阵列基板1000，所述显示装置可以为液晶显示器、手机、平板电脑、笔记本电脑、数码相机、导航仪等任何具有显示功能的产品或者部件。
本实施例中提供的一种像素电极100，将其镂空区120的两端的端部122和端部123采用膨胀体设计，使其边缘其余的液晶分子排布更加接近有效显示区域的液晶分子排布，增加背光光源的透过效果，从而改善现有面板的穿透率水准，达到提升对比度和增强续航能力的目的。并且本发明中的一种阵列基板1000，其个膜层中的挖孔根据所述像素电极100的镂空区120的两端部的增大而做出相应的调整，可以进一步消除暗纹，提高背光透过率。
实施例2
本发明实施例中提供一种像素电极100，所述像素电极为长条形。
如图2所示，所述像素电极100包括电极区110和镂空区120，在本发明实施例中，所述像素电极100具有两个镂空区120以及一个电极区110。所述镂空区120均匀分布于所述电极区110上。
所述电极区110包括第一接触部111、三个第二接触部112和三个连接部113。所述连接部113为长条形，每两个连接部113之间相互平行，并且所述连接部113与所述镂空区120相互交叠设置。所述第一接触部111和所述第二接触部112分别设于所述连接部113的两端。其中，所述第二接触部112为拐角形，所述拐角的边缘为弧形边缘，所述第二接触部112分别对应设于与所述连接部113的一端，并且所述拐角形的第二接触部112的朝向一致。所述第一接触部111和所述第二接触部112用于与阵列基板中的结构层进行接触连接，所述连接部113用于传输电流。
所述镂空区120平均分布在所述像素电极100上，并且所述镂空区120之间互相平行。每一镂空区120具有一主体部121和位于主体部121两端的端部122和端部123。其中，所述主体部121为长条形，其具有一宽度。所述镂空区120靠近所述第一接触部111的端部122为膨胀体，所述镂空区120靠近所述第二接触部112端部123为延伸至所述第二接触部112并形成镂空的缺口，促使所述第二接触部112形成所述拐角。所述膨胀体也具有一宽度，所述主体部121的宽度小于所述端部122的宽度。并且，所述膨胀体为优弧形。所述镂空区用于透过所述背光，为所述显示面板提供光线。
所述像素电极100的材料为氧化铟锡（ITO）。所述像素电极100通过加大所述镂空区120两端的端部122和端部123的设计，改善了液晶分子排布，消除或减弱了像素显示区域的暗纹，从而达到增加面板穿透率的目的。
在本发明实施例中，所述像素电极100为单像素双畴结构，但是在其他实施例中，所述像素电极100还可以为其他结构，例如双像素双畴结构等其他像素结构，其镂空区120以及电极区110的设计与本发明实施例中单像素双畴结构的像素电极100相似，因此不在此做过多赘述。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其它实施例，都属于本申请保护的范围。
如图4所示，本发明实施例中还提供一种阵列基板1000，所述阵列基板1000包括一薄膜晶体管结构层200、一平坦层300、一钝化层400以及如上所述的像素电极100。
所述薄膜晶体管结构层200中包括基层210、有源层220、第一绝缘层230、栅极层240、第二绝缘层250以及源漏极层260。
所述基板为绝缘基板，所述绝缘基板的材料可以为玻璃或石英等绝缘材料，用于保护所述阵列基板1000的整体结构。
所述有源层220设于所述基层210上。在所述有源层220的两端分别具一掺杂区221，所述掺杂区221可以通过离子掺杂技术制备而成，如通过N型重掺杂工艺将所述有源层220两端的掺杂区221掺杂相同类型的离子N型离子，或通过P型重掺杂工艺将所述有源层220两端的掺杂区221掺杂相同类型的离子P型离子。进行掺杂工艺后的所述掺杂可以减少所述源漏极层260与所述有源层220之间的接触电阻，降低所述阵列基板1000的泄露电流，并提升所述阵列基板1000的电性能。
所述第一绝缘层230设于所述基层210上，并覆盖所述有源层220。所述第一绝缘层230可以由绝缘材料沉积而成，所述绝缘材料可为氧化硅、氮化硅或氮氧化硅中的一种。所述第一绝缘层230用于保护以及隔绝所述有源层220。
所述栅极层240设于所述第一绝缘层230上，并与所述有源层相互对应。所述栅极层240由导电材料制备而成，所述导电材料可以为钨、铬、铝、铜等。所述栅极层240用于通过电压产生电场，从而改变导电沟道的厚度，以达到控制所述源漏极层260的电流的目的。
所述第二绝缘层250设于所述第一绝缘层230上，并覆盖所述栅极层240。所述第二绝缘层250可以通过化学气相沉积法沉积而成。所述第二绝缘层250还可以采用介质隔离技术，由绝缘电介质材料制成，所述绝缘电介质材料可以为氧化硅、氮化硅或氮氧化硅中的一种。所述第二绝缘层250用于隔离金属走线，所述金属走线为如所述栅极层240和所述源漏极层260，防止所述栅极层240和所述源漏极层260发生短路。
所述薄膜晶体管结构层200中还包括接触孔270，所述接触孔270从所述第二绝缘层250贯穿至所述第一绝缘层230，并延伸至所述有源层220上。其中，所述接触孔270分别对应于所述有源层220的两端的掺杂区221。所述接触孔270的孔径小于5微米。
所述源漏极层260设于所述第二绝缘层250上。所述源漏极层260可以通过将金属图案化而形成。所述源漏极层260分别通过一所述接触孔270对应连接至所述有源层220的掺杂区221。
所述平坦层300设于所述薄膜晶体管结构层200的第二绝缘层250上，并覆盖所述源漏极层260。所述平坦层300一般采用有机材料制成，其用于将所述薄膜晶体管结构层200平坦化，并保护所述源漏极层260，防止所述源漏极发生短路及腐蚀。
所述钝化层400设于所述平坦层300上，在所述钝化层400与所述平坦层300之间有公共电极500，所述钝化层400用于钝化所述公共电极500，防止所述公共电极500层发生腐蚀从而出现短路等现象。
在所述平坦层300上具有一第一过孔310，在所述钝化层400上具有一第二过孔410，所述第一过孔310与所述第二过孔410相互对应。所述第一过孔310的孔径小于7微米，所述第二过孔410的孔径小于5微米。
所述像素电极100设于所述钝化层400上，并且所述像素电极100穿过所述第一过孔310和所述第二过孔410与所述源漏极层260连接。
在本发明实施例中，所述像素电极100的两端中的一端采用膨大体设计，另一端采用缺口设计，但由于在现有技术中所述像素电极100的两端被所述公共电极500的挖孔所覆盖，故而所述像素电极100的膨大体设计的作用效果有限。在本发明实施例中可以将所述公共电极500挖孔缩小来进一步消除暗纹，同时需将所述阵列基板1000中的其他膜层做进一步调整。其中，所述公共电极500的挖孔孔径小于13微米，所述源漏极层260的走线宽度范围小于10微米，所述平坦层300上的第一过孔310的孔径小于7微米，所述钝化层400上的第二过孔410的孔径小于5微米，所述第二绝缘层250上的接触孔270的孔径小于5微米。
在本发明实施例中，所述阵列基板1000为10PEP结构，但是在其他实施例中，所述阵列基板1000还可以为其他结构，例如12PEP结构、9PEP结构、8PEP结构等其他结构，其像素电极100的设计与本发明实施例中10PEP结构的阵列基板1000相似，因此不在此做过多赘述。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其它实施例，都属于本申请保护的范围。
本发明实施例还提供一种显示装置（图未示），包括以上所述像素电极100以及所述阵列基板1000，所述显示装置可以为液晶显示器、手机、平板电脑、笔记本电脑、数码相机、导航仪等任何具有显示功能的产品或者部件。
本实施例中提供的一种像素电极100，将其镂空区120的两端的端部122设为膨胀体，端部123设为延伸至所述第二接触部112并形成镂空的缺口，并在所述第二接触部112形成拐角，这种设计使其边缘其余的液晶分子排布更加接近有效显示区域的液晶分子排布，增加背光光源的透过效果，从而改善现有面板的穿透率水准，达到提升对比度和增强续航能力的目的。并且本发明中的一种阵列基板1000，其个膜层中的挖孔根据所述像素电极100的镂空区120的两端部的增大而做出相应的调整，可以进一步消除暗纹，提高背光透过率。
实施例3
本发明实施例中提供一种像素电极100，所述像素电极为“ㄑ”形。
如图3所示，所述像素电极100包括电极区110和镂空区120，在本发明实施例中，所述像素电极100具有两个镂空区120以及一个电极区110。所述镂空区120均匀分布于所述电极区110上。
所述电极区110包括第一接触部111、三个第二接触部112和三个连接部113。所述连接部113为“ㄑ”形，每两个连接部113之间相互平行，并且所述连接部113与所述镂空区120相互交叠设置。所述第一接触部111和所述第二接触部112分别设于所述连接部113的两端。其中，所述第二接触部112为拐角形，所述拐角的边缘为弧形边缘，所述第二接触部112分别对应设于与所述连接部113的一端，并且所述拐角形的第二接触部112的朝向一致。所述第一接触部111和所述第二接触部112用于与阵列基板中的结构层进行接触连接，所述连接部113用于传输电流。
所述镂空区120平均分布在所述像素电极100上，并且所述镂空区120之间互相平行。每一镂空区120具有一主体部121和位于主体部121两端的端部122和端部123。其中，所述主体部121为“ㄑ”形，其具有一宽度。所述镂空区120靠近所述第一接触部111的端部122为膨胀体，所述镂空区120靠近所述第二接触部112端部123为延伸至所述第二接触部112并形成镂空的缺口，促使所述第二接触部112形成所述拐角。所述膨胀体也具有一宽度，所述主体部121的宽度小于所述端部122的宽度。并且，所述膨胀体为优弧形。所述镂空区用于透过所述背光，为所述显示面板提供光线。
所述像素电极100的材料为氧化铟锡（ITO）。所述像素电极100通过加大所述镂空区120两端的端部122和端部123的设计，改善了液晶分子排布，消除或减弱了像素显示区域的暗纹，从而达到增加面板穿透率的目的。
在本发明实施例中，所述像素电极100为单像素双畴结构，但是在其他实施例中，所述像素电极100还可以为其他结构，例如双像素双畴结构等其他像素结构，其镂空区120以及电极区110的设计与本发明实施例中单像素双畴结构的像素电极100相似，因此不在此做过多赘述。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其它实施例，都属于本申请保护的范围。
如图4所示，本发明实施例中还提供一种阵列基板1000，所述阵列基板1000包括一薄膜晶体管结构层200、一平坦层300、一钝化层400以及如上所述的像素电极100。
所述薄膜晶体管结构层200中包括基层210、有源层220、第一绝缘层230、栅极层240、第二绝缘层250以及源漏极层260。
所述基板为绝缘基板，所述绝缘基板的材料可以为玻璃或石英等绝缘材料，用于保护所述阵列基板1000的整体结构。
所述有源层220设于所述基层210上。在所述有源层220的两端分别具一掺杂区221，所述掺杂区221可以通过离子掺杂技术制备而成，如通过N型重掺杂工艺将所述有源层220两端的掺杂区221掺杂相同类型的离子N型离子，或通过P型重掺杂工艺将所述有源层220两端的掺杂区221掺杂相同类型的离子P型离子。进行掺杂工艺后的所述掺杂可以减少所述源漏极层260与所述有源层220之间的接触电阻，降低所述阵列基板1000的泄露电流，并提升所述阵列基板1000的电性能。
所述第一绝缘层230设于所述基层210上，并覆盖所述有源层220。所述第一绝缘层230可以由绝缘材料沉积而成，所述绝缘材料可为氧化硅、氮化硅或氮氧化硅中的一种。所述第一绝缘层230用于保护以及隔绝所述有源层220。
所述栅极层240设于所述第一绝缘层230上，并与所述有源层相互对应。所述栅极层240由导电材料制备而成，所述导电材料可以为钨、铬、铝、铜等。所述栅极层240用于通过电压产生电场，从而改变导电沟道的厚度，以达到控制所述源漏极层260的电流的目的。
所述第二绝缘层250设于所述第一绝缘层230上，并覆盖所述栅极层240。所述第二绝缘层250可以通过化学气相沉积法沉积而成。所述第二绝缘层250还可以采用介质隔离技术，由绝缘电介质材料制成，所述绝缘电介质材料可以为氧化硅、氮化硅或氮氧化硅中的一种。所述第二绝缘层250用于隔离金属走线，所述金属走线为如所述栅极层240和所述源漏极层260，防止所述栅极层240和所述源漏极层260发生短路。
所述薄膜晶体管结构层200中还包括接触孔270，所述接触孔270从所述第二绝缘层250贯穿至所述第一绝缘层230，并延伸至所述有源层220上。其中，所述接触孔270分别对应于所述有源层220的两端的掺杂区221。所述接触孔270的孔径小于5微米。
所述源漏极层260设于所述第二绝缘层250上。所述源漏极层260可以通过将金属图案化而形成。所述源漏极层260分别通过一所述接触孔270对应连接至所述有源层220的掺杂区221。
所述平坦层300设于所述薄膜晶体管结构层200的第二绝缘层250上，并覆盖所述源漏极层260。所述平坦层300一般采用有机材料制成，其用于将所述薄膜晶体管结构层200平坦化，并保护所述源漏极层260，防止所述源漏极发生短路及腐蚀。
所述钝化层400设于所述平坦层300上，在所述钝化层400与所述平坦层300之间有公共电极500，所述钝化层400用于钝化所述公共电极500，防止所述公共电极500层发生腐蚀从而出现短路等现象。
在所述平坦层300上具有一第一过孔310，在所述钝化层400上具有一第二过孔410，所述第一过孔310与所述第二过孔410相互对应。所述第一过孔310的孔径小于7微米，所述第二过孔410的孔径小于5微米。
所述像素电极100设于所述钝化层400上，并且所述像素电极100穿过所述第一过孔310和所述第二过孔410与所述源漏极层260连接。
在本发明实施例中，所述像素电极100的两端均采用膨大体设计，但由于在现有技术中所述像素电极100的两端被所述公共电极500的挖孔所覆盖，故而所述像素电极100的膨大体设计的作用效果有限。在本发明实施例中可以将所述公共电极500挖孔缩小来进一步消除暗纹，同时需将所述阵列基板1000中的其他膜层做进一步调整。其中，所述公共电极500的挖孔孔径小于13微米，所述源漏极层260的走线宽度范围小于10微米，所述平坦层300上的第一过孔310的孔径小于7微米，所述钝化层400上的第二过孔410的孔径小于5微米，所述第二绝缘层250上的接触孔270的孔径小于5微米。
在本发明实施例中，所述阵列基板1000为10次光刻背沟道刻蚀型结构，但是在其他实施例中，所述阵列基板1000还可以为其他结构，例如12次光刻背沟道刻蚀型结构、9次光刻背沟道刻蚀型结构、8次光刻背沟道刻蚀型结构等其他结构，其像素电极100的设计与本发明实施例中10次光刻背沟道刻蚀型结构的阵列基板1000相似，因此不在此做过多赘述。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其它实施例，都属于本申请保护的范围。
本发明实施例还提供一种显示装置（图未示），包括以上所述像素电极100以及所述阵列基板1000，所述显示装置可以为液晶显示器、手机、平板电脑、笔记本电脑、数码相机、导航仪等任何具有显示功能的产品或者部件。
本实施例中提供的一种像素电极100，将其镂空区120的两端的端部122设为膨胀体，端部123设为延伸至所述第二接触部112并形成镂空的缺口，并在所述第二接触部112形成拐角，这种设计使其边缘其余的液晶分子排布更加接近有效显示区域的液晶分子排布，增加背光光源的透过效果，从而改善现有面板的穿透率水准，达到提升对比度和增强续航能力的目的。并且本发明中的一种阵列基板1000，其个膜层中的挖孔根据所述像素电极100的镂空区120的两端部的增大而做出相应的调整，可以进一步消除暗纹，提高背光透过率。
虽然在本文中参照了特定的实施方式来描述本发明，但是应该理解的是，这些实施例仅仅是本发明的原理和应用的示例。因此应该理解的是，可以对示例性的实施例进行许多修改，并且可以设计出其他的布置，只要不偏离所附权利要求所限定的本发明的精神和范围。应该理解的是，可以通过不同于原始权利要求所描述的方式来结合不同的从属权利要求和本文中所述的特征。还可以理解的是，结合单独实施例所描述的特征可以使用在其他所述实施例中。

Claims (10)

  1. 一种像素电极，其包括
    电极区，以及
    至少一镂空区，分布于所述电极区之间；其中，所述镂空区具有主体部和位于主体部两端的端部，其中所述主体部具有一宽度；至少一端部为膨胀体，其也具有一宽度，所述主体部的宽度小于所述膨胀体的宽度。
  2. 如权利要求1所述的像素电极，其中，所述膨胀体为优弧形。
  3. 如权利要求1所述的像素电极，其中，位于所述主体部的两端的端部均为膨胀体。
  4. 如权利要求1所述的像素电极，其中，位于所述主体部的两端的端部其中一端为膨胀体，另一端延伸至所述电极区并形成镂空的缺口。
  5. 如权利要求4所述的像素电极，其中，在所述缺口处，所述电极区形成有拐角，所述拐角的边缘为弧形边缘。
  6. 一种阵列基板，其中，包括如权利要求1中所述的像素电极。
  7. 如权利要求6所述的阵列基板，其包括：
    薄膜晶体管结构层；
    平坦层，设于所述薄膜晶体管结构层上；以及
    钝化层，设于所述平坦层上；
    所述像素电极设于所述钝化层上。
  8. 如权利要求7所述的阵列基板，其中，
    所述薄膜晶体管结构层中具有源漏极层；
    所述平坦层上具有一第一过孔，钝化层上具有一第二过孔，所述第一过孔对应于所述第二过孔，所述像素电极穿过所述第一过孔和所述第二过孔与所述源漏极层连接。
  9. 如权利要求8所述的阵列基板，其中，所述第一过孔的孔径小于7微米，所述第二过孔的孔径小于5微米。
  10. 一种显示装置，其包括如权利要求1中所述的像素电极。
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