WO2020252955A1 - 阵列基板的制备方法和制备系统 - Google Patents

阵列基板的制备方法和制备系统 Download PDF

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Publication number
WO2020252955A1
WO2020252955A1 PCT/CN2019/106631 CN2019106631W WO2020252955A1 WO 2020252955 A1 WO2020252955 A1 WO 2020252955A1 CN 2019106631 W CN2019106631 W CN 2019106631W WO 2020252955 A1 WO2020252955 A1 WO 2020252955A1
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Prior art keywords
layer
protective layer
gate
array substrate
gate insulating
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English (en)
French (fr)
Inventor
章仟益
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]

Definitions

  • the present application relates to the field of display technology, and in particular to a manufacturing method and manufacturing system of an array substrate.
  • the conductorization process is completed after the gate insulating layer is etched, and then ashing is performed to remove the photoresist.
  • the use of oxygen in the ashing process will change the conductorization effect of the boundary layer and reduce the contact area with the source and drain
  • the size and effect of the conductive area depends on the gate insulating layer. If the etching uniformity of the gate insulating layer fluctuates or the dry etching increases horizontally, the conductor The effect of transformation becomes worse, which affects the length of the channel region that has not been made conductive.
  • the existing top-gate structure thin film transistor has the technical problem of poor conductive effect of the active layer, which needs to be improved.
  • the present application provides a preparation method and preparation system of an array substrate to solve the technical problem of poor conductive effect of the active layer in the existing array substrate.
  • This application provides a method for manufacturing an array substrate, including:
  • the protective layer pattern as a mask to etch the gate layer to form a gate
  • the protective layer pattern as a mask, conduct a conductive process on a first area of the active layer, the first area being an area not covered by the projection of the protective layer pattern on the active layer ;
  • the first region of the active layer is conductively processed using the protective layer pattern as a mask, and the first region is not covered by the protective layer.
  • the step of the area covered by the projection of the pattern on the active layer includes: irradiating the first area with an excimer laser.
  • the step of irradiating the first region with an excimer laser includes: irradiating with a krypton fluoride laser.
  • the step of irradiating the first region with an excimer laser includes: irradiating with an argon fluoride laser.
  • the step of irradiating the first region with an excimer laser includes: irradiating with a xenon chloride laser.
  • the first region of the active layer is conductively processed using the protective layer pattern as a mask, and the first region is not covered by the protective layer.
  • the step of patterning the area covered by the projection of the pattern on the active layer includes baking the first area.
  • the step of baking the first region includes: baking at a temperature of 300°C to 350°C.
  • the active layer, the gate insulating layer, the gate layer, and the protective layer are sequentially prepared on the substrate, and the protective layer is patterned to form a protective layer pattern
  • the steps include: coating photoresist on the gate layer, and patterning the photoresist.
  • the step of etching the gate layer to form a gate using the protective layer pattern as a mask includes: wet etching the gate layer .
  • the step of etching the gate insulating layer to form a gate insulating layer pattern using the protective layer pattern as a mask includes: applying a dry method to the gate insulating layer Etching.
  • the step of using dry etching on the gate insulating layer includes: using an enhanced capacitive coupling plasma dry etching method on the gate insulating layer.
  • the step of using the enhanced capacitively coupled plasma dry etching method to etch the gate insulating layer includes: using a mixed gas of fluorine gas and oxygen to perform dry etching.
  • the active layer, the gate insulating layer, the gate layer, and the protective layer are sequentially prepared on the substrate, and the protective layer is patterned to form a protective layer pattern
  • the steps include: using physical vapor deposition to deposit the active layer.
  • the method further includes: patterning the active layer.
  • the active layer, the gate insulating layer, the gate layer, and the protective layer are sequentially prepared on the substrate, and the protective layer is patterned to form a protective layer pattern
  • the steps include: depositing a gate insulating layer by chemical vapor deposition.
  • the active layer, the gate insulating layer, the gate layer, and the protective layer are sequentially prepared on the substrate, and the protective layer is patterned to form a protective layer pattern
  • the steps include: depositing the gate layer by chemical vapor deposition.
  • the active layer, the gate insulating layer, the gate layer, and the protective layer are sequentially prepared on the substrate, and the protective layer is patterned to form a protective layer pattern
  • the method further includes: forming a light shielding layer on the substrate, and forming a buffer layer on the side of the light shielding layer away from the substrate.
  • the step of peeling off the protective layer pattern after the step of peeling off the protective layer pattern, it further includes: forming a dielectric layer, a source electrode, a drain electrode, and a dielectric layer on the side of the gate electrode away from the gate insulating layer. Passivation layer.
  • the application also provides a preparation system of an array substrate, including:
  • Active layer preparation device for forming an active layer on a substrate
  • a gate insulating layer preparation device for forming a gate insulating layer on the active layer
  • a protective layer pattern forming device for forming a protective layer on the gate layer and patterning to form a protective layer pattern
  • a gate etching device which is used to etch the gate layer to form a gate using the protective layer pattern as a mask
  • the conductive device is used to use the protective layer pattern as a mask to conduct a conductive treatment on the first region of the active layer, wherein the first region is not covered by the protective layer pattern on the active layer Projection coverage on
  • a gate insulating layer etching device which is used to etch the gate insulating layer to form a gate insulating layer pattern by using the protective layer pattern as a mask;
  • the protective layer removing device is used to peel off the protective layer pattern.
  • the conductorization device includes an excimer laser irradiation member.
  • the present application provides a preparation method and preparation system of an array substrate.
  • the preparation method includes: providing a substrate; sequentially preparing stacked active layers, gate insulating layers, gate layers, and protective layers on the substrate; The protective layer is patterned to form a protective layer pattern; using the protective layer pattern as a mask, the gate layer is etched to form a gate; using the protective layer pattern as a mask, the active layer Conduction processing is performed on the first area of the first area, the area not covered by the projection of the protective layer pattern on the active layer; using the protective layer pattern as a mask, the gate is insulated The layer is etched to form a gate insulating layer pattern; the protective layer pattern is stripped.
  • the protective layer pattern is used as a mask to conduct a conductive process on the active layer through the gate insulating layer to make the conductive position more accurate.
  • the protective layer pattern is removed by stripping, which will not cause the resistivity of the active layer rise.
  • FIG. 1 is a flowchart of a method for manufacturing an array substrate provided by an embodiment of the application
  • FIG. 2 is a schematic structural diagram of the first stage in the preparation process of the array substrate provided by the embodiment of the application;
  • FIG. 3 is a schematic structural diagram of the second stage in the preparation process of the array substrate provided by the embodiment of the application;
  • FIG. 4 is a schematic structural diagram of the third stage in the preparation process of the array substrate provided by the embodiment of the application;
  • FIG. 5 is a schematic structural diagram of the fourth stage in the preparation process of the array substrate provided by the embodiment of the application;
  • FIG. 6 is a schematic structural diagram of the fifth stage in the preparation process of the array substrate provided by the embodiment of the application;
  • FIG. 7 is a schematic structural diagram of the sixth stage in the preparation process of the array substrate provided by the embodiment of the application.
  • FIG. 8 is a schematic structural diagram of the seventh stage in the preparation process of the array substrate provided by the embodiment of the application.
  • FIG. 9 is a schematic structural diagram of the eighth stage in the preparation process of the array substrate provided by an embodiment of the application.
  • FIG. 10 is a schematic structural diagram of the ninth stage in the preparation process of the array substrate provided by an embodiment of the application.
  • FIG. 11 is a schematic structural diagram of a tenth stage in the preparation process of the array substrate provided by the embodiment of the application.
  • the manufacturing method of the array substrate provided by the present application includes the following steps:
  • the active layer, the gate insulating layer, the gate layer, and the protective layer are sequentially prepared on the substrate, and the protective layer is patterned to form a protective layer pattern;
  • a substrate 10 is provided first.
  • the substrate 10 can be an insulating and transparent glass substrate or a resin substrate.
  • the substrate 10 is pre-cleaned, and then a light shielding layer 20 and a buffer layer 30 are formed on the substrate 10. .
  • the light shielding layer 20 may be a laminated molybdenum aluminum molybdenum (Mo/Al/Mo) structure or a laminated titanium aluminum titanium (Ti/Al/Ti) structure, or a single-layer molybdenum structure or a single-layer aluminum structure. It is deposited on the substrate 10 by a physical vapor deposition method, and then subjected to yellow light and dry etching and stripping processes to form a light shielding layer pattern. In an embodiment, the film thickness of the light shielding layer 20 is 150 nanometers.
  • the buffer layer 30 can be a stacked SiO x /SiN x structure, or a single-layer SiN x structure or a SiO x structure, and is deposited on the light shielding layer 20 by a chemical vapor deposition method.
  • the buffer layer 30 is a laminated SiO/SiN x structure, the film thickness of SiO is 200 nanometers, and the film thickness of SiN x is also 200 nanometers.
  • an active layer 40 is formed on the buffer layer 30 first.
  • the active layer 40 may use metal oxide materials such as zinc oxide ZnO, indium oxide InO, or multiple metal oxide semiconductors based on the above two materials such as indium gallium zinc oxide IGZO, indium zinc oxide IZO, zinc tin oxide ZTO, and hafnium oxide. Indium zinc HIZO, indium tin oxide ITO, etc.
  • the active layer 40 can be deposited on the buffer layer 30 by a method such as physical vapor deposition, after baking, a yellowing process is performed, and the active layer pattern is formed by oxalic acid etching.
  • the film thickness of the active layer 40 is 100 nanometers.
  • a gate insulating layer 50 and a gate 60 are formed on the active layer 40.
  • the material of the gate insulating layer 50 may be silicon oxide, which is deposited on the active layer 40 by a chemical vapor deposition method. In an embodiment, the thickness of the gate insulating layer 50 is 140 nanometers.
  • the material of the gate layer 60 can be conductive metals such as copper and silver, which are deposited on the gate insulating layer 50 by chemical vapor deposition.
  • the gate layer 60 has a Cu/Ti laminated structure, and a copper film The layer thickness is 400 nanometers, and the film thickness of titanium is 30 nanometers.
  • a protective layer 61 is deposited on the gate layer 60.
  • the material of the protective layer 61 is photoresist.
  • a monotone mask (not shown) is used to expose and develop the protective layer 61 to obtain a protective layer pattern 611.
  • step S3 as shown in FIG. 7, the gate layer 60 is exposed, developed, and etched using the protective layer pattern 611 as a mask to form a gate 601.
  • the gate electrode 601 is formed by wet etching with a cupric acid solution. Since the wet etching is isotropic, the width of the gate electrode 601 is smaller than the width of the protective layer pattern 611.
  • the protective layer pattern 611 is used as a mask to conduct a conductive process on the first area of the active layer 40, and the first area is the unprotected layer pattern 611 on the active layer 40
  • the area covered by the projection of, in this embodiment, the first area includes a source doped region 411 at one end of the active layer 40 and a drain doped region 412 at the other end of the active layer 40. There are many ways to conduct conductive treatment on this area.
  • the first area is irradiated with an excimer laser to realize conductorization.
  • Excimer laser is a gas pulse laser wave with strong directivity.
  • the irradiated area absorbs high energy. It generates heat through atomic vibration, which can reduce the barrier and increase the resistivity. It penetrates the gate insulating layer 50 to the active layer 40 After the bombardment, the resistivity of the active layer 40 changes significantly, and the process window is large.
  • the excimer laser is one of xenon chloride (XeCl) laser, argon fluoride (ArF) laser, krypton fluoride (KrF) laser, or xenon chloride (XeF) laser.
  • XeCl xenon chloride
  • ArF argon fluoride
  • KrF krypton fluoride
  • XeF xenon chloride
  • high-temperature baking is used for the first region to realize conductorization, and the baking temperature is 300°C to 350°C.
  • the energy in this region is increased, which can also reduce the potential barrier and increase the resistivity of the active layer 40.
  • the conductive process is performed by means of excimer laser irradiation or high-temperature baking, so that the contact performance between the active layer 40 and the source and drain contact areas is higher, the contact parasitic resistance is smaller, and the switching voltage of the semiconductor device is stable.
  • the size and effect of the conductorization area depend on the gate insulating layer. If the etching uniformity of the gate insulating layer fluctuates or the dry etching horizontally increases, it will The effect of the conduction is deteriorated, and the length of the channel region that is not processed for the conduction is affected, thereby causing the characteristics of the threshold voltage of the TFT to deteriorate, and affecting the product quality of the display device.
  • the protective layer pattern 611 is used as a mask, and the conductive area is not affected by the etching effect of the gate insulating layer, so that the conductive position is more accurate.
  • step S5 as shown in FIG. 9, a protective layer pattern 611 is used as a mask, and the gate insulating layer 50 is etched to form a gate insulating layer pattern 501.
  • the gate insulating layer 50 is etched by dry etching, including inductively coupled plasma (Inductively coupled plasma). Coupled Plasma (ICP) dry etching, enhanced capacitively coupled plasma (Enhanced Capacitive coupled Plasma (ECCP) dry etching or reactive ion etching (Reactive Ion Etching, RIE) dry etching, etc.
  • ICP inductively coupled plasma
  • ECCP Enhanced Capacitive coupled Plasma
  • RIE reactive Ion Etching
  • the etching of the gate insulating layer 50 adopts an enhanced capacitively coupled plasma (ECCP) process mode
  • the power is 500-2000W
  • the over-etching amount is 30-80%
  • the process gas can be fluorine-based gas and oxygen. mixed composition.
  • the fluorine-based gas includes one or more of sulfur hexafluoride SF 6 , nitrogen trifluoride NF 3 , carbon tetrafluoride CF 4 , and octafluorocyclobutane C 4 F 8.
  • the process gas It also includes many types, such as a mixed gas of sulfur hexafluoride SF 6 and oxygen O 2, a mixed gas of nitrogen trifluoride NF 3 and oxygen O 2 , or a mixed gas of carbon tetrafluoride CF 4 and oxygen O 2 Wait.
  • step S6 the protective layer pattern 611 is peeled off.
  • peeling refers to using a peeling liquid to remove the protective layer pattern 611, and the peeling liquid used is a mixture of acetone and ethanol.
  • an ashing process is used to remove the protective layer.
  • the use of oxygen in the ashing work may cause changes in the conductorization effect of the boundary layer and affect the contact resistance between the conductorized area and the source and drain.
  • a peeling method is used to remove the protective layer pattern 611, which can avoid the problem of increased resistivity caused by ashing after the conductorization.
  • a dielectric layer 70 is first formed on the surface of the gate 601, and a first via 711 and a second via 712 are formed in the dielectric layer 70.
  • a dielectric layer 70 is deposited on the gate 601, the dielectric layer 70 covers the active layer 40, the gate insulating pattern 501 and the gate 601, and then a layer of photoresist is coated on the dielectric layer 70, using a monotone mask
  • the plate exposes and develops the photoresist, and forms fully exposed areas at positions corresponding to the first via 711 and the second via 712 respectively. Without the photoresist, the dielectric layer 70 is exposed, and unexposed areas are formed at other positions.
  • the photoresist is left; after that, the dielectric layer 70 in the fully exposed area is etched and the remaining photoresist is stripped to form a pattern of the dielectric layer 70 with the first via 711 and the second via 712.
  • the first via 711 and the second via 712 are respectively disposed on the conductive regions at both ends of the active layer 40, wherein the first via 711 corresponds to the source doped region 411, and the second via 712 corresponds to the drain Doped region 412.
  • the material of the dielectric layer 70 is a composite layer structure composed of any combination of two or more of silicon oxide SiO x , silicon nitride SiN x , and silicon nitride compound. In one embodiment, the dielectric layer 70 The thickness of the film is 100-400 nanometers.
  • a source 81 and a drain 82 are formed on the dielectric layer 70.
  • a source metal film and a drain metal film are deposited on the dielectric layer 70, and a layer of photoresist is coated on the source metal film and the drain metal film; a single-tone mask is used for the source metal film and the drain.
  • the electrode metal film is exposed and developed, and unexposed areas are formed at the positions corresponding to the source electrode 81 and the drain electrode 82, and the photoresist is retained.
  • the fully exposed area is formed at other positions without the photoresist, exposing the source metal film and the drain electrode.
  • the electrode metal film; the source metal film and the drain metal film in the fully exposed area are etched and the remaining photoresist is stripped to form the source electrode 81 and the drain electrode 82.
  • the source 81 and the drain 82 are respectively connected to the conductive region through the first via 711 and the second via 712, wherein the source 81 is connected to the source doped region 411 through the first via 711, and the drain 82 passes through The second via 712 is connected to the drain doped region 412.
  • the material of the source electrode 81 and the drain electrode 82 can be one or more of platinum Pt, copper Cu, silver Ag, molybdenum Mo, chromium Cr, aluminum Al, tantalum Ta, titanium Ti, tungsten W and other metals.
  • the source 81 and the drain 8 adopt a copper/molybdenum structure, wherein the thickness of the copper film is 650 nanometers, and the thickness of the molybdenum film is 20 nanometers.
  • a passivation layer 90 is deposited on the dielectric layer 70.
  • the passivation layer 90 covers the source 81 and the drain 82 to protect the surface of the source 81 and the drain 82 from being oxidized.
  • the material for the passivation layer 90 can be For silicon oxide, etc.
  • the application also provides a preparation system of an array substrate, including:
  • Active layer preparation device for forming an active layer on a substrate
  • a gate insulating layer preparation device for forming a gate insulating layer on the active layer
  • the protective layer pattern forming device is used to form a protective layer on the gate layer and pattern the protective layer pattern;
  • the gate etching device is used to etch the gate layer to form a gate using the protective layer pattern as a mask;
  • the conductive device is used to conduct conductive processing on the first area of the active layer using the protective layer pattern as a mask, wherein the first area is not covered by the projection of the protective layer pattern on the active layer;
  • the gate insulating layer etching device is used to etch the gate insulating layer to form the gate insulating layer pattern by using the protective layer pattern as a mask;
  • Protective layer removal device for peeling the protective layer pattern.
  • the conductive device includes an excimer laser irradiation member for xenon chloride (XeCl) laser, argon fluoride (ArF) laser, krypton fluoride (KrF) laser, or xenon chloride (XeF) laser One of them.
  • XeCl xenon chloride
  • ArF argon fluoride
  • KrF krypton fluoride
  • XeF xenon chloride
  • the excimer laser is a gas pulse laser wave with strong directivity
  • the irradiated area absorbs high energy, and heat is generated by atomic vibration, which can reduce the barrier and increase the resistivity, and penetrate the gate insulating layer to perform the active layer After the bombardment, the resistivity of the active layer changes significantly, and the process window is large.
  • the conductorization device includes a baking member for baking the first region of the active layer at a temperature of 300°C to 350°C.
  • the energy in this region is increased, which can also reduce the potential barrier and increase the resistivity of the active layer.
  • the protective layer pattern is used as a mask, and the conductive area is not affected by the etching effect of the gate insulating layer, so that the conductive position is more accurate. At the same time, removing the protective layer pattern by means of peeling will not cause the resistivity of the active layer to increase.
  • the present application provides a preparation method and preparation system of an array substrate.
  • the preparation method includes: providing a substrate; sequentially preparing stacked active layers, gate insulating layers, gate layers, and protective layers on the substrate, and patterning the protective layer Form a protective layer pattern; use the protective layer pattern as a mask to etch the gate layer to form a gate; use the protective layer pattern as a mask to conduct a conductive treatment on the first area of the active layer, and the first area is not The area covered by the projection of the protective layer pattern on the active layer; using the protective layer pattern as a mask, the gate insulating layer is etched to form the gate insulating layer pattern; the protective layer pattern is stripped.
  • the protective layer pattern is used as a mask to conduct a conductive process on the active layer through the gate insulating layer to make the conductive position more accurate.
  • the protective layer pattern is removed by stripping, which will not cause the resistivity of the active layer rise.

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Abstract

一种阵列基板的制备方法和制备系统，制备方法包括：提供基板(S1)；在基板上制备有源层、栅绝缘层、栅极层、保护层，并图案化形成保护层图案(S2)；以保护层图案为掩模，对栅极层进行刻蚀形成栅极(S3)；对有源层的第一区域进行导体化处理，对栅绝缘层进行刻蚀形成栅绝缘层图案(S4-S5)；剥离保护层图案(S6)。上述方法使导体化位置更精准。

Description

阵列基板的制备方法和制备系统 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板的制备方法和制备系统。
 背景技术
现有的顶栅结构薄膜晶体管，一般在形成栅极及栅极绝缘层图形后，再对有源层导体化来形成源漏极的欧姆接触层。
导体化工艺在栅极绝缘层刻蚀后完成，之后进行灰化来去除光刻胶，一方面，灰化过程氧气的使用会导致有缘层的导体化效果发生变化，降低与源漏极接触区域的电阻率；另一方面，因采用自对位光罩，导体化区域大小及效果取决于栅极绝缘层，若栅极绝缘层刻蚀均一性出现波动或者干刻横向加大，会使导体化效果变差，影响未被导体化处理的沟道区长度。
因此，现有顶栅结构薄膜晶体管存在有源层导体化效果不佳的技术问题，需要改进。
 技术问题
本申请提供一种阵列基板的制备方法和制备系统，以解决现有阵列基板存在的有源层导体化效果不佳的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请提供一种阵列基板的制备方法，包括：
提供基板；
在所述基板上依次制备层叠设置的有源层、栅绝缘层、栅极层、保护层，并对所述保护层图案化形成保护层图案；
以所述保护层图案为掩模，对所述栅极层进行刻蚀形成栅极；
以所述保护层图案为掩模，对所述有源层的第一区域进行导体化处理，所述第一区域为未被所述保护层图案在所述有源层上的投影覆盖的区域；
以所述保护层图案为掩膜，对所述栅绝缘层进行刻蚀形成栅绝缘层图案；
剥离所述保护层图案。
在本申请的阵列基板的制备方法中，所述以所述保护层图案为掩模，对所述有源层的第一区域进行导体化处理，所述第一区域为未被所述保护层图案在所述有源层上的投影覆盖的区域的步骤包括：对所述第一区域进行准分子激光照射。
在本申请的阵列基板的制备方法中，所述对所述第一区域进行准分子激光照射的步骤包括：用氟化氪激光进行照射。
在本申请的阵列基板的制备方法中，所述对所述第一区域进行准分子激光照射的步骤包括：用氟化氩激光进行照射。
在本申请的阵列基板的制备方法中，所述对所述第一区域进行准分子激光照射的步骤包括：用氯化氙激光进行照射。
在本申请的阵列基板的制备方法中，所述以所述保护层图案为掩模，对所述有源层的第一区域进行导体化处理，所述第一区域为未被所述保护层图案在所述有源层上的投影覆盖的区域的步骤包括：对所述第一区域进行烘烤。
在本申请的阵列基板的制备方法中，所述对所述第一区域进行烘烤的步骤包括：用300℃至350℃温度烘烤。
在本申请的阵列基板的制备方法中，所述在所述基板上依次制备层叠设置的有源层、栅绝缘层、栅极层、保护层，并对所述保护层图案化形成保护层图案的步骤包括：在所述栅极层上涂布光刻胶，并对光刻胶图案化。
在本申请的阵列基板的制备方法中，所述以所述保护层图案为掩模，对所述栅极层进行刻蚀形成栅极的步骤包括：对所述栅极层采用湿法刻蚀。
在本申请的阵列基板的制备方法中，所述以所述保护层图案为掩膜，对所述栅绝缘层进行刻蚀形成栅绝缘层图案的步骤包括：对所述栅绝缘层采用干法刻蚀。
在本申请的阵列基板的制备方法中，所述对所述栅绝缘层采用干法刻蚀的步骤包括:对所述栅绝缘层采用增强电容耦合等离子体干刻法刻蚀。
在本申请的阵列基板的制备方法中，所述对所述栅绝缘层采用增强电容耦合等离子体干刻法刻蚀的步骤包括：采用氟系气体和氧气的混合气体进行干法刻蚀。
在本申请的阵列基板的制备方法中，所述在所述基板上依次制备层叠设置的有源层、栅绝缘层、栅极层、保护层，并对所述保护层图案化形成保护层图案的步骤包括：采用物理气相沉积法沉积有源层。
在本申请的阵列基板的制备方法中，在所述采用物理气相沉积法沉积有源层的步骤后还包括：对所述有源层进行图案化。
在本申请的阵列基板的制备方法中，所述在所述基板上依次制备层叠设置的有源层、栅绝缘层、栅极层、保护层，并对所述保护层图案化形成保护层图案的步骤包括：采用化学气相沉积法沉积栅绝缘层。
在本申请的阵列基板的制备方法中，所述在所述基板上依次制备层叠设置的有源层、栅绝缘层、栅极层、保护层，并对所述保护层图案化形成保护层图案的步骤包括：采用化学气相沉积法沉积栅极层。
在本申请的阵列基板的制备方法中，所述在所述基板上依次制备层叠设置的有源层、栅绝缘层、栅极层、保护层，并对所述保护层图案化形成保护层图案的步骤前还包括：在所述基板上形成遮光层，在所述遮光层远离所述基板的一侧形成缓冲层。
在本申请的阵列基板的制备方法中，所述剥离所述保护层图案的步骤后还包括：在所述栅极远离所述栅绝缘层的一侧形成介电层、源极、漏极和钝化层。
本申请还提供一种阵列基板的制备系统，包括：
有源层制备装置，用于在基板上形成有源层；
栅绝缘层制备装置，用于在所述有源层上形成栅绝缘层；
栅极层制备装置，用于在所述栅绝缘层上形成栅极层；
保护层图案形成装置，用于在所述栅极层上形成保护层，并图案化形成保护层图案；
栅极刻蚀装置，用于以所述保护层图案为掩模，对所述栅极层进行刻蚀形成栅极；
导体化装置，用于以所述保护层图案为掩模，对所述有源层的第一区域进行导体化处理，其中所述第一区域未被所述保护层图案在所述有源层上的投影覆盖；
栅绝缘层刻蚀装置，用于以所述保护层图案为掩膜，对所述栅绝缘层进行刻蚀形成栅绝缘层图案；
保护层去除装置，用于剥离所述保护层图案。
在本申请的阵列基板的制备系统中，所述导体化装置包括准分子激光照射构件。
 有益效果
本申请提供一种阵列基板的制备方法和制备系统，所述制备方法包括：提供基板；在所述基板上依次制备层叠设置的有源层、栅绝缘层、栅极层、保护层，并对所述保护层图案化形成保护层图案；以所述保护层图案为掩模，对所述栅极层进行刻蚀形成栅极；以所述保护层图案为掩模，对所述有源层的第一区域进行导体化处理，所述第一区域为未被所述保护层图案在所述有源层上的投影覆盖的区域；以所述保护层图案为掩膜，对所述栅绝缘层进行刻蚀形成栅绝缘层图案；剥离所述保护层图案。本申请通过保护层图案为掩膜，透过栅绝缘层对有源层进行导体化工艺，使导体化位置更精准，同时用剥离的方式去除保护层图案，不会导致有源层的电阻率上升。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的阵列基板的制备方法流程图；
图2为本申请实施例提供的阵列基板的制备过程中第一阶段的结构示意图；
图3为本申请实施例提供的阵列基板的制备过程中第二阶段的结构示意图；
图4为本申请实施例提供的阵列基板的制备过程中第三阶段的结构示意图；
图5为本申请实施例提供的阵列基板的制备过程中第四阶段的结构示意图；
图6为本申请实施例提供的阵列基板的制备过程中第五阶段的结构示意图；
图7为本申请实施例提供的阵列基板的制备过程中第六阶段的结构示意图；
图8为本申请实施例提供的阵列基板的制备过程中第七阶段的结构示意图；
图9为本申请实施例提供的阵列基板的制备过程中第八阶段的结构示意图；
图10为本申请实施例提供的阵列基板的制备过程中第九阶段的结构示意图；
图11为本申请实施例提供的阵列基板的制备过程中第十阶段的结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
如图1所示，本申请提供的阵列基板的制备方法包括以下步骤：
S1、提供基板；
S2、在基板上依次制备层叠设置的有源层、栅绝缘层、栅极层、保护层，并对保护层图案化形成保护层图案；
S3、以保护层图案为掩模，对栅极层进行刻蚀形成栅极；
S4、以保护层图案为掩模，对有源层的第一区域进行导体化处理，第一区域为未被保护层图案在有源层上的投影覆盖的区域；
S5、以保护层图案为掩膜，对栅绝缘层进行刻蚀形成栅绝缘层图案；
S6、剥离保护层图案。
下面结合图2至图11对该制备方法进行具体说明。
在步骤S1中，如图2所示，先提供基板10，基板10可以是绝缘且透明的玻璃基板或树脂基板，对基板10进行预清洗，然后在基板10上形成遮光层20和缓冲层30。
遮光层20可以是叠层的钼铝钼(Mo/Al/Mo)结构或叠层的钛铝钛(Ti/Al/Ti)结构，也可以是单层的钼结构或者单层的铝结构，通过物理气相沉积法沉积在基板10上，之后再进行黄光及干法刻蚀和剥离工艺，形成遮光层图案。在一种实施例中，遮光层20的膜厚为150纳米。
缓冲层30可以是叠层的SiO x/SiN x结构，也可以是单层的SiN x结构或SiO x结构，通过化学气相沉积法沉积在遮光层20上，在一种实施例中，缓冲层30为叠层的SiO/SiN x结构，SiO的膜层厚度为200纳米，SiN x的膜层厚度也为200纳米。
在步骤S2中，如图3所示，先在缓冲层30上形成有源层40。有源层40可以采用金属氧化物材料如氧化锌ZnO、氧化铟InO，或基于上述两种材料的多元金属氧化物半导体如氧化铟镓锌IGZO、氧化铟锌IZO、氧化锌锡ZTO，氧化铪铟锌HIZO、氧化铟锡ITO等。
有源层40可通过物理气相沉积等方法沉积在缓冲层30上，进行烘烤后进行黄光工艺，通过草酸刻蚀形成有源层图案。在一种实施例中，有源层40的膜层厚度为100纳米。
如图4所示，再在有源层40上形成栅绝缘层50和栅极60。
栅绝缘层50的材料可以为氧化硅，通过化学气相沉积法沉积在有源层40上，在一种实施例中，栅绝缘层50的膜层厚度为140纳米。
栅极层60的材料可以为铜、银等导电金属，通过化学气相沉积法沉积在栅绝缘层50上，在一种实施例中，栅极层60为Cu/Ti叠层结构，铜的膜层厚度为400纳米，钛的膜层厚度为30纳米。
如图5所示，在栅极层60上沉积保护层61，在本实施例中，保护层61的材料为光刻胶。
如图6所示，采用单色调掩膜板（图未示出）对保护层61进行曝光显影，得到保护层图案611。
在步骤S3中，如图7所示，以保护层图案611以掩膜，对栅极层60进行曝光、显影、刻蚀，形成栅极601。
在一种实施例中，采用铜酸溶液湿法刻蚀形成栅极601，由于湿法刻蚀是各向同性的，因此导致栅极601的宽度小于保护层图案611的宽度。
在步骤S4中，如图8所示，以保护层图案611以掩膜，对有源层40的第一区域进行导体化处理，第一区域为未被保护层图案611在有源层40上的投影覆盖的区域，在本实施例中，第一区域包括位于有源层40一端的源极掺杂区411、以及位于有源层40另一端的漏极掺杂区412。 对该区域进行导体化处理可以有多种方法。
在一种实施例中，对第一区域采用准分子激光照射，实现导体化。
准分子激光是一种气体脉冲激光波，方向性极强，被照射区域吸收高能量，通过原子振动产生热量，可以使势垒降低，提高电阻率，穿过栅绝缘层50对有源层40进行轰击后，使有源层40的电阻率发生显著变化，且工艺制程窗口大。
在一种实施例中，准分子激光为氯化氙(XeCl)激光、氟化氩（ArF）激光、氟化氪（KrF）激光或氯化氙（XeF）激光中的一种。
在一种实施例中，对第一区域采用高温烘焙，实现导体化，烘焙的温度为300℃至350℃。
通过对第一区域采用高温烘焙，该区域的能量升高，也可以达到降低势垒，提高有源层40电阻率的作用。
本申请实施例中采用准分子激光照射或高温烘焙的方式进行导体化制程，使有源层40与源漏极接触区域的接触性能更高，接触寄生电阻更小，保证半导体器件开关电压稳定。
在现有技术中，由于导体化制程中采用自对位光罩，导体化区域大小及效果取决于栅极绝缘层，若栅极绝缘层刻蚀均一性出现波动或者干刻横向加大，会使导体化效果变差，影响未被导体化处理的沟道区长度，从而导致TFT阈值电压的特性变差，影响显示装置的产品品质。本申请采用保护层图案611为掩膜，导体化的区域不受栅绝缘层刻蚀效果的影响，使得导体化的位置更加精准。
在步骤S5中，如图9所示，一保护层图案611为掩膜，对栅绝缘层50进行刻蚀，形成栅绝缘层图案501。
栅绝缘层50的刻蚀采用干法刻蚀，包括电感耦合等离子体(Inductively Coupled Plasma，ICP)干法刻蚀、增强电容耦合等离子体(Enhanced Capacitive coupled Plasma，ECCP)干法刻蚀或反应离子刻蚀(Reactive Ion Etching，RIE)干法刻蚀等。
在本实施例中，栅绝缘层50的刻蚀采用增强电容耦合等离子体(ECCP)工艺模式，功率为500-2000W，过刻量为30-80%，工艺气体可采用氟系气体和氧气的混合气体。其中，氟系气体包括六氟化硫SF 6、三氟化氮NF 3、四氟化碳CF 4、以及八氟环丁烷C 4F 8中的一种或多种，相应的，工艺气体也包括多种，例如可以包括六氟化硫SF 6和氧气O 2的混合气体，三氟化氮NF 3和氧气O 2的混合气体，或者四氟化碳CF 4和氧气O 2的混合气体等。
在步骤S6中，如图10所示，剥离保护层图案611。在本实施例中，剥离是指采用剥离液去除保护层图案611，采用的剥离液为丙酮和乙醇的混合物。
在现有技术中，导体化工艺完成后，使用灰化工艺去除保护层，灰化工作中氧气的使用会可能导致有缘层的导体化效果发生变化，影响导体化区域与源漏极的接触电阻，本申请中采用剥离的方法去除保护层图案611，可以避免导体化后进行灰化而导致电阻率上升的问题。
在保护层图案611去除后，如图11所示，先在栅极601表面形成介电层70，介电层70中形成有第一过孔711和第二过孔712。
在栅极601上沉积介电层70，介电层70覆盖有源层40、栅绝缘图案501和栅极601，之后在介电层70上涂覆一层光刻胶，采用单色调掩膜版对光刻胶进行曝光、显影，在对应第一过孔711和第二过孔712的位置分别形成完全曝光区域，无光刻胶，暴露介电层70，在其它位置形成未曝光区域，保留光刻胶；之后，对完全曝光区域的介电层70进行刻蚀并剥离剩余的光刻胶，形成具有第一过孔711和第二过孔712的介电层70的图案。
第一过孔711和第二过孔712分别设置在有源层40两端的导体化区域上，其中，第一过孔711对应于源极掺杂区411，第二过孔712对应于漏极掺杂区412。
介电层70的材料为氧化硅SiO x、氮化硅 SiN x、氮硅化合物中的两种或多种的任意组合所构成的复合层结构，在一种实施例中，介电层70的膜层厚度为100～400纳米。
然后，在介电层70上形成源极81和漏极82。
在介电层70上沉积源极金属薄膜和漏极金属薄膜，并在源极金属薄膜和漏极金属薄膜上涂覆一层光刻胶；采用单色调掩膜版对源极金属薄膜和漏极金属薄膜进行曝光、显影，在对应源极81和漏极82位置分别形成未曝光区域，保留光刻胶，在其它位置形成完全曝光区域，无光刻胶，暴露出源极金属薄膜和漏极金属薄膜；对完全曝光区域的源极金属薄膜和漏极金属薄膜进行刻蚀并剥离剩余的光刻胶，形成源极81和漏极82。
源极81和漏极82分别通过第一过孔711和第二过孔712与导体化区域连接，其中，源极81通过第一过孔711与源极掺杂区411连接，漏极82通过第二过孔712与漏极掺杂区412连接。
源极81和漏极82的材质可以采用铂Pt、铜Cu、银Ag、钼Mo、铬Cr、铝Al、钽Ta、钛Ti、钨W等金属中的一种或多种。
在一种实施例中，源极81和漏极8采用铜/钼结构，其中铜的膜层厚度为650纳米，钼的膜层厚度为20纳米。
最后，在介电层70上沉积形成钝化层90，钝化层90覆盖源极81和漏极82，以保护源极81和漏极82表面不被氧化，形成钝化层90的材料可以为氧化硅等。
本申请还提供一种阵列基板的制备系统，包括：
有源层制备装置，用于在基板上形成有源层；
栅绝缘层制备装置，用于在有源层上形成栅绝缘层；
栅极层制备装置，用于在栅绝缘层上形成栅极层；
保护层图案形成装置，用于在栅极层上形成保护层，并图案化形成保护层图案；
栅极刻蚀装置，用于以保护层图案为掩模，对栅极层进行刻蚀形成栅极；
导体化装置，用于以保护层图案为掩模，对有源层的第一区域进行导体化处理，其中第一区域未被保护层图案在有源层上的投影覆盖；
栅绝缘层刻蚀装置，用于以保护层图案为掩膜，对栅绝缘层进行刻蚀形成栅绝缘层图案；
保护层去除装置，用于剥离保护层图案。
在一种实施例中，导体化装置包括准分子激光照射构件，用于氯化氙(XeCl)激光、氟化氩（ArF）激光、氟化氪（KrF）激光或氯化氙（XeF）激光中的一种。
由于准分子激光是一种气体脉冲激光波，方向性极强，被照射区域吸收高能量，通过原子振动产生热量，可以使势垒降低，提高电阻率，穿过栅绝缘层对有源层进行轰击后，使有源层的电阻率发生显著变化，且工艺制程窗口大。
在一种实施例中，导体化装置包括烘焙构件，用于在300℃至350℃的温度对有源层的第一区域进行烘焙。
通过对第一区域采用高温烘焙，该区域的能量升高，也可以达到降低势垒，提高有源层电阻率的作用。
本申请采用保护层图案为掩膜，导体化的区域不受栅绝缘层刻蚀效果的影响，使得导体化的位置更加精准。同时，用剥离的方式去除保护层图案，不会导致有源层的电阻率上升。
根据上述实施例可知：
本申请提供一种阵列基板的制备方法和制备系统，制备方法包括：提供基板；在基板上依次制备层叠设置的有源层、栅绝缘层、栅极层、保护层，并对保护层图案化形成保护层图案；以保护层图案为掩模，对栅极层进行刻蚀形成栅极；以保护层图案为掩模，对有源层的第一区域进行导体化处理，第一区域为未被保护层图案在有源层上的投影覆盖的区域；以保护层图案为掩膜，对栅绝缘层进行刻蚀形成栅绝缘层图案；剥离保护层图案。本申请通过保护层图案为掩膜，透过栅绝缘层对有源层进行导体化工艺，使导体化位置更精准，同时用剥离的方式去除保护层图案，不会导致有源层的电阻率上升。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种阵列基板的制备方法，其包括：
    提供基板；
    在所述基板上依次制备层叠设置的有源层、栅绝缘层、栅极层、保护层，并对所述保护层图案化形成保护层图案；
    以所述保护层图案为掩模，对所述栅极层进行刻蚀形成栅极；
    以所述保护层图案为掩模，对所述有源层的第一区域进行导体化处理，所述第一区域为未被所述保护层图案在所述有源层上的投影覆盖的区域；
    以所述保护层图案为掩膜，对所述栅绝缘层进行刻蚀形成栅绝缘层图案；
    剥离所述保护层图案。
  2. 如权利要求1所述的阵列基板的制备方法，其中，所述以所述保护层图案为掩模，对所述有源层的第一区域进行导体化处理，所述第一区域为未被所述保护层图案在所述有源层上的投影覆盖的区域的步骤包括：对所述第一区域进行准分子激光照射。
  3. 如权利要求2所述的阵列基板的制备方法，其中，所述对所述第一区域进行准分子激光照射的步骤包括：用氟化氪激光进行照射。
  4. 如权利要求2所述的阵列基板的制备方法，其中，所述对所述第一区域进行准分子激光照射的步骤包括：用氟化氩激光进行照射。
  5. 如权利要求2所述的阵列基板的制备方法，其中，所述对所述第一区域进行准分子激光照射的步骤包括：用氯化氙激光进行照射。
  6. 如权利要求1所述的阵列基板的制备方法，其中，所述以所述保护层图案为掩模，对所述有源层的第一区域进行导体化处理，所述第一区域为未被所述保护层图案在所述有源层上的投影覆盖的区域的步骤包括：对所述第一区域进行烘烤。
  7. 如权利要求6所述的阵列基板的制备方法，其中，所述对所述第一区域进行烘烤的步骤包括：用300℃至350℃温度烘烤。
  8. 如权利要求1所述的阵列基板的制备方法，其中，所述在所述基板上依次制备层叠设置的有源层、栅绝缘层、栅极层、保护层，并对所述保护层图案化形成保护层图案的步骤包括：在所述栅极层上涂布光刻胶，并对光刻胶图案化。
  9. 如权利要求1所述的阵列基板的制备方法，其中，所述以所述保护层图案为掩模，对所述栅极层进行刻蚀形成栅极的步骤包括：对所述栅极层采用湿法刻蚀。
  10. 如权利要求1所述的阵列基板的制备方法，其中，所述以所述保护层图案为掩膜，对所述栅绝缘层进行刻蚀形成栅绝缘层图案的步骤包括：对所述栅绝缘层采用干法刻蚀。
  11. 如权利要求10所述的阵列基板的制备方法，其中，所述对所述栅绝缘层采用干法刻蚀的步骤包括:对所述栅绝缘层采用增强电容耦合等离子体干刻法刻蚀。
  12. 如权利要求11所述的阵列基板的制备方法，其中，所述对所述栅绝缘层采用增强电容耦合等离子体干刻法刻蚀的步骤包括：采用氟系气体和氧气的混合气体进行干法刻蚀。
  13. 如权利要求1所述的阵列基板的制备方法，其中，所述在所述基板上依次制备层叠设置的有源层、栅绝缘层、栅极层、保护层，并对所述保护层图案化形成保护层图案的步骤包括：采用物理气相沉积法沉积有源层。
  14. 如权利要求13所述的阵列基板的制备方法，其中，在所述采用物理气相沉积法沉积有源层的步骤后还包括：对所述有源层进行图案化。
  15. 如权利要求1所述的阵列基板的制备方法，其中，所述在所述基板上依次制备层叠设置的有源层、栅绝缘层、栅极层、保护层，并对所述保护层图案化形成保护层图案的步骤包括：采用化学气相沉积法沉积栅绝缘层。
  16. 如权利要求1所述的阵列基板的制备方法，其中，所述在所述基板上依次制备层叠设置的有源层、栅绝缘层、栅极层、保护层，并对所述保护层图案化形成保护层图案的步骤包括：采用化学气相沉积法沉积栅极层。
  17. 如权利要求1所述的阵列基板的制备方法，其中，所述在所述基板上依次制备层叠设置的有源层、栅绝缘层、栅极层、保护层，并对所述保护层图案化形成保护层图案的步骤前还包括：在所述基板上形成遮光层，在所述遮光层远离所述基板的一侧形成缓冲层。
  18. 如权利要求1所述的阵列基板的制备方法，其中，所述剥离所述保护层图案的步骤后还包括：在所述栅极远离所述栅绝缘层的一侧形成介电层、源极、漏极和钝化层。
  19. 一种阵列基板的制备系统，其包括：
    有源层制备装置，用于在基板上形成有源层；
    栅绝缘层制备装置，用于在所述有源层上形成栅绝缘层；
    栅极层制备装置，用于在所述栅绝缘层上形成栅极层；
    保护层图案形成装置，用于在所述栅极层上形成保护层，并图案化形成保护层图案；
    栅极刻蚀装置，用于以所述保护层图案为掩模，对所述栅极层进行刻蚀形成栅极；
    导体化装置，用于以所述保护层图案为掩模，对所述有源层的第一区域进行导体化处理，其中所述第一区域未被所述保护层图案在所述有源层上的投影覆盖；
    栅绝缘层刻蚀装置，用于以所述保护层图案为掩膜，对所述栅绝缘层进行刻蚀形成栅绝缘层图案；
    保护层去除装置，用于剥离所述保护层图案。
  20. 如权利要求19所述的阵列基板的制备系统，其中，所述导体化装置包括准分子激光照射构件。
PCT/CN2019/106631 2019-06-20 2019-09-19 阵列基板的制备方法和制备系统 Ceased WO2020252955A1 (zh)

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