WO2020248098A1 - 半导体结构和半导体结构的制备方法 - Google Patents

半导体结构和半导体结构的制备方法 Download PDF

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WO2020248098A1
WO2020248098A1 PCT/CN2019/090554 CN2019090554W WO2020248098A1 WO 2020248098 A1 WO2020248098 A1 WO 2020248098A1 CN 2019090554 W CN2019090554 W CN 2019090554W WO 2020248098 A1 WO2020248098 A1 WO 2020248098A1
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barrier layer
diffusion barrier
semiconductor structure
diffusion
layer
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PCT/CN2019/090554
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English (en)
French (fr)
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程凯
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苏州晶湛半导体有限公司
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Priority to PCT/CN2019/090554 priority Critical patent/WO2020248098A1/zh
Priority to CN201980096751.9A priority patent/CN113906574A/zh
Publication of WO2020248098A1 publication Critical patent/WO2020248098A1/zh
Priority to US17/535,934 priority patent/US20220085195A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/207—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds further characterised by the doping material

Definitions

  • This application relates to the field of microelectronics technology, in particular to a semiconductor structure and a manufacturing method of the semiconductor structure.
  • a chemical vapor deposition (CVD) method is often used as an epitaxial method to form an epitaxial layer on a substrate.
  • impurities can be used to dope the epitaxial layer to control the electrical properties of the layer.
  • acceptor dopants in nitride semiconductor layers include Be, Mg, C, Fe, and the like.
  • Mg, Fe, etc. can cause the problem of "memory effect", thereby adversely affecting the performance of semiconductor devices.
  • the present application provides a semiconductor structure and a manufacturing method of the semiconductor structure to avoid the memory effect of diffused elements in the prior art.
  • One aspect of the present application provides a semiconductor structure, including: a buffer layer including a diffusion element; a diffusion barrier layer formed on the buffer layer, the diffusion barrier layer including an adsorbent element; and The channel layer on the diffusion barrier layer.
  • the diffusion element in the buffer layer includes a metal element.
  • the material used for the diffusion barrier layer includes a group III-V compound, and the group III element in the group III-V compound may be the adsorbent element.
  • the III-V group compound includes an In compound.
  • the In compound includes InGaN.
  • the In compound includes AlInGaN, where the Al composition is smaller than the In composition.
  • the composition of the adsorptive element in the diffusion barrier layer decreases.
  • Another aspect of the present application provides a method for preparing a semiconductor structure, including: forming a buffer layer, the buffer layer including a diffusion element; forming a diffusion barrier layer on the buffer layer, the diffusion barrier layer including an adsorbent element; A channel layer is formed on the diffusion barrier layer.
  • the diffusion barrier layer includes a group III-V compound, and the group III element in the group III-V compound is the adsorbent element.
  • the III-V group compound includes an In compound.
  • the In compound includes InGaN.
  • the In compound includes AlInGaN, where the Al composition is smaller than the In composition.
  • the composition of the adsorbent element in the diffusion barrier layer decreases.
  • the diffusion element includes a metal element.
  • the formation temperature of the diffusion barrier layer does not exceed 900°C.
  • the diffusion barrier layer is provided with an adsorbing element that adsorbs the diffusion element, thereby effectively blocking the diffusion of the diffusion element from the buffer layer to the channel layer.
  • a change in the composition of the adsorptive element in the diffusion barrier layer is provided to avoid stress release of the diffusion barrier layer.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present application.
  • 2 to 5 are schematic diagrams of composition changes of adsorbent elements in the diffusion barrier layer according to an embodiment of the present application.
  • FIG. 6 is a schematic flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the present application.
  • FIG. 7 is a HEMT semiconductor device formed by a semiconductor structure.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present application, and the arrow direction in the figure is the epitaxial direction of the semiconductor structure.
  • the semiconductor structure includes a buffer layer 1, a diffusion barrier layer 2 and a channel layer 3.
  • the buffer layer 1 includes a diffusion element; a diffusion barrier layer 2 formed on the buffer layer 1, and the diffusion barrier layer includes an adsorbent element for preventing the diffusion of the diffusion element; formed on the diffusion barrier layer 2
  • the semiconductor structure further includes a substrate 0, and a buffer layer 1 may be formed on the substrate 0.
  • the diffusion elements in the buffer layer 1 may be realized by intentional doping, or may be inevitable in the epitaxial growth environment of the semiconductor structure.
  • the diffusion element may include metal elements, for example, Fe, Mg, and the like. It can be understood that deliberate doping of diffusing elements in the buffer layer 1 can increase the resistivity of the buffer layer 1 and effectively increase the breakdown voltage of the semiconductor structure.
  • diffusion elements generally have memory effect problems, that is, even if the doping of the diffusion elements has been stopped during the growth of the buffer layer 1, the diffusion elements can still diffuse into the channel layer 3, affecting the performance of the entire semiconductor device . Therefore, the arrangement of the diffusion barrier layer 2 can effectively block the diffusion of diffusion elements from the buffer layer 1 to the channel layer 3.
  • the diffusion barrier layer 2 includes adsorptive elements, and the composition of the adsorptive elements in the diffusion barrier layer 2 is variable. Specifically, the direction from the buffer layer 1 to the channel layer 3, that is, the semiconductor epitaxial growth In the direction, the composition of the adsorptive element in the diffusion barrier layer 2 decreases.
  • the diffusion barrier layer 2 may include a III-V group compound, wherein the III group element may be used as an adsorbent element.
  • In the diffusion barrier layer 2 composed of In x Ga y N In in In x Ga y N can be an adsorbent element, and the composition of In in In x Ga y N decreases along the epitaxial growth direction. The range of composition variation is 0 ⁇ x ⁇ 1.
  • the aforementioned In composition gradation can be formed by adjusting the growth temperature or the ratio of the indium source and the gallium source.
  • the growth temperature may not exceed 900°C. Further, it may not exceed 850°C.
  • the buffer layer 1 and the channel layer 3 include a nitride semiconductor layer, for example, a GaN-based material.
  • a GaN-based material is a semiconductor material that includes at least Ga atoms and N atoms, such as GaN, AlGaN, InGaN, AlInGaN etc.
  • the diffusion barrier layer 2 when the buffer layer 1 is GaN and the diffusion barrier layer 2 is InGaN, since the thermal mismatch and lattice mismatch between GaN and InGaN are relatively large, the diffusion barrier layer 2 will experience stress release, resulting in the quality of the semiconductor structure Decrease, by adjusting the In composition of InGaN in the diffusion barrier layer 2, it is equivalent to multiple InGaN diffusion barrier layers 2 with different compositions, which can effectively avoid the stress release of the diffusion barrier layer 2.
  • the diffusion barrier layer 2 is provided with an adsorbing element that adsorbs the diffusion element, so as to effectively block the diffusion of the diffusion element from the buffer layer 1 to the channel layer 3.
  • the stress release of the diffusion barrier layer 2 is avoided by setting the composition change of the adsorptive element in the diffusion barrier layer 2.
  • FIGS. 2 to 5 are schematic diagrams of changes in the composition of adsorbent elements in the diffusion barrier layer 2 according to an embodiment of the present application.
  • the ordinate represents the component content of the adsorptive element in the diffusion barrier layer 2
  • the abscissa represents the epitaxial direction. It can be seen from FIGS. 2 to 5 that the component content of the adsorptive element in the diffusion barrier layer 2 is along the extension The direction is decreasing.
  • the composition of the adsorbent elements in the diffusion barrier layer 2 decreases. Under such changes in adsorbing elements, a relatively flat quantum well structure can be realized.
  • the adsorptive elements may decrease stepwise. Under such changes in adsorbing elements, a multi-channel effect can be obtained, thereby reducing the spatial concentration of the two-dimensional electron gas (2DEG), thereby increasing the mobility of carriers.
  • 2DEG two-dimensional electron gas
  • the epitaxial direction of the diffusion barrier layer 2 may refer to the epitaxial growth direction of the diffusion barrier layer 2 during preparation.
  • the In component may be an adsorbent element.
  • the In composition may decrease or decrease in a stepped manner, that is, the X value may decrease or decrease in a stepped manner.
  • the adsorbent element composition in the diffusion barrier layer 2 decreases with the direction of epitaxial growth, such as the In composition content, so
  • the content of the In component can be reduced linearly, as shown in Figure 2; it can also be reduced non-linearly, as shown in Figure 5.
  • the content of the In component can be reduced in a stepped period, as shown in Figures 3 to 4; it can also be reduced in other non-periodical ways.
  • the manner in which the component of the adsorptive element decreases along with the epitaxial growth direction is not limited, as long as the component of the adsorptive element in the diffusion barrier layer 2 shows a decreasing trend along the epitaxial growth direction.
  • FIG. 6 is a schematic flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the present application.
  • the manufacturing method of the semiconductor structure may include the following steps.
  • the diffusion elements in the buffer layer 1 may be realized by intentional doping, or may be inevitable in the epitaxial growth environment of the semiconductor structure.
  • the diffusion element may include metal elements, for example, Fe, Mg, and the like. It can be understood that deliberate doping of diffusing elements in the buffer layer 1 can increase the resistivity of the buffer layer 1 and effectively increase the breakdown voltage of the semiconductor structure.
  • diffusion elements generally have memory effect problems, that is, even if the doping of the diffusion elements has been stopped during the growth of the buffer layer 1, the diffusion elements can still diffuse into the channel layer 3, affecting the performance of the entire semiconductor device . Therefore, the arrangement of the diffusion barrier layer 2 can effectively block the diffusion of diffusion elements from the buffer layer 1 to the channel layer 3.
  • the diffusion barrier layer 2 includes adsorptive elements, and the composition of the adsorptive elements in the diffusion barrier layer 2 is variable. Specifically, the direction from the buffer layer 1 to the channel layer 3, that is, the semiconductor epitaxial growth In the direction, the composition of the adsorptive element in the diffusion barrier layer 2 decreases.
  • the epitaxial direction of the diffusion barrier layer 2 may refer to the epitaxial growth direction of the diffusion barrier layer 2 during preparation.
  • the In component may be an adsorbent element.
  • the In composition can be reduced or stepped down, that is to say, the X value can be reduced or stepped down, a relatively flat quantum well structure can be achieved, and a multi-channel structure can be obtained. The effect of the channel, thereby reducing the spatial concentration of the two-dimensional electron gas (2DEG), thereby increasing the mobility of carriers.
  • 2DEG two-dimensional electron gas
  • the diffusion barrier layer 2 may include a III-V group compound, wherein the III group element may be used as an adsorbent element.
  • In the diffusion barrier layer made of In x Ga y N configuration 2 In N of In x Ga y can, and In x Ga y N in the In composition is reduced adsorptive element along the direction of epitaxial growth, In The variation range of the composition is 0 ⁇ x ⁇ 1.
  • the aforementioned In composition gradation can be formed by adjusting the growth temperature or the ratio of the indium source and the gallium source.
  • the growth temperature may be limited to not more than 900°C. Further, it may not exceed 850°C.
  • the buffer layer 1 and the channel layer 3 include a nitride semiconductor layer, for example, a GaN-based material.
  • a GaN-based material is a semiconductor material that includes at least Ga atoms and N atoms, such as GaN, AlGaN, InGaN, AlInGaN etc.
  • the thermal mismatch and lattice mismatch between GaN and InGaN are relatively large, resulting in stress release of the diffusion barrier layer 2, resulting in the quality of the semiconductor structure Decrease, by adjusting the In composition of InGaN in the diffusion barrier layer 2, it is equivalent to multiple InGaN diffusion barrier layers 2 with different compositions, which can effectively avoid the stress release of the diffusion barrier layer 2.
  • the diffusion barrier layer 2 is provided with an adsorbing element that adsorbs the diffusion element, so as to effectively block the diffusion of the diffusion element from the buffer layer 1 to the channel layer 3.
  • the stress release of the diffusion barrier layer 2 is avoided by setting the composition change of the adsorptive element in the diffusion barrier layer 2.
  • the semiconductor structure forms a semiconductor device such as a HEMT, as shown in FIG. 7, it includes a substrate 0, a buffer layer 1 formed on the substrate 0, a diffusion barrier layer 2 formed on the buffer layer 1 The channel layer on the diffusion barrier layer 2, the barrier layer 4 formed on the channel layer 3, and the gate 5, source 6, and drain 7 formed on the barrier layer 4.
  • the substrate 0 may include Si, SiC, sapphire, etc.
  • the buffer layer 1 may include metal elements, such as Fe, Mg, etc.
  • the diffusion barrier layer 2 may be InGaN, where In is adsorbed sexual elements are used to block the diffusion of metal elements in the buffer layer 1 to the channel layer 3 and affect device performance
  • the channel layer 3 may be GaN
  • the barrier layer 4 may be AlGaN
  • the channel layer 3 It is only necessary to form a heterojunction with the barrier layer 4, and a quantum well is formed at its interface to confine the carriers in the quantum well to form a two-dimensional electron gas channel.
  • Figures 8-9 are diagrams of the energy band structure of semiconductors corresponding to semiconductor devices.
  • Figure 8 corresponds to the absorption element In composition in the diffusion barrier layer 2 becoming smaller along the direction of the epitaxial layer;
  • Figure 9 corresponds to the diffusion barrier layer 2
  • the composition of the adsorptive element In remains unchanged.
  • the diffusion barrier layer 2 is provided with an adsorbing element that adsorbs the diffusion element, thereby effectively blocking the diffusion of the diffusion element from the buffer layer 1 to the channel layer 3.
  • the stress release of the diffusion barrier layer 2 is avoided by setting the composition change of the adsorptive element in the diffusion barrier layer 2.

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Abstract

本申请的实施例提供了一种半导体结构和半导体结构的制备方法，涉及微电子技术领域。该半导体结构包括缓冲层，所述缓冲层包括扩散元素；形成于所述缓冲层上的扩散阻挡层，所述扩散阻挡层包括吸附性元素；以及形成于所述扩散阻挡层上的沟道层。本实施例中，所述扩散阻挡层设置有吸附扩散元素的吸附性元素，从而有效阻挡扩散元素从缓冲层扩散至沟道层。此外，通过设置扩散阻挡层中吸附性元素的组分变化来避免扩散阻挡层的应力释放。

Description

半导体结构和半导体结构的制备方法 技术领域
本申请涉及微电子技术领域，具体涉及一种半导体结构和半导体结构的制备方法。
发明背景
目前，外延常用于半导体工业上。例如，化学气相沉积(CVD)方法常作为外延方法，以便在基底上形成外延层。在生长过程中，可以采用杂质掺杂外延层，以便控制该层的电性能。例如，氮化物半导体层中常用的受主掺杂剂包括Be、Mg、C、Fe等。但是，在这些元素中，Mg、Fe等的使用会引起“记忆效应”的问题，从而对半导体器件的性能起到反作用。
发明内容
有鉴于此，本申请提供一种半导体结构和半导体结构的制备方法，以避免现有技术中扩散元素的记忆效应。
本申请一方面提供了一种半导体结构，包括：缓冲层，所述缓冲层包括扩散元素；形成于所述缓冲层上的扩散阻挡层，所述扩散阻挡层包括吸附性元素；以及形成于所述扩散阻挡层上的沟道层。
在本申请的一个实施例中，所述缓冲层中的扩散元素包括金属元素。
在本申请的一个实施例中，所述扩散阻挡层采用的材料包括III-V族化合物，所述III-V族化合物中的III族元素可为所述吸附性元素。
在本申请的一个实施例中，所述III-V族化合物包括In的化合物。
在本申请的一个实施例中，所述In的化合物包括InGaN。
在本申请的一个实施例中，所述In的化合物包括AlInGaN，其中Al的组分小于In的组分。
在本申请的一个实施例中，沿所述扩散阻挡层外延的方向，所述扩散阻挡层中吸附性元素的组分减小。
本申请另一方面提供了一种半导体结构的制备方法，包括：形成缓冲层，所述缓冲层包括扩散元素；在所述缓冲层上形成扩散阻挡层，所述扩散阻挡层包括吸附性元素；在所述扩散阻挡层上形成沟道层。
在本申请的一个实施例中，所述扩散阻挡层包括III-V族化合物，所述III-V族化合物中的III族元素为所述吸附性元素。
在本申请的一个实施例中，所述III-V族化合物包括In的化合物。
在本申请的一个实施例中，所述In的化合物包括InGaN。
在本申请的一个实施例中，所述In的化合物包括AlInGaN，其中Al的组分小于In的组分。
在本申请的一个实施例中，沿所述扩散阻挡层外延的方向，所述扩散阻挡层中所述吸附性元素的组分减小。
在本申请的一个实施例中，所述扩散元素包括金属元素。
在本申请的一个实施例中，所述扩散阻挡层的形成温度不超过900℃。
本实施例中，所述扩散阻挡层设置有吸附扩散元素的吸附性元素，从而有效阻挡扩散元素从缓冲层扩散至沟道层。此外，通过设置扩散阻挡层中吸附性元素的组分变化来避免扩散阻挡层的应力释放。
附图简要说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本发明的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1是根据本申请一个实施例的半导体结构的示意性结构图。
图2至图5分别是根据本申请一个实施例的扩散阻挡层中吸附性元素的组分变化示意图。
图6是根据本申请一个实施例的半导体结构的制备方法的示意性流程图。
图7是半导体结构形成的HEMT半导体器件。
图8至图9对应半导体器件的能带结构图。
实施本申请的方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在可能的情况下，附图中相同或相似的部分将采用相同的附图标记。
图1是根据本申请一个实施例的半导体结构的示意性结构图，图中箭头方向为半导体结构的外延方向。
如图1所示，该半导体结构包括缓冲层1、扩散阻挡层2和沟道层3。其中所述缓冲层1包括扩散元素；形成于所述缓冲层1上的扩散阻挡层2，所述扩散阻挡层包括用于阻止扩散元素扩散的吸附性元素；形成于所述扩散阻挡层2上的沟道层3。
本实施例中，所述半导体结构还包括衬底0，可以在所述衬底0上形成缓冲层1。
具体地，所述缓冲层1中扩散元素可以是通过有意掺杂来实现的，也可以是半导体结构外延生长环境中所不可避免的。所述扩散元素可包括金属元素，例如，Fe、Mg等。可以理解的是，在缓冲层1中故意掺杂扩散元素可提高缓冲层1的电阻率，有效提升半导体结构的击穿电压。但是，扩散元素一般都会存在记忆效应问题，也就是说，即便在生长缓冲层1过程中已经停止扩散元素的掺杂，所述扩散元素仍可以向沟道层3扩散，影响整个半导体器件的性能。因此扩散阻挡层2的设置可以有效阻挡扩散元素从缓冲层1扩散至沟道层3。
进一步的，所述扩散阻挡层2包括吸附性元素，所述扩散阻挡层2中的吸附性元素的组分是变化的，具体的，从缓冲层1向沟道层3方向，即半导体外延生长方向，扩散阻挡层2中的吸附性元素的组分减小。
进一步的，所述扩散阻挡层2可包括III-V族化合物，其中III族元素可以作 为吸附性元素。例如，III-V族化合物可以包括In的化合物，且In的化合物可以优选包括In xGa yN，其中x+y＝1。在由In xGa yN构成的扩散阻挡层2中，In xGa yN中的In可以为吸附性元素，且In xGa yN中In的组分沿着外延生长方向减小，In的组分变化范围为0＜x≤1。
具体地，在由In xGa yN构成的扩散阻挡层2的外延生长过程中，可以通过调节生长温度或者调节铟源和镓源的比例来形成上述In组分的渐变。例如，对于调节生长温度的方式来说，生长温度可以不超过900℃。进一步地，可以不超过850℃。
其它实施例中，所述扩散阻挡层2还可以为Al zIn xGa yN，其中x+y+z＝1，并且其中Al的组分小于In的组分，即z＜x，以保证AlInGaN的晶格常数与GaN更好的匹配，使得外延生长质量更好。
进一步的，所述缓冲层1和所述沟道层3包括氮化物半导体层，例如，GaN基材料，所谓GaN基材料为至少包括Ga原子、N原子的半导体材料，如GaN、AlGaN、InGaN、AlInGaN等。
具体的，当缓冲层1为GaN，扩散阻挡层2为InGaN时，由于GaN、InGaN之间的热失配、晶格失配都比较大，扩散阻挡层2会出现应力释放，导致半导体结构质量下降，通过扩散阻挡层2中InGaN的In组分调节，相当于多层不同组分的InGaN扩散阻挡层2，可以有效避免扩散阻挡层2的应力释放。
本实施例中，所述扩散阻挡层2设置有吸附扩散元素的吸附性元素，从而有效阻挡扩散元素从缓冲层1扩散至沟道层3。此外，通过设置扩散阻挡层2中吸附性元素的组分变化来避免扩散阻挡层2的应力释放。
图2至图5分别是根据本申请一个实施例的扩散阻挡层2中吸附性元素的组分变化示意图。所述纵坐标表示扩散阻挡层2中吸附性元素的组分含量，横坐标表示外延方向，从图2至图5中可以看出，扩散阻挡层2中吸附性元素的组分含量沿着外延方向是减少的。
具体的，在本申请的一个实施例中，如图2和图5所示，沿扩散阻挡层2外延的方向，扩散阻挡层2中吸附性元素的组分减小。在这样的吸附性元素变化下，可以实现相对较为平坦的量子阱结构。
或者，如图3和图4所示，沿扩散阻挡层2外延的方向，吸附性元素可以呈阶梯状递减。在这样的吸附性元素变化下，可以得到多沟道的效果，从而降低二维电子气(2DEG)的空间浓度，进而提高载流子的迁移率。
在这里，扩散阻挡层2外延的方向可以是指扩散阻挡层2在制备时的外延生长方向。当扩散阻挡层2为In xGa yN时，In组分可以为吸附性元素。沿扩散阻挡层2外延的方向，In组分可以减小或呈阶梯状递减，也就是说，X值减小或者呈阶梯状递减。
具体地，如图2到图5所示，沿着扩散阻挡层2外延的方向，所述扩散阻挡层2中的吸附性元素组分随着外延生长方向减小，比如In组分含量，所述In组分含量可以线性减少，如图2所示；也可以非线性减少，如图5所示。所述In组分含量可以阶梯性的周期减少，如图3-图4所示；也可以其它非周期性减少。本案对吸附性元素组分随着外延生长方向减小方式不做限定，只要所述扩散阻挡层2中的吸附性元素组分随着外延生长方向呈现减小的趋势即可。
上面描述了根据本申请实施例的半导体结构，下面结合图6描述根据本申请实施例的半导体结构的制备方法。
图6是根据本申请一个实施例的半导体结构的制备方法的示意性流程图。
如图6所示，该半导体结构的制备方法可以包括如下步骤。
510，制备缓冲层1，所述缓冲层1包括扩散元素。
具体地，所述缓冲层1中扩散元素可以是通过有意掺杂来实现的，也可以是半导体结构外延生长环境中所不可避免的。所述扩散元素可包括金属元素，例如，Fe、Mg等。可以理解的是，在缓冲层1中故意掺杂扩散元素可提高缓冲层1的电阻率，有效提升半导体结构的击穿电压。但是，扩散元素一般都存在记忆效应问题，也就是说，即便在生长缓冲层1过程中已经停止扩散元素的掺杂，所述扩散元素仍可以向沟道层3扩散，影响整个半导体器件的性能。因此扩散阻挡层2的设置可以有效阻挡扩散元素从缓冲层1扩散至沟道层3。
520，在缓冲层1上制备扩散阻挡层2，所述扩散阻挡层2包括吸附性元素。
进一步的，所述扩散阻挡层2包括吸附性元素，所述扩散阻挡层2中的吸附 性元素的组分是变化的，具体的，从缓冲层1向沟道层3方向，即半导体外延生长方向，扩散阻挡层2中的吸附性元素的组分减小。
本实施例中，所述扩散阻挡层2外延的方向可以是指扩散阻挡层2在制备时的外延生长方向。当扩散阻挡层2为In xGa yN时，In组分可以为吸附性元素。沿扩散阻挡层2外延的方向，In组分可以减小或呈阶梯状递减，也就是说，X值减小或者呈阶梯状递减，可以实现相对较为平坦的量子阱结构，还可以得到多沟道的效果，从而降低二维电子气(2DEG)的空间浓度，进而提高载流子的迁移率。
进一步的，所述扩散阻挡层2可包括III-V族化合物，其中III族元素可以作为吸附性元素。例如，III-V族化合物可以包括In的化合物，且In的化合物可以优选包括In xGa yN，其中x+y＝1。在由In xGa yN构成的扩散阻挡层2中，In xGa yN中的In可以为吸附性元素，且In xGa yN中In的组分沿着外延生长方向减小的，In的组分变化范围为0＜x≤1。
具体地，在由In xGa yN构成的扩散阻挡层2的外延生长过程中，可以通过调节生长温度或者调节铟源和镓源的比例来形成上述In组分的渐变。例如，对于调节生长温度的方式来说，生长温度可以限定为不超过900℃。进一步地，可以不超过850℃。
530，在扩散阻挡层2上制备沟道层3。
进一步的，所述缓冲层1和所述沟道层3包括氮化物半导体层，例如，GaN基材料，所谓GaN基材料为至少包括Ga原子、N原子的半导体材料，如GaN、AlGaN、InGaN、AlInGaN等。
具体的，当缓冲层1为GaN，扩散阻挡层2为InGaN时，由于GaN、InGaN之间的热失配、晶格失配都比较大，导致扩散阻挡层2会应力释放，导致半导体结构质量下降，通过扩散阻挡层2中InGaN的In组分调节，相当于多层不同组分的InGaN扩散阻挡层2，可以有效避免扩散阻挡层2的应力释放。
本实施例中，所述扩散阻挡层2设置有吸附扩散元素的吸附性元素，从而有效阻挡扩散元素从缓冲层1扩散至沟道层3。此外，通过设置扩散阻挡层2中吸附性元素的组分变化来避免扩散阻挡层2的应力释放。
进一步的，所述半导体结构形成半导体器件如HEMT时，如图7所示，包括衬底0，形成于衬底0上的缓冲层1，形成于缓冲层1上的扩散阻挡层2、形成于扩散阻挡层2上的沟道层，形成于沟道层3上的势垒层4，以及形成于势垒层4上的栅极5、源极6、漏极7。
本实施例中，所述衬底0可包括Si、SiC、蓝宝石等；所述缓冲层1可包括金属元素，例如，Fe、Mg等；所述扩散阻挡层2可为InGaN，其中In为吸附性元素，用来阻挡缓冲层1中的金属元素向沟道层3扩散，影响器件性能；所述沟道层3可为GaN、所述势垒层4可为AlGaN，所述沟道层3与势垒层4可形成异质结即可，在其界面处形成量子阱，将载流子限制在量子阱中，形成二维电子气沟道。
图8-图9是半导体对应半导体器件的能带结构图，图8对应的是扩散阻挡层2中吸附性元素In组分沿着外延层方向变小；图9对应的是扩散阻挡层2中吸附性元素In组分不变。
所述扩散阻挡层2设置有吸附扩散元素的吸附性元素，从而有效阻挡扩散元素从缓冲层1扩散至沟道层3。此外，通过设置扩散阻挡层2中吸附性元素的组分变化来避免扩散阻挡层2的应力释放。
以上仅为本申请的较佳实施例而已，并非用于限定本申请的保护范围。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (15)

  1. 一种半导体结构，包括：
    缓冲层，所述缓冲层包括扩散元素；
    形成于所述缓冲层上的扩散阻挡层，所述扩散阻挡层包括吸附性元素；以及
    形成于所述扩散阻挡层上的沟道层。
  2. 根据权利要求1所述的半导体结构，其中，所述扩散阻挡层包括III-V族化合物，所述III-V族化合物中的III族元素为所述吸附性元素。
  3. 根据权利要求2所述的半导体结构，其中，所述III-V族化合物包括In的化合物。
  4. 根据权利要求3所述的半导体结构，其中，所述In的化合物包括InGaN。
  5. 根据权利要求3所述的半导体结构，其中，所述In的化合物包括AlInGaN，并且Al组分小于In组分。
  6. 根据权利要求1至5中任一项所述的半导体结构，其中，沿所述扩散阻挡层外延的方向，所述扩散阻挡层中所述吸附性元素的组分减小。
  7. 根据权利要求1至6中任一项所述的半导体结构，其中，所述扩散元素包括金属元素。
  8. 一种半导体结构的制备方法，包括：
    形成缓冲层，所述缓冲层包括扩散元素；
    在所述缓冲层上形成扩散阻挡层，所述扩散阻挡层包括吸附性元素；
    在所述扩散阻挡层上形成沟道层。
  9. 根据权利要求8所述的半导体结构的制备方法，其中，所述扩散阻挡层包括III-V族化合物，所述III-V族化合物中的III族元素为所述吸附性元素。
  10. 根据权利要求9所述的半导体结构的制备方法，其中，所述III-V族化合物包括In的化合物。
  11. 根据权利要求10所述的半导体结构的制备方法，其中，所述In的化合物包括InGaN。
  12. 根据权利要求10所述的半导体结构的制备方法，其中，所述In的化合物包括AlInGaN，并且Al组分小于In组分。
  13. 根据权利要求8至12中任一项所述的半导体结构的制备方法，其中，沿所述扩散阻挡层外延的方向，所述扩散阻挡层中所述吸附性元素的组分减小。
  14. 根据权利要求8至13中任一项所述的半导体结构的制备方法，其中，所述扩散元素包括金属元素。
  15. 根据权利要求8至14中任一项所述的半导体结构的制备方法，其中，所述扩散阻挡层的形成温度不超过900℃。
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