WO2020239109A1 - Mipi d-phy发送电路及设备 - Google Patents

Mipi d-phy发送电路及设备 Download PDF

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Publication number
WO2020239109A1
WO2020239109A1 PCT/CN2020/093496 CN2020093496W WO2020239109A1 WO 2020239109 A1 WO2020239109 A1 WO 2020239109A1 CN 2020093496 W CN2020093496 W CN 2020093496W WO 2020239109 A1 WO2020239109 A1 WO 2020239109A1
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circuit
data
mipi
clock
phy
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PCT/CN2020/093496
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English (en)
French (fr)
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刘兴宗
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深圳市紫光同创电子有限公司
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Priority to KR1020207029589A priority Critical patent/KR102427868B1/ko
Publication of WO2020239109A1 publication Critical patent/WO2020239109A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system

Definitions

  • the present invention relates to the technical field of high-speed serial buses, and more specifically, to a MIPI D-PHY transmission circuit and equipment.
  • MIPI (Mobile Industry Processor Interface, mobile industry processor interface) DPHY is a standard universal interface for mobile industry processor interfaces.
  • MIPI D-PHY interface is more and more widely used in the mobile industry, there are higher requirements for the diversity of MIPI D-PHY support modes.
  • the existing MIPI D-PHY circuits are all implemented by ASIC dedicated circuits, and the application modes cannot be flexibly configured.
  • the dedicated MIPI D-PHY circuits cannot meet the needs of different application scenarios; and the general MIPI D-PHY circuits and protocols (CSI- 2/DSI) The circuits are independent. Both the MIPI D-PHY and MIPI protocol layers need to process the circuits. There are problems of duplication of some functions and waste of resources.
  • the technical problem to be solved by the present invention is that the current dedicated MIPI D-PHY circuit cannot meet the requirements of different application scenarios, and the general MIPI D-PHY circuit is independent of the protocol (CSI-2 protocol/DSI protocol) circuit.
  • MIPI D-PHY Both the MIPI protocol layer and the MIPI protocol layer need to perform protocol processing on the circuit, which causes the problems of duplication of some functions and waste of resources MIPI D-PHY.
  • the present invention provides a MIPI D-PHY transmission circuit and device.
  • the MIPI D-PHY transmission circuit includes an FPGA reconfigurable transmission clock circuit, and a circuit connected to the FPGA reconfigurable transmission clock circuit.
  • FPGA can reconfigure the DPHY_IO transmission circuit.
  • the MIPI D-PHY transmission circuit further includes a data packet reassembly circuit, and an FPGA reconfigurable DPHY_IO transmission circuit connected to the data packet reassembly circuit, and the data packet reassembly circuit is used to convert the data to be transmitted according to The protocol is repacked and sent to the FPGA reconfigurable DPHY_IO sending circuit.
  • the MIPI D-PHY transmission circuit performs data transmission based on the CSI-2 protocol or the DSI protocol.
  • the FPGA reconfigurable transmitting clock circuit includes a PLL module
  • the FPGA reconfigurable DPHY_IO transmitting circuit includes a DPHY_IO clock circuit
  • the PLL module includes a clock link clock signal output circuit and a data link clock signal output circuit
  • the DPHY_IO clock circuit includes a clock link clock channel respectively connected to the clock link clock signal output circuit, and a data link clock channel connected to the data link clock signal output circuit.
  • the clock link clock channel includes a first frequency divider circuit CLKDIV, a first parallel-serial conversion module OSERDES, and a first input-output buffer IOB, wherein the first frequency divider circuit CLKDIV is used to receive the first
  • the clock channel data sent by the PLL module is divided into the clock channel data to obtain the first parallel data, and the first parallel data is transmitted in parallel to the first parallel-serial conversion module OSERDES.
  • the parallel-serial conversion module OSERDES is used for converting the first parallel data into first serial data and transmitting to the first input-output buffer 10B.
  • the data link clock channel includes a second frequency divider circuit CLKDIV, a second parallel-serial conversion module OSERDES, and a second input-output buffer IOB, and the second frequency divider circuit CLKDIV receives the signal sent by the PLL module Data channel data, the second parallel data is obtained after frequency division of the number of data channels, and the second parallel data is transmitted in parallel to the second parallel-serial conversion module OSERDES, and the second parallel-serial conversion module OSERDES It is used for converting the second parallel data into second serial data and transmitting it to the second input and output buffer IOB.
  • the second frequency divider circuit CLKDIV receives the signal sent by the PLL module Data channel data
  • the second parallel data is obtained after frequency division of the number of data channels
  • the second parallel data is transmitted in parallel to the second parallel-serial conversion module OSERDES
  • the second parallel-serial conversion module OSERDES It is used for converting the second parallel data into second serial data and transmitting it to the second input and output buffer I
  • the FPGA reconfigurable DPHY_IO sending circuit includes at most four data output channels.
  • the data output channel includes the DPHY_IO sending circuit and an external analog circuit, wherein the DPHY_IO sending circuit is connected to the external analog circuit.
  • the DPHY_IO sending circuit includes an IOL module and a sending circuit connected to the IOL module.
  • the IOL module is used to receive low-speed data or high-speed data; the sending circuit is used to output low-speed data or high-speed data to an external port;
  • the external analog circuit is connected to the external port.
  • the number of the IOL modules is four, and the four IOL modules include two first IOL modules for transmitting low-speed data and two second IOL modules for transmitting high-speed data.
  • the MIPI D-PHY transmission circuit further includes a first resistor, and the first IOL module is connected to the external port through the first resistor, wherein the resistance value of the first resistor is 330 ohms.
  • the MIPI D-PHY transmission circuit further includes a second resistor, and the second IOL module is connected to the external port through the second resistor, wherein the resistance value of the second resistor is 50 ohms.
  • the level standard of the high-speed data is LVDS.
  • the high-speed data is a current of 2 to 4 mA.
  • the level standard of the low-speed data is LVCMOS12.
  • the high-speed data is a current of 2-12 mA.
  • the clock link clock channel is a unidirectional channel
  • the data link clock channel is a unidirectional channel or a bidirectional channel.
  • the MIPI D-PHY transmitting circuit is used to generate a clock of a clock path and a clock of a data path, wherein the clock of the clock path and the clock of the data path are different by a preset phase.
  • the present invention also provides a device, which includes the MIPI D-PHY transmission circuit described above.
  • the device includes a smart phone, a tablet computer, a notebook computer, a palmtop computer, and a vehicle-mounted computer.
  • FIG. 1 is a schematic diagram of the structure of the MIPI D-PHY transmission circuit provided by Embodiment 1 of the present invention
  • FIG. 2 is a schematic diagram of the circuit structure of the logic layer of the clock circuit of the MIPI D-PHY transmission circuit according to the first embodiment of the present invention
  • FIG. 3 is a schematic diagram of the structure of the DPHY_IO transmitting circuit of the MIPI D-PHY transmitting circuit provided by the first embodiment of the present invention
  • FIG. 4 is a schematic diagram of the working flow of the MIPI D-PHY transmission circuit provided by the second embodiment of the present invention.
  • MIPI D-PHY In order to solve that the existing dedicated MIPI D-PHY circuit cannot meet the needs of different application scenarios, and the general MIPI D-PHY circuit and the protocol (CSI-2/DSI) circuit are independent, both MIPI D-PHY and MIPI protocol layers need to Perform protocol processing, which causes some duplication of functions and waste of resources.
  • a MIPI D-PHY transmission circuit is provided.
  • MIPI Field-Programmable Gate Array
  • MIPI D-PHY is a physical layer of MIPI, and its protocol layers include CSI and DSI.
  • CSI is mainly used for image access, such as image sensor sensors.
  • FIG. 1 is a schematic structural diagram of a MIPI D-PHY transmission circuit provided by an embodiment of the present invention.
  • the MIPI D-PHY transmission circuit 100 includes an FPGA reconfigurable transmission clock circuit 110, an FPGA reconfigurable DPHY_IO transmission circuit 120 connected to the FPGA reconfigurable transmission clock circuit 110, a data packet reassembly circuit (prg_tx_hs_pkg) 130, and the data
  • the FPGA reconfigurable DPHY_IO sending circuit 120 connected to the packet recombination circuit 130.
  • the FPGA reconfigurable DPHY_IO sending circuit 120 connected to the FPGA reconfigurable sending clock circuit 110 will be referred to as the DPHY_IO clock circuit 121 for short.
  • the connected FPGA reconfigurable DPHY_IO transmitting circuit 120 is referred to as the DPHY_IO transmitting circuit 122 for short.
  • the FPGA reconfigurable transmitting clock circuit 110 is a PLL module, which can generate the required clock according to user configuration. It should be noted that there are two types of generated clocks, one is the clock of the clock path, and the other One is the clock of the data path. The two clocks maintain a certain phase relationship to meet the setup and hold time required by the digital circuit.
  • the DPHY_IO clock circuit 121 receives the clock of the clock channel and the clock of the data channel respectively transmitted from the PLL module through hs_clk and hs_clk_i, where hs_cl is the drive clock of the clock channel, and hs_clk_i is the drive clock of the data channel, which is output by the clock channel.
  • the data packet reassembly circuit (prg_tx_hs_pkg) 130 is used to reassemble the received user data according to the protocol requirements and send it to the DPHY_IO sending circuit 122 for output by the data channel.
  • the data packet reassembly circuit 130 processes the received user data, converts it into a format that can be received and processed by the DPHY_IO sending circuit 122 according to the protocol requirements, and then reassembles the packet and sends it out.
  • the MIPI D-PHY transmission circuit 100 is integrated with the CSI-2 protocol/DSI protocol, that is, the MIPI D-PHY transmission circuit 100 can perform data transmission based on the CSI-2 protocol or the DSI protocol.
  • the specific selection Which protocol is determined by the user, this method can effectively reduce the circuit area and improve the resource utilization rate of the circuit.
  • the MIPI D-PHY transmission circuit uses a pair of source-synchronized clocks and one to four pairs of differential clock data lines for data transmission. It should be noted that the clock channel is unidirectional and the data channel is unidirectional. Or two-way.
  • the PLL module includes a clock signal input terminal (clk_in) 111, a first clock signal output terminal (clkout0) 112, a second clock signal output terminal (clkout1) 113, a clock link clock signal output circuit 114, and a data link clock signal output circuit 115.
  • the DPHY_IO clock circuit includes a clock link clock channel 1211 connected to the clock link clock signal output circuit 114, and a data link clock channel 1212 connected to the data link clock signal output circuit 115.
  • the clock link clock channel includes Frequency divider circuit (CLKDIV) 1211a, parallel-serial converter module (OSERDES) 1211b, input and output buffer (IOB) 1211c, data link clock channel includes frequency divider circuit (CLKDIV) 1212a, parallel-serial converter module (OSERDES) 1212b, input Output buffer (IOB) 1212c.
  • CLKDIV Frequency divider circuit
  • OSERDES parallel-serial converter module
  • IOB input and output buffer
  • the clock signal input terminal (clk_in) 111 in the PLL module receives the clock signal configured by the user.
  • the clock signal includes the clock signal of the clock path and the clock signal of the data path.
  • the clock signal of the clock path is output by the first clock signal.
  • the terminal (clkout0) 112 enters the clock link clock channel 1211 through the clock link clock signal output circuit 114, and the clock signal of the data path enters the data link through the second clock signal output terminal (clkout1) 113 through the data link clock signal output circuit 115
  • the clock channel 1212; the clock link clock channel 1211 receives the clock channel clock signal and divides it by the frequency divider circuit (CLKDIV) 1211a, outputs two clock channel clock signals, and converts the signal to serial through the parallel-serial conversion module (OSERDES) 1211b
  • the line signal is transmitted to the input and output buffer (IOB) 1211c, and output to the external port 200 through the input and output buffer (IOB) 1211c.
  • the phase of the output clock path clock signal is opposite; the data link clock channel 1212 receives the clock of the data path After the signal is divided by the frequency divider circuit (CLKDIV) 1212a, two data path clock signals are output, and the signal is converted into a serial signal through the parallel-serial conversion module (OSERDES) 1212b and transmitted to the input and output buffer (IOB) 1212c.
  • the input output buffer (IOB) 1212c outputs to the external port 200, and the output data path clock signal phase is opposite.
  • each data path clock signal transmission corresponds to one data channel.
  • each data channel corresponds to a parallel-serial conversion module.
  • OSERDES parallel-serial conversion module
  • IOB input/output buffer
  • each parallel-serial conversion module (OSERDES) 1212b will receive the two data path clock signals outputted by the frequency divider circuit (CLKDIV) 1212a.
  • both the data channel and the clock channel of the MIPI D-PHY transmission circuit can be reconstructed by FPGA, and the phase of the signal of the data channel and the signal of the clock channel can be adjusted.
  • the MIPI D-PHY transmission circuit includes two transmission modes, a low-speed mode (LP, Lower Power) and a high-speed mode (HS, high speed).
  • the two modes work together to realize the transmission of data and commands in the MIPI interface protocol layer.
  • the DPHY_IO sending circuit 122 includes an IOL module 1221 and a sending circuit 1222.
  • the DPHY_IO sending circuit includes four IOL modules 1221, and the four IOL modules 1221 include two first IOL modules 1221a for transmitting low-speed data and two second IOL modules 1221b for transmitting high-speed data.
  • the low-speed data is output from the IOB (I/O buffer, not shown in the figure) of IO0 (terminal p) and IO3 (terminal n) to the external port 200, and the level standard uses LVCMOS12.
  • the TS of the high-speed channel is set to 0, and the high-speed channel is enabled.
  • the high-speed channel TS is set to 1, and the high-speed channel is closed; during the opening of the high-speed channel, the low-speed channel needs Send LP00.
  • LP01 means that the P terminal is 0, the n terminal is 1, and the rest are similar; after receiving high-speed data, the two second IOL modules 1221b cooperate with each other for data processing, and the high-speed signal uses differential level LVDS (Low Voltage Differential Signaling, low-voltage differential signal standards, enter the IOL module to achieve parallel-to-serial conversion (OSERDES), for example, convert 8-bit parallel data into serial data, pass IO1 and IO2 IOB (I/O buffer, not shown in the figure) Out) output to external port 200, IOB (I/O buffer, not shown in the figure) needs to be controlled, TS is 0, turn off tri-state enable, the signal can be output from IOB to external port 200, when TS is 1, , Turn on the three-state enable, and the external port 200 is enabled to high configuration.
  • OSERDES Parallel-to-serial conversion
  • IO0, IO1, IO2, and IO3 are connected to the external analog circuit 300 through the external port 200.
  • the high-speed channels IO1 and IO2 are connected in series with a first resistor 140, where the first resistor can be a 330 ohm resistor, and the low-speed channels IO0 and IO4 are connected in series with a Two resistors 150, where the second resistor may be a 50 ohm resistor to achieve the electrical characteristics required by the MIPI specification.
  • the electrical characteristics include common mode voltage (DC characteristics) and differential swing (AC characteristics).
  • tx_byte_i_clk in FIG. 2 is the byte clock of the clock channel. It is understandable that other related names in FIG. 2 are corresponding byte clocks.
  • the drive capability of the DPHY_IO transmission circuit can be adjusted through IOB.
  • the LVDS level standard is used, and 2mA ⁇ 4mA is optional; in the low-speed mode, the LVCMOS12 level standard is used, and the optional 2 ⁇ 12mA is needed. , Use different drive currents to adapt to different application scenarios.
  • the embodiment of the present invention provides a MIPI D-PHY transmission circuit 100, including an FPGA reconfigurable transmission clock circuit 110, and an FPGA reconfigurable DPHY_IO transmission circuit 120 connected to the FPGA reconfigurable transmission clock circuit 110, and a data packet
  • the recombination circuit 130 and the FPGA reconfigurable DPHY_IO transmission circuit 120 connected to the data packet recombination circuit 130 can effectively reduce the circuit area and improve the circuit resources by integrating the MIPI D-PHY transmission circuit 110 and the MIPI protocol layer.
  • Utilization rate by adjusting the phase of the MIPI D-PHY data channel and the clock channel to improve the transmission performance, the drive capacity of the MIPI D-PHY transmission circuit can be adjusted to improve the adaptability, and the MIPI D-PHY transmission circuit can meet the CSI- 2 Different application scenarios with DSI.
  • this embodiment proposes a MIPI D-PHY transmission circuit 4-channel protocol transmission flowchart.
  • MIPI D-PHY transmission circuit 4-channel protocol transmission flowchart For details, please refer to FIG. 4.
  • ST_LP_STOP is a low-speed idle state.
  • the detection of whether the initialization is completed can be determined according to whether LP11 is sent. If LP11 is sent, the initialization is completed, otherwise, the initialization is continued.
  • the length of time is configured by the user, and the clock period is set by the FPGA reconfigurable sending clock circuit PLL module. After the clock period is set, the user can configure the number of clock periods as needed, so the length of time is It is determined by the number of clock cycles.
  • the valid_hs signal is detected. It is a high-speed data request signal that indicates that high-speed data is about to be sent and enters the ST_HS_RQST state, otherwise it stays and waits.
  • ST_HS_RQST In the ST_HS_RQST state, send LP01, the length of time is configured by the user, and enter the ST_HS_PRPR state when it is completed, otherwise it stays and waits. Among them, ST_HS_RQST is to enter the high-speed request state.
  • ST_HS_PRPR In the ST_HS_PRPR state, send LP00, the length of time is configured by the user, and enter the ST_HS_GO state when it is completed, otherwise it stays and waits. Among them, ST_HS_PRPR is to enter the high-speed preparation state.
  • ST_HS_GO In the ST_HS_GO state, send high speed 0, the time length is configured by the user, and enter the ST_HS_SYNC state when it is completed, otherwise it stays and waits. Among them, ST_HS_GO is to enter the high-speed conversion state.
  • ST_HS_SYNC In the ST_HS_SYNC state, send the MIPI D-PHY synchronization header B8, and automatically jump to the ST_HS_DATA state.
  • ST_HS_SYNC is the high-speed data synchronization state.
  • MIPI D-PHY synchronization header B8 is used to locate and synchronize each data during the data transmission process, that is, after the receiving end receives the aligned data, the data can be transmitted and sent.
  • ST_HS_DATA is the occurrence of high-speed data status.
  • ST_HS_TRAIL In the ST_HS_TRAIL state, send a high-speed tail signal. The length of time is defined by the user. When it is completed, it will jump back to the IDLE state, otherwise it will stay in this state. Among them, ST_HS_TRAIL is the end state of sending high-speed data packets.
  • the length of time in this embodiment can be configured by the user, and the clock cycle is set by the FPGA reconfigurable sending clock circuit PLL module. After the clock cycle is set, the user can configure the number of clock cycles as needed. The length of this time is determined by the number of clock cycles.
  • the length of the high-speed tail signal can be determined by the length of time.
  • the embodiment of the present invention provides a specific implementation process of the MIPI D-PHY transmission circuit.
  • the MIPI D-PHY transmission circuit is integrated and designed with the MIPI protocol layer through the FPGA reconfigurable MIPI D-PHY transmission circuit, which can effectively reduce the circuit Area, improve the resource utilization rate of the circuit.
  • the drive capacity of the MIPI D-PHY transmission circuit can be adjusted to improve adaptability, and the MIPI D-PHY transmission circuit can meet CSI-2 and DSI A variety of different application scenarios requirements.
  • This embodiment provides a device, which may be, but is not limited to, a smart phone, a tablet computer, a notebook computer, a palmtop computer, a personal digital assistant (Personal Digital Assistant, PDA) mobile smart device with a screen projection function.
  • a device may be, but is not limited to, a smart phone, a tablet computer, a notebook computer, a palmtop computer, a personal digital assistant (Personal Digital Assistant, PDA) mobile smart device with a screen projection function.
  • PDA Personal Digital Assistant
  • the device includes the MIPI D-PHY transmission circuit as exemplified in the above-mentioned embodiment to realize the corresponding function, which will not be repeated here.

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Abstract

本发明提供了一种MIPI D-PHY发送电路及设备，MIPI D-PHY发送电路包括FPGA可重构发送时钟电路，以及与该FPGA可重构发送时钟电路连接的FPGA可重构DPHY_IO发送电路，数据包重组电路，以及与该数据包重组电路连接的FPGA可重构DPHY_IO发送电路，通过FPGA可重构MIPI D-PHY发送电路，将MIPI D-PHY发送电路与MIPI协议层进行整合设计，调整MIPID-PHY发送电路的驱动能力，能够有效的减少电路面积，提高电路的资源使用率，提高发送性能，提高适配性，还可以满足CSI-2与DSI多种不同应用场景需求。

Description

MIPI D-PHY发送电路及设备
本申请要求于2019年05月29日提交的申请号为CN201910458822.7的中国申请的优先权，其在此出于所有目的通过引用将其全部内容并入本文。
技术领域
本发明涉及高速串行总线技术领域，更具体地说，涉及一种MIPI D-PHY发送电路及设备。
背景技术
MIPI(Mobile Industry Processor Interface，移动产业处理器接口)DPHY是移动行业处理器接口的标准通用接口。随着MIPI D-PHY接口在移动行业中的应用越来越广泛，对MIPI D-PHY支持模式的多样性有了更高的要求。但是，现有MIPI D-PHY电路都采用ASIC专用电路实现，不能对应用模式进行灵活配置，专用MIPI D-PHY电路不能满足不同应用场景的需求；而且通用MIPI D-PHY电路与协议(CSI-2/DSI)电路分别独立，MIPI D-PHY与MIPI协议层都需要对电路进行协议处理，存在部分功能重复与资源浪费的问题。
发明内容
本发明要解决的技术问题在于目前的专用MIPI D-PHY电路不能满足不同应用场景的需求，且通用MIPI D-PHY电路与协议(CSI-2协议/DSI协议)电路分别独立，MIPI D-PHY与MIPI协议层都需要对电路进行协议处理，造 成部分功能重复与资源浪费的问题MIPI D-PHY。
为解决上述技术问题，本发明提供一种MIPI D-PHY发送电路及设备，所述MIPI D-PHY发送电路包括FPGA可重构发送时钟电路，以及与所述FPGA可重构发送时钟电路连接的FPGA可重构DPHY_IO发送电路。
可选地，所述MIPI D-PHY发送电路还包括数据包重组电路，以及与所述数据包重组电路连接的FPGA可重构DPHY_IO发送电路，所述数据包重组电路用于将待发送数据根据协议进行重新组包后发给所述FPGA可重构DPHY_IO发送电路。
可选地，所述MIPI D-PHY发送电路基于CSI-2协议或者DSI协议进行数据传输。
可选地，所述FPGA可重构发送时钟电路包括PLL模块，FPGA可重构DPHY_IO发送电路包括DPHY_IO时钟电路，所述PLL模块包括时钟链路时钟信号输出电路，数据链路时钟信号输出电路，所述DPHY_IO时钟电路包括分别与所述时钟链路时钟信号输出电路连接的时钟链路时钟通道，以及与所述数据链路时钟信号输出电路连接的数据链路时钟通道。
可选地，所述时钟链路时钟通道包括第一分频电路CLKDIV、第一并串转换模块OSERDES、第一输入输出缓冲器IOB，其中，所述第一分频电路CLKDIV用于接收第一所述PLL模块发送的时钟通道数据，并对所述时钟通道数据进行分频后得到第一并行数据，并将所述第一并行数据并行传输给第一并串转换模块OSERDES，所述第一并串转换模块OSERDES用于将所述第一并行数据转换为第一串行数据传输到所述第一输入输出缓冲器IOB。
可选地，所述数据链路时钟通道包括第二分频电路CLKDIV、第二并串转换模块OSERDES、第二输入输出缓冲器IOB，所述第二分频电路CLKDIV接 收所述PLL模块发送的数据通道数据，并对所述数据通道数分频后得到第二并行数据，并将所述第二并行数据并行传输给所述第二并串转换模块OSERDES，所述第二并串转换模块OSERDES用于将所述第二并行数据转换为第二串行数据传输到所述第二输入输出缓冲器IOB。
可选地，所述FPGA可重构DPHY_IO发送电路包括至多四路数据输出通道。
可选地，所述数据输出通道包括所述DPHY_IO发送电路以及外部模拟电路，其中所述DPHY_IO发送电路与所述外部模拟电路连接。
可选地，所述DPHY_IO发送电路包括IOL模块以及与所述IOL模块连接的发送电路，IOL模块用于接收低速数据或者高速数据；发送电路用于将低速数据或者高速数据输出到外部端口；所述外部模拟电路与所述外部端口连接。
可选地，所述IOL模块的数量为四个，其中，四个IOL模块中包括两个用于传输低速数据的第一IOL模块以及两个用于传输高速数据的第二IOL模块。
可选地，所述MIPI D-PHY发送电路还包括第一电阻，所述第一IOL模块通过所述第一电阻连接所述外部端口，其中第一电阻的电阻值为330欧姆。
可选地，所述MIPI D-PHY发送电路还包括第二电阻，所述第二IOL模块通过所述第二电阻连接所述外部端口，其中第二电阻的电阻值为50欧姆。
可选地，所述高速数据的电平标准为LVDS。
可选地，所述高速数据为2～4mA的电流。
可选地，所述低速数据的电平标准为LVCMOS12。
可选地，所述高速数据为2～12mA的电流。
可选地，所述时钟链路时钟通道为单向通道，所述数据链路时钟通道为单 向通道或双向通道。
可选地，所述MIPI D-PHY发送电路用于产生时钟通路的时钟和数据通路的时钟，其中，所述时钟通路的时钟和所述数据通路的时钟相差预设相位。
进一步地，本发明还提供了一种设备，该设备包括如上所述的MIPI D-PHY发送电路。
可选地，所述设备包括智能手机、平板电脑、笔记本电脑、掌上电脑以及车载电脑。
MIPI D-PHYMIPI D-PHYMIPI D-PHY
附图说明
图1为本发明实施例一提供的MIPI D-PHY发送电路结构示意图；
图2为本发明实施例一提供的MIPI D-PHY发送电路的时钟电路逻辑层电路结构示意图；
图3为本发明实施例一提供的MIPI D-PHY发送电路的DPHY_IO发送电路结构示意图；
图4为本发明实施例二提供的MIPI D-PHY发送电路的工作流程示意图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，下面通过具体实施方式结合附图对本发明实施例作进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
实施例一：
为了解决现有专用MIPI D-PHY电路不能满足不同应用场景的需求，且通用MIPI D-PHY电路与协议(CSI-2/DSI)电路分别独立，MIPI D-PHY与MIPI 协议层都需要对电路进行协议处理，造成部分功能重复与资源浪费的问题，提供了一种MIPI D-PHY发送电路。
应当理解的是，本发明是采用FPGA((Field－Programmable Gate Array，现场可编程门阵列)来实现MIPI D-PHY发送电路的可重构。其中，MIPI为移动产业处理器接口，其全称为Mobile Industry Processor Interface。其中，MIPI D-PHY是MIPI的一种物理层，其协议层有CSI和DSI两种，其中CSI主要用于图像接入，如图像传感器Sensor。
请参见图1，图1为本发明实施例提供的MIPI D-PHY发送电路结构示意图。MIPI D-PHY发送电路100包括FPGA可重构发送时钟电路110、与该FPGA可重构发送时钟电路110连接的FPGA可重构DPHY_IO发送电路120、数据包重组电路(prg_tx_hs_pkg)130以及与该数据包重组电路130连接的FPGA可重构DPHY_IO发送电路120，下文将与FPGA可重构发送时钟电路110连接的FPGA可重构DPHY_IO发送电路120简称为DPHY_IO时钟电路121，将与数据包重组电路130连接的FPGA可重构DPHY_IO发送电路120简称为DPHY_IO发送电路122。
本实施例中，FPGA可重构发送时钟电路110为PLL模块，PLL模块可以根据用户配置产生需要的时钟，需要说明的是，产生的时钟有两种类型，一种是时钟通路的时钟，另一种是数据通路的时钟，两个时钟保持一定的相位关系，以满足数字电路所需要的建立保持时间。DPHY_IO时钟电路121接收PLL模块通过hs_clk和hs_clk_i分别传输过来的时钟通道的时钟和数据通道的时钟，其中，hs_cl为时钟通道的驱动时钟，hs_clk_i为数据通道的驱动时钟，由时钟通道输出。数据包重组电路(prg_tx_hs_pkg)130用来将接收到的用户数据按照协议要求，重新组包送给DPHY_IO发送电路122，由数据通道输出。
需要说明的是，数据包重组电路130将接受到的用户数据进行处理，根据协议要求转换成能被DPHY_IO发送电路122接收处理的格式再重新组包发送出去。
本实施例中，将MIPI D-PHY发送电路100与CSI-2协议/DSI协议进行整合，也就是说，MIPI D-PHY发送电路100可以基于CSI-2协议或者DSI协议进行数据传输，具体选择哪一种协议由用户自己决定，这种方式能有效降低电路面积，提高电路的资源使用率。
本实施例中，MIPI D-PHY发送电路采用的是一对源同步的时钟和一到四对差分时钟数据线来进行数据传输，需要说明的是，时钟通道是单向的，数据通道是单向或者双向的。
本实施例中，时钟信号的传输参见图2。PLL模块包括时钟信号输入端(clk_in)111、第一时钟信号输出端(clkout0)112、第二时钟信号输出端(clkout1)113、时钟链路时钟信号输出电路114以及数据链路时钟信号输出电路115，DPHY_IO时钟电路包括分别与时钟链路时钟信号输出电路114连接的时钟链路时钟通道1211，以及与数据链路时钟信号输出电路115连接的数据链路时钟通道1212，时钟链路时钟通道包括分频电路(CLKDIV)1211a、并串转换模块(OSERDES)1211b、输入输出缓冲器(IOB)1211c，数据链路时钟通道包括分频电路(CLKDIV)1212a、并串转换模块(OSERDES)1212b、输入输出缓冲器(IOB)1212c。
具体的，PLL模块中的时钟信号输入端(clk_in)111接收到用户配置的时钟信号，该时钟信号包括时钟通路的时钟信号和数据通路的时钟信号，时钟通路的时钟信号由第一时钟信号输出端(clkout0)112通过时钟链路时钟信号输出电路114进入时钟链路时钟通道1211，数据通路的时钟信号由第二时钟 信号输出端(clkout1)113通过数据链路时钟信号输出电路115进入数据链路时钟通道1212；时钟链路时钟通道1211接收时钟通路时钟信号由分频电路(CLKDIV)1211a进行分频，输出两条时钟通路时钟信号，经过并串转换模块(OSERDES)1211b将信号转换为串行信号传输给输入输出缓冲器(IOB)1211c，经输入输出缓冲器(IOB)1211c输出到外部端口200，输出的时钟通路时钟信号相位是相反的；数据链路时钟通道1212接收数据通路的时钟信号由分频电路(CLKDIV)1212a进行分频后，输出两条数据通路时钟信号，经过并串转换模块(OSERDES)1212b将信号转换为串行信号传输给输入输出缓冲器(IOB)1212c，经输入输出缓冲器(IOB)1212c输出到外部端口200，输出的数据通路时钟信号相位是相反的。
需要说明的是，上述数据通路时钟信号的传输对应于一条数据通道，MIPI D-PHY发送电路100工作时，最多可以有4个通道同时进行数据传输，每一条数据通道都对应一个并串转换模块(OSERDES)1212b以及输入输出缓冲器(IOB)1212c，每一个并串转换模块(OSERDES)1212b都会接收到分频电路(CLKDIV)1212a分频后输出的两条数据通路时钟信号。
本实施例中，MIPI D-PHY发送电路的数据通道与时钟通道都可以由FPGA实现重构，数据通道的信号与时钟通道的信号可以进行相位调整。
本实施例中，DPHY_IO发送电路具体的工作流程参见图3。
MIPI D-PHY发送电路包含两种传输模式，低速模式(LP，Lower Power)和高速模式(HS，high speed)，两种模式共同工作，实现MIPI接口协议层中的数据和命令的传输。
如图3所示，DPHY_IO发送电路122包括IOL模块1221和发送电路1222。本实施例中，DPHY_IO发送电路包含四个IOL模块1221，四个IOL模块1221 包括两个用来传输低速数据的第一IOL模块1221a以及两个用来传输高速数据的第二IOL模块1221b，当接收到低速数据后，将低速数据从IO0(p端)与IO3(n端)的IOB(I/O缓冲器，图中未示出)输出到外部端口200，电平标准使用LVCMOS12。当发送完LP11->LP01->LP00后，高速通道的TS置0，打开高速通道使能，当再次发送LP11时，高速的通道TS置1，关闭高速通道；打开高速通道期间，低速通道需要发送LP00。需要说明的是，LP01表示P端为0，n端为1，其余类似；当接收到高速数据后，两个第二IOL模块1221b相互配合进行数据处理，高速信号采用差分电平LVDS(Low Voltage Differential Signaling，低压差分信号)标准，进入IOL模块实现并串转换(OSERDES)，例如，将8比特并行数据转化成串行数据，通过IO1与IO2的IOB(I/O缓冲器，图中未示出)输出到外部端口200，IOB(I/O缓冲器，图中未示出)需要受到控制，TS为0，关闭三态使能，信号可从IOB输出到外部端口200，TS为1时，打开三态使能，外部端口200被使能为高组态。IO0、IO1、IO2和IO3通过外部端口200与外部模拟电路300连接，高速通道IO1和IO2串接有第一电阻140，其中第一电阻可以为330欧姆电阻，低速通道IO0和IO4串接有第二电阻150，其中第二电阻可以为50欧姆电阻，以实现MIPI规范要求的电气特性，电气特性包括共模电压(直流特性)和差分摆幅(交流特性)。其中，图2中的tx_byte_i_clk为时钟通道的字节时钟，可以理解的是，图2中其他相关名称为相应的字节时钟。
本实施例中，DPHY_IO发送电路驱动能力可通过IOB进行调整，高速模式下采用LVDS电平标准，可选2mA～4mA；低速模式下采用LVCMOS12电平标准,可选2～12mA，需要说明的是，采用不同的驱动电流，以适应不同的应用场景。
本发明实施例提供了一种MIPI D-PHY发送电路100，包括FPGA可重构发送时钟电路110，以及与该FPGA可重构发送时钟电路110连接的FPGA可重构DPHY_IO发送电路120，数据包重组电路130，以及与数据包重组电路130连接的FPGA可重构DPHY_IO发送电路120，通过将MIPI D-PHY发送电路110与MIPI协议层进行整合设计，能够有效的减少电路面积，提高电路的资源使用率，通过将MIPI D-PHY数据通道与时钟通道进行相位调整，提高发送性能，MIPI D-PHY发送电路的驱动能力可以进行调整，提高适配性，MIPI D-PHY发送电路可以满足CSI-2与DSI多种不同应用场景需求。
实施例二：
在上述实施例的基础上，本实施例提出了一种MIPI D-PHY发送电路4通道协议发送流程图，具体请参见图4。
系统系统初始化时，进入等待IDLE状态；
S401、在IDLE状态，检测初始化是否完成，完成则init_done置高，进入ST_LP_STOP状态，初始化时间长短由用户配置。，其中，ST_LP_STOP为低速空闲状态。
需要说明的是，检测初始化是否完成可以根据是否发送LP11来进行判断，如果发送LP11则说明初始化已完成，否则，继续进行初始化。本实施例中，时间长短是由用户配置的，时钟周期由FPGA可重构发送时钟电路PLL模块进行设置，时钟周期设置好以后，用户可以根据需要配置时钟周期的个数，这样时间的长短则是由时钟周期的个数决定的。
S402、在ST_LP_STOP状态，检测valid_hs信号，为高速数据请求信号表示即将发送高速数据，进入ST_HS_RQST状态，否则停留等待。
S403、在ST_HS_RQST状态，发送LP01，时间长短由用户配置，完成则进入ST_HS_PRPR状态，否则停留等待。其中，ST_HS_RQST为进入高速请求状态。
S404、在ST_HS_PRPR状态，发送LP00，时间长短由用户配置，完成则进入ST_HS_GO状态，否则停留等待。其中，ST_HS_PRPR为进入高速准备状态。
S405、在ST_HS_GO状态，发送高速0，时间长短由用户配置，完成则进入ST_HS_SYNC状态，否则停留等待。其中，ST_HS_GO为进入高速转换状态。
S406、在ST_HS_SYNC状态，发送MIPI D-PHY同步头B8，自动跳到ST_HS_DATA状态。其中，ST_HS_SYNC为高速数据同步状态。
需要说明的是，MIPI D-PHY同步头B8用于在数据传输过程中对每个数据进行定位和同步，也就是说，接收端接收到对齐数据后，便可进行数据的传输发送。
S407、在ST_HS_DATA状态，检测valid_hs是否为高，如果为高，则停留在本状态发送用户的高速数据，如果为低，则进入ST_HS_TRAIL状态。
应当理解的是，发送的高速数据为有效数据。其中，ST_HS_DATA为发生高速数据状态。
S408、在ST_HS_TRAIL状态，发送高速尾巴信号，时间长短由用户自定义，完成则跳回IDLE状态，否则停留在本状态。其中，ST_HS_TRAIL为发送高速数据包尾状态。
需要说明的是，本实施例中的时间长短都可以由用户配置，时钟周期由FPGA可重构发送时钟电路PLL模块进行设置，时钟周期设置好以后，用户可 以根据需要配置时钟周期的个数，这样时间的长短则是由时钟周期的个数决定的。
本实施例中，高速尾巴信号长度可以由时间长短来决定。
本发明实施例提供了一种MIPI D-PHY发送电路的具体实现过程，通过FPGA可重构MIPI D-PHY发送电路将MIPI D-PHY发送电路与MIPI协议层进行整合设计，能够有效的减少电路面积，提高电路的资源使用率。通过将MIPI D-PHY数据通道与时钟通道进行相位调整，提高发送性能，MIPI D-PHY发送电路的驱动能力可以进行调整，提高适配性，MIPI D-PHY发送电路可以满足CSI-2与DSI多种不同应用场景需求。
实施例三：
本实施例提供了一种设备，该设备可以为但不限于智能手机、平板电脑、笔记本电脑、掌上电脑、个人数字助理(Personal Digital Assistant，PDA)具有投屏功能的移动类智能设备。当然，也可为但不限于具有投屏功能的PC、车载电脑固定类智能设备。该设备中包含如上述实施例中所示例的MIPI D-PHY发送电路以实现相应的功能，这里不再赘述。
以上内容是结合具体的实施方式对本发明实施例所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。

Claims (20)

  1. 一种MIPI D-PHY发送电路，其特征在于，包括FPGA可重构发送时钟电路，以及与所述FPGA可重构发送时钟电路连接的FPGA可重构DPHY_IO发送电路。
  2. 如权利要求1所述的MIPI D-PHY发送电路，其特征在于，还包括数据包重组电路，以及与所述数据包重组电路连接的FPGA可重构DPHY_IO发送电路，所述数据包重组电路用于将待发送数据根据协议进行重新组包后发给所述FPGA可重构DPHY_IO发送电路。
  3. 如权利要求1所述的MIPI D-PHY发送电路，其特征在于，所述MIPI D-PHY发送电路基于CSI-2协议或者DSI协议进行数据传输。
  4. 如权利要求1-3任一项所述的MIPI D-PHY发送电路，其特征在于，所述FPGA可重构发送时钟电路包括PLL模块，FPGA可重构DPHY_IO发送电路包括DPHY_IO时钟电路，所述PLL模块包括时钟链路时钟信号输出电路，数据链路时钟信号输出电路，所述DPHY_IO时钟电路包括分别与所述时钟链路时钟信号输出电路连接的时钟链路时钟通道，以及与所述数据链路时钟信号输出电路连接的数据链路时钟通道。
  5. 如权利要求4所述的MIPI D-PHY发送电路，其特征在于，所述时钟链路时钟通道包括第一分频电路CLKDIV、第一并串转换模块OSERDES、第一输入输出缓冲器IOB，其中，所述第一分频电路CLKDIV用于接收第一所述PLL模块发送的时钟通道数据，并对所述时钟通道数据进行分频后得到第一并行数据，并将所述第一并行数据并行传输给第一并串转换模块OSERDES，所述第一并串转换模块OSERDES用于将所述第一并行数据转换为第一串行数据传输到所述第一输入输出缓冲器IOB。
  6. 如权利要求4所述的MIPI D-PHY发送电路，其特征在于，所述数据链路时钟通道包括第二分频电路CLKDIV、第二并串转换模块OSERDES、第二输入输出缓冲器IOB，所述第二分频电路CLKDIV接收所述PLL模块发 送的数据通道数据，并对所述数据通道数分频后得到第二并行数据，并将所述第二并行数据并行传输给所述第二并串转换模块OSERDES，所述第二并串转换模块OSERDES用于将所述第二并行数据转换为第二串行数据传输到所述第二输入输出缓冲器IOB。
  7. 如权利要求1所述的MIPI D-PHY发送电路，其特征在于，所述FPGA可重构DPHY_IO发送电路包括至多四路数据输出通道。
  8. 如权利要求7所述的MIPI D-PHY发送电路，其特征在于，所述数据输出通道包括所述DPHY_IO发送电路以及外部模拟电路，其中所述DPHY_IO发送电路与所述外部模拟电路连接。
  9. 如权利要求8所述的MIPI D-PHY发送电路，其特征在于，所述DPHY_IO发送电路包括IOL模块以及与所述IOL模块连接的发送电路，IOL模块用于接收低速数据或者高速数据；发送电路用于将低速数据或者高速数据输出到外部端口；所述外部模拟电路与所述外部端口连接。
  10. 如权利要求9所述的MIPI D-PHY发送电路，其特征在于，所述IOL模块的数量为四个，其中，四个IOL模块中包括两个用于传输低速数据的第一IOL模块以及两个用于传输高速数据的第二IOL模块。
  11. 如权利要求10所述的MIPI D-PHY发送电路，其特征在于，所述MIPI D-PHY发送电路还包括第一电阻，所述第一IOL模块通过所述第一电阻连接所述外部端口，所述第一电阻的电阻值为330欧姆。
  12. 如权利要求10所述的MIPI D-PHY发送电路，其特征在于，所述MIPI D-PHY发送电路还包括第二电阻，所述第二IOL模块通过所述第二电阻连接所述外部端口，所述第二电阻的电阻值为50欧姆。
  13. 如权利要求9所述的MIPI D-PHY发送电路，其特征在于，所述高速数据的电平标准为LVDS。
  14. 如权利要求13所述的MIPI D-PHY发送电路，其特征在于，所述高速数据为2～4mA的电流。
  15. 如权利要求9所述的MIPI D-PHY发送电路，其特征在于，所述低速数据的电平标准为LVCMOS12。
  16. 如权利要求15所述的MIPI D-PHY发送电路，其特征在于，所述高速数据为2～12mA的电流。
  17. 如权利要求4所述的MIPI D-PHY发送电路，其特征在于，所述时钟链路时钟通道为单向通道，所述数据链路时钟通道为单向通道或双向通道。
  18. 如权利要求1-17任一项所述的MIPI D-PHY发送电路，其特征在于，所述MIPI D-PHY发送电路用于产生时钟通路的时钟和数据通路的时钟，其中，所述时钟通路的时钟和所述数据通路的时钟相差预设相位。
  19. 一种设备，包括权利要求1-18任一项所述的MIPI D-PHY发送电路。
  20. 如权利要求19所述的设备，其特征在于，所述设备包括智能手机、平板电脑、笔记本电脑、掌上电脑以及车载电脑。
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