WO2020238030A1 - 薄膜晶体管基板及其制作方法 - Google Patents

薄膜晶体管基板及其制作方法 Download PDF

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Publication number
WO2020238030A1
WO2020238030A1 PCT/CN2019/116129 CN2019116129W WO2020238030A1 WO 2020238030 A1 WO2020238030 A1 WO 2020238030A1 CN 2019116129 W CN2019116129 W CN 2019116129W WO 2020238030 A1 WO2020238030 A1 WO 2020238030A1
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layer
metal
gate
source
thin film
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PCT/CN2019/116129
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English (en)
French (fr)
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章仟益
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深圳市华星光电半导体显示技术有限公司
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Priority to US16/624,206 priority Critical patent/US11289605B2/en
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Publication of WO2020238030A1 publication Critical patent/WO2020238030A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1303—Apparatus specially adapted to the manufacture of LCDs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present disclosure relates to the field of display panels, in particular to a thin film transistor substrate and a manufacturing method thereof.
  • LCD Liquid Crystal Display
  • the Thin Film Transistor (TFT) substrate is an important part of the liquid crystal display that can achieve the display effect.
  • indium gallium zinc oxide Indium Gallium Zinc Oxide, IGZO
  • IGZO Indium Gallium Zinc Oxide
  • the etching process will damage the indium gallium zinc oxide, cause surface defects of indium gallium zinc oxide, and affect device leakage current, threshold voltage and stability.
  • the source and drain in the thin film transistor substrate when the source and drain adopts a copper (Cu) structure, additional problems such as poor adhesion to the substrate or silicon oxide and silicon nitride and copper diffusion into the channel are required. Add barrier material. On the one hand, the etching cost is increased, and on the other hand, barrier layers such as molybdenum (Mo) will remain, causing short circuit and other risks.
  • Cu copper
  • barrier layers such as molybdenum (Mo) will remain, causing short circuit and other risks.
  • the purpose of the present disclosure is to provide a thin film transistor substrate and a manufacturing method thereof, which can solve the problems in the prior art.
  • the present disclosure provides a thin film transistor substrate including a substrate; a gate layer formed on the substrate; a gate insulating layer formed on the gate layer; and a metal oxide layer , Formed on the gate insulating layer; and a source and drain are respectively formed at both ends of the metal oxide layer, the source and drain respectively have a stacked structure, the stacked structure includes a first metal layer and A second metal layer, and the first metal layer is formed on the second metal layer.
  • the gate layer has a laminated structure, and its material is copper and molybdenum.
  • the gate insulating layer covers the gate layer and the surface of the substrate; and the metal oxide layer is made of indium gallium zinc oxide.
  • the material of the first metal layer is copper; and the material of the second metal layer is indium tin oxide.
  • it further includes: a passivation layer formed on the source and drain electrodes, the passivation layer covering the gate insulating layer, the source and drain electrodes, and the surface of the metal oxide layer .
  • the present disclosure provides a thin film transistor substrate including a substrate; a gate layer formed on the substrate; a gate insulating layer formed on the gate layer, the gate layer It is a laminated structure, the material of which is copper and molybdenum; a metal oxide layer is formed on the gate insulating layer; a source and drain are formed on both ends of the metal oxide layer, and the source and drain are respectively It has a stacked structure, the stacked structure includes a first metal layer and a second metal layer, the first metal layer is formed on the second metal layer; and a passivation layer is formed on the source and drain electrodes Above, the passivation layer covers the surfaces of the gate insulating layer, the source and drain electrodes, and the metal oxide layer.
  • the gate insulating layer covers the gate layer and the surface of the substrate; and the metal oxide layer is made of indium gallium zinc oxide.
  • the material of the first metal layer is copper; and the material of the second metal layer is indium tin oxide.
  • the present disclosure provides a method for manufacturing a thin film transistor substrate, including the following steps:
  • a metal layer is formed on the photoresist layer and the notch.
  • the metal layer adopts a laminated structure.
  • the laminated structure includes a first metal layer and a second metal layer.
  • the first metal layer is formed on the On the second metal layer;
  • the step S2 includes the gate layer is made by sputtering film formation; the gate layer is a laminated structure, and the material is copper and molybdenum; and the gate layer is yellowed Process, followed by wet etching to form a gate pattern.
  • the gate insulating layer is made by chemical vapor deposition, the gate insulating layer covers the gate layer and the surface of the substrate; the metal oxide layer is made by sputtering. ⁇ ; and the metal oxide layer is made of indium gallium zinc oxide.
  • the material of the first metal layer is copper; and the material of the second metal layer is indium tin oxide.
  • the step S8 further includes the following steps: S9, forming a passivation layer on the source and drain; the passivation layer covers the gate insulating layer, the source and drain, and the The surface of the metal oxide layer.
  • the source and drain electrodes are formed by a lift-off process, and no etching process is used to prevent the metal oxide channel from being etched by acid when the source and drain electrodes are etched. Defects, which in turn affect the leakage current and threshold voltage and stability of the device; the source and drain use a layered structure of copper and indium tin oxide. After patterning, the copper is on the surface of the indium tin oxide, which effectively prevents the copper from spreading down to the high temperature and other conditions. In the metal oxide channel; by using a laminated structure of copper and indium tin oxide, there is no need to add additional barrier layer materials, which reduces production costs, and at the same time reduces the risk of short circuits caused by residual barrier layer materials.
  • FIG. 1 shows a schematic diagram of the structure of a thin film transistor substrate according to an embodiment of the present disclosure.
  • FIG. 2 shows a schematic flow chart of a manufacturing method of a thin film transistor substrate according to an embodiment of the present disclosure.
  • Fig. 3 shows a schematic diagram of the structure corresponding to step S1 in Fig. 2.
  • FIG. 4 shows a schematic diagram of the structure corresponding to step S2 in FIG. 2.
  • Fig. 5 shows a schematic diagram of the structure corresponding to step S3 in Fig. 2.
  • FIG. 6 shows a schematic diagram of the structure corresponding to step S4 in FIG. 2.
  • FIG. 7 shows a schematic diagram of the structure corresponding to step S5 in FIG. 2.
  • FIG. 8 shows a schematic diagram of the structure corresponding to step S6 in FIG. 2.
  • FIG. 9 shows a schematic diagram of the structure corresponding to step S7 in FIG. 2.
  • Fig. 10 shows a schematic diagram of the structure corresponding to step S7 in Fig. 2.
  • FIG. 11 shows a schematic diagram of the structure corresponding to step S8 in FIG. 2.
  • FIG. 12 shows a schematic diagram of the structure corresponding to step S9 after step S8 in FIG. 11.
  • FIG. 1 is a schematic structural diagram of the thin film transistor substrate in an embodiment of the present invention.
  • the thin film transistor substrate includes: a substrate 1, a gate layer 2, a gate insulating layer 3, a metal oxide layer 4, a source drain 5 and a passivation layer 6.
  • the substrate 1 serves as the bottom of the thin film transistor substrate.
  • the substrate 1 is a glass substrate, but it is not limited thereto.
  • the gate layer 2 is formed on the substrate 1.
  • the gate layer 2 is formed in the middle of the substrate 1.
  • the gate layer 2 is made by a sputtering film forming process.
  • the film structure of the gate layer 2 is a laminated structure, and its materials are copper and molybdenum.
  • the copper film is located above the molybdenum film.
  • the thickness of the copper film is, for example, but not limited to, 400 nm-820 nm, which can play a very good role as a wire.
  • the thickness of the molybdenum film is, for example, but not limited to, 20 nm-45 nm, which can play a blocking role while improving the adhesion between the substrate 1 and the copper film.
  • the gate insulating layer 3 is formed on the gate layer 2.
  • the gate insulating layer 3 covers the upper surfaces of the substrate 1 and the gate layer 2.
  • the gate insulating layer 3 is made by a chemical vapor deposition process.
  • the metal oxide layer 4 is formed on the gate insulating layer 3.
  • the metal oxide layer 4 is formed in the middle of the gate insulating layer 3.
  • the metal oxide layer 4 is formed by a sputtering film forming process.
  • the metal oxide layer 4 is, for example, but not limited to, indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO).
  • the metal oxide layer 4 serves as a semiconductor layer.
  • the metal oxide layer 4 is patterned so that the metal oxide layer 4 is patterned.
  • the metal oxide layer 4 is thermally baked, and then developed through a yellow halftone mask to obtain a photoresist layer 7 with different steps, so that the photoresist in the contact area between the metal oxide layer 4 and the source and drain 5 Layer 7 is thinner than other areas.
  • the photoresist with different steps is modified and ashed by a dry etching process, so that there is no photoresist in the area where the metal oxide layer 4 is in contact with the source and drain electrodes 5, and the metal oxide layer 4 and The photoresist layer 7 still exists in the area where the source and drain 5 are not in contact.
  • the photoresist layer 7 in the regions where the metal oxide layer 4 is not in contact with the source and drain electrodes 5 are all at a certain angle for better peeling off the photoresist layer 7.
  • the angle is 30-65 degrees.
  • the source and drain electrodes 5 include a source electrode and a drain electrode, which are respectively formed at two ends above the metal oxide layer 4.
  • the source and drain 5 adopt a stacked structure.
  • the stacked structure of the source and drain 5 is a double-layer structure, including a first metal layer 501 and a second metal layer 502.
  • the material of the metal layer 501 is copper
  • the material of the second metal layer 502 is indium tin oxide.
  • the film thickness of the first metal layer 501 is, for example, but not limited to, 400 nm-820 nm, which can play a good role as a wire.
  • the film thickness of the second metal layer 502 is, for example, but not limited to, 20 nm-45 nm, which can serve as a barrier.
  • the first metal layer 501 is above the second metal layer 502.
  • the second metal layer 502 is indium tin oxide, it has the characteristics of normal operation under high temperature conditions. Such a structure can effectively prevent copper Diffusion down to the metal oxide layer 4 below. Similarly, it is not necessary to add an additional barrier layer material to prevent copper from diffusing downward under high temperature conditions, which reduces the production cost and at the same time solves the risk of short circuit caused by residual barrier layer materials such as molybdenum.
  • the source and drain 5 are directly deposited on the metal oxide layer 4, and after the metal film layer of the source and drain 5 is deposited, the original remaining photoresist layer 7 is directly stripped to form the pattern of the channel and the source and drain 8.
  • the source and drain electrodes 5 formed by the lift-off process avoid the problem that the channel of the metal oxide layer 4 is corroded by acid caused by the traditional etching process and increases semiconductor defects.
  • the passivation layer 6 is formed on the source and drain electrodes 8 and simultaneously covers the surfaces of the gate insulating layer 3, the metal oxide layer 4, and the source and drain electrodes 5.
  • the passivation layer 6 is used for isolating water and oxygen and prolonging the working life of the thin film transistor substrate.
  • FIG. 2 shows a schematic flow chart of the method for manufacturing a thin film transistor substrate in an embodiment of the present invention, including the following steps:
  • a substrate 1 is provided.
  • a substrate 1 is provided as the bottom of the thin film transistor substrate.
  • the substrate 1 is, for example, but not limited to, a glass substrate.
  • the gate layer 2 is deposited on the surface of the substrate 1 through a physical vapor deposition (PVD) process.
  • the gate layer 2 is formed in the middle of the substrate 1 and has a trapezoidal shape.
  • the film structure of the gate layer 2 is a laminated structure, and its materials are copper and molybdenum.
  • the copper film is located above the molybdenum film.
  • the thickness of the copper film is, for example, but not limited to, 400 nm-820 nm, which can play a very good role as a wire.
  • the thickness of the molybdenum film is, for example, but not limited to, 20 nm-45 nm, which can play a blocking role while improving the adhesion between the substrate 1 and the copper film.
  • the gate insulating layer 3 is deposited on the surface of the gate layer 2 by a chemical vapor deposition (Chemical Vapor Deposition, CVD) process.
  • CVD Chemical Vapor Deposition
  • the gate insulating layer 3 covers the upper surfaces of the substrate 1 and the gate layer 2.
  • a metal oxide layer 4 is deposited on the surface of the gate insulating layer 3 by a sputtering film forming process.
  • the metal oxide layer 4 is formed in the middle of the gate insulating layer 3. , Is a trapezoid.
  • the metal oxide layer 4 is, for example, but not limited to, Indium Gallium Zinc Oxide (IGZO).
  • IGZO Indium Gallium Zinc Oxide
  • the metal oxide layer 4 serves as a semiconductor layer. Indium gallium zinc oxide can increase the charge and discharge rate of the thin film transistor substrate to the pixel electrode, realize a faster refresh rate, and increase the line scan rate of the pixel. Then, a yellow light process is performed, and after etching is performed, the remaining photoresist layer 7 on the surface is peeled off.
  • the metal oxide layer 4 is thermally baked, and then developed through a yellow halftone mask to obtain photoresist layers 7 with different steps.
  • the photoresist layer 7 is thinner in the metal oxide layer 4 and the region where the source and drain electrodes 8 are expected to be formed than other regions.
  • the photoresist layer 7 with different steps is modified and ashed by a dry etching process, so that the metal oxide layer 4 and the region where the source and drain electrodes 5 are expected to be formed do not have the photoresist layer 7, and the metal The photoresist layer 7 still exists in the region outside the oxide layer 4 and the expected source and drain electrodes 5.
  • the metal oxide layer 4 and the region where the source and drain electrodes 5 are expected to be formed are notched due to the absence of the photoresist layer 7.
  • the metal oxide layer 4 is at a certain angle with the photoresist layer 7 expected to form the regions outside the source and drain electrodes 5, so as to better peel off the photoresist.
  • the angle is 30-65 degrees.
  • a metal layer 5 is formed on the photoresist layer 7 and the notch.
  • the metal layer 5 adopts a laminated structure.
  • the laminated structure includes a first metal layer 501 and a second metal layer 502.
  • the layer 501 is formed on the second metal layer 502.
  • the metal layer 5 is formed on the photoresist layer 7 and the notch, and the metal layer 5 simultaneously covers the photoresist layer 7 and the notch.
  • the metal layer 5 is divided into several segments, correspondingly formed above the photoresist layer 7 and the notch.
  • the laminated structure of the metal layer 5 is a two-layer structure, including a first metal layer 501 and a second metal layer 502.
  • the first metal layer 501 is made of copper
  • the second metal layer 502 is made of indium tin. Oxide.
  • the film thickness of the first metal layer 501 is, for example, but not limited to, 400 nm-820 nm, which can play a good role as a wire.
  • the film thickness of the second metal layer 502 is, for example, but not limited to, 20 nm-45 nm, which can serve as a barrier.
  • the first metal layer 501 is above the second metal layer 502.
  • the second metal layer 502 is indium tin oxide, this structure can effectively prevent copper from diffusing down to the metal oxide layer 4 under high temperature conditions. . Similarly, it is not necessary to add an additional barrier layer material to prevent copper from diffusing downward under high temperature conditions, which reduces the production cost and at the same time solves the risk of short circuit caused by residual barrier layer materials such as molybdenum.
  • the metal layer 5 covering the photoresist layer 7 is peeled off, and the photoresist layer 7 is peeled off, and the remaining metal layer 5 covering the gap is used as the source and drain electrodes 8.
  • a lift-off process is performed.
  • the metal layer 5 covering the photoresist layer 7 is peeled off, and the original remaining photoresist layer 7 is directly peeled off, leaving only the metal layer 5 covering the notch.
  • the remaining metal layer 5 covering the gap forms the source and drain 8 and then forms the channel source and drain pattern.
  • the source and drain electrodes 8 formed by the lift-off process avoid the problem of acid corrosion of the channel of the metal oxide layer 4 caused by the traditional etching process and increase of semiconductor defects.
  • the source and drain electrodes 8 include a source electrode and a drain electrode, which are respectively formed at the corresponding notches, that is, formed on the metal oxide layer 4.
  • the source electrode and the drain electrode of the source and drain electrodes 8 are respectively deposited on the two ends above the metal oxide layer 4. Since the source and drain 8 are the metal layer 5 covering the gap, the structure and properties of the source and drain 8 are the same as the metal layer 5. Since the structure and properties of the metal layer 5 have been described above, it will not be repeated here.
  • step S8 the following steps are further included:
  • the passivation layer 6 is deposited and then annealed.
  • the passivation layer 6 covers the surfaces of the gate insulating layer 3, the metal oxide layer 4, and the source and drain electrodes 5 at the same time.
  • the passivation layer 6 covers the surfaces of the gate insulating layer 3, the metal oxide layer 4, and the source and drain electrodes 8.
  • the passivation layer 6 is used for isolating water and oxygen and prolonging the working life of the thin film transistor substrate.
  • the source and drain electrodes are formed by a stripping process, and no etching process is used to avoid acid corrosion of the metal oxide channel when the source and drain electrodes are etched, thereby increasing semiconductor defects, thereby affecting device leakage current And threshold voltage and stability;
  • the source and drain uses a layered structure of copper and indium tin oxide, and the copper is on the surface of the indium tin oxide after patterning, effectively preventing copper from diffusing down into the metal oxide channel under high temperature and other conditions;
  • the use of a laminated structure of copper and indium tin oxide eliminates the need to add additional barrier materials, which reduces production costs, and at the same time reduces the risk of short circuits caused by residual barrier materials.

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  • Engineering & Computer Science (AREA)
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Abstract

一种薄膜晶体管基板及其制作方法，避免源漏极刻蚀时金属氧化物沟道受到酸腐蚀增加半导体缺陷，有效防止铜在高温等条件向下扩散至金属氧化物沟道内。无需额外添加阻挡层材料，降低了生产成本的同时，减少阻挡层材料残留导致短路等风险。

Description

薄膜晶体管基板及其制作方法 技术领域
本揭示涉及显示面板领域，特别是涉及一种薄膜晶体管基板及其制作方法。
 背景技术
液晶显示器(Liquid Crystal Display，LCD) 是目前市场上应用最为广泛的显示产品，其本身具有高亮度、长寿命、广视角、大尺寸显示等优点，并且液晶显示器相关的生产工艺技术十分成熟，产品良率高，生产成本相对较低，市场接受度高。
薄膜晶体管(Thin Film Transistor，TFT)基板是液晶显示器能够实现显示效果的重要一环。在形成薄膜晶体管基板中的金属氧化物时，氧化铟镓锌（Indium Gallium Zinc Oxide，IGZO）由于其载流子迁移率是非晶硅的20~30倍，可以大大提高薄膜晶体管对像素电极的充放电速率，实现更快的刷新率，大大提高像素的行扫描速率。但目前底栅型氧化铟镓锌在制作过程因选择比等问题，导致刻蚀工艺会对氧化铟镓锌有损伤，造成氧化铟镓锌表面缺陷，影响器件漏电流及阈值电压和稳定性。
另外，在形成薄膜晶体管基板中的源漏极时，当源漏极采用铜(Cu)结构，因其与基板或者氧化硅及氮化硅附着力差，铜扩散至沟道等问题，需要额外添加进行阻挡层材料。一方面增加了刻蚀成本，另一方面会有钼(Mo)等阻挡层残留，造成短路等风险。
因此需要对现有技术中的问题提出解决方法。
 技术问题
本揭示的目的在于提供一种薄膜晶体管基板及其制作方法，其能解决现有技术中的问题。
 技术解决方案
为解决上述问题，本揭示提供的一种薄膜晶体管基板包括一基板；一栅极层，形成于所述基板上；一栅极绝缘层，形成于所述栅极层上；一金属氧化物层，形成于所述栅极绝缘层上；以及一源漏极，分别形成于所述金属氧化物层两端，所述源漏极分別具有层叠结构，所述层叠结构包括一第一金属层及一第二金属层，所述第一金属层形成于所述第二金属层上。
于一实施例中，所述栅极层为层叠结构，其材质为铜和钼。
于一实施例中，所述栅极绝缘层覆盖所述栅极层和所述基板的表面；以及所述金属氧化物层的材质为氧化铟镓锌。
于一实施例中，所述第一金属层的材质为铜；以及所述第二金属层的材质为铟锡氧化物。
于一实施例中，还包括：一钝化层，形成于所述源漏极上，所述钝化层覆盖所述栅极绝缘层、所述源漏极和所述金属氧化物层的表面。
为解决上述问题，本揭示提供的一种薄膜晶体管基板包括一基板；一栅极层，形成于所述基板上；一栅极绝缘层，形成于所述栅极层上，所述栅极层为层叠结构，其材质为铜和钼；一金属氧化物层，形成于所述栅极绝缘层上；一源漏极，分别形成于所述金属氧化物层两端，所述源漏极分別具有层叠结构，所述层叠结构包括一第一金属层及一第二金属层，所述第一金属层形成于所述第二金属层上；以及一钝化层，形成于所述源漏极上，所述钝化层覆盖所述栅极绝缘层、所述源漏极和所述金属氧化物层的表面。
于一实施例中，所述栅极绝缘层覆盖所述栅极层和所述基板的表面；以及所述金属氧化物层的材质为氧化铟镓锌。
于一实施例中，所述第一金属层的材质为铜；以及所述第二金属层的材质为铟锡氧化物。
为解决上述问题，本揭示提供的一种薄膜晶体管基板的制作方法，包括如下步骤：
S1、提供一基板；
S2、形成栅极层于所述基板上；
S3、形成栅极绝缘层于所述栅极层上；
S4、形成金属氧化物层于所述栅极绝缘层上；
S5、形成光阻层于所述金属氧化物层上；
S6、对所述光阻层进行修饰灰化，以使所述金属氧化物层上预计形成源漏极的区域形成缺口；
S7、形成金属层于所述光阻层及所述缺口上，所述金属层采用层叠结构，所述层叠结构包括第一金属层及第二金属层，所述第一金属层形成于所述第二金属层上；
S8、剥离覆盖在所述光阻层上的所述金属层，并剥离所述光阻层，剩余的覆盖在所述缺口上的所述金属层作为所述源漏极。
于一实施例中，所述S2步骤包括所述栅极层通过溅射成膜制成；所述栅极层为层叠结构，其材质为铜和钼；以及对所述栅极层进行黄光工艺，之后通过湿法刻蚀形成栅极图案。
于一实施例中，所述栅极绝缘层通过化学气相沉积制成，所述栅极绝缘层覆盖所述栅极层和所述基板的表面；所述金属氧化物层通过溅射成膜制成；以及所述金属氧化物层的材质为氧化铟镓锌。
于一实施例中，所述第一金属层的材质为铜；以及所述第二金属层的材质为铟锡氧化物。
于一实施例中，所述步骤S8后还包括如下步骤：S9、形成钝化层于所述源漏极上；所述钝化层覆盖所述栅极绝缘层、所述源漏极和所述金属氧化物层的表面。
 有益效果
相较于现有技术，本揭示之薄膜晶体管基板及其制作方法中，通过剥离工艺形成源漏极，不使用刻蚀工艺，避免源漏极刻蚀时金属氧化物沟道受到酸腐蚀增加半导体缺陷，进而影响器件漏电流及阈值电压和稳定性；源漏极使用铜和铟锡氧化物的层叠结构，形成图案后铜在铟锡氧化物表面，有效防止铜在高温等条件向下扩散至金属氧化物沟道内；通过使用铜和铟锡氧化物的层叠结构，无需额外添加阻挡层材料，降低了生产成本，同时减少阻挡层材料残留导致短路等风险。
 附图说明
图1显示根据本揭示一实施例之薄膜晶体管基板的结构示意图。
图2显示根据本揭示一实施例之薄膜晶体管基板的制作方法的流程示意图。
图3显示图2中S1步骤对应的结构示意图。
图4显示图2中S2步骤对应的结构示意图。
图5显示图2中S3步骤对应的结构示意图。
图6显示图2中S4步骤对应的结构示意图。
图7显示图2中S5步骤对应的结构示意图。
图8显示图2中S6步骤对应的结构示意图。
图9显示图2中S7步骤对应的结构示意图。
图10显示图2中S7步骤对应的结构示意图。
图11显示图2中S8步骤对应的结构示意图。
图12显示图11中S8步骤之后的S9步骤对应的结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图式，用以例示本揭示可用以实施的特定实施例。
下面参考图1至图12描述本发明实施例薄膜晶体管基板和薄膜晶体管基板的制作方法。
本发明提供了一种薄膜晶体管基板，图1所示为本发明一实施例中的薄膜晶体管基板的结构示意图。薄膜晶体管基板包括:基板1、栅极层2、栅极绝缘层3、金属氧化物层4、源漏极5和钝化层6。
如图3所示，基板1作为薄膜晶体管基板的底部。本发明实施例中基板1为玻璃基板，但不限于此。
如图4所示，栅极层2形成于基板1上。优选地，在本实施例中，栅极层2形成于基板1的中间。栅极层2通过溅射成膜工艺制成。栅极层2的膜层结构为层叠结构，其材质为铜和钼。优选地，在本实施例中，铜膜位于钼膜的上方。铜膜厚度例如但不限于为400nm-820nm，可以起到很好的导线作用。钼膜厚度例如但不限于为20nm-45nm，可以起到阻挡作用，同时提高基板1与铜膜的黏附力。
如图5所示，栅极绝缘层3形成于栅极层2上。优选地，在本实施例中，栅极绝缘层3覆盖基板1和栅极层2的上表面。栅极绝缘层3通过化学气相沉积工艺制成。
如图6所示，金属氧化物层4形成于栅极绝缘层3上。优选地，在本实施例中，金属氧化物层4形成于栅极绝缘层3的中间。金属氧化物层4通过溅射成膜工艺制成。金属氧化物层4例如但不限于为氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)。金属氧化物层4作为一半导体层。
如图7所示，对金属氧化物层4图案化，使得金属氧化物层4形成图案。之后，对金属氧化物层4进行热烘烤，然后通过黄光半色调掩膜板进行显影，得到不同段差的光阻层7，使得金属氧化物层4与源漏极5接触区域的光阻层7比其他区域更薄。如图8所示，在显影后，通过干刻工艺对不同段差的光阻进行修饰灰化，使得金属氧化物层4与源漏极5接触的区域不存在光阻，金属氧化物层4与源漏极5不接触的区域依然存在光阻层7。金属氧化物层4与源漏极5不接触的区域的光阻层7均处于一定角度，用于更好地剥离光阻层7。优选地，在本实施例中，该角度为30-65度。
如图9所示，源漏极5包括源极和漏极，分别形成于金属氧化物层4上方的两端。
结合参阅图10，源漏极5采用层叠结构，优选地，在本实施例中，源漏极5采用的层叠结构为双层结构，包括第一金属层501及第二金属层502，第一金属层501的材质铜，第二金属层502的材质为铟锡氧化物。优选地，在本实施例中，第一金属层501膜厚例如但不限于为400nm-820nm，可以起到很好的导线作用。第二金属层502膜厚例如但不限于为20nm-45nm，可以起到阻挡作用。第一金属层501在第二金属层502的上方，由于第二金属层502为铟锡氧化物，具有在高温情况下正常工作的特性，这样的结构可以有效地防止铜在高温等情况下向下扩散至下面的金属氧化物层4。同样的，不必额外添加阻挡层材料，以阻挡铜在高温等情况下向下扩散，降低了生产成本的同时，也解决了阻挡层材料如钼等残留引起的短路等风险。
如图11所示，结合参阅图9。源漏极5直接沉积在金属氧化物层4上，并且在源漏极5金属膜层沉积后，直接对原来残留的光阻层7进行剥离，形成沟道和源漏极8的图案。这种通过剥离工艺形成的源漏极5，避免了传统的使用刻蚀工艺而引起的金属氧化物层4沟道受酸腐蚀，增加半导体缺陷的问题。
如图12所示，钝化层6形成于源漏极8上，同时覆盖栅极绝缘层3、金属氧化物层4和源漏极5的表面。钝化层6用于隔绝水氧，延长薄膜晶体管基板的工作寿命。
本发明还提供了一种薄膜晶体管基板的制作方法，图2所示为本发明一实施例中的薄膜晶体管基板的制作方法的流程示意图，包括如下步骤：
S1、提供一基板1。
如图3所示，提供一基板1作为薄膜晶体管基板的底部。基板1例如但不限于为玻璃基板。
S2、形成栅极层2于所述基板1上。
如图4所示，在基板1的表面通过溅射成膜(Physical Vapor Deposition，PVD)工艺沉积栅极层2。优选地，在本实例中，栅极层2形成于基板1的中间，呈梯形。栅极层2的膜层结构为层叠结构，其材质为铜和钼。优选地，在本实施例中，铜膜位于钼膜的上方。铜膜厚度例如但不限于为400nm-820nm，可以起到很好的导线作用。钼膜厚度例如但不限于为20nm-45nm，可以起到阻挡作用，同时提高基板1与铜膜的黏附力。
S3、形成栅极绝缘层3于所述栅极层2上。
如图5所示，在栅极层2的表面通过化学气相沉积(Chemical Vapor Deposition,CVD)工艺沉积栅极绝缘层3。优选地，在本实例中，栅极绝缘层3覆盖基板1和栅极层2的上表面。
S4、形成金属氧化物层4于所述栅极绝缘层3上。
如图6所示，在栅极绝缘层3的表面通过溅射成膜工艺沉积金属氧化物层4，优选地，在本实施例中，金属氧化物层4形成于栅极绝缘层3的中间，呈梯形。金属氧化物层4例如但不限于为氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)。金属氧化物层4作为一半导体层。氧化铟镓锌可以提高薄膜晶体管基板对像素电极的充放电速率，实现更快的刷新率，提高像素的行扫描速率。之后进行黄光工艺，再进行蚀刻后，将表面剩余的光阻层7剥离。
S5、形成光阻层7于所述金属氧化物层4上。
如图7所示，在金属氧化物层4形成图案后，对金属氧化物层4进行热烘烤，然后通过黄光半色调掩膜板进行显影，得到不同段差的光阻层7。光阻层7在金属氧化物层4和预计形成源漏极8的区域比其他区域薄。
S6、对所述光阻层7进行修饰灰化，以使所述金属氧化物层4上预计形成源漏极8的区域形成缺口。
如图8所示，在显影后，通过干刻工艺对不同段差的光阻层7进行修饰灰化，使得金属氧化物层4与预计形成源漏极5的区域不存在光阻层7，金属氧化物层4与预计形成源漏极5之外的区域依然存在光阻层7。金属氧化物层4与预计形成源漏极5的区域由于不存在光阻层7，形成缺口。金属氧化物层4与预计形成源漏极5之外的区域的光阻层7均处于一定角度，用于更好地剥离光阻。优选地，在本实施例中，角度为30-65度。
S7、形成金属层5于所述光阻层7及所述缺口上，所述金属层5采用层叠结构，所述层叠结构包括第一金属层501及第二金属层502，所述第一金属层501形成于所述第二金属层502上。
如图9所示，金属层5形成于光阻层7上及缺口上，金属层5同时覆盖光阻层7以及缺口。优选地，在本实施例中，金属层5分为几段，对应形成于光阻层7及缺口的上方。
如图10所示，金属层5采用的层叠结构为双层结构，包括第一金属层501及第二金属层502，第一金属层501的材质铜，第二金属层502的材质为铟锡氧化物。优选地，在本实施例中，第一金属层501膜厚例如但不限于为400nm-820nm，可以起到很好的导线作用。第二金属层502膜厚例如但不限于为20nm-45nm，可以起到阻挡作用。第一金属层501在第二金属层502的上方，由于第二金属层502为铟锡氧化物，这样的结构可以有效地防止铜在高温等情况下向下扩散至下面的金属氧化物层4。同样的，不必额外添加阻挡层材料，以阻挡铜在高温等情况下向下扩散，降低了生产成本的同时，也解决了阻挡层材料如钼等残留引起的短路等风险。
S8、剥离覆盖在所述光阻层7上的所述金属层5，并剥离所述光阻层7，剩余的覆盖在所述缺口上的所述金属层5作为源漏极8。
如图11所示，在沉积金属层5后，进行剥离工艺。剥离覆盖在光阻层7上的金属层5，并且直接对原来残留的光阻层7进行剥离，只剩余覆盖在缺口上的金属层5。剩余的覆盖在缺口上的金属层5形成源漏极8，之后形成沟道源漏极图案。这种通过剥离工艺形成的源漏极8，避免了传统的使用刻蚀工艺而引起的金属氧化物层4沟道受酸腐蚀、增加半导体缺陷的问题。
源漏极8包括源极和漏极，分别形成于对应缺口处，即形成于金属氧化物层4上方。优选地，在本实施例中，源漏极8的源极和漏极分别沉积于金属氧化物层4上方的两端。由于源漏极8为覆盖在缺口上的金属层5，所以源漏极8的结构和性质与金属层5相同。因上文已对金属层5的结构与性质做出阐述，此处不再赘述。
在本发明另一实施例中，在步骤S8后还包括如下步骤：
S9、形成钝化层6于所述源漏极8上。
如图12所示，沉积钝化层6，之后进行退火。钝化层6同时覆盖栅极绝缘层3、金属氧化物层4和源漏极5的表面。优选地，在本实施例中，钝化层6覆盖栅极绝缘层3、金属氧化物层4和源漏极8的表面。钝化层6用于隔绝水氧，延长薄膜晶体管基板的工作寿命。
本揭示之薄膜晶体管基板及其制作方法中，通过剥离工艺形成源漏极，不使用刻蚀工艺，避免源漏极刻蚀时金属氧化物沟道受到酸腐蚀增加半导体缺陷，进而影响器件漏电流及阈值电压和稳定性；源漏极使用铜和铟锡氧化物的层叠结构，形成图案后铜在铟锡氧化物表面，有效防止铜在高温等条件向下扩散至金属氧化物沟道内；通过使用铜和铟锡氧化物的层叠结构，无需额外添加阻挡层材料，降低了生产成本，同时减少阻挡层材料残留导致短路等风险。
综上所述，虽然本揭示已以优选实施例揭露如上，但上述优选实施例并非用以限制本揭示，本领域的普通技术人员，在不脱离本揭示的精神和范围内，均可作各种更动与润饰，因此本揭示的保护范围以权利要求界定的范围为准。

Claims (13)

  1. 一种薄膜晶体管基板，包括：
    一基板；
    一栅极层，形成于所述基板上；
    一栅极绝缘层，形成于所述栅极层上；
    一金属氧化物层，形成于所述栅极绝缘层上；以及
    一源漏极，分别形成于所述金属氧化物层两端，所述源漏极分別具有层叠结构，所述层叠结构包括一第一金属层及一第二金属层，所述第一金属层形成于所述第二金属层上。
  2. 根据权利要求1所述的薄膜晶体管基板，其中
    所述栅极层为层叠结构，其材质为铜和钼。
  3. 根据权利要求1所述的薄膜晶体管基板，其中
    所述栅极绝缘层覆盖所述栅极层和所述基板的表面；以及
    所述金属氧化物层的材质为氧化铟镓锌。
  4. 根据权利要求1所述的薄膜晶体管基板，其中
    所述第一金属层的材质为铜；以及
    所述第二金属层的材质为铟锡氧化物。
  5. 根据权利要求1所述的薄膜晶体管基板，还包括：
    一钝化层，形成于所述源漏极上，所述钝化层覆盖所述栅极绝缘层、所述源漏极和所述金属氧化物层的表面。
  6. 一种薄膜晶体管基板，包括：
    一基板；
    一栅极层，形成于所述基板上，所述栅极层为层叠结构，其材质为铜和钼；
    一栅极绝缘层，形成于所述栅极层上；
    一金属氧化物层，形成于所述栅极绝缘层上；
    一源漏极，分别形成于所述金属氧化物层两端，所述源漏极分別具有层叠结构，所述层叠结构包括一第一金属层及一第二金属层，所述第一金属层形成于所述第二金属层上；以及
    一钝化层，形成于所述源漏极上，所述钝化层覆盖所述栅极绝缘层、所述源漏极和所述金属氧化物层的表面。
  7. 根据权利要求6所述的薄膜晶体管基板，其中
    所述栅极绝缘层覆盖所述栅极层和所述基板的表面；以及
    所述金属氧化物层的材质为氧化铟镓锌。
  8. 根据权利要求6所述的薄膜晶体管基板，其中
    所述第一金属层的材质为铜；以及
    所述第二金属层的材质为铟锡氧化物。
  9. 一种薄膜晶体管基板的制作方法，包括如下步骤：
    S1、提供一基板；
    S2、形成栅极层于所述基板上；
    S3、形成栅极绝缘层于所述栅极层上；
    S4、形成金属氧化物层于所述栅极绝缘层上；
    S5、形成光阻层于所述金属氧化物层上；
    S6、对所述光阻层进行修饰灰化，以使所述金属氧化物层上预计形成源漏极的区域形成缺口；
    S7、形成金属层于所述光阻层及所述缺口上，所述金属层采用层叠结构，所述层叠结构包括第一金属层及第二金属层，所述第一金属层形成于所述第二金属层上；
    S8、剥离覆盖在所述光阻层上的所述金属层，并剥离所述光阻层，剩余的覆盖在所述缺口上的所述金属层作为所述源漏极。
  10. 根据权利要求9所述的薄膜晶体管基板的制作方法，其中所述S2步骤包括：
    所述栅极层通过溅射成膜制成；
    所述栅极层为层叠结构，其材质为铜和钼；以及
    对所述栅极层进行黄光工艺，之后通过湿法刻蚀形成栅极图案。
  11. 根据权利要求9所述的薄膜晶体管基板的制作方法，其中
    所述栅极绝缘层通过化学气相沉积制成，所述栅极绝缘层覆盖所述栅极层和所述基板的表面；
    所述金属氧化物层通过溅射成膜制成；以及
    所述金属氧化物层的材质为氧化铟镓锌。
  12. 根据权利要求9所述的薄膜晶体管基板的制作方法，其中
    所述第一金属层的材质为铜；以及
    所述第二金属层的材质为铟锡氧化物。
  13. 根据权利要求12所述的薄膜晶体管基板的制作方法，其中所述步骤S8后还包括如下步骤：
    S9、形成钝化层于所述源漏极上；
    所述钝化层覆盖所述栅极绝缘层、所述源漏极和所述金属氧化物层的表面。
PCT/CN2019/116129 2019-05-28 2019-11-07 薄膜晶体管基板及其制作方法 WO2020238030A1 (zh)

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