WO2020228202A1 - 降低功率器件反向恢复电流的栅极驱动电路 - Google Patents

降低功率器件反向恢复电流的栅极驱动电路 Download PDF

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WO2020228202A1
WO2020228202A1 PCT/CN2019/105484 CN2019105484W WO2020228202A1 WO 2020228202 A1 WO2020228202 A1 WO 2020228202A1 CN 2019105484 W CN2019105484 W CN 2019105484W WO 2020228202 A1 WO2020228202 A1 WO 2020228202A1
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voltage
power device
diode
tube
reverse recovery
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PCT/CN2019/105484
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English (en)
French (fr)
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祝靖
杨柏炜
余思远
陆扬扬
孙伟锋
陆生礼
时龙兴
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东南大学
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
    • H03K17/08104—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0081—Power supply means, e.g. to the switch driver

Definitions

  • the invention discloses a gate drive circuit for reducing the reverse recovery current of a power device, relates to a monolithic integrated circuit (Monolithic IC) gate drive technology, and belongs to the technical field of basic electronic circuits.
  • Formula 1 shows that the on-resistance is limited by the breakdown voltage, which is called the "silicon limit", that is, the power device requires high withstand voltage and cannot achieve low on-resistance.
  • the super junction MOS tube meets the high withstand voltage (above 600V) on the same chip area while greatly reducing the on-resistance.
  • the relationship between the on-resistance R on and the breakdown voltage V B of super junction MOS transistors is (see document: Chen Xingbi. Superjunction device power electronics technology[J],Power Electronics,2008,42(12):2-7 .):
  • the parasitic body diode in the super-junction MOS tube plays a role of freewheeling during its operation and protects the super-junction MOS tube from reverse electromotive force breakdown.
  • the reverse recovery current of the parasitic body diode is extremely large.
  • the N-type super junction MOS tube is shown in Figure 2.
  • the PN junction columnar structure in the super junction structure brings two serious consequences to the internal parasitic body diode: First, the PN junction area is much larger than that of the traditional power MOS tube.
  • the LIGBT structure does not have a body diode, so an anti-parallel freewheeling diode is required to provide a freewheeling path. Similarly, the reverse recovery current of the freewheeling diode is also very large.
  • the double-pulse test waveform of the super junction MOS tube is shown in Figure 3.
  • the reverse recovery current spike of the freewheeling diode is very large, causing the body diode to produce large power consumption or even burn out during the reverse recovery process.
  • PN junction diode Compared with the body diode of super junction MOS tube or other power device body diode, PN junction diode has very small reverse recovery current.
  • the reverse recovery current generation process of the PN junction diode is shown in Figure 4.
  • the PN junction diode When the PN junction diode is forward-biased, the multi-child holes in the P+ region flow to the N+ region, and the multi-electrons in the N+ region flow to the P+ region and enter the P+ region.
  • the electrons and the holes entering the N+ region become the minority carriers in this region respectively, that is, the unbalanced minority carriers increase at this time.
  • the phenomenon of the accumulation of unbalanced minority carriers during forward conduction is usually called the charge storage effect.
  • the unbalanced minority carriers will gradually decrease in two ways: First, under the action of the reverse electric field, the electrons in the P+ region are pulled back to the N+ region, and the holes in the N+ region are pulled back to the P+ region to form Reverse recovery current, that is, minority carrier extraction occurs; the second is recombination with majority carriers.
  • the reverse recovery current formed by the minority carrier extraction is very small, so the PN junction diode and the super junction MOS tube body diode In comparison, the reverse recovery current is very small.
  • the freewheeling diode adopts a Schottky structure.
  • the Schottky diode has multiple sons participating in conduction, and there is no minority carrier storage and recombination effect, so there is no minority
  • this technology needs to add an additional layer, the process technology requirements are high, and the cost will increase.
  • the source of the high-side super junction MOS transistor T1 and the high-side floating ground Add a resistor and diode parallel network between the VS terminals.
  • One end of the resistor R1 is connected to the anode of the ordinary diode D1 and the source of the high-side super junction MOS transistor T1.
  • the other end of the resistor R1 is connected to the cathode of the ordinary diode D1.
  • Side suspended ground VS. Connect the gate of the high-side super junction MOS tube directly to the high-side floating ground VS, and add an inductor L1 as an inductive load between the bus voltage V BUS and the high-side floating ground VS.
  • a double pulse waveform is added to the gate of the low-side super junction MOS transistor T2.
  • the low-side super junction MOS transistor T2 is turned off, and the inductor L1 generates freewheeling
  • the current I L and the freewheeling current I L flow to the source of the high-side super junction MOS transistor T1, thereby forming a voltage drop across the resistor R1.
  • This voltage drop is the gate-source voltage Vgs of the high-side super junction MOS transistor T1.
  • the resistance of the resistor R1 is very large.
  • the purpose is to make the voltage drop Vgs across the resistor greater than the turn-on voltage VTH of the high-side super junction MOS transistor T1, so that the channel of the high-side super junction MOS transistor T1 is turned on and the freewheeling current IL flows through
  • the conductive channel of the high-side super junction MOS transistor T1 has almost no freewheeling current on the body diode FWD1, so there is almost no reverse recovery current Irr in the body diode FWD1.
  • the ordinary diode D1 begins to conduct after the low-side super junction MOS transistor T2 is turned on.
  • the equivalent on-resistance of the ordinary diode D1 is very small compared with the large resistance R1, and the large resistance R1 is basically ignored under the condition of parallel connection.
  • the conduction voltage of the diode D1 is reduced, that is, the ordinary diode D1 connected in parallel at both ends of the resistor can eliminate the influence of the large resistor R1 on the voltage of the high-side floating ground VS at this time.
  • This method reduces the problem of excessive body diode reverse recovery current, it brings another serious problem.
  • the excessively high resistance R1 makes the high-side floating ground VS end at the first gate of the low-side super junction MOS transistor T2. When the two pulses fall, a larger overshoot voltage is generated, as shown at time t4 in Figure 5(b). The overshoot voltage will have a greater impact on the performance and reliability of the power device.
  • the purpose of the present invention is to address the shortcomings of the above-mentioned background technology and provide a gate drive circuit that reduces the reverse recovery current of a power device.
  • the freewheeling current flows through the conductive channel of the power device instead of the freewheeling diode of the power device, thus realizing freewheeling.
  • the recovery current generated by the diode is extremely small, which solves the technical problem that the drive circuit that reduces the reverse recovery current of the body diode through the resistor-diode parallel structure generates an overshoot voltage at the gate of the low-voltage side super junction MOS transistor due to excessive resistance.
  • High-voltage LDMOS tube its drain and the drain of the power device are connected to the bus voltage, and its gate and the gate of the power device are connected to the output of the drive circuit.
  • the first diode has its anode connected to the source of the high-voltage LDMOS tube, and its cathode is grounded together with the source of the power device,
  • the switch tube connected in series with the source of the high-voltage LDMOS tube has its current input terminal and the source of the power device grounded together, and its current output terminal is connected to the source of the high-voltage LDMOS tube.
  • the voltage detection circuit whose input terminal is connected to the current output terminal of the switch tube, outputs a detection value after detecting the conduction voltage drop of the switch tube,
  • one input terminal is connected to the input signal after the analog-to-digital processing of the previous stage circuit, and the other input terminal is connected to the output terminal of the voltage detection circuit, and,
  • the driving circuit has its input terminal connected to the output terminal of the OR gate, and outputs a driving signal that the power device and the high-voltage LDMOS tube are both turned on when the switch tube is turned on.
  • the switch tube connected in series with the source of the high-voltage LDMOS tube is a second diode connected in anti-parallel to the two poles of the first diode.
  • the switch tube connected in series with the source of the high-voltage LDMOS tube is a low-voltage MOS tube with a body diode in anti-parallel connection.
  • the gate of the low-voltage MOS tube and the power device The gates of the low-voltage MOS transistors are connected to the output terminal of the driving circuit, the drain of the low-voltage MOS transistor is connected to the source of the high-voltage LDMOS transistor, and the source of the low-voltage MOS transistor and the source of the power device are jointly grounded.
  • the gate drive circuit that reduces the reverse recovery current of the power device is used to drive the high-voltage side power device
  • the source of the power device, the cathode of the first diode, and the current input end of the switch tube are connected to the high-voltage side suspension. Ground.
  • the gate drive circuit that reduces the reverse recovery current of the power device when used to drive the low-side power device, the source of the power device, the cathode of the first diode, and the current input end of the switch tube are commonly connected to the input signal Ground.
  • the voltage detection circuit includes: a reference circuit, a first resistor, a second resistor, and a voltage comparator.
  • One end of the second resistor is connected to the current output terminal of the switch tube ,
  • the other end of the second resistor and one end of the first resistor are both connected to the non-inverting end of the voltage comparator, the other end of the first resistor is connected to a reference voltage output by the reference circuit, and the reverse end of the voltage comparator is connected to the output of the reference circuit
  • the voltage comparator outputs the detected value after detecting the conduction voltage drop of the switch tube.
  • the two reference voltages output by the reference circuit satisfy:
  • V 1 and V 2 are the reference voltages output to the reverse and non-inverting terminals of the voltage comparator
  • V d is the node potential of the cathode when the diode is turned on
  • V d -0.7V
  • R 1 and R 2 are respectively Is the resistance of the first resistor and the second resistor.
  • the two reference voltages generated by the reference circuit in the voltage detection circuit are 3.8V and 5V, respectively.
  • the resistance values of the first resistor and the second resistor satisfy: This constraint.
  • the resistance of the resistor R2 is twice that of the resistor R1.
  • Figure 1 is a structural diagram of a monolithic integrated circuit with an internal integrated power device.
  • Figure 2 is a structural diagram of an N-type super junction MOS tube.
  • Figure 3 is a waveform diagram of the double pulse test of a super junction MOS tube.
  • Figure 4 is a diagram showing the process of generating reverse recovery current for a PN junction diode.
  • Fig. 5(a) is a schematic diagram of a circuit for reducing the reverse recovery current of a super junction MOS tube in the prior art.
  • Figure 5(b) is a waveform diagram of the large overshoot voltage generated at the VS terminal of the high-side floating ground in Figure 5(a).
  • Fig. 6 is a structural block diagram of a circuit for reducing reverse recovery current of a power device proposed by the present invention.
  • Fig. 7 is an embodiment of a circuit for reducing reverse recovery current of a power device proposed by the present invention.
  • FIG. 8 is another embodiment of the circuit for reducing the reverse recovery current of the power device proposed by the present invention.
  • FIG. 9 is a comparison diagram of operating waveforms between the circuit shown in FIG. 8 and the conventional circuit in FIG. 1.
  • the circuit for reducing the reverse recovery current of the power device proposed by the present invention is shown in Figure 6.
  • the previous stage circuit, the first power stage circuit, the OR gate, and the high-side drive circuit form a high-side channel.
  • the front-stage circuit, the second power-stage circuit, the OR gate, and the low-side drive circuit form a low-side channel.
  • the structure and working principle of the first and second power stage circuits are exactly the same, so only the working principle and characteristics of the first power stage circuit are analyzed.
  • the first power stage circuit outputs a high level, and is processed by the OR gate together with the output signal of the previous stage circuit.
  • the OR gate is output to the high-side drive circuit, and the output signal of the high-side drive circuit turns on the first In the conductive channel of the power device M1, the freewheeling current flows through the conductive channel instead of the freewheeling diode at this time.
  • the freewheeling diode generates a very low reverse recovery current, which reduces the reverse recovery current of the power device.
  • Specific embodiment 1 The purpose of reducing the reverse recovery current of the power device is achieved by a high-voltage LDMOS tube connected to the high-voltage side power device with a common drain and common gate and an ordinary diode connected in reverse series with the high-voltage LDMOS tube.
  • the first power stage circuit of the high-side channel is shown in Figure 7, including: high-voltage LDMOS tube M3, diode D1, diode D2 and voltage detection circuit, the drain of the high-voltage LDMOS tube M3 is connected to the bus voltage V BUS , and the gate of the high-voltage LDMOS tube M3 Connect to the output HO of the high-side drive circuit, the anode of diode D2 is connected to the high-side floating ground VS, the cathode of diode D2 and the source of the high-voltage LDMOS tube M3 are connected to the input terminal IN of the voltage detection circuit, and the second power device M2 is turned off After that, the freewheeling current generated by the inductive load flows through the diode D2, the diode D2 is turned on, and the voltage detection circuit detects the conduction voltage drop of the diode D2 and then outputs a high level signal OUT to the input terminal IN2 of the OR gate, a high level signal OUT and the signal output from the
  • the diode D2 changes from the on state to the off state. At this time, the reverse recovery current generated by the ordinary diode D2 is very small compared with the power device, that is, the purpose of reducing the reverse recovery current of the power device is achieved. .
  • the voltage detection circuit in the high-side channel is shown in Figure 7, including: a reference circuit, resistor R1, resistor R2, and a voltage comparator.
  • a reference voltage generated by the reference circuit is connected to the inverting terminal of the voltage comparator.
  • the other reference voltage is connected to one end of resistor R1.
  • the other end of resistor R1 and one end of resistor R2 are connected to the positive phase end of the voltage comparator.
  • the other end of resistor R2 serves as the input terminal IN of the voltage detection circuit and the cathode of diode D2.
  • the output terminal of the voltage comparator is used as the output terminal of the voltage detection circuit, and the output OUT of the voltage detection circuit is connected to the input terminal IN2 of the subsequent logic OR gate.
  • the second power stage circuit of the low-side channel is shown in Figure 7, including: high-voltage LDMOS tube M4, diode D5, diode D6 and voltage detection circuit, the drain of the high-voltage LDMOS tube M4 is connected to the high-side floating ground VS, and the gate of the high-voltage LDMOS tube M4 The pole is connected to the output LO of the low-side drive circuit, the anode of the diode D6 is grounded, and the cathode of the diode D6 and the source of the high-voltage LDMOS tube M4 are connected to the input terminal IN of the voltage detection circuit.
  • the inductive load flows through the diode D6, the diode D6 is turned on, and the voltage detection circuit detects the voltage drop of the diode D6 and then outputs a high-level signal OUT to the OR gate input terminal IN4.
  • the high-level signal and the previous circuit output to The signal at the input terminal IN3 of the OR gate is logically OR processed to obtain the OR operation result that makes the output LO of the low-side drive circuit high, then the channel of the second power device M2 and the LDMOS tube M4 are turned on, and the freewheeling current flows from the conductive channel There is almost no freewheeling current flowing through the body diode of the high-voltage LDMOS tube M4 and the second power device M2, so the reverse recovery current generated by the body diode is very small.
  • the diode D6 is The on state changes to the off state. At this time, the reverse recovery current generated by the ordinary diode D6 is very small compared with the power device, that is, the purpose of reducing the reverse recovery current of the power device is achieved.
  • the voltage detection circuit in the low-side channel is shown in Figure 7, including: a reference circuit, resistor R3, resistor R4, and a voltage comparator.
  • a reference voltage generated by the reference circuit is connected to the inverting terminal of the voltage comparator.
  • Another reference voltage is connected to one end of the resistor R3, the other end of the resistor R3 and one end of the resistor R4 are connected to the positive phase end of the voltage comparator, and the other end of the resistor R4 is used as the input terminal IN of the voltage detection circuit and the cathode of the diode D6
  • the output terminal of the voltage comparator is used as the output terminal of the voltage detection circuit, and the output OUT of the voltage detection circuit is connected to the input terminal IN4 of the subsequent logic OR gate logic.
  • the function of the diode D1 is to provide a conductive path for the voltage detection circuit when the high-voltage LDMOS tube M3 and the diode D2 are turned off at the same time; in the second power stage circuit, the function of the diode D4 is to connect the high-voltage LDMOS tube M4 and When diode D6 is turned off at the same time, it provides a conductive path for the voltage detection circuit.
  • the two reference voltages generated by the reference circuit in the voltage detection circuit meet:
  • the two reference voltages generated by the reference circuit in the voltage detection circuit are 3.8V and 5V respectively, the resistance of the resistor R2 is twice that of the resistor R1, and the resistance of the resistor R4 is twice that of the resistor R3.
  • the freewheeling current generated in the load inductance first flows through the diode D2, and the diode D2 is turned on.
  • the cathode of the diode D2 the potential of the node Vd, is the potential of the high-side floating ground VS minus 0.7V , That is, the potential of node Vd is -0.7V, and the negative voltage of node Vd -0.7V cannot be directly connected to the positive phase terminal of the voltage comparator.
  • the negative voltage is raised to the input range of the voltage comparator by the divided voltage of R1 and R2 Inside, the resistance of resistor R2 is twice that of resistor R1.
  • the reference circuit provides two reference voltages of 5V and 3.8V.
  • the non-inverting terminal voltage V+ of the comparator can be calculated by the following resistor divider formula:
  • the voltage of the node V- is 3.8V, that is, the reference voltage of 3.8V is connected to the inverting terminal of the voltage comparator.
  • the latter-stage voltage comparator detects the conduction voltage of the diode D2, it outputs a high-level signal to one end of the OR gate and inputs IN2.
  • the high-level signal IN2 and the previous-stage signal IN1 are used as the two inputs of the OR gate, and the OR gate output signal makes The output HO of the high-side drive circuit is high, so that the channels of the first power device M1 and the high-voltage LDMOS tube M3 are turned on, the freewheeling current flows through the conductive channel, and the freewheeling current hardly passes through the body diode D3 and the first The freewheeling diode of a power device, at this time, there is almost no reverse recovery current in the body diode; after the second power device M2 is turned on, the diode D2 changes from the on state to the off state, and the diode D2 generates a lower reverse recovery current.
  • the function of the diode D1 is to provide a conductive path for the voltage detection circuit when the first power device M1, the high-voltage LDMOS tube M3, and the diode D2 are turned off. That is, in this embodiment, the circuit makes the freewheeling current flow through the conduction channel of the power device instead of the freewheeling diode.
  • the freewheeling diode hardly generates reverse recovery current, but ordinary diodes generate lower reverse recovery current. , That is, replacing the extremely high reverse recovery current of the freewheeling diode in the power device with the lower reverse recovery current of the ordinary diode, so as to achieve the purpose of reducing the reverse recovery current of the power device.
  • the purpose of reducing the reverse recovery current of the power device is achieved by a high-voltage LDMOS tube connected to the high-voltage side power device with a common drain and a gate and a low-voltage MOS tube connected in series with the high-voltage LDMOS tube.
  • FIG 8. Another circuit for reducing the reverse recovery current of a power device proposed by the present invention is shown in Figure 8.
  • the structure, working principle and characteristics of the first and second power stage circuits are exactly the same, so only the first power is analyzed.
  • the characteristics of the working principle of the first-level circuit, the first power-level circuit includes: a high-voltage LDMOS tube M3, a low-voltage MOS tube M4, a diode D1 and a voltage detection circuit.
  • the voltage detection circuit includes: a reference circuit, resistors R1, R2, and a voltage comparator.
  • the freewheeling current generated in the load inductance first flows through the body diode D4 of the low-voltage MOS tube M4 and the body diode D3 of the high-voltage LDMOS tube M3, and the body diode D4 of the low-voltage MOS tube M4 is turned on.
  • the potential of node Vd is the potential of the high-side floating ground VS minus 0.7V, that is, the potential of node Vd is -0.7V, and the negative voltage of node Vd -0.7V cannot be directly connected to the positive phase terminal of the voltage comparator
  • the voltage divider circuit R1 and R2 is used to raise the negative voltage to the input range of the voltage comparator.
  • the resistance of the resistor R2 is twice that of the resistor R1.
  • the reference circuit provides two reference voltages of 5V and 3.8V.
  • the non-inverting terminal voltage V+ can be calculated by the following resistor divider formula:
  • the voltage of the node V- is 3.8V, that is, the reference voltage of 3.8V is connected to the inverting terminal of the voltage comparator.
  • the latter-stage voltage comparator detects the conduction voltage of the diode D2, it outputs a high-level signal to one end of the OR gate and inputs IN2.
  • the high-level signal IN2 and the previous-stage signal IN1 are used as the two inputs of the OR gate, and the OR gate output signal makes The output HO of the high-side drive circuit is high, so that the channels of the first power device M1, the high-voltage LDMOS tube M3, and the low-voltage MOS tube M4 are turned on, and the freewheeling current flows through the conductive channel, almost not through the body diode D3, D4 and the freewheeling diode in the first power device, at this time, there is almost no reverse recovery current in the body diode.
  • the function of the diode D1 is to be the voltage when the first power device M1, the low voltage MOS tube M4 and its body diode D4 are turned off.
  • the detection circuit provides a conductive path. That is, in this embodiment, this circuit also makes the freewheeling current flow through the conduction channel of the power device instead of the freewheeling diode, the freewheeling diode hardly generates reverse recovery current and no ordinary diode generates reverse recovery current, so The purpose of reducing the reverse recovery current of the power device is achieved.
  • FIG. 9 (b) (FIG. 6 showing a circuit configuration operating waveforms) shown, t 3 time, in contrast to FIG. 9 (a), a freewheeling current flows through the conductive I D4 almost ditch high-voltage LDMOS transistor M3 and the low voltage MOS transistor M4 Therefore, the freewheeling current I VD4 on the body diodes D3 and D4 is very small, so the reverse recovery current I rr generated is very small.

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Abstract

一种降低功率器件反向恢复电流的栅极驱动电路，属于基本电子电路的技术领域。该栅极驱动电路包括高压LDMOS管、导通时构成续流通路的二极管或反并联有体二极管的低压MOS管、电压检测电路，功率器件关断时，电感负载产生续流电流流过续流二极管，电压检测电路检测到续流二极管导通，输出信号经控制电路处理后，使驱动电路输出高电平，从而使功率器件、高压LDMOS管的沟道导通，则续流电流从导电沟道流过，几乎不通过续流二极管，此时续流二极管几乎不存在反向恢复电流，从而达到降低功率器件反向恢复电流的目的。

Description

降低功率器件反向恢复电流的栅极驱动电路 技术领域
本发明公开了降低功率器件反向恢复电流的栅极驱动电路，涉及单片集成电路(Monolithic IC)栅驱动技术，属于基本电子电路的技术领域。
背景技术
单片集成电路(Monolithic IC)栅驱动领域中，耐压高、导通电流密度大、导通电阻低等性能优异的功率开关器件已经被广泛使用，如：超结功率MOS管(Superjunction Mosfet)或基于SOI技术的LIGBT。传统的单片集成电路如图1所示，由驱动电路与功率器件直接集成在一起。
传统功率MOS管存在的最大问题就是在高压工作下的导通压降过高，即导通电阻过高。对于理想的N沟道功率MOS管，导通电阻R on与击穿电压V B之间的关系为(见文献：陈星弼.超结器件电力电子技术[J],电力电子技术,2008,42(12):2-7.)：
Figure PCTCN2019105484-appb-000001
公式1表明导通电阻受到击穿电压的限制，称之为“硅限”，即，对功率器件要求高耐压的同时无法做到低的导通电阻。然而，相对于传统功率MOS管，超结MOS管在相同的芯片面积上满足高耐压(600V以上)的同时大大降低导通电阻。超结MOS管导通电阻R on与击穿电压V B之间的关系为(见文献：陈星弼.超结器件电力电子技术[J],电力电子技术,2008,42(12):2-7.)：
Figure PCTCN2019105484-appb-000002
由公式1和公式2可以证明，在同样的击穿电压下，超结MOS管与传统MOS管相比，导通电阻显著降低。
超结MOS管内的寄生体二极管在其工作时起续流作用，保护超结MOS管免于反向电动势击穿，然而，寄生体二极管反向恢复电流极大。N型超结MOS管如图2所示，超结结构中的PN结柱状结构给内部寄生体二极管带来两个严重后果：一是PN结面积较传统的功率MOS管大了许多，寄生体二极管作为续流二极管导通时，非平衡少数载流子大量积累，使超结MOS管具有很高的反向恢复电荷Qrr；二是PN结柱状结构的快速耗尽会使这些非平衡少数载流子迅速排 出，即，反向恢复时间Trr很小。所以，由于超结MOS管内体二极管的反向恢复电荷非常高，反向恢复时间短，这就导致超结MOS管内体二极管的反向恢复电流极大。
对于基于SOI技术的LIGBT而言，LIGBT结构没有体二极管，故需要反向并联的续流二极管提供续流通路，同样的，该续流二极管的反向恢复电流也非常大。
超结MOS管的双脉冲测试波形如图3所示，在t3时刻，续流二极管的反向恢复电流尖峰非常大，导致体二极管在反向恢复过程中产生较大的功耗甚至烧毁。
PN结二极管与超结MOS管体二极管或者其它功率器件体二极管相比，反向恢复电流非常小。PN结二极管反向恢复电流产生过程如图4所示，PN结二极管外加正向偏置时，P+区的多子空穴流向N+区，N+区的多子电子流向P+区，进入P+区的电子和进入N+区的空穴分别成为该区的少子，即，此时非平衡少数载流子增多，通常把正向导通时非平衡少数载流子积累的现象叫做电荷存储效应。当PN结二极管施加反向电压时，非平衡少子会通过两个途径逐渐减少：一是在反向电场作用下，P+区电子被拉回N+区，N+区空穴被拉回P+区，形成反向恢复电流，即，发生少子抽取；二是与多数载流子复合。
由于少子的密度很低，不会随反向偏压的上升而明显变化，因此，在击穿电压之前，少子抽取形成的反向恢复电流很小，所以PN结二极管与超结MOS管体二极管相比，反向恢复电流非常小。
为了解决功率器件反向恢复电流过大的问题，有如下三种现有技术：
(1)使用重金属掺杂，在器件漂移层中形成新的复合中心，将过剩的非平衡载流子复合掉，降低了反向恢复电荷Qrr，从而减小反向恢复电流Irr，但是这种方法工艺技术要求高，成本高，器件漏电流也比较大；
(2)使用辐射技术在器件漂移层中形成缺陷，减小非平衡少数载流子的寿命，从而降低了反向恢复电荷Qrr，从而减小反向恢复电流Irr，但是所形成的缺陷稳定性极差，影响器件使用的可靠性，并且器件漏电流仍然比较大；
(3)对于LIGBT之类需要反并联续流二极管的功率器件而言，续流二极管采用肖特基结构，肖特基二极管是多子参与导电，不存在少子存储与复合效应，故不存在少数载流子所引起的反向恢复电流问题，该技术需要添加附加层，工艺 技术要求高，成本也会增加。
现有技术中，有一种添加额外电阻二极管并联结构的方法可以较好地解决上述超结MOS管内体二极管反向恢复电流过高的问题。该方法的思路是在体二极管续流时，在高侧超结MOS管栅源之间加上电阻产生压降，使得高侧超结MOS管导电沟道打开，续流电流从导电沟道上流过，体二极管上几乎没有续流电流，即可降低体二极管的反向恢复电流，其电路原理如图5(a)所示，在高侧超结MOS管T1的源极与高侧悬浮地VS端之间增添一个电阻与二极管并联的网络，电阻R1的一端与普通二极管D1的阳极以及高侧超结MOS管T1的源极相连，电阻R1的另一端与普通二极管D1的阴极相连于高侧悬浮地VS。将高侧超结MOS管的栅极与高侧悬浮地VS直接相连，在母线电压V BUS与高侧悬浮地VS端之间加上一个电感L1作为感性负载。在低侧超结MOS管T2的栅极加上一个双脉冲波形，在第一个脉冲下降后即图3所示的t2时刻后，低侧超结MOS管T2关断，电感L1产生续流电流I L，续流电流I L流向高侧超结MOS管T1的源极，从而在电阻R1的两端形成压降，此压降正是高侧超结MOS管T1的栅源电压Vgs。电阻R1的阻值非常大，目的是使电阻两端的压降Vgs大于高侧超结MOS管T1的开启电压VTH，从而使高侧超结MOS管T1沟道导通，续流电流IL流过高侧超结MOS管T1的导电沟道而在体二极管FWD1上几乎无续流电流，则体二极管FWD1几乎不存在反向恢复电流Irr。在图3的t3时刻，低侧超结MOS管T2开启后普通二极管D1开始导通，普通二极管D1的等效导通电阻与大电阻R1相比非常小，并联条件下大电阻R1基本被忽略，二极管D1导通压降低即电阻两端并联的普通二极管D1可以消去此时大电阻R1对高侧悬浮地VS端电压的影响。虽然这种方法降低了体二极管反向恢复电流过大的问题，但是带来另一个严重的问题，过高的电阻R1使得高侧悬浮地VS端在低侧超结MOS管T2栅极的第二个脉冲下降时产生较大的过冲电压，如图5(b)t4时刻所示，该过冲电压对功率器件的性能与可靠性都会产生较大影响。
发明内容
本发明的发明目的是针对上述背景技术的不足，提供了降低功率器件反向恢复电流的栅极驱动电路，续流电流流过功率器件导电沟道而不是功率器件续流二极管，实现了续流二极管产生的恢复电流极小，解决了通过电阻二极管并联结构降低体二极管反向恢复电流的驱动电路因电阻过大在低压侧超结MOS管栅极产 生过冲电压的技术问题。
本发明为实现上述发明目的采用如下技术方案：
降低功率器件反向恢复电流的栅极驱动电路，其特征在于，包括：
高压LDMOS管，其漏极和功率器件的漏极共同接母线电压，其栅极和功率器件的栅极共同接驱动电路的输出端，
第一二极管，其阳极接高压LDMOS管的源极，其阴极与功率器件的源极共同接地，
与高压LDMOS管源极串联的开关管，其电流输入端与功率器件的源极共同接地，其电流输出端接高压LDMOS管的源极，
电压检测电路，其输入端接所述开关管的电流输出端，检测到开关管的导通压降后输出检测值，
或门，其一输入端接经前级电路模数处理后的输入信号，其另一输入端接电压检测电路的输出端，及，
驱动电路，其输入端接或门的输出端，输出所述开关管管导通时功率器件和高压LDMOS管均导通的驱动信号。
作为降低功率器件反向恢复电流的栅极驱动电路的进一步优化方案，与高压LDMOS管源极串联的开关管为反并联在第一二极管两极的第二二极管。
作为降低功率器件反向恢复电流的栅极驱动电路的进一步优化方案，与高压LDMOS管源极串联的开关管为反并联有体二极管的低压MOS管，所述低压MOS管的栅极和功率器件的栅极共同接驱动电路的输出端，低压MOS管的漏极接高压LDMOS管的源极，低压MOS管的源极和功率器件的源极共同接地。
再进一步的，降低功率器件反向恢复电流的栅极驱动电路用于驱动高压侧功率器件时，功率器件的源极、第一二极管的阴极、开关管的电流输入端共同接高压侧悬浮地。
再进一步的，降低功率器件反向恢复电流的栅极驱动电路用于驱动低压侧功率器件时，功率器件的源极、第一二极管的阴极、开关管的电流输入端共同接输入信号的地。
再进一步的，降低功率器件反向恢复电流的栅极驱动电路中，电压检测电路包括：基准电路、第一电阻、第二电阻、电压比较器，第二电阻的一端接开关管的电流输出端，第二电阻的另一端和第一电阻的一端均与电压比较器的同相端相 连，第一电阻的另一端接基准电路输出的一路基准电压，电压比较器的反向端接基准电路输出的另一路基准电压，电压比较器检测到开关管的导通压降后输出检测值。
更进一步的，降低功率器件反向恢复电流的栅极驱动电路中，基准电路输出的两路基准电压满足：
Figure PCTCN2019105484-appb-000003
这一约束，V 1、V 2分别为输出至电压比较器反向端和同相端的基准电压，V d为二极管导通时阴极的节点电位，V d＝-0.7V，R 1、R 2分别为第一电阻和第二电阻的阻值。优选地，电压检测电路中基准电路产生两个的基准电压分别为3.8V、5V。
更进一步的，降低功率器件反向恢复电流的栅极驱动电路中，第一电阻和第二电阻的阻值满足：
Figure PCTCN2019105484-appb-000004
这一约束。优选地，电阻R2阻值是电阻R1的两倍。
本发明采用上述技术方案，具有以下有益效果：
(1)摒弃了传统通过辐射、重金属掺杂解决功率器件反向恢复电流过高的方法，节约了成本，降低了工艺制造难度。
(2)用普通二极管或低压MOS管代替上述现有技术采用的大电阻R1，普通二极管或低压MOS管导通压降很低，能够有效削减高侧悬浮地VS端的电压过冲并降低功耗。
(3)摒弃了LIGBT反并联肖特基二极管的方法，不添加额外层的同时降低了成本和工艺制造难度。
附图说明
图1是内部集成功率器件单片集成电路的结构图。
图2是N型超结MOS管的结构图。
图3是超结MOS管双脉冲测试的波形图。
图4是PN结二极管反向恢复电流产生过程的图。
图5(a)是现有技术下降低超结MOS管反向恢复电流的电路原理图。
图5(b)是图5(a)中高侧悬浮地VS端产生较大过冲电压的波形图。
图6是本发明提出的降低功率器件反向恢复电流电路的结构框图。
图7是本发明提出的降低功率器件反向恢复电流电路的一个实施例。
图8是本发明提出的降低功率器件反向恢复电流电路的另一个实施例。
图9是图8所示电路与图1传统电路的工作波形对比图。
具体实施方式
下面结合附图对发明的技术方案进行详细说明。
本发明提出的降低功率器件反向恢复电流电路如图6所示，驱动高压侧第一功率器件M1时，前级电路、第一功率级电路、或门、高侧驱动电路构成高侧通道，驱动低压侧第二功率器件M2时，前级电路、第二功率级电路、或门、低压侧驱动电路构成低侧通道。第一、第二功率级电路的结构、工作原理完全一样，故只分析第一功率级电路的工作原理和特征。第二功率器件M2关断后，第一功率级电路输出高电平，与前级电路的输出信号一起经过或门处理，或门输出给高侧驱动电路，高侧驱动电路输出信号打开第一功率器件M1的导电沟道，续流电流此时流过导电沟道而不是续流二极管，续流二极管则产生极低的反向恢复电流，则降低了功率器件反向恢复电流。
具体实施例一：通过与高压侧功率器件共漏共栅连接的高压LDMOS管以及与高压LDMOS管反向串联的普通二极管实现降低功率器件反向恢复电流的目的。
高侧通道的第一功率级电路如图7所示，包括：高压LDMOS管M3、二极管D1、二极管D2和电压检测电路，高压LDMOS管M3漏极接母线电压V BUS，高压LDMOS管M3栅极接高侧驱动电路的输出HO，二极管D2阳极连接在高侧悬浮地VS上，二极管D2阴极和高压LDMOS管M3源极一同连接在电压检测电路的输入端IN上，第二功率器件M2关断后，电感负载产生的续流电流流过二极管D2，二极管D2导通，电压检测电路检测到二极管D2导通压降后输出高电平信号OUT至或门的一端输入端IN2，高电平信号OUT与前级电路输出至或门输入端IN1的信号经过逻辑或处理后使得高侧驱动电路的输出信号HO为高电平的或运算结果，则第一功率器件M1和高压LDMOS管M3的沟道导通，续流电流从导电沟道上流过，高压LDMOS管M3和第一功率器件M1的体二极管几乎没有续流电流流过，则此时体二极管产生的反向恢复电流非常小，第二功率器件M2开启时，二极管D2由导通状态变为截止状态，此时由普通二极管D2产生的反向恢复电流与功率器件相比非常小，即达到了降低功率器件反向恢复电流的目的。
高侧通道中的电压检测电路如图7所示，包括：基准电路、电阻R1、电阻R2、电压比较器，基准电路产生的一路基准电压接在电压比较器的反相端，基准电路产生的另一路基准电压接在电阻R1的一端，电阻R1的另一端与电阻R2的一端一同连接在电压比较器的正相端，电阻R2的另一端作为电压检测电路的输入端IN与二极管D2的阴极相连，电压比较器的输出端作为电压检测电路的输出端，电压检测电路输出的OUT与后级逻辑或门的输入端IN2相连。
低侧通道的第二功率级电路如图7所示，包括：高压LDMOS管M4、二极管D5、二极管D6和电压检测电路，高压LDMOS管M4漏极接高侧悬浮地VS，高压LDMOS管M4栅极接低侧驱动电路的输出LO，二极管D6的阳极接地，二极管D6的阴极和高压LDMOS管M4的源极一同连接在电压检测电路的输入端IN，第一功率器件M1关断后，电感负载产生续流电流流过二极管D6，二极管D6导通，电压检测电路检测到二极管D6导通压降后输出高电平信号OUT至或门输入端IN4上，高电平信号与前级电路输出至或门输入端IN3的信号经逻辑或处理后得到使得低侧驱动电路输出LO为高电平的或运算结果，则第二功率器件M2和LDMOS管M4沟道导通，续流电流从导电沟道上流过，高压LDMOS管M4和第二功率器件M2的体二极管几乎没有续流电流流过，则此时体二极管产生的反向恢复电流非常小，第一功率器件M1开启时，二极管D6由导通状态变为截止状态，此时由普通二极管D6产生的反向恢复电流与功率器件相比非常小，即达到了降低功率器件反向恢复电流的目的。
低侧通道中的电压检测电路如图7所示，包括：基准电路、电阻R3、电阻R4、电压比较器，基准电路产生的一路基准电压接在电压比较器的反相端，基准电路产生的另一路基准电压接在电阻R3的一端，电阻R3的另一端与电阻R4的一端一同连接在电压比较器的正相端，电阻R4的另一端作为电压检测电路的输入端IN与二极管D6的阴极相连，电压比较器的输出端作为电压检测电路的输出端，电压检测电路输出的OUT与后级逻辑或门逻辑的输入端IN4相连。
第一功率级电路种，二极管D1的作用是在高压LDMOS管M3和二极管D2同时关断时为电压检测电路提供导电通路；第二功率级电路中，二极管D4的作用是在高压LDMOS管M4和二极管D6同时关断时为电压检测电路提供导电通路。电压检测电路中基准电路产生的两路基准电压满足：
Figure PCTCN2019105484-appb-000005
电阻R1和电阻R2的阻值需满足：
Figure PCTCN2019105484-appb-000006
V d为二极管导通时阴极的节点电位，V d＝-0.7V。本例中，电压检测电路中基准电路产生的两路基准电压分别为3.8V、5V，电阻R2阻值是电阻R1的两倍，电阻R4阻值是电阻R3的两倍。
第二功率器件M2关断后，负载电感上产生续流电流首先流过二极管D2，二极管D2导通，此时二极管D2的阴极即节点Vd的电位为高侧悬浮地VS的电位减去0.7V，即节点Vd的电位为-0.7V，节点Vd负压-0.7V不能直接接在电压比较器的正相端，此时利用R1、R2分压将负压抬高至电压比较器的输入范围内，电阻R2阻值是电阻R1的两倍，基准电路提供两个基准电压5V和3.8V，比较器的同相端电压V+可由以下电阻分压公式计算：
Figure PCTCN2019105484-appb-000007
则节点V-的电压为3.8V，即3.8V的基准电压接在电压比较器的反相端。后级电压比较器检测到二极管D2导通电压后，输出高电平信号给或门的一端输入IN2，高电平信号IN2与前级信号IN1作为或门的两个输入，或门输出信号使高侧驱动电路输出HO为高电平，从而使第一功率器件M1、高压LDMOS管M3沟道导通，则续流电流从导电沟道流过，续流电流几乎不通过体二极管D3和第一功率器件的续流二极管，此时体二极管几乎不存在反向恢复电流；第二功率器件M2开启后，二极管D2由导通状态转变为截止状态，二极管D2产生较低的反向恢复电流。二极管D1作用是在第一功率器件M1与高压LDMOS管M3、二极管D2关断时为电压检测电路提供导电通路。即在本实施例中，此电路使续流电流流过功率器件的导电沟道而不是续流二极管，续流二极管几乎不产生反向恢复电流，只是普通二极管产生了较低的反向恢复电流，即用普通二极管的较低反向恢复电流来代替功率器件内续流二极管的极高反向恢复电流，达到了降低功率器件管反向恢复电流的目的。
具体实施例二：通过与高压侧功率器件共漏共栅连接的高压LDMOS管以及与高压LDMOS管串联的低压MOS管实现降低功率器件反向恢复电流的目的。
本发明提出的另一种降低功率器件反向恢复电流电路如图8所示，在本实施例中，第一、第二功率级电路的结构、工作原理特征完全一样，故只分析第一功 率级电路工作原理特征，第一功率级电路包括：高压LDMOS管M3、低压MOS管M4、二极管D1和电压检测电路，电压检测电路包括：基准电路、电阻R1、R2、电压比较器。
第二功率器件M2关断后，负载电感上产生续流电流首先流过低压MOS管M4的体二极管D4和高压LDMOS管M3的体二极管D3，低压MOS管M4的体二极管D4导通，此时二极管D4的阴极即节点Vd的电位为高侧悬浮地VS的电位减去0.7V，即节点Vd的电位为-0.7V，节点Vd负压-0.7V不能直接接在电压比较器的正相端，此时利用R1、R2分压电路将负压抬高至电压比较器的输入范围内，电阻R2阻值是电阻R1的两倍，基准电路提供两个基准电压5V和3.8V，比较器的同相端电压V+可由以下电阻分压公式计算：
Figure PCTCN2019105484-appb-000008
则节点V-的电压为3.8V，即3.8V的基准电压接在电压比较器的反相端。后级电压比较器检测到二极管D2导通电压后，输出高电平信号给或门的一端输入IN2，高电平信号IN2与前级信号IN1作为或门的两个输入，或门输出信号使高侧驱动电路输出HO为高电平，从而使第一功率器件M1、高压LDMOS管M3及低压MOS管M4沟道导通，则续流电流导电沟道流过，几乎不通过体二极管D3、D4和第一功率器件中的续流二极管，则此时体二极管几乎不存在反向恢复电流，二极管D1作用是在第一功率器件M1、低压MOS管M4及其体二极管D4关断时为电压检测电路提供导电通路。即在本实施例中，此电路同样使续流电流流过功率器件的导电沟道而不是续流二极管，则续流二极管几乎不产生反向恢复电流且没有普通二极管产生反向恢复电流，从而达到了降低功率器件反向恢复电流的目的。
如图9(a)(图1传统电路结构工作波形图)所示，t 3时刻，第一功率器件M1导电沟道续流电流I m1极小，续流电流I VD1几乎流过第一功率器件M1体二极管，故产生反向恢复电流I rr非常大。
如图9(b)(图6电路结构工作波形图)所示，t 3时刻，对比于图9(a)，续流电流I D4几乎流过高压LDMOS管M3及低压MOS管M4的导电沟道，体二极管D3、D4上续流电流I VD4极小，故产生反向恢复电流I rr非常小。
以上所述仅为本发明的优选实例而已，并不限制本发明的保护范围，对于本 领域的技术人员来说，可根据本发明的记载做出类似或等同于上述实施例的改进和/或变化。凡在本发明的精神和原则之内做出的任何修改、等同替换、改进均应包含在本发明的保护范围之内。

Claims (8)

  1. 降低功率器件反向恢复电流的栅极驱动电路，其特征在于，包括：
    高压LDMOS管，其漏极和功率器件的漏极共同接母线电压，其栅极和功率器件的栅极共同接驱动电路的输出端，
    第一二极管，其阳极接高压LDMOS管的源极，其阴极与功率器件的源极共同接地，
    与高压LDMOS管源极串联的开关管，其电流输入端与功率器件的源极共同接地，其电流输出端接高压LDMOS管的源极，
    电压检测电路，其输入端接所述开关管的电流输出端，检测到开关管的导通压降后输出检测值，
    或门，其一输入端接经前级电路模数处理后的输入信号，其另一输入端接电压检测电路的输出端，及，
    驱动电路，其输入端接或门的输出端，输出所述开关管管导通时功率器件和高压LDMOS管均导通的驱动信号。
  2. 根据权利要求1所述降低功率器件反向恢复电流的栅极驱动电路，其特征在于，与高压LDMOS管源极串联的开关管为反并联在第一二极管两极的第二二极管。
  3. 根据权利要求1所述降低功率器件反向恢复电流的栅极驱动电路，其特征在于，与高压LDMOS管源极串联的开关管为反并联有体二极管的低压MOS管，所述低压MOS管的栅极和功率器件的栅极共同接驱动电路的输出端，低压MOS管的漏极接高压LDMOS管的源极，低压MOS管的源极和功率器件的源极共同接地。
  4. 根据权利要求1或2或3所述降低功率器件反向恢复电流的栅极驱动电路，其特征在于，该栅极驱动电路用于驱动高压侧功率器件时，功率器件的源极、第一二极管的阴极、开关管的电流输入端共同接高压侧悬浮地。
  5. 根据权利要求1或2或3所述降低功率器件反向恢复电流的栅极驱动电路，其特征在于，该栅极驱动电路用于驱动低压侧功率器件时，功率器件的源极、 第一二极管的阴极、开关管的电流输入端共同接输入信号的地。
  6. 根据权利要求1或2或3所述降低功率器件反向恢复电流的栅极驱动电路，其特征在于，所述电压检测电路包括：基准电路、第一电阻、第二电阻、电压比较器，第二电阻的一端接开关管的电流输出端，第二电阻的另一端和第一电阻的一端均与电压比较器的同相端相连，第一电阻的另一端接基准电路输出的一路基准电压，电压比较器的反向端接基准电路输出的另一路基准电压，电压比较器检测到开关管的导通压降后输出检测值。
  7. 根据权利要求6所述降低功率器件反向恢复电流的栅极驱动电路，其特征在于，基准电路输出的两路基准电压满足：
    Figure PCTCN2019105484-appb-100001
    这一约束，V 1、V 2分别为输出至电压比较器反向端和同相端的基准电压，V d为二极管导通时阴极的节点电位，V d＝-0.7V，R 1、R 2分别为第一电阻和第二电阻的阻值。
  8. 根据权利要求7所述降低功率器件反向恢复电流的栅极驱动电路，其特征在于，第一电阻和第二电阻的阻值满足：
    Figure PCTCN2019105484-appb-100002
    这一约束。
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