WO2020227976A1 - 一种数据传输方法和装置 - Google Patents

一种数据传输方法和装置 Download PDF

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Publication number
WO2020227976A1
WO2020227976A1 PCT/CN2019/087058 CN2019087058W WO2020227976A1 WO 2020227976 A1 WO2020227976 A1 WO 2020227976A1 CN 2019087058 W CN2019087058 W CN 2019087058W WO 2020227976 A1 WO2020227976 A1 WO 2020227976A1
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WO
WIPO (PCT)
Prior art keywords
chip
data stream
data
code
fec
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PCT/CN2019/087058
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English (en)
French (fr)
Inventor
何向
Original Assignee
华为技术有限公司
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Publication date
Priority to CN201980095737.7A priority Critical patent/CN113728569B/zh
Priority to BR112021022883A priority patent/BR112021022883A2/pt
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN202211516321.8A priority patent/CN116032422A/zh
Priority to CA3177569A priority patent/CA3177569A1/en
Priority to PCT/CN2019/087058 priority patent/WO2020227976A1/zh
Priority to CN202211516507.3A priority patent/CN115987450A/zh
Priority to EP19929100.6A priority patent/EP3958485A4/en
Priority to JP2021565966A priority patent/JP2022533326A/ja
Priority to BR112021022737A priority patent/BR112021022737A2/pt
Priority to PCT/CN2019/096055 priority patent/WO2020228126A1/zh
Priority to CN201980096406.5A priority patent/CN113875177A/zh
Priority to JP2021567829A priority patent/JP7424724B2/ja
Priority to EP19928816.8A priority patent/EP3965325A4/en
Priority to CA3178909A priority patent/CA3178909A1/en
Publication of WO2020227976A1 publication Critical patent/WO2020227976A1/zh
Priority to US17/525,189 priority patent/US20220077875A1/en
Priority to US17/525,178 priority patent/US20220077958A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0064—Concatenated codes
    • H04L1/0065—Serial concatenated codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0064—Concatenated codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1515—Reed-Solomon codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes

Definitions

  • This application relates to the field of communication technology, and in particular to a data transmission method and device.
  • Forward error correction (English: forward error correction, abbreviated as: FEC) code can provide error correction protection for data in transmission, thereby improving the data transmission rate and transmission distance in the channel.
  • FEC forward error correction
  • the sending device can use a specific FEC code pattern to encode the original data and then send the encoded data to the receiving device, and the receiving device can use the same FEC code pattern for the received data. The data is decoded to obtain the original data.
  • the FEC code pattern may need to be converted during data transmission.
  • the FEC code pattern in order to adapt to high-rate and/or long-distance data transmission, when the original FEC code pattern adopted by the original data transmission interface cannot meet the requirements of data transmission, the FEC code pattern needs to be converted to make the original FEC code pattern It is replaced by a higher gain FEC pattern.
  • the conversion process of the FEC code pattern tends to increase the time delay of the data transmission process and the power consumption of the data transmission equipment, thereby affecting the data transmission efficiency.
  • the embodiments of the present application provide a data transmission method and device to simplify the conversion process of the FEC code pattern during data transmission, thereby reducing the time delay and equipment power consumption during the conversion of the FEC code pattern, and improving data transmission. effectiveness.
  • an embodiment of the present application provides a data transmission method, including: a first chip receives a first data stream sent by a second chip; the first data stream is encoded using a first forward error correction FEC code pattern The data stream; the first chip encodes the first data stream at least once to obtain a second data stream; wherein, the second data stream uses at least the first FEC code pattern and the second FEC Concatenated FEC code stream of code type encoding; the first chip sends the second data stream to the third chip. It can be seen that for the first data stream encoded by the first FEC code pattern sent by the second chip to the first chip, the first chip does not need to use the first FEC code pattern to decode the first data stream and then re-encode the original data.
  • a higher gain FEC code pattern but at least the second FEC code pattern can be used on the basis of the first data stream to perform at least one encoding, so that at least the first FEC code pattern and the second FEC code pattern can be obtained.
  • the second data stream is cascaded to achieve higher gain. Therefore, the conversion process of the FEC code type is simplified, the time delay and the power consumption of the device during the conversion of the FEC code type are reduced, and the data transmission efficiency is improved.
  • the first FEC code type is specifically: RS code, BCH code, Staircase code, LDPC code, Turbo code, or TPC. It can be seen that the first chip can support encoding to obtain concatenated FEC codes on the basis of multiple different first FEC code types.
  • the second FEC code type is specifically: BCH code, RS code, Staircase code, LDPC code, Turbo code or TPC. It can be seen that the first chip can support a concatenated FEC code obtained by encoding on the basis of the first FEC code type according to multiple different second FEC code types.
  • the first chip encodes the first data stream at least once to form a second data stream, including : The first chip distributes the first data stream into n third data streams; wherein the data of the same codeword block in the first data stream is distributed to different third data streams ; The first chip separately encodes the plurality of third data streams at least once to form the second data stream. It can be seen that the data in the same codeword block in the first data stream can be encoded into multiple different codeword blocks in the second data stream, so that the concatenated FEC code has stronger error correction capability.
  • the k codeword blocks identified from the first data stream are distributed to n third data streams
  • each piece of data belonging to the k codeword blocks in the third data stream is encoded into a codeword block in the second data stream; wherein, k codewords in the first data stream
  • the total amount of data contained in the block is equal to the amount of payload data contained in the n codeword blocks in the second data stream.
  • the payload in the n second codeword blocks is all the data in the k codeword blocks
  • the n second codeword blocks can directly follow the second FEC code pattern and the first FEC code
  • the type is decoded into original data, which facilitates the decoding operation of the first FEC code type and the second FEC code type on the same chip.
  • the data in the first data stream is distributed according to FEC symbol blocks, and the same in the first data stream
  • the data of the FEC symbol block is encoded in the same codeword block in the second data stream. It can be seen that the first chip can distribute the first data stream with the granularity of the symbol block.
  • the data in the first data stream is distributed according to a bit stream, and the data in the third data stream is distributed according to The bitstream is encoded. It can be seen that the first chip can distribute and process the first data stream with bit granularity.
  • the first chip and the second chip are located in a first data transmission device, and the third chip is located in In the second data transmission device, the first chip is an electrical chip, the second chip is a device using an Ethernet interface, and the third chip is an electrical chip.
  • the first data transmission device can encode the first data stream of the first FEC code pattern output by the device using the Ethernet interface into at least the first FEC code pattern and the second FEC code pattern cascaded to form the first data stream through the electronic chip.
  • the two data streams are then sent to the second data transmission device, thereby realizing data transmission between the first data transmission device and the second data transmission device through concatenated FEC codes.
  • the first data stream passes through interference between the second chip and the first chip. Physical link for transmission. It can be seen that, for the first data stream that has errors during transmission on the physical link with interference, the first chip can directly perform the first data stream at least one more time without decoding and correcting the first data stream.
  • the encoding forms a concatenated second data stream.
  • an embodiment of the present application provides a data transmission method, including: a first chip receives a second data stream sent by a second chip; the second data stream adopts at least a first FEC code pattern and a second FEC Concatenated FEC code stream of code type encoding; said first chip decodes said second data stream at least once to form a first data stream; said first data stream is coded using said first FEC code type Data stream; the first chip sends the first data stream to the third chip. It can be seen that, for the second data stream that is at least cascaded by the first FEC code pattern and the second FEC code pattern sent by the second chip to the first chip, the first chip may use other codes other than the first FEC code pattern.
  • the FEC code type decodes the second data stream to form a first data stream encoded with the first FEC code type and sends it to the third chip, without having to decode the second data stream into original data and then re-encode it into the first FEC
  • the data stream of the pattern is sent to the third chip. Therefore, the conversion process of the FEC code type is simplified, the time delay and the power consumption of the device during the conversion of the FEC code type are reduced, and the data transmission efficiency is improved.
  • the first FEC code type is specifically: RS code, BCH code, Staircase code, LDPC code, Turbo Code or TPC.
  • the second FEC code type is specifically: BCH code, RS code, Staircase code, LDPC code, Turbo Code or TPC. It can be seen that the first chip can support the decoding of multiple different second FEC code patterns.
  • the first data stream is used to be decoded by the third chip according to the first FEC code pattern . It can be seen that the first chip can support cascaded FEC code decoding and output multiple different first FEC code types.
  • the second chip is located in the first data transmission device, and the first chip and the third The chip is located in the second data transmission device, the first chip is an electrical chip, the second chip is a chip, and the third chip is a device using an Ethernet interface.
  • the first data transmission device can use the first data transmission device through the electronic chip.
  • Two FEC code pattern The second data stream is decoded into the first data stream of the first FEC code pattern and then sent to the device using the Ethernet interface, so as to realize the cascaded FEC between the first data transmission device and the second data transmission device Code for data transmission.
  • the first data stream passes through a physical medium between the first chip and the third chip.
  • the first chip can decode the second data stream into a second data stream encoded with the first FEC code type by using other FEC code types except the first FEC code type without decoding the second data stream into the original data.
  • a data stream so that the first data stream is transmitted to the third chip through a physical medium with interference, and the third chip decodes the first data stream to obtain the original data.
  • the physical medium may be, for example, an optical fiber, an optical waveguide, a circuit, air, and the like.
  • an embodiment of the present application provides a data transmission device applied to a first chip, including a receiver, an encoder, and a transmitter.
  • the receiver is used to receive the first data stream sent by the second chip;
  • the first data stream is the data stream encoded with the first forward error correction FEC code type;
  • the encoder is used to The data stream is encoded again at least once to obtain a second data stream;
  • the second data stream is a concatenated FEC code stream that uses at least the first FEC code type and the second FEC code type code;
  • the transmitter uses Yu sends the second data stream to the third chip.
  • the first FEC code type is specifically: RS code, BCH code, Staircase code, LDPC code, Turbo code or TPC.
  • the second FEC code type is specifically: BCH code, RS code, Staircase code, LDPC code, Turbo code or TPC.
  • the encoder is specifically configured to: distribute the first data stream into n third data streams; Wherein, the data of the same codeword block in the first data stream is distributed to the different third data streams; the multiple third data streams are respectively encoded at least once to form the second data flow.
  • the k codeword blocks identified from the first data stream are distributed to n third data streams Wherein, each piece of data belonging to the k codeword blocks in the third data stream is encoded into one codeword block in the second data stream;
  • the total amount of data included in the k codeword blocks in the first data stream is equal to the amount of payload data included in the n codeword blocks in the second data stream.
  • the data in the first data stream is distributed according to FEC symbol blocks, and the same in the first data stream
  • the data of the FEC symbol block is encoded in the same codeword block in the second data stream.
  • the data in the first data stream is distributed according to a bit stream
  • the data in the third data stream is distributed according to The bitstream is encoded.
  • the first chip and the second chip are located in a first data transmission device, and the third chip is located in In the second data transmission device, the first chip is an electrical chip, the second chip is a device using an Ethernet interface, and the third chip is an electrical chip.
  • the first data stream passes through a physical medium between the second chip and the first chip To transfer. It can be seen that, for the first data stream that has an error during transmission in the physical medium with interference, the first chip can directly encode the first data stream at least one more time without decoding and correcting the first data stream. Form a cascaded second data stream.
  • the data transmission device provided in the third aspect corresponds to the data transmission method provided in the first aspect. Therefore, the technical effects of the various possible implementations of the data transmission device provided in the second aspect can be referred to the aforementioned first aspect. An introduction to the data transmission method provided by the aspect.
  • an embodiment of the present application provides a data transmission device applied to a first chip, including a receiver, a decoder, and a transmitter.
  • the receiver is used to receive the second data stream sent by the second chip;
  • the second data stream is a concatenated FEC code stream encoded with at least the first FEC code type and the second FEC code type;
  • the decoder is used The second data stream is decoded at least once to form a first data stream;
  • the first data stream is a data stream encoded with the first FEC code pattern;
  • a transmitter is used to send all data streams to a third chip The first data stream.
  • the first FEC code type is specifically: RS code, BCH code, Staircase code, LDPC code, Turbo Code or TPC.
  • the second FEC code type is specifically: BCH code, RS code, Staircase code, LDPC code, Turbo Code or TPC.
  • the first data stream is used to be decoded by the third chip according to the first FEC code pattern .
  • the second chip is located in the first data transmission device, and the first chip and the third The chip is located in the second data transmission device, the first chip is an electrical chip, the second chip is a chip, and the third chip is a device using an Ethernet interface.
  • the first data stream passes through a physical medium between the first chip and the third chip To transfer. It can be seen that the first chip can decode the second data stream into a second data stream encoded with the first FEC code type by using other FEC code types except the first FEC code type without decoding the second data stream into the original data. A data stream, so that the first data stream is transmitted to the third chip through a physical medium with interference, and the third chip decodes the first data stream to obtain the original data.
  • the data transmission device provided in the fourth aspect corresponds to the data transmission method provided in the second aspect. Therefore, the technical effects of the various possible implementations of the data transmission device provided in the fourth aspect may refer to the aforementioned second aspect. An introduction to the data transmission method provided by the aspect.
  • an embodiment of the present application also provides a communication method, the communication method comprising: the data transmission method described in any one of the implementations of the first aspect, and the data transmission method described in any of the implementations of the second aspect. Data transfer method.
  • an embodiment of the present application also provides a communication system, which includes: the data transmission device described in any one of the foregoing third aspect implementation manners, and the aforementioned data transmission device in any one implementation manner of the foregoing fourth aspect Data transmission device.
  • an embodiment of the present application also provides a network device, which includes the data transmission device described in any one of the implementation manners of the third aspect.
  • an embodiment of the present application also provides a network device, which includes the data transmission apparatus described in any one of the foregoing fourth aspects.
  • the embodiments of the present application also provide a computer program product, which when running on a computer, causes the computer to execute the data transmission method described in any one of the foregoing first aspects or any of the foregoing second aspects.
  • the embodiments of the present application also provide a computer-readable storage medium that stores instructions in the computer-readable storage medium, which when run on a computer or processor, causes the computer or processor to execute the aforementioned first
  • FIG. 1 is a schematic diagram of an example of an application scenario in an embodiment of the application
  • FIG. 2 is a schematic flowchart of a data transmission method in an embodiment of this application.
  • FIG. 3 is a schematic diagram of an example of a data distribution method in an embodiment of the application.
  • FIG. 4 is a schematic diagram of an example of a data distribution method in an embodiment of the application.
  • FIG. 5 is a schematic diagram of an example of a data distribution method in an embodiment of the application.
  • FIG. 6 is a schematic diagram of an example of a data distribution method in an embodiment of the application.
  • FIG. 7 is a schematic diagram of a network structure in an exemplary scenario in an embodiment of the application.
  • FIG. 8 is a schematic flowchart of a data transmission method in an embodiment of this application.
  • FIG. 9 is a schematic flowchart of a data transmission method in an embodiment of this application.
  • FIG. 10 is a schematic flowchart of an encoding method in an embodiment of this application.
  • FIG. 11 is a schematic flowchart of a data transmission method in an embodiment of this application.
  • FIG. 12 is a schematic flowchart of a data transmission method in an embodiment of this application.
  • FIG. 13 is a schematic structural diagram of a data transmission method in an embodiment of this application.
  • FIG. 14 is a schematic structural diagram of a data transmission method in an embodiment of this application.
  • the sending device can use a specific FEC code pattern to encode the original data and then send the encoded FEC code to the receiving device, and the receiving device can receive the data according to the same FEC code pattern.
  • the FEC code is decoded to obtain the original data. In this way, even if the transmission channel causes errors in certain positions in the FEC code, the receiving device can obtain the original data before the error by performing reverse calculations based on the check bits in the FEC code during decoding, thereby realizing the error correction function.
  • the FEC code pattern may need to be converted during data transmission.
  • the concatenated FEC code adopts one or more basic FEC code types to construct the code type to form a multi-level FEC code, which can provide stronger error correction protection for the transmission data. Therefore, cascaded FEC codes can be used to transmit data between devices to cope with the noise introduced during high-speed or long-distance data transmission.
  • the original FEC code pattern used by the original data transmission interface of the device is the code type specified by the standard. For example, the original Ethernet interface of many devices only supports Reed-Solomon (English: Reed-Solomon, referred to as RS) code.
  • RS Reed-Solomon
  • the device needs to convert the data to be transmitted from the original FEC code pattern to a higher gain FEC code.
  • the data encoded using the original FEC code type needs to be decoded into original data, and then the original data is coded using the new FEC code type.
  • such a conversion process will not only bring additional power consumption to the data transmission device, but also increase the time delay of the data transmission process.
  • the cascaded FEC code when data is transmitted between two chips, is a FEC code pattern that can provide high gain for high-rate and/or long-distance data transmission and is
  • the concatenated FEC code is formed by cascading multi-level FEC code types.
  • the chip When receiving the first data stream encoded with the first FEC code type, the chip does not need to decode the first data stream first FEC code type. Then re-encode the original data into concatenated FEC codes.
  • at least the second FEC code pattern can be used for at least one encoding, so that at least the first FEC code pattern and the second FEC code pattern can be obtained.
  • the second data stream formed by cascading FEC patterns to obtain higher gain. Therefore, the conversion process of the FEC code type is simplified, the time delay and the power consumption of the device required for the FEC code type conversion are reduced, and the data transmission efficiency is improved.
  • the embodiments of this application can be applied to the scenario shown in FIG. 1.
  • the data transmission device 101 is provided with a chip 103 and a chip 105
  • the data transmission device 102 is provided with a chip 107 and a chip 109.
  • the chip 103 can use the first FEC code pattern
  • the original data is encoded to form a first data stream, and the first data stream is sent to the chip 105 through the channel 104.
  • the chip 105 After the chip 105 receives the first data stream, it can use at least the second FEC code pattern to encode the first data stream at least once to obtain a second cascade of at least the first FEC code pattern and the second FEC code pattern. Data stream, and send the second data stream to the chip 107 through the channel 106. After the chip 107 receives the second data stream, it can decode the second data stream at least once using the second FEC code type to obtain the first data stream coded using the first FEC code type, and transmit the first data stream through the channel 108. The data stream is sent to the chip 109. After the chip 109 receives the first data stream, it can use the first FEC code pattern to decode the first data stream to obtain the original data.
  • the first FEC code type may be an FEC code type such as RS code supported by the Ethernet interface
  • the second FEC code type may be Bose-Chaudhuri-Hocquenghem (English: Bose-Chaudhuri-Hocquenghem, abbreviated as: BCH) code and other code types.
  • BCH Bose-Chaudhuri-Hocquenghem
  • the channel 104, the channel 106, and the channel 108 may all be physical links with interference, and bit errors will occur when the data stream is transmitted in the channel 104, the channel 106, and the channel 108.
  • the first data stream sent by chip 103 to chip 105 will generate errors when transmitted in channel 104
  • the second data stream sent by chip 105 to chip 107 will generate errors when transmitted in channel 106.
  • errors will occur again.
  • FIG. 2 is a schematic flowchart of a data transmission method 200 in an embodiment of this application.
  • the method may include, for example:
  • Chip 1 receives a first data stream sent by chip 2; the first data stream is a data stream encoded with a first forward error correction FEC code pattern.
  • chip 2 may use the first FEC code pattern to encode the original data to form a first data stream and send it to chip 1. Therefore, the first data stream received by chip 1 is a data stream that has been coded with the first FEC code type. In other words, the first data stream is a code stream composed of codeword blocks (English: codeword) of the first FEC code type. .
  • the first FEC code type can be RS code, BCH code, ladder (English: Staircase) code, low-density parity-check (English: low-density parity-check, abbreviation: LDPC) code, turbo (English: Turbo) Code, turbo product code (English: Turbo product code, TPC for short) and other code types.
  • the first FEC code pattern may be an RS code.
  • the codeword block of the first FEC pattern contains an additional parity code (English: parity code) provided for the original data, and the parity code is used to correct errors generated during data transmission. Perform error correction.
  • the first FEC code type may be a systematic FEC code (English: systematic FEC), that is, the codeword block of the first FEC code type may include original data and a check code provided for the original data.
  • the codeword block of the first FEC code type can be processed based on a finite field.
  • the codeword block may be divided into multiple FEC symbol (English: symbol) blocks, and the processing of the codeword block may be based on the FEC symbol block as the granularity.
  • a 5440-bit codeword block includes 5140-bit original data and a 300-bit check code.
  • Galois Field English: Galois Field, abbreviated: GF
  • a codeword block includes 544 FEC symbol blocks, that is, 514 FEC symbol blocks The original data and check code of 30 FEC symbol blocks.
  • a 5280-bit codeword block includes 5140-bit original data and 140-bit check code. If the GF (210) domain is used for processing, every 10 bits of data forms an FEC symbol block, then a codeword block includes 528 FEC symbol blocks, that is, the original data of 514 FEC symbol blocks and the checksum of 14 FEC symbol blocks code. It is understandable that for consecutive errors (English: consecutive errors) or burst errors (English: burst errors), consecutive multi-bit errors will only be reflected as errors in a small number of FEC symbol blocks. Therefore, When the FEC symbol block is used as the granularity to process the FEC codeword block, the FEC error correction capability is stronger.
  • chip 1 and chip 2 are two different chips, and data can be transmitted through a physical link with interference between the two. Therefore, the first data stream sent by chip 2 to chip 1 is in the physical link. When transmitting on the road, it will be affected by interference and cause bit errors. It can be seen that the first data stream received by chip 1 is a data stream that has already generated bit errors.
  • the chip 1 encodes the first data stream at least once to obtain a second data stream; wherein, the second data stream is encoded using at least the first FEC code type and the second FEC code type The cascaded FEC code stream.
  • the chip 1 may not need to use the first FEC code pattern to decode the first data stream into original data, but may at least be based on the first data stream.
  • the second FEC code type is used to perform at least one encoding, so as to form a second data stream formed by cascading at least the first FEC code type and the second FEC code type.
  • the second data stream may be a cascaded FEC code stream in which the first FEC code type and the second FEC code type are cascaded, that is, the second data stream is a two-level cascaded FEC code stream, or the second data stream It is also possible to cascade one or more levels of cascaded FEC code streams on the basis of the cascade of the first FEC code pattern and the second FEC code pattern, that is, the second data stream is a three-level or more cascaded FEC code stream. Code stream. It is understandable that if chip 2 sends the first data stream to chip 1 through a physical link with interference, the first data stream received by chip 1 is a data stream that has caused bit errors. Therefore, chip 1 is Without decoding the first data stream that has generated errors, directly encode the first data stream that has generated errors at least once to form a second data stream of multi-level FEC cascade.
  • the second FEC code type may be a code type such as BCH code, RS code, Staircase code, LDPC code, Turbo code, TPC, etc. It is understandable that the second FEC code type may be the same as the first FEC code type, or the second FEC code type may be different from the first FEC code type. For example, both the first FEC code type and the second FEC code type may be RS codes, or the first FEC code type may be RS codes and the second FEC code type may be BCH codes.
  • the second data stream is a code stream composed of codeword blocks of the FEC code type used in the last level of encoding.
  • the second data stream is a data stream formed by concatenating the first FEC code type and the second FEC code type, the first level uses the first FEC code type encoding, and the second level uses the second FEC code type encoding, Then the second data stream is a code stream composed of codeword blocks of the second FEC code type. Since the second data stream is obtained by using the second FEC code type encoding on the basis of the first data stream, the codeword block of the second FEC code type includes an additional check code provided for the first data stream. If the second FEC code type is a systematic code, the code word block of the second FEC code type includes the data in the first data stream and the check code provided for the data.
  • the data in the same codeword block in the first data stream can be encoded into multiple different codeword blocks in the second data stream, so that even if the second data A small part of the codeword blocks in the stream cannot be decoded correctly, and it will not affect the correct decoding of the codeword blocks in the first data stream.
  • the chip 1 can distribute the first data stream to n different channels to form n third data streams, so that the data of the same codeword block in the first data stream is distributed To multiple different third data streams, where n represents a natural number greater than 1. Then, the chip 1 can respectively encode the third data streams on the n channels at least once to form a second data stream.
  • the first FEC codeword block is a codeword block in the first data stream, and the data in the codeword block is distributed to the third data stream on n channels, each The third data stream on the channel is respectively encoded into second FEC codeword blocks to form n second FEC code streams, and the n second FEC code streams form the second data stream.
  • the first FEC codeword block represents the codeword block obtained by using the first FEC code type
  • the second FEC codeword block represents the codeword block obtained by using the second FEC code type
  • the second FEC code stream represents A data stream composed of two FEC codeword blocks.
  • the first data stream can be a data stream on one channel, or it can be composed of data streams on multiple channels, that is, the first data stream can be one code stream or multiple barcodes. Stream composition.
  • the first data stream is a data stream on a channel
  • the first data stream is distributed into a third data stream, which is equivalent to one data stream being distributed into multiple data streams.
  • n is a natural number greater than 1
  • the first data stream is the first FEC code stream on one channel
  • the third data stream on n channels is formed after distribution processing.
  • the third data streams on the channels are respectively encoded into a second FEC code stream, and these n FEC code streams constitute the second data stream.
  • the first FEC code stream represents a data stream composed of a first FEC codeword block
  • the first FEC codeword block represents a codeword block obtained by encoding the first FEC code type
  • the second FEC code stream represents a data stream composed of a second FEC codeword block.
  • the distribution from the first data stream to the third data stream is equivalent to the distribution from multiple data streams to multiple data streams.
  • This distribution can be interleaved (English: interleave) technology and/or multiplexing (English: multiplex) technology and other distribution strategies to achieve. For example, in the example shown in FIG.
  • the first data stream is composed of the first FEC stream on k channels, and passes through an interleaver (English: interleaver)
  • the fourth data stream on m channels can be formed, and after multiplexers such as bit multiplexer (English: bit multiplexer) or symbol multiplexer (English: symbol multiplexer)
  • the third data stream on n channels can be formed.
  • the third data stream on each channel is respectively encoded into a second FEC code stream, and these n FEC code streams form the second data stream.
  • the first FEC code stream represents a data stream composed of a first FEC codeword block
  • the first FEC codeword block represents a codeword block obtained by encoding the first FEC code type
  • the second FEC code stream represents a data stream composed of a second FEC codeword block.
  • the chip 1 may perform distribution processing on the first data stream with a bit granularity, that is, the data in the first data stream may be distributed to n third data streams according to the bit stream.
  • chip 1 can obtain one bit of data from the first data stream, and select a channel for the data from n channels according to the distribution strategy, thereby distributing the data to the third data stream on the channel in.
  • the chip 1 may also perform encoding processing on the third data stream with bit granularity, that is, the data in the third data stream may be encoded according to the bit stream.
  • the chip 1 may distribute the first data stream with the granularity of FEC symbol blocks, that is, the data in the first data stream may be distributed according to the FEC symbol stream.
  • chip 1 can identify an FEC symbol block from the first data stream, and select a channel for the FEC symbol block from n channels according to the distribution strategy, thereby distributing the FEC symbol block to the channel In the third data stream.
  • the chip 1 can also encode the third data stream with the granularity of FEC symbol blocks.
  • chip 1 can identify a certain number of FEC symbol blocks from the third data stream and encode them into the same codeword block in the second data stream. Therefore, the same FEC symbol block in the first data stream The data will be encoded in the same codeword block in the second data stream.
  • the FEC symbol block can be identified by an alignment marker (English: alignment marker, AM for short).
  • the chip 1 may perform distribution processing on the first data stream with a granularity of multiple codeword blocks.
  • the chip 1 can identify multiple codeword blocks from the first data stream, and distribute the data of the multiple codeword blocks to the third data stream on n channels according to the distribution strategy.
  • the distribution strategy can be implemented by, for example, interleaving (English: interleave) technology and/or multiplexing (English: multiplexer) technology.
  • the first data stream may be one code stream, that is, the multiple codeword blocks may be identified from one code stream, or the first data stream may be composed of multiple code streams, that is,
  • the k codeword blocks may be identified from multiple barcode streams.
  • the first data stream is composed of k barcode streams, and the multiple codeword blocks may be identified from each barcode stream. K codeword blocks obtained from one codeword block.
  • chip 1 can use all the data of the k codeword blocks in the first data stream as the payload of the n codeword blocks in the second data stream, so that The k codeword blocks in the first data stream are encoded into n codeword blocks in the second data stream.
  • the chip 1 can identify k codeword blocks from the first data stream, and distribute the data of these k codeword blocks to the third data stream on n channels according to the distribution strategy.
  • the data of these k codeword blocks distributed to each channel can be respectively encoded into a codeword block in the second data stream, so that n codeword blocks in the second data stream are encoded on n channels. .
  • the k first FEC codeword blocks identified from the first data stream are input to the interleaver (English: interleaver In ), the data output by the interleaver to m channels is then input to a multiplexer such as bit multiplexer (English: bit multiplexer) or symbol multiplexer (English: symbol multiplexer), and the multiplexer outputs n
  • a multiplexer such as bit multiplexer (English: bit multiplexer) or symbol multiplexer (English: symbol multiplexer)
  • the multiplexer outputs n
  • the data on the channels, and the data on each channel are respectively encoded into a second FEC codeword block, thereby obtaining n second FEC codeword blocks in the second data stream.
  • the first FEC codeword block represents a codeword block obtained by using the first FEC code type encoding, and can be identified from the first data stream through AM.
  • the second FEC codeword block represents a codeword block obtained by using the second FEC code type encoding.
  • the total data volume of the k codeword blocks in the first data stream needs to be the same as that of the second data stream.
  • the amount of payload data of the n codeword blocks of the stream is equal.
  • the RS codeword block of the first data stream includes a payload of 5140 bits and a check code of 300 bits.
  • the BCH of the second data stream The codeword block includes a 340-bit payload and a 20-bit check code.
  • the total data volume of 4 RS codeword blocks is 21760 bits, and the payload data volume of 64 BCH codeword blocks is also 21760 bits. Therefore, The 4 RS codeword blocks of the first data stream can be encoded into 64 BCH codeword blocks of the second data stream.
  • the chip 1 sends the second data stream to the chip 3.
  • the chip 3 After the chip 3 receives the second data stream, it can decode the second data stream. In this way, the cascaded FEC code is used to transmit data between chip 1 and chip 3.
  • the chip 3 may decode all FEC code patterns including the first FEC code pattern and the second FEC code pattern in the second data stream, so as to obtain the original data.
  • chip 3 can decode other FEC code patterns in the second data stream except the first FEC code pattern to obtain the first data stream and send it to chip 4, and chip 4 can then decode the first data stream.
  • the first FEC code pattern in the stream is decoded to obtain the original data. It is understandable that chip 1 and chip 3 are two different chips, and data can be transmitted between them through a physical link with interference. Similarly, chip 3 and chip 4 are two different chips, and data can be transmitted through a physical link between the two.
  • the second data stream sent by chip 1 to chip 3 when the second data stream sent by chip 1 to chip 3 is transmitted on the physical link, it will be interfered by the physical link and cause errors. Chip 3 does not remove the second data that has already generated errors.
  • the second data stream of cascaded FEC is decoded into the first data stream encoded with the first FEC code pattern and sent to chip 4, and the first data stream sent from chip 3 to chip 4 When transmitting on the physical link, it will be affected by interference again and cause bit errors, so that chip 4 decodes and corrects the first data into original data. It can be seen that the first data stream received by chip 1 has already caused bit errors. data flow.
  • the decoding of each level of FEC code pattern can be realized by identifying the code word block of the level FEC code pattern and performing reverse calculation on the identified code word block.
  • the second data stream is formed by cascading the first FEC code pattern and the second FEC code pattern
  • the second data stream can be decoded from the second data stream by means of AM or self-synchronization technology.
  • the codeword block of the second FEC code type is identified in the second FEC code type, and the codeword block of the second FEC code type is inversely calculated to obtain the first data stream.
  • the codeword block of the second FEC code type can be compared with the first data stream.
  • the fixed mapping relationship between the codeword blocks of the FEC code type or AM and other methods identify the codeword block of the first FEC code type from the first data stream, and perform reverse calculation on the codeword block of the first FEC code type, thereby Get the original data.
  • chip 1 and chip 2 may be two chips located in the first data transmission device, and chip 3 and chip 4 may be one chip located in the second data transmission device. chip.
  • the first data transmission device and the second data transmission device need to use cascaded FEC codes to transmit data, but chip 2 and chip 4 only support the first FEC code type and do not support the cascaded FEC code, therefore, chip 1 pair chip 2
  • the output data stream is then encoded to form a cascaded FEC code stream and sent to chip 3.
  • the chip decodes the cascaded FEC code stream into a data stream of the first FEC code pattern and then outputs it to chip 4, so that the difference between chip 1 and chip 3 Then, data can be transmitted through concatenated FEC codes, so that data can be transmitted between the first data transmission device and the second data transmission device through concatenated FEC codes.
  • the chip 1 may be an electrical chip, for example, a relay electrical chip or an electrical chip of an optical module, such as a digital signal processing (English: Digital Signal Processing, DSP for short) chip.
  • Chip 2 may be a chip using an Ethernet interface, such as a physical (English: physical, abbreviated: PHY) layer chip.
  • the chip 3 may be an electrical chip, for example, an electrical chip that relays an electrical chip or an optical module, such as a DSP chip.
  • the chip 4 may be a chip using an Ethernet interface, such as a physical (English: physical, abbreviated: PHY) layer chip.
  • the concatenated FEC code provided in this embodiment achieves a better error correction effect in simulation verification.
  • an additive Gaussian is inserted in the channel between chip 2 and chip 1, the channel between chip 1 and chip 3, and the channel between chip 3 and chip 4.
  • White noise (English: Additive White Gaussian Noise, abbreviated as: AWGN), thus forming a simulation environment.
  • chip 2 sends the data stream of the first FEC code pattern to chip 1, and chip 1 converts the data stream of the first FEC code pattern into a cascaded FEC code stream and sends it to chip 3, and chip 3 will cascade
  • the FEC code stream is converted into a data stream of the first FEC code type and then sent to the chip 4.
  • chip 4 can correctly decode the received data stream of the first FEC pattern;
  • chip 2 sends the data stream of the first FEC pattern to chip 1, and chip 1 sends the data stream of the first FEC pattern directly to Chip 3 and chip 3 directly send the data stream of the first FEC pattern to chip 4.
  • chip 4 cannot correctly decode the received data stream of the first FEC pattern.
  • the simulation verification performed in the above simulation environment shows that: Compared with the cascaded FEC code stream formed by chip 1 decoding the code stream of the first FEC code pattern and then performing multi-level coding, chip 1 is not correcting the first FEC code stream.
  • the second FEC code type is used to encode the code stream of the first FEC code type to form a cascaded FEC code stream, which can not only save 60 to 100 ns of time delay, but also It can achieve a net coding gain (English: net coding gain, abbreviated: NCG) above 9dB.
  • chip 1 does not need to use the first FEC code pattern to decode the first data stream and then reconstruct the original data.
  • Encoded into a concatenated FEC code but on the basis of the first data stream, at least the second FEC code pattern can be used for at least one encoding, so that at least the first FEC code pattern and the second FEC code pattern can be cascaded Into the second data stream. Therefore, the conversion process of the FEC code type is simplified, the time delay and the power consumption of the device during the conversion of the FEC code type are reduced, and the data transmission efficiency is improved.
  • FIG. 8 is a schematic flowchart of a data transmission method 800 in an embodiment of this application.
  • the method may include, for example:
  • Chip 3 receives a second data stream sent by chip 1.
  • the second data stream is a concatenated FEC code stream that uses at least a first FEC code type and a second FEC code type encoding;
  • the chip 3 decodes the second data stream at least once to form a first data stream; the first data stream is a data stream encoded with the first FEC code pattern;
  • the chip 3 sends the first data stream to the chip 4.
  • the chip 4 After the chip 4 receives the first data stream, it can decode the first data stream according to the first FEC code pattern to obtain the original data.
  • the first FEC code type may be RS code, BCH code, ladder code, LDPC code, Turbo code, TPC and other code types
  • the second FEC code type may be BCH code, RS code, Staircase code, LDPC Code, Turbo code, TPC and other code types.
  • the chip 1 may be located in a first data transmission device, the chip 3 and the chip 4 may be located in a second data transmission device, and the chip 3 and the chip 1 may be Electric chip.
  • the chip 4 may be a chip using an Ethernet interface.
  • this embodiment corresponds to the decoding process of the second data stream
  • the embodiment shown in FIG. 2 corresponds to the encoding process of the second data stream. Therefore, various specific implementations related to this embodiment, such as For the specific implementations of the first data stream, the second data stream, the first FEC code pattern, the second FEC code pattern, chip 1, chip 3, chip 4, etc., please refer to the introduction of the embodiment shown in FIG. 2, namely The method in the embodiment corresponding to FIG. 8 is the inverse decoding solution of encoding introduced in the embodiment corresponding to FIG.
  • chip 3 may use a data stream other than the first FEC code pattern.
  • Other FEC code types decode the second data stream to form a first data stream coded with the first FEC code type and send it to the chip 4 without having to decode the second data stream into original data and then re-encode it into the first FEC
  • the data stream of the code pattern is sent to the chip 4. Therefore, the conversion process of the FEC code type is simplified, the time delay and the power consumption of the device during the conversion of the FEC code type are reduced, and the data transmission efficiency is improved.
  • the first data transmission device includes a first PHY layer chip and a first optical module
  • the first optical module has a first DSP chip
  • the second data transmission device includes a second PHY layer chip and a second optical module.
  • Module, the second optical module has a second DSP.
  • the first data transmission device and the second data transmission device use cascaded FEC codes to transmit data
  • the first PHY layer chip and the second PHY layer chip support RS codes but do not support cascaded FEC codes.
  • the data transmission method 900 between the first data transmission device and the second data transmission device may include, for example:
  • the first PHY chip uses the RS code to encode the original data once to form an RS code stream.
  • the first PHY chip sends an RS code stream to the first DSP.
  • the first DSP uses the BCH code to encode the RS code stream again to form a BCH code stream.
  • the BCH code stream is actually a concatenated FEC code stream formed by concatenating the RS code and the BCH code.
  • the first DSP sends the BCH code stream to the second DSP.
  • the second DSP uses the BCH code to decode the BCH code stream once to form an RS code stream.
  • the second DSP sends the RS code stream to the second PHY chip.
  • the second PHY chip uses the RS code to decode the RS code stream again to obtain the original data.
  • the first DSP does not need to use the RS code to decode the RS code stream and then re-encode the original data into the concatenated FEC code stream, but can use the BCH code on the basis of the RS code stream to do it again.
  • the BCH code can be used to decode the concatenated FEC code stream once to form the RS code stream, so that the second PHY chip can receive the RS code stream . Therefore, the conversion process of the FEC code type is simplified, the time delay and the power consumption of the device during the conversion of the FEC code type are reduced, and the data transmission efficiency is improved.
  • FIG. 10 is a schematic flowchart of an encoding method 1000 in an embodiment of this application.
  • the method 1000 is used to encode k codeword blocks of the first FEC code type by using the second FEC code type to form n codeword blocks of the second FEC code type.
  • the method 1000 may include:
  • the first data stream is a data stream encoded with the first FEC code type. Therefore, the first code word block in the first data stream is a code word block of the first FEC code type.
  • the first codeword block can be identified from the first data stream by AM
  • the distribution strategy can be implemented by interleaving (English: interleave) technology and/or multiplexing (English: multiplexer) technology.
  • the k first FEC codeword blocks can be input to the interleaver (English: interleaver), and the data output by the interleaver to m channels are then input to the bit multiplexer (English: bit multiplexer) or symbol complex.
  • the multiplexer outputs data on n channels.
  • the data from the k first codeword blocks is encoded as a payload into a second codeword block, that is, the payload of the second codeword block is The data allocated from the k first codeword blocks on this channel. Therefore, the total payload of the n second codeword blocks encoded on n channels is all the data of the k first codeword blocks, that is to say, the total data volume of the k first codeword blocks needs to be equal to The payload data amount of the n second codeword blocks is equal.
  • the n second codeword blocks can directly follow the second FEC code pattern and The first FEC code pattern is decoded into original data, which facilitates the decoding operations of the first FEC code pattern and the second FEC code pattern on the same chip.
  • FIG. 11 is a schematic structural diagram of a data transmission method 1100 in an embodiment of this application.
  • the method 1100 includes:
  • a first chip receives a first data stream sent by a second chip; the first data stream is a data stream encoded with a first forward error correction FEC code pattern;
  • the first chip encodes the first data stream at least once to obtain a second data stream; wherein, the second data stream adopts at least the first FEC code pattern and the second FEC code pattern Encoded concatenated FEC code stream.
  • the first FEC code type is specifically: RS code, BCH code, Staircase code, LDPC code, Turbo code, or turbo product code TPC.
  • the second FEC code type is specifically: BCH code, RS code, Staircase code, LDPC code, Turbo code, or TPC.
  • the first chip encodes the first data stream at least once to form a second data stream, including:
  • the first chip distributes the first data stream into n third data streams; wherein the data of the same codeword block in the first data stream is distributed to different third data streams;
  • the first chip separately encodes the plurality of third data streams at least once to form the second data stream.
  • the k codeword blocks identified from the first data stream are distributed to n third data streams, and each third data stream belongs to the k codes
  • the data of the word block is encoded into a code word block in the second data stream;
  • the total amount of data included in the k codeword blocks in the first data stream is equal to the amount of payload data included in the n codeword blocks in the second data stream.
  • the data in the first data stream is distributed according to FEC symbol blocks, and the data of the same FEC symbol block in the first data stream is encoded in the same FEC symbol block in the second data stream.
  • a codeword block In a codeword block.
  • the data in the first data stream is distributed according to a bit stream
  • the data in the third data stream is encoded according to a bit stream.
  • the first chip and the second chip are located in the same data transmission device, the first chip is an electrical chip, and the second chip is a chip using an Ethernet interface.
  • the first chip is the chip 1 mentioned in the data transmission method 200
  • the second chip is the chip 2 mentioned in the data transmission method 200
  • the third chip is the chip mentioned in the data transmission method. 3. Therefore, the various specific embodiments of the operations performed by the first chip, the second chip, and the third chip in this embodiment can be found in the data transmission method 200 shown in FIG. The introduction is not repeated in this embodiment.
  • chip 1 does not need to use the first FEC code pattern to decode the first data stream and then reconstruct the original data.
  • Encoded into a concatenated FEC code but on the basis of the first data stream, at least the second FEC code pattern can be used for at least one encoding, so that at least the first FEC code pattern and the second FEC code pattern can be cascaded Into the second data stream. Therefore, the conversion process of the FEC code type is simplified, the time delay and the power consumption of the device during the conversion of the FEC code type are reduced, and the data transmission efficiency is improved.
  • FIG. 12 is a schematic structural diagram of a data transmission method 1200 in an embodiment of this application.
  • the method 1200 includes:
  • a first chip receives a second data stream sent by a second chip; the second data stream is a concatenated FEC code stream that uses at least a first FEC code type and a second FEC code type encoding;
  • the first chip decodes the second data stream at least once to form a first data stream; the first data stream is a data stream encoded with the first FEC code pattern;
  • the first chip sends the first data stream to a third chip.
  • the first FEC code type is specifically: RS code, BCH code, Staircase code, LDPC code, Turbo code, or TPC.
  • the second FEC code type is specifically: BCH code, RS code, Staircase code, LDPC code, Turbo code, or TPC.
  • the first data stream is used to be decoded by the third chip according to the first FEC code pattern.
  • the second chip is located in a first data transmission device, the first chip and the third chip are located in a second data transmission device, the first chip is an electrical chip, so The second chip is an electrical chip, and the third chip is a chip using an Ethernet interface.
  • the first chip is the chip 3 mentioned in the data transmission method 200
  • the second chip is the chip 1 mentioned in the data transmission method 200
  • the third chip is the chip mentioned in the data transmission method. 4. Therefore, the various specific embodiments of the operations performed by the first chip, the second chip, and the third chip in this embodiment can be found in the data transmission method 200 shown in FIG. 2 for chip 3, chip 1, and chip 4. The introduction is not repeated in this embodiment.
  • the first chip may use the first FEC code pattern except The other FEC code types decode the second data stream to form the first data stream encoded with the first FEC code type and send it to the third chip, instead of re-encoding the second data stream after decoding the original data
  • the data stream in the first FEC code pattern is sent to the third chip. Therefore, the conversion process of the FEC code type is simplified, the time delay and the power consumption of the device during the conversion of the FEC code type are reduced, and the data transmission efficiency is improved.
  • FIG. 13 is a schematic structural diagram of a data transmission device 1300 in an embodiment of this application.
  • the device 1300 is the first chip and includes:
  • the receiver 1301 is configured to receive a first data stream sent by the second chip; the first data stream is a data stream encoded with a first forward error correction FEC code pattern;
  • the encoder 1302 is configured to encode the first data stream at least once to obtain a second data stream; wherein, the second data stream is encoded by at least the first FEC code type and the second FEC code type The cascaded FEC code stream.
  • the first FEC code type is specifically: RS code, BCH code, Staircase code, LDPC code, Turbo code, or TPC.
  • the second FEC code type is specifically: BCH code, RS code, Staircase code, LDPC code, Turbo code, or TPC.
  • the encoder 1302 is specifically used for:
  • the plurality of third data streams are respectively encoded again at least once to form the second data stream.
  • the k codeword blocks identified from the first data stream are distributed to n third data streams, and each third data stream belongs to the k codes
  • the data of the word block is encoded into a code word block in the second data stream;
  • the total amount of data included in the k codeword blocks in the first data stream is equal to the amount of payload data included in the n codeword blocks in the second data stream.
  • the data in the first data stream is distributed according to FEC symbol blocks, and the data of the same FEC symbol block in the first data stream is encoded in the same FEC symbol block in the second data stream.
  • a codeword block In a codeword block.
  • the data in the first data stream is distributed according to a bit stream
  • the data in the third data stream is encoded according to a bit stream.
  • the first chip and the second chip are located in the same data transmission device, the first chip is an electrical chip, and the second chip is a device using an Ethernet interface.
  • the device 1100 shown in FIG. 11 is the chip 1 mentioned in the embodiment shown in FIG. 2. Therefore, for various specific embodiments of the device 1100 in this embodiment, refer to FIG. 2 The description of the chip 1 in the embodiment is omitted in this embodiment.
  • the first chip does not need to use the first FEC code pattern to decode the first data stream before decoding the first data stream.
  • the original data is re-encoded into concatenated FEC codes, but on the basis of the first data stream, at least the second FEC code pattern can be used for at least one encoding, so that at least the first FEC code pattern and the second FEC code can be obtained Type cascade into the second data stream. Therefore, the conversion process of the FEC code type is simplified, the time delay and the power consumption of the device during the conversion of the FEC code type are reduced, and the data transmission efficiency is improved.
  • FIG. 14 is a schematic structural diagram of a data transmission device 1400 in an embodiment of this application.
  • the device 1400 is specifically the first chip and includes:
  • the receiver 1401 is configured to receive a second data stream sent by a second chip; the second data stream is a concatenated FEC code stream that uses at least a first FEC code type and a second FEC code type encoding;
  • the decoder 1402 is configured to decode the second data stream at least once to form a first data stream; the first data stream is a data stream encoded with the first FEC code type;
  • the transmitter 1403 is configured to send the first data stream to the third chip.
  • the first FEC code type is specifically: RS code, BCH code, Staircase code, LDPC code, Turbo code, or TPC.
  • the second FEC code type is specifically: BCH code, RS code, Staircase code, LDPC code, Turbo code or TPC.
  • the first data stream is used to be decoded by the third chip according to the first FEC code pattern.
  • the second chip is located in a first data transmission device, the first chip and the third chip are located in a second data transmission device, the first chip is an electrical chip, so The second chip is a chip, and the third chip is a device using an Ethernet interface.
  • the device 1400 shown in FIG. 14 is the chip 3 mentioned in the embodiment shown in FIG. 2. Therefore, for various specific embodiments of the device 1400 in this embodiment, refer to FIG. 2 The introduction of the chip 3 in the embodiment of, will not be repeated in this embodiment.
  • chip 1 may use a code other than the first FEC code pattern.
  • Other FEC code types decode the second data stream to form a first data stream encoded with the first FEC code type and send it to the chip 3, without having to decode the second data stream into original data and then re-encode it into the first FEC
  • the data stream of the code pattern is sent to chip 3. Therefore, the conversion process of the FEC code type is simplified, the time delay and the power consumption of the device during the conversion of the FEC code type are reduced, and the data transmission efficiency is improved.
  • an embodiment of the present application also provides a communication method, which includes: the aforementioned data transmission method 1100 and the aforementioned data transmission method 1200.
  • an embodiment of the present application also provides a communication system, which includes the aforementioned data transmission device 1300 and the aforementioned data transmission device 1400.
  • an embodiment of the present application also provides a network device, which includes the aforementioned data transmission apparatus 1300 or 1400.
  • the embodiment of the present application also provides a computer program product containing instructions, which when running on a computer, causes the computer to execute the data transmission method 1100 or 1200 described in the method embodiment of the embodiment of the present application.
  • the embodiments of the present application also provide a computer-readable storage medium that stores instructions in the computer-readable storage medium. When it runs on a computer or a processor, the computer or the processor executes the Method of Example The data transmission method 1100 or 1200 described in the embodiment.
  • the computer software product can be stored in a storage medium, such as read-only memory (English: read-only memory, ROM)/RAM, magnetic disk, An optical disc, etc., includes a number of instructions to enable a computer device (which may be a personal computer, a server, or a network communication device such as a router) to execute the method described in each embodiment of the application or some parts of the embodiment.
  • a computer device which may be a personal computer, a server, or a network communication device such as a router
  • the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments.
  • the description is relatively simple, and for related parts, please refer to the partial description of the method embodiment.
  • the above-described device and system embodiments are only illustrative.
  • the modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, they may be located in One place, or it can be distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the objectives of the solutions of the embodiments. Those of ordinary skill in the art can understand and implement it without creative work.

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Abstract

本申请实施例公开了一种数据传输方法，包括：第一芯片接收第二芯片发送的第一数据流；所述第一数据流为采用第一前向纠错FEC码型编码的数据流；所述第一芯片对所述第一数据流再进行至少一次编码，得到第二数据流；其中，所述第二数据流为至少采用所述第一FEC码型和第二FEC码型编码的级联FEC码流。可见，FEC码型的转换过程得以简化，FEC码型转换时所要耗费的时延及设备功耗都得以减小，从而数据传输效率得以提高。此外，本申请实施例还公开了一种数据传输装置。

Description

一种数据传输方法和装置 技术领域
本申请涉及通信技术领域，特别是涉及一种数据传输方法和装置。
背景技术
前向纠错(英文：forward error correction，简称：FEC)码可以为传输中的数据提供纠错保护，从而能够提高信道中的数据传输速率及传输距离。在使用FEC码的数据传输过程中，发送设备可以采用特定的FEC码型对原始数据进行编码之后再将编码后的数据发送给接收设备，接收设备则可以采用同样的FEC码型对接收到的数据进行解码，从而得到原始数据。
在有些场景下，数据在传输过程中可能需要转换FEC码型。例如，为了适应高速率和/或远距离的数据传输当原有数据传输接口采用的原有FEC码型无法满足数据传输的要求时，需要对FEC码型进行转换，使得原有的FEC码型被替换为一种更高增益的FEC码型。但是，FEC码型的转换过程往往会增大数据传输过程的时延以及数据传输设备的功耗，从而影响到数据传输效率。
发明内容
基于此，本申请实施例提供了一种数据传输方法和装置，以简化数据传输时FEC码型的转换过程，从而减小FEC码型转换时所要耗费的时延及设备功耗，提高数据传输效率。
第一方面，本申请实施例提供了一种数据传输方法，包括：第一芯片接收第二芯片发送的第一数据流；所述第一数据流为采用第一前向纠错FEC码型编码的数据流；所述第一芯片对所述第一数据流再进行至少一次编码，得到第二数据流；其中，所述第二数据流为至少采用所述第一FEC码型和第二FEC码型编码的级联FEC码流；所述第一芯片向第三芯片发送所述第二数据流。可见，对于第二芯片向第一芯片发送的采用第一FEC码型编码的第一数据流，第一芯片可以不必先采用第一FEC码型对第一数据流进行解码再将原始数据重新编码成更高增益的FEC码型，而是可以在第一数据流的基础上至少采用第二FEC码型再进行至少一次编码，从而就可以得到至少由第一FEC码型和第二FEC码型级联成的第二数据流，以实现更高的增益。因此，FEC码型的转换过程得以简化，FEC码型转换时所要耗费的时延及设备功耗都得以减小，从而数据传输效率得以提高。
结合第一方面的任何一种实现方式，在第一方面的第一种可能的实现方式中，所述第一FEC码型具体为：RS码、BCH码、Staircase码、LDPC码、Turbo码或TPC。可见，第一芯片可以支持在多种不同的第一FEC码型的基础上编码得到级联FEC码。
结合第一方面的任何一种实现方式，在第一方面的第二种可能的实现方式中，所述第二FEC码型具体为：BCH码、RS码、Staircase码、LDPC码、Turbo码或TPC。可见，第 一芯片可以支持按照多种不同的第二FEC码型在第一FEC码型的基础上编码得到级联FEC码。
结合第一方面的任何一种实现方式，在第一方面的第三种可能的实现方式中，所述第一芯片对所述第一数据流再进行至少一次编码，形成第二数据流，包括：所述第一芯片将所述第一数据流分发成n条第三数据流；其中，所述第一数据流中同一个码字块的数据被分发到不同的所述第三数据流中；所述第一芯片分别对所述多条第三数据流再进行至少一次编码，形成所述第二数据流。可见，第一数据流中同一个码字块中的数据可以被编码到第二数据流中多个不同的码字块中，从而使得级联FEC码具有更强的纠错能力。
结合第一方面的第三种实现方式，在第一方面的第四种可能的实现方式中，从所述第一数据流中识别出来的k个码字块被分发到n条第三数据流中，每一条所述第三数据流中属于所述k个码字块的数据被编码成所述第二数据流中的一个码字块；其中，所述第一数据流中k个码字块所包含的全部数据量与所述第二数据流中n个码字块所包含的有效载荷数据量相等。可见，由于n个第二码字块中的有效载荷即是k个码字块中的全部数据，因此，这n个第二码字块就可以直接按照第二FEC码型和第一FEC码型解码成原始数据，这样便于在同一个芯片上进行第一FEC码型和第二FEC码型的解码操作。
结合第一方面的第三种实现方式，在第一方面的第五种可能的实现方式中，所述第一数据流中的数据按照FEC符号块进行分发，所述第一数据流中同一个FEC符号块的数据被编码在所述第二数据流中的同一个码字块中。可见，第一芯片可以以符号块为粒度对第一数据流进行分发处理。
结合第一方面的第三种实现方式，在第一方面的第六种可能的实现方式中，所述第一数据流中的数据按照比特流进行分发，所述第三数据流中的数据按照比特流进行编码。可见，第一芯片可以以比特为粒度对第一数据流进行分发处理。
结合第一方面的任何一种实现方式，在第一方面的第七种可能的实现方式中，所述第一芯片和所述第二芯片位于第一数据传输设备内，所述第三芯片位于第二数据传输设备内，所述第一芯片为电芯片，所述第二芯片为采用以太网接口的器件，所述第三芯片为电芯片。可见，第一数据传输设备可以通过电芯片将采用以太网接口的器件输出的第一FEC码型的第一数据流编码成至少由第一FEC码型和第二FEC码型级联成的第二数据流再发送给第二数据传输设备，从而实现第一数据传输设备与第二数据传输设备之间通过级联FEC码来进行数据传输。
结合第一方面的任何一种可能的实现方式，在第一方面的第八种可能的实现方式中，所述第一数据流在所述第二芯片与所述第一芯片之间通过具有干扰的物理链路进行传输。可见，对于在具有干扰的物理链路中传输时产生了误码的第一数据流，第一芯片可以在不对第一数据流进行解码纠错的情况下直接对第一数据流再进行至少一次编码形成级联的第二数据流。
第二方面，本申请实施例提供了一种数据传输方法，包括：第一芯片接收第二芯片发送的第二数据流；所述第二数据流为至少采用第一FEC码型和第二FEC码型编码的级联FEC码流；所述第一芯片对所述第二数据流进行至少一次解码，形成第一数据流；所述第 一数据流为采用所述第一FEC码型编码的数据流；所述第一芯片向第三芯片发送所述第一数据流。可见，对于第二芯片向第一芯片发送的至少由第一FEC码型和第二FEC码型级联而成的第二数据流，第一芯片可以采用除第一FEC码型之外的其他FEC码型对第二数据流进行解码，形成采用第一FEC码型编码的第一数据流并向第三芯片发送，而不必将第二数据流解码成原始数据之后再重新编码成第一FEC码型的数据流向第三芯片发送。因此，FEC码型的转换过程得以简化，FEC码型转换时所要耗费的时延及设备功耗都得以减小，从而数据传输效率得以提高。
结合第二方面的任何一种可能的实现方式，在第二方面的第一种可能的实现方式中，所述第一FEC码型具体为：RS码、BCH码、Staircase码、LDPC码、Turbo码或TPC。
结合第二方面的任何一种可能的实现方式，在第二方面的第二种可能的实现方式中，所述第二FEC码型具体为：BCH码、RS码、Staircase码、LDPC码、Turbo码或TPC。可见，第一芯片可以支持对多种不同的第二FEC码型进行解码。
结合第二方面的任何一种可能的实现方式，在第二方面的第三种可能的实现方式中，所述第一数据流用于被所述第三芯片按照所述第一FEC码型进行解码。可见，第一芯片可以支持级联FEC码解码后输出多种不同的第一FEC码型。
结合第二方面的任何一种可能的实现方式，在第二方面的第四种可能的实现方式中，所述第二芯片位于第一数据传输设备内，所述第一芯片和所述第三芯片位于第二数据传输设备内，所述第一芯片为电芯片，所述第二芯片为芯片，所述第三芯片为采用以太网接口的器件。可见，对于第一数据传输设备向第二数据传输设备发送的至少由第一FEC码型和第二FEC码型级联而成的第二数据流，第一数据传输设备可以通过电芯片利用第二FEC码型将第二数据流解码成第一FEC码型的第一数据流再发送给采用以太网接口的器件，从而实现第一数据传输设备与第二数据传输设备之间通过级联FEC码来进行数据传输。
结合第二方面的任何一种可能的实现方式，在第二方面的第五种可能的实现方式中，所述第一数据流在所述第一芯片与所述第三芯片之间通过物理介质进行传输。可见，第一芯片可以在不将第二数据流解码成原始数据的情况下采用除第一FEC码型之外的其他FEC码型将第二数据流解码成采用第一FEC码型编码的第一数据流，从而使得第一数据流通过具有干扰的物理介质中传输给第三芯片再由第三芯片对第一数据流进行解码得到原始数据。所述物理介质例如可以是光纤，光波导，电路，空气等。
第三方面，本申请实施例提供了一种应用于第一芯片的数据传输装置，包括接收器、编码器和发送器。其中：接收器，用于接收第二芯片发送的第一数据流；所述第一数据流为采用第一前向纠错FEC码型编码的数据流；编码器，用于对所述第一数据流再进行至少一次编码，得到第二数据流；其中，所述第二数据流为至少采用所述第一FEC码型和第二FEC码型编码的级联FEC码流；发送器，用于向第三芯片发送所述第二数据流。
结合第三方面的任何一种实现方式，在第三方面的第一种可能的实现方式中，所述第一FEC码型具体为：RS码、BCH码、Staircase码、LDPC码、Turbo码或TPC。
结合第三方面的任何一种实现方式，在第三方面的第二种可能的实现方式中，所述第二FEC码型具体为：BCH码、RS码、Staircase码、LDPC码、Turbo码或TPC。
结合第三方面的任何一种实现方式，在第三方面的第三种可能的实现方式中，所述编码器，具体用于：将所述第一数据流分发成n条第三数据流；其中，所述第一数据流中同一个码字块的数据被分发到不同的所述第三数据流中；分别对所述多条第三数据流再进行至少一次编码，形成所述第二数据流。
结合第三方面的第三种实现方式，在第三方面的第四种可能的实现方式中，从所述第一数据流中识别出来的k个码字块被分发到n条第三数据流中，每一条所述第三数据流中属于所述k个码字块的数据被编码成所述第二数据流中的一个码字块；
其中，所述第一数据流中k个码字块所包含的全部数据量与所述第二数据流中n个码字块所包含的有效载荷数据量相等。
结合第三方面的第三种实现方式，在第三方面的第五种可能的实现方式中，所述第一数据流中的数据按照FEC符号块进行分发，所述第一数据流中同一个FEC符号块的数据被编码在所述第二数据流中的同一个码字块中。
结合第三方面的第三种实现方式，在第三方面的第六种可能的实现方式中，所述第一数据流中的数据按照比特流进行分发，所述第三数据流中的数据按照比特流进行编码。
结合第三方面的任何一种实现方式，在第三方面的第七种可能的实现方式中，所述第一芯片和所述第二芯片位于第一数据传输设备内，所述第三芯片位于第二数据传输设备内，所述第一芯片为电芯片，所述第二芯片为采用以太网接口的器件，所述第三芯片为电芯片。
结合第三方面的任何一种可能的实现方式，在第三方面的第八种可能的实现方式中，所述第一数据流在所述第二芯片与所述第一芯片之间通过物理介质进行传输。可见，对于在具有干扰的物理介质中传输时产生了误码的第一数据流，第一芯片可以在不对第一数据流进行解码纠错的情况下直接对第一数据流再进行至少一次编码形成级联的第二数据流。
可以理解的是，第三方面提供的数据传输装置，对应于第一方面提供的数据传输方法，故第二方面提供的数据传输装置的各种可能的实现方式的技术效果，可以参照前述第一方面提供的数据传输方法的介绍。
第四方面，本申请实施例提供了一种应用于第一芯片的数据传输装置，包括接收器、解码器和发送器。其中：接收器，用于接收第二芯片发送的第二数据流；所述第二数据流为至少采用第一FEC码型和第二FEC码型编码的级联FEC码流；解码器，用于对所述第二数据流进行至少一次解码，形成第一数据流；所述第一数据流为采用所述第一FEC码型编码的数据流；发送器，用于向第三芯片发送所述第一数据流。
结合第四方面的任何一种可能的实现方式，在第四方面的第一种可能的实现方式中，所述第一FEC码型具体为：RS码、BCH码、Staircase码、LDPC码、Turbo码或TPC。
结合第四方面的任何一种可能的实现方式，在第四方面的第二种可能的实现方式中，所述第二FEC码型具体为：BCH码、RS码、Staircase码、LDPC码、Turbo码或TPC。
结合第四方面的任何一种可能的实现方式，在第四方面的第三种可能的实现方式中，所述第一数据流用于被所述第三芯片按照所述第一FEC码型进行解码。
结合第四方面的任何一种可能的实现方式，在第四方面的第四种可能的实现方式中，所述第二芯片位于第一数据传输设备内，所述第一芯片和所述第三芯片位于第二数据传输 设备内，所述第一芯片为电芯片，所述第二芯片为芯片，所述第三芯片为采用以太网接口的器件。
结合第四方面的任何一种可能的实现方式，在第四方面的第五种可能的实现方式中，所述第一数据流在所述第一芯片与所述第三芯片之间通过物理介质进行传输。可见，第一芯片可以在不将第二数据流解码成原始数据的情况下采用除第一FEC码型之外的其他FEC码型将第二数据流解码成采用第一FEC码型编码的第一数据流，从而使得第一数据流通过具有干扰的物理介质中传输给第三芯片再由第三芯片对第一数据流进行解码得到原始数据。
可以理解的是，第四方面提供的数据传输装置，对应于第二方面提供的数据传输方法，故第四方面提供的数据传输装置的各种可能的实现方式的技术效果，可以参照前述第二方面提供的数据传输方法的介绍。
第五方面，本申请实施例还提供了一种通信方法，该通信方法包括：前述第一方面任意一种实现方式所述的数据传输方法，以及，前述第二方面任意一种实现方式所述的数据传输方法。
第六方面，本申请实施例还提供了一种通信系统，该通信系统包括：前述第三方面任意一种实现方式所述的数据传输装置，以及，前述第四方面任意一种实现方式所述的数据传输装置。
第七方面，本申请实施例还提供了一种网络设备，该网络设备包括前述第三方面任意一种实现方式所述的数据传输装置。
第八方面，本申请实施例还提供了一种网络设备，该网络设备包括前述第四方面任意一种实现方式所述的数据传输装置。
第九方面，本申请实施例还提供了一种计算机程序产品，当其在计算机上运行时，使得计算机执行前述第一方面中任意一种实现方式所述的数据传输方法或前述第二方面任意一种实现方式所述的数据传输方法。
第十方面，本申请实施例还提供了一种计算机可读存储介质，该计算机可读存储介质中存储有指令，当其在计算机或处理器上运行时，使得该计算机或处理器执行前述第一方面中任意一种可能的实现方式中所述的数据传输方法或前述第二方面中任意一种可能的实现方式中所述的数据传输方法。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请中记载的一些实施例，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。
图1为本申请实施例中一种应用场景示例的示意图；
图2为本申请实施例中一种数据传输方法的流程示意图；
图3为本申请实施例中一种数据分发方式示例的示意图；
图4为本申请实施例中一种数据分发方式示例的示意图；
图5为本申请实施例中一种数据分发方式示例的示意图；
图6为本申请实施例中一种数据分发方式示例的示意图；
图7为本申请实施例中一种示例性场景下的网络结构示意图；
图8为本申请实施例中一种数据传输方法的流程示意图；
图9为本申请实施例中一种数据传输方法的流程示意图；
图10为本申请实施例中一种编码方法的流程示意图；
图11为本申请实施例中一种数据传输方法的流程示意图；
图12为本申请实施例中一种数据传输方法的流程示意图；
图13为本申请实施例中一种数据传输方法的结构示意图；
图14为本申请实施例中一种数据传输方法的结构示意图。
具体实施方式
在使用FEC码的数据传输过程中，发送设备可以采用特定的FEC码型对原始数据进行编码之后再将编码得到的FEC码发送给接收设备，接收设备则可以按照同样的FEC码型对接收到的FEC码进行解码，从而得到原始数据。这样，即使传输信道引起了FEC码中某些位置出现误码，接收设备通过解码时根据FEC码中的校验位进行逆向计算，也可以得到误码前的原始数据，从而实现纠错功能。
在有些场景下，数据在传输过程中可能需要转换FEC码型。例如，作为一种增强型的FEC码型，级联FEC码采用一种或多种基础的FEC码型进行码型构造形成多级FEC编码，从而能够对传输数据提供更强的纠错保护。因此，设备间可以采用级联FEC码传输数据，以应对数据在进行高速率或远距离传输时被引入的噪声。但是，设备的原有数据传输接口所采用的原有FEC码型是标准规定的码型，如许多设备原有的以太网接口仅支持里德-所罗门(英文：Reed-Solomon，简称：RS)码。当设备应用于比标准规定的速率更高或者距离更远的数据传输场景时，标准规定的FEC码型往往无法满足要求。因此，该设备就需要将要传输的数据从原有FEC码型转换成增益更高的FEC码。通常，在转换FEC码型时，采用原FEC码型编码的数据需要被解码成原始数据，然后再采用新FEC码型对原始数据进行编码。但这样的转换过程不仅会给数据传输设备带来额外的功耗，而且也会增大数据传输过程的时延。
为了解决上述问题，在本申请实施例中，两个芯片之间传输数据时，由于级联FEC码是一种能够为高速率和/或远距离的数据传输提供高增益的FEC码型且级联FEC码是由多级FEC码型级联而成的，当接收到采用第一FEC码型编码的第一数据流时，芯片可以不必先对第一数据流进行第一FEC码型的解码再将原始数据重新编码成级联FEC码，而是可以在第一数据流的基础上至少采用第二FEC码型再进行至少一次编码，从而就可以得到至少由第一FEC码型和第二FEC码型级联成的第二数据流，以获得更高的增益。因此，FEC码型的转换过程得以简化，FEC码型转换需要耗费的时延及设备功耗都得以减小，从而数据传输效率得以提高。
举例说明，本申请实施例可以应用到如图1所示的场景中。数据传输设备101中设置有芯片103和芯片105，数据传输设备102中设置有芯片107和芯片109。假设芯片103和芯片109都是支持第一FEC码型，但数据传输设备101与数据传输设备102之间的信道106需要采用级联FEC码进行数据传输，则芯片103可以采用第一FEC码型对原始数据进行编码而形成第一数据流，并通过信道104将第一数据流发送给芯片105。芯片105在接收到第一数据流之后，可以至少采用第二FEC码型对第一数据流再进行至少一次编码，得到至少由第一FEC码型和第二FEC码型级联成的第二数据流，并通过信道106将第二数据流发送给芯片107。芯片107在接收到第二数据流之后，可以至少采用第二FEC码型对第二数据流进行至少一次解码，得到采用第一FEC码型编码的第一数据流，并通过信道108将第一数据流发送给芯片109。芯片109在接收到第一数据流之后，可以采用第一FEC码型对第一数据流进行解码，得到原始数据。其中，第一FEC码型可以是以太网接口支持的RS码等FEC码型，第二FEC码型可以是博斯-乔赫里-霍克文黑姆(英文：Bose-Chaudhuri-Hocquenghem，简称：BCH)码等码型。需要说明的是，信道104、信道106和信道108均可以是具有干扰的物理链路，数据流在信道104、信道106和信道108中传输时均会产生误码。也就是说，芯片103向芯片105发送的第一数据流在信道104中传输时会产生误码，芯片105向芯片107发送的第二数据流在信道106中传输时会再产生误码，芯片107向芯片109发送的第一数据流在信道108中传输时会再产生误码。
在本申请中，“物理介质”和“物理链路”经常交替使用，本领域技术人员可以理解，它们都指代相同的含义。
可以理解的是，上述场景仅是本申请实施例提供的一个场景示例，本申请实施例并不限于此场景。
下面结合附图，通过实施例来详细说明本申请实施例中一种数据传输方法和装置的具体实现方式。
图2为本申请实施例中一种数据传输方法200的流程示意图。该方法例如可以包括：
201、芯片1接收芯片2发送的第一数据流；所述第一数据流为采用第一前向纠错FEC码型编码的数据流。
具体实现时，芯片2可以采用第一FEC码型对原始数据进行编码，形成第一数据流并向芯片1发送。因此，芯片1接收到的第一数据流是已采用第一FEC码型编码的数据流，换言之，第一数据流是由第一FEC码型的码字块(英文：codeword)组成的码流。
其中，第一FEC码型可以是RS码、BCH码、阶梯(英文：Staircase)码、低密度奇偶校验(英文：low-density parity-check，简称：LDPC)码、涡轮(英文：Turbo)码、涡轮乘积码(英文：Turbo product code，简称：TPC)等码型。例如，在一种示例性的场景中，假设芯片2采用以太网接口与芯片1进行通信，则第一FEC码型可以是RS码。
可以理解的是，在第一FEC码型的码字块中包含有为原始数据提供的额外的校验码(英文：parity code)，该校验码用于对数据传输过程中产生的误码进行纠错。例如，第一FEC 码型可以是系统FEC码(英文：systematic FEC)，也即，第一FEC码型的码字块可以包括原始数据和为该原始数据提供的校验码。
其中，第一FEC码型的码字块可以基于有限域进行处理。码字块可以划分成多个FEC符号(英文：symbol)块，针对码字块的处理可以是以FEC符号块为粒度。例如，在一种RS码中，一个5440比特的码字块中包括5140比特的原始数据和300比特的校验码。若采用伽罗华域(英文：Galois Field，简称：GF)(210)进行处理，每10比特数据形成一个FEC符号块，则一个码字块包括544个FEC符号块，即514个FEC符号块的原始数据和30个FEC符号块的校验码。又如，在另一种RS码中，一个5280比特的码字块中包括5140比特的原始数据和140比特的校验码。若采用GF(210)域进行处理，每10比特数据形成一个FEC符号块，则一个码字块包括528个FEC符号块，即514个FEC符号块的原始数据和14个FEC符号块的校验码。可以理解的是，对于连续发生的误码(英文：consecutive errors)或称突发误码(英文：burst errors)，连续多比特的误码仅会体现为少量FEC符号块的误码，因此，采用FEC符号块为粒度对FEC码字块进行处理时FEC的纠错能力更强。
可以理解的是，芯片1和芯片2是两个不同的芯片，两者之间可以通过具有干扰的物理链路来传输数据，因此，芯片2向芯片1发送的第一数据流在该物理链路上传输时会受到干扰的影响而产生误码，可见，芯片1接收到的第一数据流是已经产生了误码的数据流。
202、所述芯片1对所述第一数据流再进行至少一次编码，得到第二数据流；其中，所述第二数据流为至少采用所述第一FEC码型和第二FEC码型编码的级联FEC码流。
具体实现时，对于采用第一FEC码型编码的第一数据流，芯片1可以不必采用第一FEC码型将第一数据流解码成原始数据，而是可以在第一数据流的基础上至少采用第二FEC码型再进行至少一次编码，从而形成至少由第一FEC码型和第二FEC码型级联而成的第二数据流。换言之，第二数据流可以是级联了第一FEC码型和第二FEC码型的级联FEC码流，即第二数据流是两级级联的FEC码流，或者，第二数据流也可以在第一FEC码型和第二FEC码型级联的基础上再级联一级或多级的级联FEC码流，即第二数据流是三级或三级以上级联的FEC码流。可以理解的是，若芯片2通过具有干扰的物理链路向芯片1发送的第一数据流，芯片1接收到的第一数据流是已经产生了误码的数据流，因此，芯片1是在不对已经产生了误码的第一数据流进行解码的情况下直接对已经产生了误码的第一数据流再进行至少一次编码，形成多级FEC级联的第二数据流。
其中，第二FEC码型可以是BCH码、RS码、Staircase码、LDPC码、Turbo码、TPC等码型。可以理解的是，第二FEC码型可以与第一FEC码型相同，或者，第二FEC码型可以与第一FEC码型不同。例如，第一FEC码型和第二FEC码型都可以是RS码，或者，第一FEC码型可以是RS码而第二FEC码型可以是BCH码。
需要说明的是，第二数据流是由最后一级编码所采用的FEC码型的码字块组成的码流。例如，若第二数据流是由第一FEC码型和第二FEC码型级联而成的数据流，第一级采用第一FEC码型编码，第二级采用第二FEC码型编码，则第二数据流是由第二FEC码型的码字块组成的码流。由于第二数据流是在第一数据流的基础上采用第二FEC码型编码得到的， 在第二FEC码型的码字块中包含有为第一数据流提供的额外的校验码。若第二FEC码型为系统码，则第二FEC码型的码字块包括第一数据流中的数据和为该数据提供的校验码。
在一些实施方式中，为了使得纠错能力更强，第一数据流中同一个码字块中的数据可以被编码到第二数据流中多个不同的码字块中，这样即使第二数据流中的少部分码字块不能正确解码，也不会影响第一数据流中的码字块正确解码。具体实现时，芯片1可以通过分发的方式，将第一数据流分发到n个不同的通道上，形成n条第三数据流，从而使得第一数据流中同一个码字块的数据被分发到多条不同的第三数据流中，其中n表示大于1的自然数。然后，芯片1可以分别对n条通道上的第三数据流再进行至少一次编码，形成第二数据流。例如，在图3的示例中，第一FEC码字块为第一数据流中的一个码字块，该码字块中的数据被分发到n条通道上的第三数据流中，每条通道上的第三数据流分别被编码成第二FEC码字块，形成n条第二FEC码流，这n条第二FEC码型的码流组成了第二数据流。其中，第一FEC码字块表示采用第一FEC码型编码得到的码字块，第二FEC码字块表示采用第二FEC码型编码得到的码字块，第二FEC码流表示由第二FEC码字块组成的数据流。
可以理解的是，第一数据流可以是一条通道上的数据流，也可以是由多条通道上的数据流组成，也即，第一数据流可以是一条码流，也可以是由多条码流组成。
若第一数据流是一条通道上的数据流，则第一数据流被分发成第三数据流，相当于一条数据流被分发成多条数据流。例如，在图4所示的示例中，假设n是大于1的自然数，第一数据流是一条通道上的第一FEC码流，经过分发处理之后形成n条通道上的第三数据流，每条通道上的第三数据流分别被编码成一条第二FEC码流，这n条FEC码流组成了第二数据流。其中，第一FEC码流表示由第一FEC码字块组成的数据流，第一FEC码字块表示采用第一FEC码型编码得到的码字块，第二FEC码流表示由第二FEC码字块组成的数据流，第二FEC码字块表示采用第二FEC码型编码得到的码字块。
若第一数据流是由多条通道上的数据流组成，则从第一数据流到第三数据流的分发相当于从多条数据流到多条数据流的分发，这种分发可以通过交织(英文：interleave)技术和/或复用(英文：multiplex)技术等分发策略来实现。例如，在图5所示的示例中，假设k、m和n均为大于1的自然数，第一数据流是由k条通道上的第一FEC码流组成，经过交织器(英文：interleaver)之后可以形成m条通道上的第四数据流，再经过比特复用器(英文：bit multiplexer)或符号复用器(英文：symbol multiplexer)等复用器之后可以形成n条通道上的第三数据流，每条通道上的第三数据流再分别被编码成一条第二FEC码流，这n条FEC码流组成了第二数据流。其中，第一FEC码流表示由第一FEC码字块组成的数据流，第一FEC码字块表示采用第一FEC码型编码得到的码字块，第二FEC码流表示由第二FEC码字块组成的数据流，第二FEC码字块表示采用第二FEC码型编码得到的码字块。
需要说明的是，多种分发方式可以用于将第一数据流分发成n条第三数据流。
作为一种示例，芯片1可以以比特为粒度对第一数据流进行分发处理，也即，第一数据流中的数据可以按照比特流被分发到n条第三数据流中。具体实现时，芯片1可以从第 一数据流中获取一比特的数据，并根据分发策略从n条通道中为该数据选择一条通道，从而将该数据分发到该条通道上的第三数据流中。相应地，芯片1也可以以比特为粒度对第三数据流进行编码处理，也即，第三数据流中的数据可以按照比特流进行编码。
作为另一种示例，芯片1可以以FEC符号块为粒度对第一数据流进行分发处理，也即，第一数据流中的数据可以按照FEC符号流进行分发。具体实现时，芯片1可以从第一数据流中识别出一个FEC符号块，并根据分发策略从n条通道中为该FEC符号块选择一条通道，从而将该FEC符号块分发到该条通道上的第三数据流中。相应地，芯片1也可以以FEC符号块为粒度对第三数据流进行编码。具体实现时，芯片1可以从第三数据流中识别出一定数量的FEC符号块并编码到第二数据流中的同一个码字块中，因此，第一数据流中同一个FEC符号块的数据会被编码在第二数据流中的同一个码字块中。其中，FEC符号块可以通过对齐标记(英文：alignment marker，简称：AM)来进行识别。
作为又一种示例，芯片1可以以多个码字块为粒度对第一数据流进行分发处理。具体实现时，芯片1可以从第一数据流中识别出多个码字块，并按照分发策略将这多个码字块的数据分发到n条通道上的第三数据流中。其中，分发策略例如可以通过交织(英文：interleave)技术和/或多路复用(英文：multiplexer)技术来实现。此外，所述第一数据流可以是一条码流，即所述多个码字块可以是从一条码流中识别出的，或者，所述第一数据流可以是由多条码流组成，即所述k个码字块可以是从多条码流中识别出的，例如，所述第一数据流由k条码流组成，所述多个码字块可以是通过从每条码流中分别识别出一个码字块而得到的k个码字块。
为了便于第二数据流在同一芯片上解码成原始数据，芯片1可以将第一数据流中的k个码字块的全部数据作为第二数据流中的n个码字块的有效载荷，使得第一数据流中的k个码字块被编码成第二数据流中的n个码字块。具体实现时，芯片1可以从第一数据流中识别出k个码字块，并按照分发策略将这k个码字块的数据分发到n条通道上的第三数据流中。这k个码字块被分发到每条通道上的数据可以分别被编码成第二数据流中的一个码字块，从而在n条通道上编码得到第二数据流中的n个码字块。例如，在图6所示的示例中，假设k、m和n均为大于1的自然数，从第一数据流中识别出的k个第一FEC码字块被输入到交织器(英文：interleaver)中，交织器输出到m条通道上的数据再被输入到比特复用器(英文：bit multiplexer)或符号复用器(英文：symbol multiplexer)等复用器中，复用器则输出n条通道上的数据，每条通道上的数据再分别被编码成一个第二FEC码字块，从而得到了第二数据流中的n个第二FEC码字块。其中，第一FEC码字块表示采用第一FEC码型编码得到的码字块，可以通过AM来从第一数据流中进行识别。第二FEC码字块表示采用第二FEC码型编码得到的码字块。
其中，为了使得第一数据流中的k个码字块能够被编码成第二数据流中的n个码字块，第一数据流的k个码字块的全部数据量需要与第二数据流的n个码字块的有效载荷数据量相等。例如，假设第一数据流为RS码流且第二数据流为BCH码流，第一数据流的RS码字块包括5140比特的有效载荷和300比特的校验码，第二数据流的BCH码字块包括340比特的有效载荷和20比特的校验码，可见，4个RS码字块的全部数据量是21760比特， 64个BCH码字块的有效载荷数据量也是21760比特，因此，第一数据流的4个RS码字块可以被编码成第二数据流的64个BCH码字块。
203、所述芯片1向芯片3发送所述第二数据流。
芯片3在接收到第二数据流之后，可以对所述第二数据流进行解码。这样就实现了芯片1与芯片3之间采用级联FEC码来传输数据。
作为一种示例，芯片3可以对所述第二数据流中包括第一FEC码型和第二FEC码型在内的所有FEC码型进行解码，从而得到原始数据。作为另一种示例，芯片3可以对所述第二数据流中除第一FEC码型之外的其他FEC码型进行解码，得到第一数据流并向芯片4，芯片4再对第一数据流中的第一FEC码型进行解码，从而得到原始数据。可以理解的是，芯片1和芯片3是两个不同的芯片，两者之间可以通过具有干扰的物理链路来传输数据。同样的，芯片3和芯片4是两个不同的芯片，两者之间可以通过物理链路来传输数据。因此，芯片1向芯片3发送的第二数据流在物理链路上传输时，会受到所述物理链路的干扰而产生误码，芯片3是在没有将已经产生了误码的第二数据流解码纠错成原始数据的情况下将级联FEC的第二数据流解码成采用第一FEC码型编码的第一数据流并发送给芯片4，芯片3向芯片4发送的第一数据流在物理链路上传输时会再受到干扰的影响而产生误码，从而芯片4将第一数据解码纠错成原始数据，可见，芯片1接收到的第一数据流是已经产生了误码的数据流。
其中，对于第二数据流中级联FEC码，每一级FEC码型的解码可以通过识别该级FEC码型的码字块并对识别出的码字块进行逆向计算来实现。例如，若第二数据流是由第一FEC码型和第二FEC码型级联而成的，则对第二数据流进行解码时，可以通过AM或自同步技术等方式从第二数据流中识别出第二FEC码型的码字块，对第二FEC码型的码字块进行逆向计算，从而得到第一数据流，然后，可以通过第二FEC码型的码字块与第一FEC码型的码字块之间的固定映射关系或AM等方式从第一数据流中识别出第一FEC码型的码字块，对第一FEC码型的码字块进行逆向计算，从而得到原始数据。
在一种示例性的场景中，如图7所示，芯片1和芯片2可以是位于第一数据传输设备内的两个芯片，芯片3和芯片4可以是位于第二数据传输设备内的一个芯片。第一数据传输设备与第二数据传输设备之间需要采用级联FEC码来传输数据，但芯片2和芯片4仅支持第一FEC码型而不支持级联FEC码，因此，芯片1对芯片2输出的数据流再进行编码形成级联FEC码流并发送给芯片3，芯片将级联FEC码流解码成第一FEC码型的数据流再输出给芯片4，这样芯片1与芯片3之间就可以通过级联FEC码来传输数据，从而实现了第一数据传输设备与第二数据传输设备之间通过级联FEC码来传输数据。其中，芯片1可以是电芯片，例如可以是中继电芯片或光模块的电芯片，如数字信号处理(英文：Digital Signal Processing，简称：DSP)芯片。芯片2可以为采用以太网接口的芯片，如物理(英文：physical，简称：PHY)层芯片。芯片3可以是电芯片，例如可以是中继电芯片或光模块的电芯片，如DSP芯片。芯片4可以为采用以太网接口的芯片，如物理(英文：physical，简称：PHY)层芯片。
需要说明的是，本实施例提供的级联FEC码在仿真验证中达到了较好的纠错效果。假设在图7所示的示例性场景中进行仿真验证，在芯片2与芯片1之间的信道、芯片1与芯片3之间的信道以及芯片3与芯片4之间的信道中插入加性高斯白噪声(英文：Additive White Gaussian Noise，简称：AWGN)，从而形成仿真环境。在该仿真环境下：芯片2向芯片1发送第一FEC码型的数据流，芯片1将第一FEC码型的数据流转换成级联FEC码流再发送给芯片3，芯片3将级联FEC码流转换成第一FEC码型的数据流再发送给芯片4。此时，芯片4能够对接收到的第一FEC码型的数据流正确解码；芯片2向芯片1发送第一FEC码型的数据流，芯片1将第一FEC码型的数据流直接发送给芯片3，芯片3将第一FEC码型的数据流直接发送给芯片4，此时，芯片4无法对接收到的第一FEC码型的数据流正确解码。
在上述仿真环境中进行的仿真验证，结果表明：与芯片1先对第一FEC码型的码流进行解码再进行多级编码形成的级联FEC码流相比，芯片1在不对第一FEC码型的码流进行解码的情况下采用第二FEC码型对第一FEC码型的码流再进行一次编码而形成的级联FEC码流，不仅能够节省60至100ns的时延，而且也能够达到9dB以上的净编码增益(英文：net coding gain，简称：NCG)。
在本实施例中，对于芯片2向芯片1发送的采用第一FEC码型编码的第一数据流，芯片1可以不必先采用第一FEC码型对第一数据流进行解码再将原始数据重新编码成级联FEC码，而是可以在第一数据流的基础上至少采用第二FEC码型再进行至少一次编码，从而就可以得到至少由第一FEC码型和第二FEC码型级联成的第二数据流。因此，FEC码型的转换过程得以简化，FEC码型转换时所要耗费的时延及设备功耗都得以减小，从而数据传输效率得以提高。
图8为本申请实施例中一种数据传输方法800的流程示意图。该方法例如可以包括：
801、芯片3接收芯片1发送的第二数据流；所述第二数据流为至少采用第一FEC码型和第二FEC码型编码的级联FEC码流；
802、所述芯片3对所述第二数据流进行至少一次解码，形成第一数据流；所述第一数据流为采用所述第一FEC码型编码的数据流；
803、所述芯片3向芯片4发送所述第一数据流。
芯片4在接收到第一数据流之后，可以按照第一FEC码型对第一数据流进行解码，从而得到原始数据。
其中，所述第一FEC码型可以是RS码、BCH码、阶梯码、LDPC码、Turbo码、TPC等码型，所述第二FEC码型可以是BCH码、RS码、Staircase码、LDPC码、Turbo码、TPC等码型。
在一个示例性的场景中，所述芯片1可以位于第一数据传输设备内，所述芯片3和所述芯片4可以位于第二数据传输设备内，所述芯片3和所述芯片1可以为电芯片。例如中继电芯片或光模块的电芯片，所述芯片4可以为采用以太网接口的芯片。
可以理解的是，本实施例对应于第二数据流的解码过程，而图2所示的实施例对应于第二数据流的编码过程，因此，本实施例相关的各种具体实施方式，如第一数据流、第二数据流、第一FEC码型、第二FEC码型、芯片1、芯片3、芯片4等的具体实施方式，均可以参见图2所示的实施例的介绍，即图8对应的实施例的方法为图2对应的实施例所介绍的编码的逆向解码的方案，本领域技术人员可以理解，本申请不再赘述。
在本实施例中，对于芯片1向芯片3发送的至少由第一FEC码型和第二FEC码型级联而成的第二数据流，芯片3可以采用除第一FEC码型之外的其他FEC码型对第二数据流进行解码，形成采用第一FEC码型编码的第一数据流并向芯片4发送，而不必将第二数据流解码成原始数据之后再重新编码成第一FEC码型的数据流向芯片4发送。因此，FEC码型的转换过程得以简化，FEC码型转换时所要耗费的时延及设备功耗都得以减小，从而数据传输效率得以提高。
下面通过一个具体场景示例，介绍本申请实施例提供的数据传输方法在具体场景中的应用示例。在该具体场景示例中，第一数据传输设备包括第一PHY层芯片和第一光模块，第一光模块上具有第一DSP芯片，第二数据传输设备包括第二PHY层芯片和第二光模块，第二光模块上具有第二DSP。第一数据传输设备与第二数据传输设备之间采用级联FEC码传输数据，而第一PHY层芯片和第二PHY层芯片支持RS码但不支持级联FEC码。在该具体场景下，如图9所示，第一数据传输设备与第二数据传输设备之间的数据传输方法900例如可以包括：
901、第一PHY芯片采用RS码对原始数据进行一次编码，形成RS码流。
902、第一PHY芯片向第一DSP发送RS码流。
903、第一DSP采用BCH码对RS码流再进行一次编码，形成BCH码流。
其中，该BCH码流实际上是由RS码与BCH码级联而成的级联FEC码流。
904、第一DSP向第二DSP发送BCH码流。
905、第二DSP采用BCH码对BCH码流进行一次解码，形成RS码流。
906、第二DSP向第二PHY芯片发送RS码流。
907、第二PHY芯片采用RS码对RS码流再进行一次解码，得到原始数据。
在本实施例中，第一DSP可以不必先采用RS码对RS码流进行解码再将原始数据重新编码成级联FEC码流，而是可以在RS码流的基础上采用BCH码再进行一次编码，形成RS码与BCH码级联而成的级联FEC码流，从而使得第一DSP与第二DSP之间可以采用级联FEC码流来传输数据，并且，第二DSP可以不必将级联FEC码流解码成原始数据之后再重新编码成RS码流，而是可以采用BCH码对级联FEC码流进行一次解码来形成RS码流，从而使得第二PHY芯片可以接收到RS码流。因此，FEC码型的转换过程得以简化，FEC码型转换时所要耗费的时延及设备功耗都得以减小，从而数据传输效率得以提高。
图10为本申请实施例中一种编码方法1000的流程示意图。该方法1000用于采用第二FEC码型对第一FEC码型的k个码字块进行编码，形成第二FEC码型的n个码字块。具体地，该方法1000可以包括：
1001、从第一数据流中识别出k个第一码字块。
其中，第一数据流为采用第一FEC码型编码的数据流，因此，第一数据流中的第一码字块为第一FEC码型的码字块。第一码字块可以通过AM来从第一数据流中进行识别
1002、将所述k个第一码字块的数据分发到n条通道上。
其中，分发的策略可以通过交织(英文：interleave)技术和/或多路复用(英文：multiplexer)技术来实现。例如，k个第一FEC码字块可以被输入到交织器(英文：interleaver)中，交织器输出到m条通道上的数据再被输入到比特复用器(英文：bit multiplexer)或符号复用器(英文：symbol multiplexer)等复用器中，复用器则输出n条通道上的数据。
1003、在每条通道上，采用第二FEC码型对从所述k个第一码字块中分到的数据进行编码，形成一个第二码字块，从而在n条通道上得到第二数据流中的n个第二码字块。
其中，在每条通道上，从所述k个第一码字块的数据是作为有效载荷被编码到一个第二码字块中的，也即，该第二码字块的有效载荷即是该条通道上从所述k个第一码字块中分到的数据。因此，n条通道上编码出的n个第二码字块的全部有效载荷即是k个第一码字块的全部数据，也就是说，k个第一码字块的全部数据量需要与n个第二码字块的有效载荷数据量相等。
在本实施例中，由于n个第二码字块中的有效载荷即是k个码字块中的全部数据，因此，这n个第二码字块就可以直接按照第二FEC码型和第一FEC码型解码成原始数据，这样便于在同一个芯片上进行第一FEC码型和第二FEC码型的解码操作。
图11为本申请实施例中一种数据传输方法1100的结构示意图。该方法1100包括：
1101、第一芯片接收第二芯片发送的第一数据流；所述第一数据流为采用第一前向纠错FEC码型编码的数据流；
1102、所述第一芯片对所述第一数据流再进行至少一次编码，得到第二数据流；其中，所述第二数据流为至少采用所述第一FEC码型和第二FEC码型编码的级联FEC码流。
在一些可能的实现方式中，所述第一FEC码型具体为：RS码、BCH码、Staircase码、LDPC码、Turbo码或涡轮乘积码TPC。
在一些可能的实现方式中，所述第二FEC码型具体为：BCH码、RS码、Staircase码、LDPC码、Turbo码或TPC。
在一些可能的实现方式中，所述第一芯片对所述第一数据流再进行至少一次编码，形成第二数据流，包括：
所述第一芯片将所述第一数据流分发成n条第三数据流；其中，所述第一数据流中同一个码字块的数据被分发到不同的所述第三数据流中；
所述第一芯片分别对所述多条第三数据流再进行至少一次编码，形成所述第二数据流。
在一些可能的实现方式中，从所述第一数据流中识别出来的k个码字块被分发到n条第三数据流中，每一条所述第三数据流中属于所述k个码字块的数据被编码成所述第二数据流中的一个码字块；
其中，所述第一数据流中k个码字块所包含的全部数据量与所述第二数据流中n个码字块所包含的有效载荷数据量相等。
在一些可能的实现方式中，所述第一数据流中的数据按照FEC符号块进行分发，所述第一数据流中同一个FEC符号块的数据被编码在所述第二数据流中的同一个码字块中。
在一些可能的实现方式中，所述第一数据流中的数据按照比特流进行分发，所述第三数据流中的数据按照比特流进行编码。
在一些可能的实现方式中，所述第一芯片和所述第二芯片位于同一数据传输设备内，所述第一芯片为电芯片，所述第二芯片为采用以太网接口的芯片。
可以理解的是，第一芯片即是数据传输方法200中提及的芯片1，第二芯片即是数据传输方法200中提及的芯片2，第三芯片即是数据传输方法中提及的芯片3，因此，本实施例中第一芯片、第二芯片、第三芯片执行操作的各种具体实施例方式，可以参见图2所示的数据传输方法200中对芯片1、芯片2、芯片3的介绍，本实施例不再赘述。
在本实施例中，对于芯片2向芯片1发送的采用第一FEC码型编码的第一数据流，芯片1可以不必先采用第一FEC码型对第一数据流进行解码再将原始数据重新编码成级联FEC码，而是可以在第一数据流的基础上至少采用第二FEC码型再进行至少一次编码，从而就可以得到至少由第一FEC码型和第二FEC码型级联成的第二数据流。因此，FEC码型的转换过程得以简化，FEC码型转换时所要耗费的时延及设备功耗都得以减小，从而数据传输效率得以提高。
图12为本申请实施例中一种数据传输方法1200的结构示意图。该方法1200包括：
1201、第一芯片接收第二芯片发送的第二数据流；所述第二数据流为至少采用第一FEC码型和第二FEC码型编码的级联FEC码流；
1202、所述第一芯片对所述第二数据流进行至少一次解码，形成第一数据流；所述第一数据流为采用所述第一FEC码型编码的数据流；
1203、所述第一芯片向第三芯片发送所述第一数据流。
在一些可能的实现方式中，所述第一FEC码型具体为：RS码、BCH码、Staircase码、LDPC码、Turbo码或TPC。
在一些可能的实现方式中，所述第二FEC码型具体为：BCH码、RS码、Staircase码、LDPC码、Turbo码或TPC。
在一些可能的实现方式中，所述第一数据流用于被所述第三芯片按照所述第一FEC码型进行解码。
在一些可能的实现方式中，所述第二芯片位于第一数据传输设备内，所述第一芯片和所述第三芯片位于第二数据传输设备内，所述第一芯片为电芯片，所述第二芯片为电芯片，所述第三芯片为采用以太网接口的芯片。
可以理解的是，第一芯片即是数据传输方法200中提及的芯片3，第二芯片即是数据传输方法200中提及的芯片1，第三芯片即是数据传输方法中提及的芯片4，因此，本实施例中第一芯片、第二芯片、第三芯片执行操作的各种具体实施例方式，可以参见图2所示的数据传输方法200中对芯片3、芯片1、芯片4的介绍，本实施例不再赘述。
在本实施例中，对于第二芯片向第一芯片发送的至少由第一FEC码型和第二FEC码型级联而成的第二数据流，第一芯片可以采用除第一FEC码型之外的其他FEC码型对第二数据流进行解码，形成采用第一FEC码型编码的第一数据流并向第三芯片发送，而不必将第二数据流解码成原始数据之后再重新编码成第一FEC码型的数据流向第三芯片发送。因此，FEC码型的转换过程得以简化，FEC码型转换时所要耗费的时延及设备功耗都得以减小，从而数据传输效率得以提高。
图13为本申请实施例中一种数据传输装置1300的结构示意图。该装置1300为第一芯片，包括：
接收器1301，用于接收第二芯片发送的第一数据流；所述第一数据流为采用第一前向纠错FEC码型编码的数据流；
编码器1302，用于对所述第一数据流再进行至少一次编码，得到第二数据流；其中，所述第二数据流为至少采用所述第一FEC码型和第二FEC码型编码的级联FEC码流。
在一些可能的实现方式中，所述第一FEC码型具体为：RS码、BCH码、Staircase码、LDPC码、Turbo码或TPC。
在一些可能的实现方式中，所述第二FEC码型具体为：BCH码、RS码、Staircase码、LDPC码、Turbo码或TPC。
在一些可能的实现方式中，所述编码器1302，具体用于：
将所述第一数据流分发成n条第三数据流；其中，所述第一数据流中同一个码字块的数据被分发到不同的所述第三数据流中；
分别对所述多条第三数据流再进行至少一次编码，形成所述第二数据流。
在一些可能的实现方式中，从所述第一数据流中识别出来的k个码字块被分发到n条第三数据流中，每一条所述第三数据流中属于所述k个码字块的数据被编码成所述第二数据流中的一个码字块；
其中，所述第一数据流中k个码字块所包含的全部数据量与所述第二数据流中n个码字块所包含的有效载荷数据量相等。
在一些可能的实现方式中，所述第一数据流中的数据按照FEC符号块进行分发，所述第一数据流中同一个FEC符号块的数据被编码在所述第二数据流中的同一个码字块中。
在一些可能的实现方式中，所述第一数据流中的数据按照比特流进行分发，所述第三数据流中的数据按照比特流进行编码。
在一些可能的实现方式中，所述第一芯片和所述第二芯片位于同一数据传输设备内，所述第一芯片为电芯片，所述第二芯片为采用以太网接口的器件。
可以理解的是，图11所示的装置1100即是图2所示的实施例中提及的芯片1，因此，本实施例中装置1100的各种具体实施例方式，可以参见图2所示的实施例对芯片1的介绍，本实施例不再赘述。
在本实施例中，对于第二芯片向第一芯片发送的采用第一FEC码型编码的第一数据流，第一芯片可以不必先采用第一FEC码型对第一数据流进行解码再将原始数据重新编码成级联FEC码，而是可以在第一数据流的基础上至少采用第二FEC码型再进行至少一次编码，从而就可以得到至少由第一FEC码型和第二FEC码型级联成的第二数据流。因此，FEC码型的转换过程得以简化，FEC码型转换时所要耗费的时延及设备功耗都得以减小，从而数据传输效率得以提高。
图14为本申请实施例中一种数据传输装置1400的结构示意图。该装置1400具体为第一芯片，包括：
接收器1401，用于接收第二芯片发送的第二数据流；所述第二数据流为至少采用第一FEC码型和第二FEC码型编码的级联FEC码流；
解码器1402，用于对所述第二数据流进行至少一次解码，形成第一数据流；所述第一数据流为采用所述第一FEC码型编码的数据流；
发送器1403，用于向第三芯片发送所述第一数据流。
在一些可能的实施方式中，所述第一FEC码型具体为：RS码、BCH码、Staircase码、LDPC码、Turbo码或TPC。
在一些可能的实施方式中，所述第二FEC码型具体为：BCH码、RS码、Staircase码、LDPC码、Turbo码或TPC。
在一些可能的实施方式中，所述第一数据流用于被所述第三芯片按照所述第一FEC码型进行解码。
在一些可能的实施方式中，所述第二芯片位于第一数据传输设备内，所述第一芯片和所述第三芯片位于第二数据传输设备内，所述第一芯片为电芯片，所述第二芯片为芯片，所述第三芯片为采用以太网接口的器件。
可以理解的是，图14所示的装置1400即是图2所示的实施例中提及的芯片3，因此，本实施例中装置1400的各种具体实施例方式，可以参见图2所示的实施例对芯片3的介绍，本实施例不再赘述。
在本实施例中，对于芯片1向芯片3发送的至少由第一FEC码型和第二FEC码型级联而成的第二数据流，芯片1可以采用除第一FEC码型之外的其他FEC码型对第二数据流进行解码，形成采用第一FEC码型编码的第一数据流并向芯片3发送，而不必将第二数据流解码成原始数据之后再重新编码成第一FEC码型的数据流向芯片3发送。因此，FEC码型的转换过程得以简化，FEC码型转换时所要耗费的时延及设备功耗都得以减小，从而数据传输效率得以提高。
此外，本申请实施例还提供了一种通信方法，该通信方法包括：前述数据传输方法1100以及前述数据传输方法1200。
此外，本申请实施例还提供了一种通信系统，该通信系统包括前述数据传输装置1300以及前述数据传输装置1400。
此外，本申请实施例还提供了一种网络设备，该网络设备包括前述数据传输装置1300或1400。
此外，本申请实施例还提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行本申请实施例的方法实施例中所述的数据传输方法1100或1200。
此外，本申请实施例还提供了一种计算机可读存储介质，该计算机可读存储介质中存储有指令，当其在计算机或处理器上运行时，使得该计算机或处理器执行如本申请实施例的方法实施例中所述的数据传输方法1100或1200。
本申请实施例中提到的“1”、“2”、“3”、“第一”、“第二”、“第三”等序数词用于对多个对象进行区分，不用于限定多个对象的顺序。
通过以上的实施方式的描述可知，本领域的技术人员可以清楚地了解到上述实施例方法中的全部或部分步骤可借助软件加通用硬件平台的方式来实现。基于这样的理解，本申请的技术方案可以以软件产品的形式体现出来，该计算机软件产品可以存储在存储介质中，如只读存储器(英文：read-only memory，ROM)/RAM、磁碟、光盘等，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者诸如路由器等网络通信设备)执行本申请各个实施例或者实施例的某些部分所述的方法。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于装置实施例而言，由于其基本相似于方法实施例，所以描述得比较简单，相关之处参见方法实施例的部分说明即可。以上所描述的设备及系统实施例仅仅是示意性的，其中作为分离部件说明的模块可以是或者也可以不是物理上分开的，作为模块显示的部件可以是或者也可以不是物理模块，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。本领域普通技术人员在不付出创造性劳动的情况下，即可以理解并实施。
以上所述仅是本申请示例性的实施方式，并非用于限定本申请的保护范围。

Claims (29)

  1. 一种数据传输方法，其特征在于，包括：
    第一芯片接收第二芯片发送的第一数据流；所述第一数据流为采用第一前向纠错FEC码型编码的数据流；
    所述第一芯片对所述第一数据流再进行至少一次编码，得到第二数据流；其中，所述第二数据流为至少采用所述第一FEC码型和第二FEC码型编码的级联FEC码流。
  2. 根据权利要求1所述的方法，其特征在于，所述第一FEC码型具体为：里德-所罗门RS码、博斯-乔赫里-霍克文黑姆BCH码、阶梯Staircase码、低密度奇偶校验LDPC码、涡轮Turbo码或涡轮乘积码TPC。
  3. 根据权利要求1或2所述的方法，其特征在于，所述第二FEC码型具体为：BCH码、RS码、Staircase码、LDPC码、Turbo码或TPC。
  4. 根据权利要求1至3任意一项所述的方法，其特征在于，所述第一芯片对所述第一数据流再进行至少一次编码，形成第二数据流，包括：
    所述第一芯片将所述第一数据流分发成n条第三数据流；其中，所述第一数据流中同一个码字块的数据被分发到不同的所述第三数据流中；
    所述第一芯片分别对所述多条第三数据流再进行至少一次编码，形成所述第二数据流。
  5. 根据权利要求4所述的方法，其特征在于，从所述第一数据流中识别出来的k个码字块被分发到n条第三数据流中，每一条所述第三数据流中属于所述k个码字块的数据被编码成所述第二数据流中的一个码字块；
    其中，所述第一数据流中k个码字块所包含的全部数据量与所述第二数据流中n个码字块所包含的有效载荷数据量相等。
  6. 根据权利要求4所述的方法，其特征在于，所述第一数据流中的数据按照FEC符号块进行分发，所述第一数据流中同一个FEC符号块的数据被编码在所述第二数据流中的同一个码字块中。
  7. 根据权利要求4所述的方法，其特征在于，所述第一数据流中的数据按照比特流进行分发，所述第三数据流中的数据按照比特流进行编码。
  8. 根据权利要求1至7所述的方法，其特征在于，所述第一芯片和所述第二芯片位于同一数据传输设备内，所述第一芯片为电芯片，所述第二芯片为采用以太网接口的芯片。
  9. 一种数据传输方法，其特征在于，包括：
    第一芯片接收第二芯片发送的第二数据流；所述第二数据流为至少采用第一FEC码型和第二FEC码型编码的级联FEC码流；
    所述第一芯片对所述第二数据流进行至少一次解码，形成第一数据流；所述第一数据流为采用所述第一FEC码型编码的数据流；
    所述第一芯片向第三芯片发送所述第一数据流。
  10. 根据权利要求9所述的方法，其特征在于，所述第一FEC码型具体为：RS码、BCH码、Staircase码、LDPC码、Turbo码或TPC。
  11. 根据权利要求9或10所述的方法，其特征在于，所述第二FEC码型具体为：BCH码、RS码、Staircase码、LDPC码、Turbo码或TPC。
  12. 根据权利要求9至11所述的方法，其特征在于，所述第一数据流用于被所述第三芯片按照所述第一FEC码型进行解码。
  13. 根据权利要求9至12所述的方法，其特征在于，所述第二芯片位于第一数据传输设备内，所述第一芯片和所述第三芯片位于第二数据传输设备内，所述第一芯片为电芯片，所述第二芯片为电芯片，所述第三芯片为采用以太网接口的芯片。
  14. 一种数据传输装置，其特征在于，所述装置为第一芯片，包括：
    接收器，用于接收第二芯片发送的第一数据流；所述第一数据流为采用第一前向纠错FEC码型编码的数据流；
    编码器，用于对所述第一数据流再进行至少一次编码，得到第二数据流；其中，所述第二数据流为至少采用所述第一FEC码型和第二FEC码型编码的级联FEC码流。
  15. 根据权利要求14所述的装置，其特征在于，所述第一FEC码型具体为：RS码、BCH码、Staircase码、LDPC码、Turbo码或TPC。
  16. 根据权利要求14或15所述的装置，其特征在于，所述第二FEC码型具体为：BCH码、RS码、Staircase码、LDPC码、Turbo码或TPC。
  17. 根据权利要求14至16任意一项所述的装置，其特征在于，所述编码器，具体用于：
    将所述第一数据流分发成n条第三数据流；其中，所述第一数据流中同一个码字块的数据被分发到不同的所述第三数据流中；
    分别对所述多条第三数据流再进行至少一次编码，形成所述第二数据流。
  18. 根据权利要求17所述的装置，其特征在于，从所述第一数据流中识别出来的k个码字块被分发到n条第三数据流中，每一条所述第三数据流中属于所述k个码字块的数据被编码成所述第二数据流中的一个码字块；
    其中，所述第一数据流中k个码字块所包含的全部数据量与所述第二数据流中n个码字块所包含的有效载荷数据量相等。
  19. 根据权利要求17所述的装置，其特征在于，所述第一数据流中的数据按照FEC符号块进行分发，所述第一数据流中同一个FEC符号块的数据被编码在所述第二数据流中的同一个码字块中。
  20. 根据权利要求17所述的装置，其特征在于，所述第一数据流中的数据按照比特流进行分发，所述第三数据流中的数据按照比特流进行编码。
  21. 根据权利要求14至20所述的装置，其特征在于，所述第一芯片和所述第二芯片位于同一数据传输设备内，所述第一芯片为电芯片，所述第二芯片为采用以太网接口的芯片。
  22. 一种数据传输装置，其特征在于，所述装置为第一芯片，包括：
    接收器，用于接收第二芯片发送的第二数据流；所述第二数据流为至少采用第一FEC码型和第二FEC码型编码的级联FEC码流；
    解码器，用于对所述第二数据流进行至少一次解码，形成第一数据流；所述第一数据流为采用所述第一FEC码型编码的数据流；
    发送器，用于向第三芯片发送所述第一数据流。
  23. 根据权利要求22所述的装置，其特征在于，所述第一FEC码型具体为：RS码、BCH码、Staircase码、LDPC码、Turbo码或TPC。
  24. 根据权利要求22或23所述的装置，其特征在于，所述第二FEC码型具体为：BCH码、RS码、Staircase码、LDPC码、Turbo码或TPC。
  25. 根据权利要求22至24所述的装置，其特征在于，所述第一数据流用于被所述第三芯片按照所述第一FEC码型进行解码。
  26. 根据权利要求22至25所述的装置，其特征在于，所述第二芯片位于第一数据传输设备内，所述第一芯片和所述第三芯片位于第二数据传输设备内，所述第一芯片为电芯片，所述第二模块为芯片，所述第三芯片为采用以太网接口的芯片。
  27. 一种通信系统，其特征在于，包括权利要求14-21任一项所述的数据传输装置以及权利要求22-26任一项所述的数据传输装置。
  28. 一种网络设备，其特征在于，包括权利要求14-21任一项所述的数据传输装置。
  29. 一种网络设备，其特征在于，包括权利要求22-26任一项所述的数据传输装置。
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