WO2024055954A1 - 一种数据处理方法以及数据处理装置 - Google Patents

一种数据处理方法以及数据处理装置 Download PDF

Info

Publication number
WO2024055954A1
WO2024055954A1 PCT/CN2023/118196 CN2023118196W WO2024055954A1 WO 2024055954 A1 WO2024055954 A1 WO 2024055954A1 CN 2023118196 W CN2023118196 W CN 2023118196W WO 2024055954 A1 WO2024055954 A1 WO 2024055954A1
Authority
WO
WIPO (PCT)
Prior art keywords
data stream
channel
data streams
data
sequence
Prior art date
Application number
PCT/CN2023/118196
Other languages
English (en)
French (fr)
Inventor
杨小玲
黄科超
严增超
马会肖
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Publication of WO2024055954A1 publication Critical patent/WO2024055954A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received

Definitions

  • Embodiments of the present application relate to the field of communications, and in particular, to a data processing method and a data processing device.
  • FEC Forward error correction
  • a cascaded FEC transmission solution in which the originating device and the originating processing module are connected through an attachment unit interface (AUI).
  • the originating device performs a first FEC encoding on the data to be transmitted, and sends the first FEC encoded data to the originating end processing module.
  • the originating processing module first performs cascade coding and interleaving on the first FEC encoded data and then performs the second FEC encoding, modulates and maps the second FEC encoded bit sequence to generate a corresponding modulation symbol sequence, and finally uses the generated modulation symbols to The sequence is transmitted to the receiving end through the optical transmission network. After the receiving end demodulates and decodes the received modulation symbol sequence, the information sent by the sending end can be obtained.
  • the originating processing module Since the originating processing module will receive multiple data streams, it must first conduct convolution and interleaving on the multiple data streams, and then perform second FEC encoding on each data stream after convolution and interleaving to obtain multiple second FECs. The encoded bit sequences are then separately modulated and mapped to generate corresponding multiple modulation symbol sequences.
  • a direct detection solution there may be a problem that multiple modulation symbol sequences arrive out of synchronization at the receiving end processing module, thereby increasing the processing complexity of the receiving end processing module.
  • This application provides a data processing method and a data processing device for reducing the processing complexity of the receiving end processing module.
  • this application provides a data processing method, which is applied in the originating processing module.
  • the originating processing module performs channel replacement processing on every R/2 channel data streams from the first channel data stream set and every R/2 channel data streams from the second channel data stream set among the n channel data streams.
  • the n channel data streams are all subjected to the first forward error correction FEC encoding.
  • the data in the first channel data stream set is the same as the data in the second channel data stream set.
  • the data comes from different first FEC codewords.
  • the consecutive a symbols in the channel data stream come from a different first FEC codewords.
  • the consecutive 2a symbols in the first data stream come from 2a different first FEC codewords.
  • n is an integer greater than 1
  • a is an integer greater than 1
  • R is an even number greater than 1 and n is divisible by R;
  • the originating processing module performs volume processing on each of the n first data streams.
  • the product interleaving process obtains n second data streams.
  • the consecutive b symbols in the second data stream come from b different first FEC codewords.
  • b is an integer greater than 1, and b can be evenly divided by a.
  • the originating processing module Perform a second FEC encoding process on each of the n second data streams to obtain n encoded data streams.
  • the n encoded data streams include S encoded data stream sets, and each encoded data stream set includes R codes.
  • the data from the first channel data stream set is The R/2 channel data streams and the R/2 channel data streams from the second channel data stream set are subjected to channel replacement processing, and each channel data stream in the R/2 channel data streams of the first channel data stream set can be Part of the data is replaced with part of the data of each channel data stream in the R/2 channel data streams of the second channel data stream set to obtain R first data streams, so that the data in the same channel data stream is dispersed to Different first data streams.
  • the data streams are respectively subjected to convolution interleaving processing and second FEC coding processing to obtain R coded data streams, and then the aforementioned R coded data streams are interleaved into the same third data stream through the channel. Therefore, the data dispersed into R first data streams through channel replacement is interleaved into the same third data stream through channel interleaving processing. That is to say, even if the data from a certain channel data stream is dispersed to different first data streams through channel replacement, it can still be interleaved into the same third data stream through channel interleaving processing, and then transmitted to the same physical channel. Therefore, the problem of inconsistent transmission delays for the same channel data stream will not be caused, and the end processing module can avoid aligning the channel data stream, effectively reducing the complexity of the end processing module.
  • R 2 or 4.
  • the originating processing module can use any of the following implementation methods to perform channel replacement processing on n channel data streams:
  • the originating processing module can compare each channel data stream from the first channel data stream set and each channel data stream from the second channel data stream set among the n channel data streams.
  • the channel data stream is subjected to channel replacement processing to obtain 2 first data streams, and a total of n first data streams are obtained.
  • the originating processing module can perform channel replacement on channel data stream i and channel data stream i+(n/2) to obtain two first data streams, where i is an integer greater than or equal to 0 and less than n/2.
  • the channel data flow i comes from a channel data flow set (for example, the first channel data flow set), and the channel data flow i+(n/2) comes from another channel data flow set (for example, the second channel data flow set) .
  • the originating processing module can perform channel replacement on channel data stream i and channel data stream i+16 to obtain two first data streams, where 0 ⁇ i ⁇ 16, that is, channel data stream 0 to channel data Stream 15 performs channel replacement with channel data stream 16 to channel data stream 31 respectively to obtain two corresponding first data streams, and a total of 32 data streams are obtained.
  • the originating processing module can process every 2 channel data streams from the first channel data stream set and every 2 channel data streams from the second channel data stream set among the n channel data streams.
  • the channel data streams are subjected to channel replacement processing to obtain 4 first data streams, and a total of n first data streams are obtained.
  • the originating processing module can perform channel replacement on channel data stream i 0 , channel data stream i 1 , channel data stream i 2 , and channel data stream i 3 to obtain four first data streams.
  • any two channel data streams among channel data stream i 0 , channel data stream i 1 , channel data stream i 2 , and channel data stream i 3 come from the first channel data stream set, while the other two channel data streams come from the first channel data stream set.
  • Two-channel data stream collection For example, channel data stream i 0 and channel data stream i 1 come from the first channel data stream set, and channel data stream i 2 and channel data stream i 3 come from the second channel data stream set.
  • the originating processing module can perform channel replacement on channel data stream 0, channel data stream 8, channel data stream 16, and channel data stream 24 to obtain four first data streams.
  • the originating processing module can perform channel replacement on channel data stream 1, channel data stream 9, channel data stream 17, and channel data stream 25 to obtain four first data streams.
  • the originating processing module can perform channel replacement on channel data stream 2, channel data stream 10, channel data stream 18, and channel data stream 26 to obtain four first data streams.
  • the originating processing module can perform channel replacement on channel data stream 3, channel data stream 11, channel data stream 19, and channel data stream 27, to obtain four first data streams.
  • the originating processing module can perform channel replacement on channel data stream 4, channel data stream 12, channel data stream 20, and channel data stream 28 to obtain four first data streams.
  • the originating processing module can perform channel replacement on channel data stream 5, channel data stream 13, channel data stream 21, and channel data stream 29 to obtain four first data streams.
  • the originating processing module can perform channel replacement on channel data stream 6, channel data stream 14, channel data stream 22, and channel data stream 30 to obtain four first data streams.
  • the originating processing module can perform channel replacement on channel data stream 7, channel data stream 15, channel data stream 23, and channel data stream 31 to obtain four first data streams.
  • the originating processing module performs channel interleaving on each q set of coded data streams among the n coded data streams into one third data stream, resulting in a total of m third data streams.
  • any of the following implementation methods can be adopted:
  • the originating processing module can convert the encoded data stream i 0 , the encoded data stream i 1 , the encoded data stream i 0 +(n /2), coded data stream i 1 + (n/2), a total of four coded data streams are channel interleaved into one third data stream, where 0 ⁇ i 0 ⁇ 15, 0 ⁇ i 1 ⁇ 15.
  • the originating processing module performs channel interleaving on each of the 32 encoded data streams, including two encoded data streams, into one third data stream. stream, a total of 8 third data streams are obtained.
  • the originating processing module converts each of the 32 encoded data streams into 4 pieces of encoded data.
  • the coded data stream set of the stream is channel interleaved into one third data stream, and a total of eight third data streams are obtained.
  • the originating processing module can convert the encoded data stream i 0 , the encoded data stream i 1 , the encoded data stream i 2 , and the encoded data stream i 0 , encoded data stream i 1 , encoded data stream i 2 , and Data stream i 3 , coded data stream i 0 +(n/2), coded data stream i 1 +(n/2), coded data stream i 2 +(n/2), and coded data stream i 3 +(n/ 2) Channel interleaving is performed into a third data stream; where, 0 ⁇ i 0 ⁇ 15, 0 ⁇ i 1 ⁇ 15, 0 ⁇ i 2 ⁇ 15, 0 ⁇ i 3 ⁇ 15.
  • the data processing method in this application can also scramble the data, which can facilitate the receiving end processing module to synchronize the second FEC codeword without adding additional redundant information, which is beneficial to reducing the second FEC
  • the probability of codeword mis-synchronization and false lock loss improves the reliability of synchronization.
  • any of the following implementation methods can be used for scrambling:
  • the originating processing module performs channel interleaving on each q set of coded data streams among the n coded data streams into one third data stream, and obtains a total of m third data streams.
  • the method also includes: the originating processing module uses a pseudo-random binary sequence (PRBS) with a length of Q*N bits to scramble the Q consecutive second FEC codewords in each encoded data stream to obtain For the scrambled n coded data streams, N is the length of the second FEC codeword, N is an integer greater than 1, and Q is an integer greater than or equal to 1.
  • PRBS pseudo-random binary sequence
  • Q is an integer greater than or equal to 8 or less than or equal to 16.
  • scrambling is performed on the encoded data stream after the second FEC encoding (ie, inner code encoding), which is beneficial to reducing the probability of erroneous locking and erroneous lock loss of the second FEC codeword.
  • the originating processing module performs channel interleaving on each q set of coded data streams among the n coded data streams into one third data stream.
  • the method It also includes: the originating processing module uses a PRBS sequence with a length of R*q*Q*N bits to scramble the continuous R*q*Q*N bits in each third data stream to obtain the scrambled m The third data stream.
  • the consecutive R*q*Q*N bits in the third data stream are R*q*Q* generated by channel interleaving Q consecutive second FEC codewords in each of the R*q encoded data streams.
  • N bits, N is an integer greater than 1
  • Q is an integer greater than or equal to 1.
  • Q is an integer greater than or equal to 8 or less than or equal to 16.
  • scrambling is performed on the third data stream after channel interleaving, which is beneficial to reducing the probability of false locking and false lock loss of the second FEC codeword.
  • the method before the originating processing module performs a second FEC encoding process on each of the n second data streams to obtain n encoded data streams, the method further includes: the originating processing module uses The PRBS sequence with a length of Q*K bits scrambles Q consecutive second FEC code words in each second data stream to obtain n second data streams after scrambling. K is the consecutive second FEC code.
  • the length of word information bits, K is an integer greater than 1
  • Q is an integer greater than or equal to 1.
  • Q is an integer greater than or equal to 8 or less than or equal to 16.
  • scrambling is performed on the second data stream after convolutional interleaving, which is beneficial to reducing the probability of false locking and false lock loss of the second FEC codeword.
  • the originating processing module processes every R/2 channel data streams from the first channel data stream set and every R/2 channel data streams from the second channel data stream set among the n channel data streams.
  • the method also includes: the originating processing module performs channel reordering on the n channel data streams, so that the n The channel data streams are arranged in a preset order.
  • the method before the originating processing module performs channel reordering on the n channel data streams, the method further includes: the originating processing module performs alignment processing on the n channel data streams, wherein the alignment processing is based on external Alignment processing of code symbols, or alignment processing based on AM sequence.
  • the AM sequence is the AM sequence carried in the channel data stream.
  • each of the n first data streams includes an AM p sequence at an interval of L 1 bits, and the AM p sequence includes 15 bytes; wherein, each first data stream The first 8 bytes of the AM p sequence in the stream are the same as those in the corresponding channel data stream. The first 8 bytes of the AM sequence are the same, and the last 7 bytes of the AM p sequence in each first data stream are different from the last 7 bytes of the AM sequence in the corresponding channel data stream. Different first data The last 7 bytes of the AM p sequence in the stream vary.
  • the originating processing module performs convolution interleaving processing on each of the n first data streams to obtain n second data streams, including: the originating processing module converts each first data stream into Each consecutive T*L 1 symbol in the data stream is polled and input into the p delay lines of the convolutional interleaver in units of d symbols to obtain the second data stream. Each consecutive T*L 1 symbol
  • the first t bits are the AM p sequence.
  • the second data stream contains an AM o sequence every L 2 symbol interval.
  • the AM o sequence is the first d symbols of the AM p sequence.
  • L 2 T*L 1.
  • T*L 1 can Divisible by d*p.
  • the originating processing module performs a second FEC encoding process on each of the n second data streams to obtain n encoded data streams, including: the originating processing module performs a second FEC encoding process on each of the n second data streams.
  • the continuous L 2 symbols in the stream are subjected to the second FEC encoding to obtain c second FEC codewords.
  • the first d symbols of the continuous L 2 symbols are AM o sequences, c is L 2 /K, and K is the continuous second FEC codeword.
  • the length of information bits, K is an integer greater than 1.
  • the encoded data stream or the third data stream can be periodically The occurrence of a known sequence allows the receiving end processing module to use this periodic known sequence to synchronize the inner code.
  • the method further includes: the originating processing module, converting each of the n channel data streams
  • the AM sequence in the channel data stream is replaced by the AM * sequence, and the first 5 bytes of the AM * sequence in different channel data streams are the same.
  • the AM sequence can be replaced by the AM * sequence, which allows the receiving end processing module to use a long enough known sequence to synchronize the inner code, thereby reducing the probability of incorrect synchronization of the inner code and the probability of erroneous lock loss.
  • this application also provides a data processing device, which is located in the originating processing module.
  • the data processing device includes the following functional modules:
  • the channel replacement module is used to perform channel replacement processing on every R/2 channel data streams from the first channel data stream set and every R/2 channel data streams from the second channel data stream set among the n channel data streams.
  • R first data streams are obtained, and a total of n first data streams are obtained.
  • the n channel data streams are all subjected to the first forward error correction FEC encoding.
  • the data in the first channel data stream set is the same as the data in the second channel data stream set.
  • the data comes from different first FEC codewords.
  • the continuous a symbols in the channel data stream come from a different first FEC codewords.
  • the continuous 2a symbols in the first data stream come from 2a different first FEC codes. word, n is an integer greater than 1, a is an integer greater than 1, R is an even number greater than 1 and n can be divided by R;
  • the convolution interleaving module is used to perform convolution and interleave processing on each of the n first data streams to obtain n second data streams.
  • the continuous b symbols in the channel data stream come from b different first data streams.
  • An FEC codeword, b is an integer greater than 1, and b can be evenly divided by a;
  • the FEC encoding module performs a second FEC encoding process on each of the n second data streams to obtain n encoded data streams.
  • the channel interleaving module is specifically used to combine the coded data stream i 0 , the coded data stream i 1 , the coded data stream i 2 , the coded data stream i 3 , and the coded data stream i 0 +(n/2), coded data stream i 1 +(n/2), coded data stream i 2 +(n/2) and coded data stream i 3 +(n/2) are interleaved into one channel
  • the third data stream among them, 0 ⁇ i 0 ⁇ 15, 0 ⁇ i 1 ⁇ 15, 0 ⁇ i 2 ⁇ 15, 0 ⁇ i 3 ⁇ 15.
  • the data processing device further includes a first scrambling module located at the second FEC encoding Between the module and the channel interleaving module; the first scrambling module is used to scramble the Q consecutive second FEC codewords in each encoded data stream using a pseudo-random binary sequence PRBS sequence with a length of Q*N bits. , obtain the scrambled n coded data streams, N is the length of the second FEC codeword, N is an integer greater than 1, and Q is an integer greater than or equal to 1.
  • the data processing device further includes a second scrambling module, the second scrambling module is located after the channel interleaving module; the second scrambling module is used to use a method with a length of R*q*Q*N bits.
  • the PRBS sequence scrambles the continuous R*q*Q*N bits in each third data stream to obtain m third data streams after scrambling.
  • the continuous R*q*Q bits in the third data stream are obtained.
  • *N bits are R*q*Q*N bits generated by channel interleaving of Q consecutive second FEC codewords in R*q encoded data streams.
  • N is an integer greater than 1
  • Q is greater than or equal to 1. integer.
  • the data processing device further includes a third scrambling module, the third scrambling module is located between the convolutional interleaving module and the second FEC encoding module; the third scrambling module is used to use a method with a length of The Q*K bit PRBS sequence scrambles the Q consecutive second FEC codewords in each second data stream to obtain n second data streams after scrambling.
  • K is the continuous second FEC codeword information.
  • the bit length, K is an integer greater than 1
  • Q is an integer greater than or equal to 1.
  • the data processing device before the channel interleaving module, further includes: an alignment processing module, configured to perform alignment processing on n channel data streams based on AM sequences, where the AM sequence is the AM carried in the channel data stream. sequence.
  • each of the n first data streams includes an AM p sequence at an interval of L 1 bits, and the AM p sequence includes 15 bytes; wherein, each first data stream The first 8 bytes of the AM p sequence in the stream are the same as the first 8 bytes of the AM sequence in the corresponding channel data stream. The last 7 bytes of the AM p sequence in each first data stream are the same as the corresponding The last 7 bytes of the AM sequence in the channel data stream are different, and the last 7 bytes of the AM p sequence in different first data streams are different.
  • the convolutional interleaving module is specifically configured to poll and input each consecutive T*L 1 symbol in each first data stream to the convolutional interleaver in units of d symbols.
  • the second data stream is obtained.
  • the first t bits of each consecutive T*L 1 symbol are AM p sequences.
  • the second data stream contains an AM o sequence every L 2 symbols.
  • the FEC encoding module is specifically used to perform second FEC encoding on the consecutive L 2 symbols in each second data stream to obtain c second FEC codewords, the first d of the consecutive L 2 symbols symbols are AM o sequences, c is L 2 /K, K is the length of the second consecutive FEC codeword information bit, and K is an integer greater than 1.
  • the data processing device further includes: an AM sequence processing module, configured to replace the AM sequence in each of the n channel data streams with an AM * sequence in different channel data streams.
  • the first 5 bytes of the AM * sequence are the same.
  • Q is an integer greater than or equal to 8 or less than or equal to 16.
  • this application provides a data processing method, which is applied in the originating processing module.
  • the originating processing module obtains f first data streams.
  • the f first data streams are all subjected to the first forward error correction FEC code.
  • a consecutive data units in the first data stream come from a different first FEC codes. words, each interval of L 2 symbols in each first data stream contains an AM p2 sequence, the length of the AM p2 sequence is Y symbols, and at least the first X symbols of the AM p2 sequences in the f first data streams are the same, The last (YX) symbols are different from each other.
  • f is an integer greater than 1
  • a is an integer greater than 1
  • L 2 is an integer greater than 1
  • X is an integer greater than 1 and less than or equal to a
  • Y is an integer greater than X.
  • the originating end processing module performs convolution and interleaving processing on each consecutive X symbols in each of the f first data streams as a convolutional interleaving block to obtain f second data streams.
  • the interval L 3 symbols contains an AM o2 sequence.
  • the AM o2 sequence is the first X symbols of the AM p2 sequence.
  • L 3 is an integer greater than 1.
  • L 3 can be evenly divided by L 2 .
  • the originating processing module performs the second FEC encoding process on each consecutive K bits in each of the f second data streams as a coding block to obtain f coded data streams. 10 times L 3 can be evenly divided by K. , K is the length of the continuous second FEC codeword information bit, and K is an integer greater than 1.
  • the originating processing module can be aligned with the AM p2 sequence during the convolution interleaving process and with the AM o2 sequence during the inner code encoding process. This can be achieved without adding additional redundant information. Known sequences appear periodically in the second data stream and the encoded data stream, so that the receiving end processing module can use this periodic known sequence to synchronize the inner code, which in turn helps reduce the processing complexity of the receiving end.
  • the originating processing module performs convolution and interleaving processing on each consecutive X symbols in each of the f first data streams as a convolutional interleaving block to obtain f pieces of second data.
  • the originating processing module performs the second FEC encoding process on each K continuous bits in each of the f second data streams as a coding block to obtain f coded data streams, including :
  • the originating processing module performs the second FEC encoding on L 3 consecutive symbols in each second data stream to obtain c second FEC codewords.
  • the first X symbols of the L 3 consecutive symbols are AM o2 sequences, and the c-th
  • the first second FEC codeword among the two FEC codewords includes the AM o2 sequence, c is (L 3 *10)/K, and c is an integer greater than 1.
  • each first data stream is a data stream obtained based on multiplexing of g PCS channel data streams
  • the AM p2 sequence is an AM sequence of g PCS channel data streams that has been multiplexed.
  • the length Y of the AM p2 sequence is g times the length of the AM sequence.
  • the originating processing module obtains f first data streams, including: the originating processing module receives e PMA channel data streams from the connection unit interface AUI, and analyzes the AM p2 in each PMA channel data stream.
  • the sequence performs AM locking to obtain f first data streams, e is the number of physical channels included in the AUI interface, f is equal to e, and each first data stream is multiplexed based on bit granularity based on g PCS channel data streams or A data stream obtained by multiplexing processing based on symbol granularity; wherein, if each of the first data streams is multiplexed based on bit granularity based on the g PCS channel data streams, then the a data unit is a bit; if each of the first data streams is multiplexed based on symbol granularity based on the g PCS channel data streams, then the a data units are a symbols.
  • the originating processing module obtains f first data streams, including: the originating processing module performs a first demultiplexing process on the e PMA channel data streams received from the connection unit interface AUI, and obtains n PCS channel data stream, e is the number of physical channels included in the AUI interface; then, the originating processing module performs AM locking and AM alignment on the n PCS channel data streams, and then processes each g PCS channel data in the n PCS channel data streams.
  • the streams undergo first multiplexing processing to obtain f first data streams, where f is equal to n/g, and f is greater than or equal to e.
  • each PMA channel data stream is a data stream obtained by performing bit-granularity-based multiplexing processing on n/e PCS channel data streams, and the first demultiplexing process is bit-granularity-based.
  • Demultiplexing processing the first multiplexing processing is multiplexing processing based on symbol granularity, and the a data unit is a symbol; or each PMA channel data stream is based on n/e PCS channel data streams.
  • the data stream obtained by multiplexing processing at symbol granularity, the first demultiplexing process is demultiplexing processing based on symbol granularity, the first multiplexing process is multiplexing processing based on symbol granularity, and the a data units are a bits.
  • f 4 or 8 or 16
  • X 2 or 4
  • K 120, 136 or 160.
  • T 2 or 3 or 7
  • p 3 or 4 or 7.
  • g 2 or 4 or 8.
  • this application provides a data processing device, which is located in the originating processing module.
  • the data processing device includes the following functional modules:
  • the receiving and processing module is used to obtain f first data streams.
  • the f first data streams are all encoded by the first forward error correction FEC.
  • a consecutive data units in the first data stream come from a different first FECs.
  • Codewords, each interval of L 2 symbols in each first data stream contains an AM p2 sequence, the length of the AM p2 sequence is Y symbols, and at least the first X symbols of the AM p2 sequences in the f first data streams are the same , the last (YX) symbols are different from each other, f is an integer greater than 1, a is an integer greater than 1, L 2 is an integer greater than 1, X is an integer greater than 1 and less than or equal to a, Y is an integer greater than X .
  • the convolution interleaving module is used to perform convolution and interleave processing on each consecutive X symbols in each of the f first data streams as a convolution interleaving block to obtain f second data streams, and the second data
  • the stream contains an AM o2 sequence every L 3 symbols.
  • the AM o2 sequence is the first X symbols of the AM p2 sequence.
  • L 3 is an integer greater than 1. L 3 can be evenly divided by L 2 .
  • the FEC encoding module is used to perform the second FEC encoding process on each K continuous bits in each of the f second data streams as a coding block to obtain f coded data streams. 10 times L 3 can be K Divisible, K is the length of the continuous second FEC codeword information bit, and K is an integer greater than 1.
  • the convolutional interleaving module is specifically configured to poll and input each consecutive T*L 2 symbols in each first data stream to the convolutional interleaver in units of X symbols. In p delay lines, the second data stream is obtained.
  • the FEC encoding module is specifically used to perform second FEC encoding on L 3 consecutive symbols in each second data stream to obtain c second FEC codewords, L 3 consecutive symbols.
  • each first data stream is a data stream obtained based on multiplexing of g PCS channel data streams
  • the AM p2 sequence is an AM sequence of g PCS channel data streams that has been multiplexed.
  • the length Y of the AM p2 sequence is g times the length of the AM sequence.
  • the reception processing module is specifically configured to receive e PMA channel data streams from the connection unit interface AUI, and perform AM locking on the AM p2 sequence in each PMA channel data stream to obtain f first Data stream, e is the number of physical channels included in the AUI interface, and f is equal to e.
  • Each first data stream is obtained by performing bit-granularity-based multiplexing processing or symbol-granularity-based multiplexing processing based on g PCS channel data streams.
  • the a data unit is a bit; if each of the first data streams If the first data stream is multiplexed based on symbol granularity based on the g PCS channel data streams, then the a data units are a symbols.
  • the reception processing module is specifically configured to perform a first demultiplexing process on e PMA channel data streams received from the connection unit interface AUI to obtain n PCS channel data streams, where e is the AUI interface.
  • f is equal to n/g, and f is greater than or equal to e.
  • each PMA channel data stream is a data stream obtained by performing bit-granularity-based multiplexing processing on n/e PCS channel data streams, and the first demultiplexing process is bit-granularity-based.
  • Demultiplexing processing the first multiplexing processing is multiplexing processing based on symbol granularity, and the a data unit is a symbol; or each PMA channel data stream is based on n/e PCS channel data streams.
  • the data stream obtained by multiplexing processing at symbol granularity, the first demultiplexing process is demultiplexing processing based on symbol granularity, the first multiplexing process is multiplexing processing based on symbol granularity, and the a data units are a bits.
  • f 4 or 8 or 16
  • X 2 or 4
  • K 120, 136 or 160.
  • T 2 or 3 or 7
  • p 3 or 4 or 7.
  • g 2 or 4 or 8.
  • the present application provides a computer-readable storage medium.
  • the computer-readable storage medium stores a computer program, wherein when the computer program is executed by hardware, it can implement any one of the methods of the first aspect or the third aspect. Some or all of the steps.
  • Figure 1 is a schematic diagram of a communication system applied in the embodiment of the present application.
  • FIG 2 is a schematic diagram of a data transmission process in the communication system shown in Figure 1;
  • FIG. 3 is a flow chart of the data processing method in this application.
  • Figure 4 is an example diagram of alignment processing and reordering processing performed by the originating processing module in this application;
  • FIG. 5 is an example diagram of the processing flow of the data processing method in this application.
  • Figure 6 is an example diagram of alignment processing performed by the originating processing module in this application.
  • Figure 7A is an example diagram of channel replacement processing by the originating processing module in this application.
  • Figure 7B is another example diagram of channel replacement processing by the originating processing module in this application.
  • Figure 7C is another example diagram of channel replacement processing by the originating processing module in this application.
  • Figure 7D is another example diagram of channel replacement processing by the originating processing module in this application.
  • Figure 8 is a schematic structural diagram of performing convolution and interleaving on n channel data streams in this application;
  • Figure 9A is an example diagram of the second FEC encoding process performed by the originating processing module in this application.
  • Figure 9B is another example diagram of the second FEC encoding process performed by the originating processing module in this application.
  • Figure 10A is an example diagram of channel interleaving processing performed by the transmitter processing module in this application.
  • Figure 10B is another example diagram of channel interleaving processing performed by the originating end processing module in this application.
  • Figure 10C is another example diagram of channel interleaving processing performed by the transmitter processing module in this application.
  • Figure 10D is another example diagram of channel interleaving processing performed by the transmitter processing module in this application.
  • Figure 10E is another example diagram of channel interleaving processing performed by the transmitter processing module in this application.
  • Figure 10F is another example diagram of channel interleaving processing performed by the transmitter processing module in this application.
  • Figure 10G is another example diagram of channel interleaving processing performed by the transmitter processing module in this application.
  • Figure 10H is another example diagram of channel interleaving processing performed by the transmitter processing module in this application.
  • Figure 11A is another flow chart of the data processing method in this application.
  • Figure 11B is another example diagram of the processing flow of the data processing method in this application.
  • Figure 12A is an example diagram of scrambling processing performed by the originating processing module in this application.
  • Figure 12B is another example diagram of scrambling processing performed by the originating processing module in this application.
  • Figure 13A is another flow chart of the data processing method in this application.
  • Figure 13B is another example diagram of the processing flow of the data processing method in this application.
  • Figure 14A is another flow chart of the data processing method in this application.
  • Figure 14B is another example diagram of the processing flow of the data processing method in this application.
  • Figure 15 is another flow chart of the data processing method in this application.
  • Figure 16 is an example diagram of the AM sequence in the channel data stream in this application.
  • Figure 17 is an example diagram of the originating processing module in this application performing alignment processing and reordering processing based on AM sequences;
  • Figure 18 is an example diagram of the originating processing module in this application performing channel replacement processing based on AM sequences
  • Figure 19 is an example diagram of the transmitter processing module in this application performing convolution and interleaving processing based on AM sequences
  • Figure 20 is another example diagram of the transmitter processing module in this application performing convolution and interleaving processing based on AM sequences
  • Figure 21 is an example diagram of the second FEC encoding process performed by the originating end processing module based on the AM sequence in this application;
  • Figure 22 is an example diagram of the transmitter processing module in this application performing channel interleaving processing based on AM sequences
  • Figure 23 is an example diagram of the AM * sequence in this application.
  • Figure 24 is another example diagram of the AM * sequence in this application.
  • Figure 25 is a schematic diagram of an embodiment of the data processing device in this application.
  • Figure 26 is a schematic diagram of another embodiment of the data processing device in this application.
  • Figure 27 is another flow chart of the data processing method in this application.
  • Figure 28 is an example diagram of the flow of the data processing method in this application.
  • Figure 29A is an example diagram of the implementation of obtaining the first data stream in this application.
  • Figure 29B is another example diagram of the implementation of obtaining the first data stream in this application.
  • Figure 30 is an example diagram of the pattern of the first FEC codeword contained in the first data stream in this application.
  • Figure 31 is an example diagram of multiplexing processing in this application.
  • Figure 32A is an example diagram of a convolutional interleaver involved in the data processing method in this application.
  • Figure 32B is another example diagram of a convolutional interleaver involved in the data processing method in this application.
  • Figure 32C is another example diagram of a convolutional interleaver involved in the data processing method in this application.
  • Figure 33A is an example diagram of convolutional interleaving block delimitation in this application.
  • Figure 33B is another example diagram of dividing convolutional interleaving block delimitation in this application.
  • Figure 33C is another example diagram of dividing convolutional interleaving block delimitation in this application.
  • Figure 34A is an example diagram of the transmitter processing module in this application performing convolutional interleaving processing based on AMP2 sequence alignment;
  • Figure 34B is another example diagram of the transmitter processing module in this application performing convolutional interleaving processing based on AMP2 sequence alignment;
  • Figure 34C is another example diagram of the transmitter processing module in this application performing convolutional interleaving processing based on AMP2 sequence alignment;
  • Figure 35A is another example diagram of the second FEC encoding process performed by the originating processing module in this application based on AM O2 sequence alignment;
  • Figure 35B is another example diagram of the second FEC encoding process performed by the originating processing module in this application based on AM O2 sequence alignment;
  • Figure 35C is another example diagram of the second FEC encoding process performed by the originating end processing module based on AM O2 sequence alignment in this application;
  • Figure 36 is a schematic diagram of another embodiment of the data processing device in this application.
  • Figure 37 is a schematic diagram of another embodiment of the data processing device in this application.
  • FIG 1 is a schematic diagram of a communication system applied in an embodiment of the present application.
  • the communication system includes a sending end device 01, a sending end processing module 02, a channel transmission medium 03, a receiving end processing module 04 and a receiving end device 05.
  • the originating device 01 and the receiving device 05 can be switches or routers, and the originating device 01 is also called the client chip (host chip) located at the originating end, and the receiving device 05 is also called a host chip. It is called the client-side chip located at the receiving end. Client-side chips are sometimes also called client-side devices (host devices).
  • the originating device 01 and the originating processing module 02 can be connected through an attachment unit interface (attachment unit interface, AUI), and the receiving device 05 and the receiving processing module 04 can be connected through the AUI.
  • the sending end processing module 02 and the receiving end processing module 04 can be optical modules, electrical modules, connectors, or other modules that process data during data transmission.
  • the processing module can be an 800G DR module (an 800G direct detection optical module).
  • the channel transmission medium 03 may be an optical fiber.
  • the originating device 01, the originating processing module 02, the channel transmission medium 03, the receiving processing module 04 and the receiving device 05 in the communication system can all support bidirectional transmission or unidirectional transmission, and there are no specific limitations here.
  • Figure 2 is a schematic diagram of a data transmission process in the communication system shown in Figure 1.
  • the originating device 01 is used to encode the data with an outer code, and then transmits the data encoded with the outer code to the originating processing module 02.
  • the originating processing module 02 is used to perform inner code encoding on the outer code encoded data, obtain outer code encoded and inner code encoded data, and transmit the outer code encoded and inner code encoded data to the channel transmission medium 03 .
  • the channel transmission medium 03 is used to transmit the data encoded by the outer code and the inner code to the receiving end processing module 04 .
  • the receiving end processing module 04 is used to perform inner code decoding on the data encoded by the outer code and the inner code, and transmit the inner code decoded data to the receiving end device 05 .
  • the receiving device 05 is used to perform outer code decoding on the data decoded by the inner code.
  • inner in the inner code and outer in the outer code are only distinguished based on the distance of the execution subject that operates on the data relative to the channel transmission medium 03.
  • the execution subject that operates the inner code is closer to the channel transmission medium, and the execution subject that operates the outer code is farther away from the channel transmission medium.
  • the data encoded by the originating device 01 is farther from the channel transmission medium 03 than the data encoded by the originating processing module 02, and the data decoded by the receiving device 05 is farther from the channel transmission medium than the data decoded by the receiving processing module 04. 03 is far away. Therefore, the data encoded by the originating device 01 is called the data encoded by the outer code, the data encoded by the originating processing module 02 is called the data encoded by the inner code, and the data decoded by the receiving device 05 is called the data decoded by the outer code.
  • the data decoded by the receiving processing module 04 is called the data decoded by the inner code.
  • the above-mentioned inner code encoding and outer code encoding adopt FEC encoding, thereby forming a cascaded FEC transmission scheme.
  • the data encoded by the originating device 01 is called the first FEC-encoded data
  • the data encoded by the originating processing module 02 is called the second FEC-encoded data
  • the data decoded by the receiving device 05 is called the data encoded by the first FEC.
  • the data decoded by the first FEC and the data decoded by the receiving processing module 04 are called data decoded by the second FEC.
  • the originating device 01 can use Reed-Solomon codes (RS codes) to perform the first FEC encoding (ie, outer code encoding), and the originating processing module 02 can use Hamming codes to perform the second FEC encoding. (i.e. internal code encoding).
  • RS codes Reed-Solomon codes
  • the originating device 01 can use the RS code to perform the first FEC encoding (that is, the outer code encoding), and the originating processing module 02 can use the Bose-Chaudhuri-Hocquenghem (BCH) code.
  • BCH Bose-Chaudhuri-Hocquenghem
  • this application designs a data processing scheme including "channel replacement” and “channel interleaving corresponding to channel replacement” to achieve better performance of the overall cascaded FEC scheme and reduce the processing at the receiving end. the complexity.
  • the originating processing module mainly performs the following steps:
  • Step 301 Perform channel replacement processing on every R/2 channel data streams from the first channel data stream set and every R/2 channel data streams from the second channel data stream set among the n channel data streams to obtain R For the first data stream, a total of n first data streams are obtained.
  • the channel data stream may be a physical coding sublayer (PCS) channel data stream.
  • the n channel data streams are all data streams encoded by the first FEC, that is, the data streams encoded by the outer code introduced above, where n is an integer greater than 1.
  • the n-channel data streams encoded by the first FEC may include a plurality of first FEC codewords. The consecutive a symbols in each of the aforementioned n channel data streams come from a different first FEC codewords, and a is an integer greater than 1.
  • the data stream may include multiple RS codewords. The consecutive a symbols in each channel data stream come from a different RS codewords, and a is an integer greater than 0.
  • the two consecutive symbols in each channel data stream come from two different first FEC codewords, that is, the 0th symbol and the 1st symbol in a channel data stream come from two different In the first FEC codeword, the first symbol and the second symbol come from two different first FEC codewords, the second symbol and the third symbol come from two different first FEC codewords, and so on.
  • the value of the first FEC code length in this application is calculated in units of symbols, where a symbol may include one or more bits.
  • the first FEC encoding adopts KP4RS (544, 514) code
  • one symbol contains 10 bits.
  • each PCS channel data stream comes from different RS code words, and two adjacent symbols at the same position in two adjacent PCS channel data streams come from different RS code words.
  • the two adjacent symbols in each PCS channel data stream come from different RS code words, and the two adjacent symbols at the same position in the two adjacent PCS channel data streams come from different RS code words; and the PCS channel data stream 0 ⁇
  • the RS codewords contained in 15 are different from the RS codewords contained in PCS channel data streams 16-31, that is, the data in PCS channel data streams 0-15 and the data in PCS channel data streams 16-31 come from different RS codewords.
  • the data flow of 32 PCS channels is processed by the PMA layer of the sending device and then sent to the sending end processing module through the connection unit interface 800GAUI-8.
  • the n-channel data streams are n-channel data streams obtained through processing such as identification lock (alignment lock), channel data alignment, and lane reordering (lane reordering).
  • identification lock alignment lock
  • channel data alignment channel data alignment
  • lane reordering lane reordering
  • the above-mentioned channel data alignment processing may be an AM sequence-based alignment processing.
  • the lane de-skew defined by existing standards makes the data of the n-channel data streams output by it completely aligned.
  • the above-mentioned channel data alignment processing can also be alignment processing based on channel symbols, so that the data on the n channel data streams output are based on foreign code symbol alignment. Specifically, it can be based on one foreign code symbol alignment, or it can be based on Alignment of multiple foreign code symbols.
  • two channel data streams are taken as an example to illustrate the specific operations of the above channel data alignment processing.
  • scenario (a) in Figure 6 shows that the two channel data streams have a deviation of 75 bits.
  • AM0 and AM1 are the alignment identifiers of channel data stream 0 and channel data stream 1 respectively.
  • Scenario (b) in Figure 6 uses channel correction processing defined by existing standards. (lane de-skew), so that there is no deviation between the output channel data stream 0 and the channel data stream 1.
  • Scenario (c) in Figure 6 uses alignment processing based on 1 RS symbol, so that 1 RS symbol of channel data stream 0 and 1 RS symbol of channel data stream 1 after output are aligned. At this time, the two The channel still has a 70-bit offset.
  • Scenario (d) in Figure 6 is an alignment process based on 2 RS symbols, so that the 2 RS symbols of the output channel data stream 0 and the 2 RS symbols of the channel data stream 1 are aligned. At this time There is still a 60-bit offset between the two channels.
  • the "channel data alignment process” is an alignment process based on channel symbols as an example.
  • the "channel data alignment process” is an alignment process based on AM sequences. Examples are introduced.
  • the channel reordering process is to sort n channel data streams according to a preset sorting method.
  • the sorting method can be according to channel data stream 0 to channel data stream n-1. Sort in such a way that the data of any two channel data streams from channel data stream 0 to channel data stream (n/2)-1 come from the same first FEC codeword, and channel data stream n/2 to channel data stream n- The data of any two channel data streams in 1 comes from the same first FEC codeword, and any one channel data stream from channel data stream 0 to channel data stream (n/2)-1 is the same as channel data stream n The data in any one of the channel data streams from /2 to channel data stream n-1 comes from different first FEC codewords.
  • two parts of the channel data streams from different first FEC codewords among the n channel data streams are called two different channel data stream sets.
  • a total of n/2 channel data streams from channel data stream 0 to channel data stream (n/2)-1 are marked as the first channel data stream set
  • a total of n/2 channel data streams from channel data stream n/2 to channel data stream n-1 are marked as the first channel data stream set.
  • n/2 channel data streams are marked as the second channel data stream set.
  • the data of any two channel data streams among the n/2 channel data streams included in the first channel data stream set come from the same first FEC codeword
  • the n/2 channel data streams included in the second channel data stream set are The data of any two channel data streams in the data stream come from the same first FEC codeword
  • the data in any one channel data stream in the first channel data stream set is the same as any one in the second channel data stream set.
  • the data of the channel data stream comes from different first FEC codewords.
  • the 32 channel data streams after reordering are sorted from channel data stream 0 to channel data stream 31.
  • channel data streams 0 to 15 are sorted. It is called the first channel data stream set.
  • the data of any two channel data streams from channel data stream 0 to channel data stream 15 come from the same first FEC codeword.
  • Channel data streams 16 to 31 are called the second channel data.
  • the data of any two channel data streams in channel data stream 16 to channel data stream 31 come from the same first FEC codeword.
  • the data of any one channel data stream in the first channel data stream set and the data of any one channel data stream in the second channel data stream set come from different first FEC codewords.
  • boxes with the same pattern represent symbols of the same first FEC codeword
  • boxes with different patterns represent symbols of different first FEC codewords.
  • the originating processing module extracts R/2 items from the first channel data stream set among the n channel data streams, and extracts R/2 items from the second channel data stream set among the n channel data streams. , then, the originating processing module performs channel replacement processing on the R/2 channel data streams from the first channel data stream set and the R/2 channel data streams from the first channel data stream set, to obtain R first data streams. .
  • the R first data streams obtained after channel replacement processing are called a first data stream set. It should be noted that the first data stream set is only a way of describing the plurality of first data streams, and is not used as a data structure to limit the plurality of first data streams.
  • each group of channel data streams includes R/2 channel data streams from the first channel data stream set and R/2 channel data streams from the second channel data stream set, R/2 Channel data streams from the first channel data stream set and R/2 channel data streams from the second channel data stream set undergo channel replacement processing.
  • S first data stream sets are obtained, where each first data stream set contains R first data streams and S first data stream sets. There are n first data streams in total. It should be noted that the channel replacement process is not repeated for different groups of channel data streams. That is, if a certain channel data stream #1 in the first channel data stream set is divided into the first group of channel data streams, it will be used with the first channel data stream set.
  • the channel data stream #1 will not undergo channel replacement processing with other channel data streams again.
  • One first data flow set is obtained by replacement, and a total of 16 first data flow sets are obtained, in which each first data flow set contains two first data flows.
  • the originating processing module can channel-replace the 2 channel data streams in the first data stream set and the 2 channel data streams in the second channel data stream set to obtain a first data stream set.
  • the specific process of channel replacement may be to replace R/2 channel data streams from the first channel data stream set with R/2 channel data streams from the second channel data stream set every ⁇ symbols.
  • ⁇ symbols R first data streams are obtained, so that the first ⁇ symbols and the last ⁇ symbols of every 2 ⁇ symbols in each first data stream come from the first channel data stream set and the second channel data respectively.
  • the first FEC codeword is an RS codeword as an example. Every 2 consecutive RS symbols in each channel data stream come from 2 different RS codewords. After channel replacement processing, every 4 consecutive symbols in each first data stream come from 4 different RS codewords, and every consecutive RS codeword comes from 4 different RS codewords. Two of the four RS symbols come from the first channel data stream set, and the other two RS symbols come from the second channel data stream set.
  • the specific processing process of channel replacement may be to replace the first channel data stream and the second channel data stream by ⁇ symbols every ⁇ symbols to obtain 2 first data streams, Therefore, the first ⁇ symbols and the last ⁇ symbols of every 2 ⁇ symbols in each first data stream come from the first channel data stream and the second channel data stream respectively.
  • the first channel data stream is a channel data stream from the first channel stream data set
  • the second channel data stream is a channel data stream from the second channel stream data set.
  • the ⁇ 1 or 2.
  • the originating processing module selects any channel data stream i 0 from the channel data stream set 0 (i.e., channel data stream 0 to channel data stream (n/2)-1), and selects any channel data stream i 0 from the channel data stream set 1 (i.e., channel data stream 0 to channel data stream (n/2)-1). Select any channel data stream i 1 from channel data stream n/2 to channel data stream n- 1 ).
  • Channel data stream i 0 and channel data stream i 1 replace ⁇ symbols every ⁇ symbols to generate a first Data stream set
  • the first data stream set includes 2 first data streams, respectively identified as the first data stream i 0 and the first data stream i 1 , so that every 4 consecutive symbols of the first data stream come from 4 different code words.
  • i 1 i 0 +(n/2).
  • i 0 0 ⁇ i 0 ⁇ (n/2)-1
  • i 0 is an integer
  • i 1 is an integer.
  • the specific processing process of the aforementioned channel replacement can be expressed as the j-th symbol in the first data stream i comes from the channel data stream The jth symbol of .
  • i is an integer
  • j is an integer
  • "%" indicates the remainder operation.
  • FIG. 7A For ease of understanding, take Figure 7A as an example.
  • a first data stream set including a first data stream i 0 and a first data stream i 1 .
  • the first two RS symbols i.e., the first RS symbol and the second RS symbol
  • the channels data stream i 0 are marked 0 and 2.
  • the symbols of and the symbols marked 1 and 3 in the channel data stream i 1 remain unchanged.
  • the first two RS symbols of the obtained first data stream i 0 are symbols marked 0 and 2 respectively.
  • the obtained first data stream i The first two RS symbols of 1 are symbols marked 1 and 3 respectively; the third RS symbol of channel data stream i 0 is interchanged with the third RS symbol of channel data stream i 1 , and the third RS symbol of channel data stream i 0 is interchanged.
  • the four RS symbols are interchanged with the fourth RS symbol of channel data stream i 1 , that is, the symbols marked 4 and 6 in channel data stream i 0 are respectively exchanged with the symbols marked 5 and 7 in channel data stream i 1 , the third and fourth RS symbols of the obtained first data stream i 0 are symbols marked 5 and 7 respectively, and the third and fourth RS symbols of the obtained first data stream i 1 are marked 4 and 7 respectively. 6 symbol.
  • After channel replacement processing based on the first 4 RS symbols of channel data stream i 0 (i.e. "0, 2, 4, 6") and the first 4 RS symbols of channel data stream i 1 (i.e.
  • the originating processing module adopts the same method based on the last 4 RS symbols of the channel data stream i 0 (i.e., "8, 10, 12, 14") and the last 4 RS symbols of the channel data stream i 1 (i.e., "9"). , 11, 13, 15"), the last 4 RS symbols of the first data stream i 0 obtained are “8, 10, 13, 15” and the last 4 RS symbols of the first data stream i 1 are “9, 11, 12, 14”.
  • the first RS symbol of channel data stream i 0 and channel data stream i 1 remains unchanged, that is, the symbol marked 0 in channel data stream i 0 and the symbol marked 1 in channel data stream i 1 remain unchanged.
  • the second RS symbol of channel data stream i 0 is interchanged with the second RS symbol of channel data stream i 1 , that is, in channel data stream i 0
  • the symbol marked 2 is interchanged with the symbol marked 3 in channel data stream i 1
  • the third RS symbol of channel data stream i 0 and channel data stream i 1 remains unchanged, that is, the symbol marked 4 in channel data stream i 0
  • the symbol of is unchanged from the symbol marked 5 in channel data stream i 1
  • the fourth RS symbol of channel data stream i 0 is interchanged with the fourth RS symbol of channel data stream i 1 , that is, in channel data stream i 0
  • the symbol marked 6 is interchanged with the symbol marked 7 in channel data stream i 1 .
  • the first 4 RS symbols based on channel data stream i 0 i.e. "0, 2, 4, 6" and the first 4 RS symbols based on channel data stream i 1 (i.e. "1, 3, 5, 7")
  • the first 4 RS symbols of the first data stream i 0 obtained are "0, 3, 4, 7"
  • the first 4 RS symbols of the first data stream i 1 are "1, 2, 5",6”.
  • the originating processing module uses the same method to convert the last 4 RS symbols of channel data stream i 0 (i.e. "8, 10, 12, 14") and the last 4 RS symbols of channel data stream i 1 (i.e.
  • the originating processing module can perform channel replacement on the channel data stream i in the first data stream set and the channel data stream i+16 in the second channel data stream set to obtain the first data stream i and the first data stream i+16.
  • a first data flow set, a total of 16 first data flow sets are obtained. Among them, 0 ⁇ i ⁇ 15, and i is an integer.
  • channel data stream i and channel data stream i+16 replace every 2 RS symbols with 2 RS symbols to generate first data stream i and first data stream i+16.
  • channel data stream i and channel data stream i+16 replace every other RS symbol with one symbol to generate first data stream i and first data stream i+16.
  • the first data stream 0 and the first data stream 16 the first data stream 1 and the first data stream 17, the first data stream 2 and the first data stream 18, the first Data stream 3 and the first data stream 19, the first data stream 4 and the first data stream 20, the first data stream 5 and the first data stream 21, the first data stream 6 and the first data stream 22, the first data stream 7 and the first data stream 23, the first data stream 8 and the first data stream 24, the first data stream 9 and the first data stream 25, the first data stream 10 and the first data stream 26, the first data stream 11 and The first data stream 27, the first data stream 12 and the first data stream 28, the first data stream 13 and the first data stream 29, the first data stream 14 and the first data stream 30, the first data stream 15 and the first data stream
  • the data streams 31 respectively belong to 16 different first data stream sets.
  • the specific processing process of channel replacement can be any selection from the first channel data stream set (ie, channel data stream 0 to channel data stream (n/2)-1) 2 channel data streams (for example, channel data stream i 0 and channel data stream i 1 ), any 2 channels are selected from the second channel data stream set (ie, channel data stream n/2 to channel data stream n-1) Data streams (for example, channel data stream i 2 and channel data stream i 3 ), the aforementioned 4 channel data streams undergo channel replacement processing to generate a first data stream set, and the first data stream set contains 4 first data streams , respectively identified as the first data stream i 0 , the first data stream i 1 , the first data stream i 2 and the first data stream i 3 , so that every 4 consecutive symbols of the first data stream come from 4 different codewords.
  • the originating processing module can combine a certain RS symbol in the channel data stream i 0 and/or the channel data stream i 1 with an RS symbol in the channel data stream i 2 and/or the channel data stream i 3 A certain RS symbol replacement.
  • the third symbol of channel data stream i 0 i.e., the symbol identified as “8”
  • the third symbol of channel data stream i 2 i.e., the symbol identified as “8”.
  • the third symbol of channel data stream i 1 (i.e., the symbol identified as "9") interchanges with the third symbol of channel data stream i 3 (i.e., the symbol identified as "11") Change.
  • the fourth symbol of the channel data stream i 0 (ie, the symbol identified as “12”) is the same as the fourth symbol of the channel data stream i 3 (ie, the symbol identified as “12”).
  • the symbol of "15" is interchanged, and the fourth symbol of channel data stream i 1 (that is, the symbol identified as "13") is interchanged with the fourth symbol of channel data stream i 2 (that is, the symbol identified as "14") exchange.
  • the originating processing module can exchange a certain RS symbol in the channel data stream i 0 with the channel data stream i 1 , or can exchange the channel data stream i 2 with the channel data stream i
  • One of the RS symbols in 3 is interchanged.
  • the second symbol of channel data stream i 0 i.e., the symbol identified as “4”
  • the second symbol of channel data stream i 1 i.e., the symbol identified as “ 5" symbol
  • the second symbol of channel data stream i 2 that is, the symbol identified as "6”
  • the second symbol of channel data stream i 3 that is, the symbol identified as "7"
  • the originating processing module can cyclically shift a certain RS symbol in the channel data stream i 0 , channel data stream i 1 , channel data stream i 2 and channel data stream i 3 .
  • the fourth channel data stream i 0 symbol i.e., the symbol identified as "12"
  • the fourth symbol of channel data stream i 1 i.e., the symbol identified as "13"
  • the fourth symbol of channel data stream i 2 i.e., the symbol identified as "14” symbol
  • the fourth symbol of channel data stream i 3 that is, the symbol identified as "15
  • the fourth symbols of the first data stream i 0 , the first data stream i 1 , the first data stream i 2 and the first data stream i 3 among the multiple first data streams after channel replacement are respectively is "15
  • example (a) shown in FIG. 7D and the example (b) shown in FIG. 7D are just two examples of multiple replacement methods of channel replacement processing. In practical applications, any of the aforementioned examples can be used.
  • One or more specific symbol replacement methods are combined to obtain four channel data streams for implementation of channel replacement. Each consecutive 2a symbols of the first data stream obtained after channel replacement come from 2a different RS codewords, and a symbol in each consecutive 2a symbols comes from the first channel data stream set, and the other a The symbols are from the second channel data stream collection.
  • the originating processing module can perform channel replacement on a total of four channel data streams: channel data stream i 0 , channel data stream i 0 +8, channel data stream i 0 +16, and channel data stream i 0 +24, to obtain the first data stream including A first data stream set j 0 of a total of 4 first data streams i 0 , first data stream i 0 +8, first data stream i 0 +16, and first data stream i 0 +24, and a total of 8 are obtained The first data stream collection. Among them, 0 ⁇ i 0 ⁇ 6, and i 0 is an integer; 0 ⁇ j 0 ⁇ 7, and j 0 is an integer.
  • Step 302 Perform convolution and interleaving processing on each of the n first data streams to obtain n second data streams.
  • the b consecutive symbols in the second data stream come from b different first FEC codewords, where b is an integer greater than 1, and b can be evenly divided by a.
  • the n first data streams after channel replacement will enter the convolution interleaver for convolution and interleaving processing, and n second data streams will be obtained.
  • the first FEC codeword is the RS codeword
  • a 2
  • the delay value of delay line 0 is 0 RS symbols
  • the delay value of delay line 1 is 4Q RS symbols
  • the delay value of delay line 2 is 8Q symbols, that is, No lag.
  • the delay value of delay line 0 is 8Q RS symbols
  • the delay value of delay line 1 is 4Q RS symbols
  • the delay value of delay line 2 is 0 symbols, that is, No lag.
  • the convolutional interleaved delay line 0 delay line 1 and delay line 2 poll the 12 RS output once.
  • the symbols are from 12 different RS codewords.
  • Sr(3t), Sr(3t+1), and Sr(3t+2) are sequentially input to delay line 0, delay line 1, and delay line 2 of the convolutional interleaver shown in example (b) of FIG.
  • delay line 0, delay line 1 and delay line 2 respectively output Sr(3t-6Q), Sr(3t-3Q+1) and Sr(3t+2), and then, Sr(3t+3), Sr( 3t+4) and Sr(3t+5) are input to delay line 0, delay line 1 and delay line 2 respectively, while delay line 0, delay line 1 and delay line 2 output Sr(3t-6Q+3) respectively. , Sr(3t-3Q+4) and Sr(3t+5).
  • delay line 1 and delay line 2 poll the 12 RS symbols output at a time from 12 different RS codewords.
  • Step 303 Perform a second FEC encoding process on each of the n second data streams to obtain n encoded data streams.
  • Each of the n encoded data streams includes a plurality of second FEC codewords, and each second FEC codeword includes second FEC information data and second FEC check data.
  • the second FEC information data is data from the second data stream.
  • the bits where the second FEC information data is located are called information bits or information bits.
  • the second FEC verification data is added by the originating processing module for verification.
  • the redundant data, the bit where the second FEC check data is located is called the check bit or parity bit.
  • FIG. 9A is a schematic structural diagram of performing second FEC encoding on n second data streams in an embodiment of the present application.
  • n second data streams are respectively subjected to second FEC encoding (ie, the inner code encoding mentioned above) to obtain n encoded data streams.
  • second FEC encoding ie, the inner code encoding mentioned above
  • FIG. 9B shows that the second FEC is eHamming(128, 120) as an example.
  • the originating processing module treats each continuous 12 symbols (i.e.
  • each second FEC 120 bits in each second data stream as a second FEC information data, performs eHamming (128, 120) encoding on each second FEC information data, and adds Redundant bits are used to obtain the second FEC codeword with a length of 128 bits.
  • the information bits of each second FEC come from 12 different RS codewords.
  • Step 304 Channel interleave each set of q coded data streams among the n coded data streams into one third data stream, obtaining a total of m third data streams.
  • n coded data streams include S coded data stream sets, each coded data stream set includes R coded data streams, and the data of the R coded data streams come from R channel data streams that undergo channel replacement, and the R coded data streams
  • the channel data streams for channel replacement include R/2 channel data streams from the first channel data stream set and R/2 channel data streams from the second channel data stream set. It can also be understood that the R coded data streams are obtained by performing convolutional interleaving and second FEC coding on R first data streams in a first data stream set respectively.
  • the data of the R coded data streams refers to the second FEC information data in the R coded data streams, and does not include the second FEC check data in the R coded data streams, that is, there are only R pieces of coded data.
  • the second FEC information data of the stream comes from R channel data streams undergoing channel replacement.
  • n/R n/R
  • m S/q
  • q is an integer greater than 0, and S can be divided by q.
  • the originating processing module can convert the encoded data stream i 0 , the encoded data stream i 1 , the encoded data stream i 0 +(n /2), coded data stream i 1 + (n/2), a total of four coded data streams are channel interleaved into one third data stream, where 0 ⁇ i 0 ⁇ 15, 0 ⁇ i 1 ⁇ 15.
  • the originating processing module performs channel interleaving on each of the 32 encoded data streams, including two encoded data streams, into one third data stream. stream, a total of 8 third data streams are obtained.
  • the originating processing module can convert the encoded data stream i 0 , the encoded data stream i 1 , the encoded data stream i 2 , and the encoded data stream i 0 , encoded data stream i 1 , encoded data stream i 2 , and Data stream i 3 , coded data stream i 0 +(n/2), coded data stream i 1 +(n/2), coded data stream i 2 +(n/2), and coded data stream i 3 +(n/ 2) Channel interleaving is performed into a third data stream; where, 0 ⁇ i 0 ⁇ 15, 0 ⁇ i 1 ⁇ 15, 0 ⁇ i 2 ⁇ 15, 0 ⁇ i 3 ⁇ 15.
  • each encoded data stream set includes 2 encoded data streams, and the 2 encoded data streams are composed of 1 channel data stream from the first channel data stream set and 1 channel data stream from the first channel data stream set.
  • the other channel data stream in the second channel data stream set is determined by the two first data streams obtained by channel replacement processing.
  • the two first data streams are respectively subjected to convolution interleaving and second FEC encoding to obtain the aforementioned A collection of encoded data streams of 2 encoded data streams.
  • the originating processing module performs channel interleaving on every four coded data stream sets among the 32 coded data streams into one third data stream, resulting in a total of four third data streams. Therefore, the originating end processing module can transmit the third data stream to the receiving end processing module through 4 physical channels.
  • the 4 physical channels can be 4 optical fibers or 4 waves on 1 optical fiber. This is not done here. limited.
  • the originating processing module regards every 2 coded data streams among the 32 coded data streams as a coded data stream set, and performs channel interleaving on a total of 8 coded data streams in the 4 coded data stream sets to obtain 4 Third data stream.
  • a coded data stream set includes coded data stream i and coded data stream i+16, where 0 ⁇ i ⁇ 15, and i is an integer.
  • the encoded data stream i and the encoded data stream i+16 are the two first data streams in the first data stream set obtained by line channel replacement of the channel data stream i and the channel data stream i+16, which are respectively subjected to convolution interleaving and interleaving. Coded.
  • the channel data stream i and the channel data stream i+16 are channel-permuted to obtain the first data stream i and the first data stream i+16. Then, the first data stream i and the first data stream i+16 are respectively convolved and interleaved to obtain The second data stream i and the second data stream i+16 are then subjected to the second FEC encoding respectively to obtain the encoded data stream i and the encoded data stream i+16, then Coded data stream i and coded data stream i+16 are identified as a coded data stream set, and the originating processing module obtains a total of 16 coded data stream sets. Then, the originating processing module randomly selects 4 coded data stream sets from the 16 coded data stream sets and performs channel interleaving to obtain a third data stream, and a total of 4 third data streams are obtained.
  • the originating processing module may use any of the following examples to interleave the encoded data stream into the third data stream.
  • the originating processing module can encode the data stream 4*j, the coded data stream 4*j+1, the coded data stream 4*j+2, the coded data stream 4*j+3, and the coded data stream 4*j+ 16.
  • a total of 8 coded data streams, coded data stream 4*j+17, coded data stream 4*j+18, and coded data stream 4*j+19, are interleaved to obtain the third data stream j, where 0 ⁇ j ⁇ 3.
  • a specific interleaving process is to map each consecutive 2 bits in each second FEC codeword into a four-level pulse amplitude modulation (4-Level Pulse Amplitude Modulation, PAM4), where, S ( ) represents a PAM4 symbol.
  • each second FEC codeword can be mapped to 64 PAM4 symbols.
  • the originating processing module will encode data stream 4*j, encode data stream 4*j+1, encode data stream 4*j+2, encode data stream 4*j+3, encode data stream 4*j+16, encode data stream 4*j+17, the encoded data stream 4*j+18, the data of the encoded data stream 4*j+19 are polled and output to the third data stream j according to the PAM4 symbol.
  • another specific interleaving process is to combine the coded data stream 4*j, the coded data stream 4*j+1, the coded data stream 4*j+2, the coded data stream 4*j+3, the coded data Stream 4*j+16, encoded data stream 4*j+17, encoded data stream 4*j+18, encoded data stream 4*j+19 are output to the third data stream j according to 1-bit polling, where, b () represents 1-bit data of the encoded data stream.
  • the originating processing module can also encode the encoded data stream j, the encoded data stream 4+j, the encoded data stream 8+j, the encoded data stream 12+j, the encoded data stream 16+j, the encoded data stream 20+j, The encoded data stream 24+j and the encoded data stream 28+j, a total of 8 encoded data streams are interleaved into the third data stream j, where 0 ⁇ j ⁇ 3.
  • the specific method may still be the PAM4 symbol polling-based method shown in Figure 10B, or the 1-bit polling-based method shown in Figure 10C, which will not be described again here.
  • the originating processing module performs channel interleaving on every two coded data stream sets among the 32 coded data streams into one third data stream, resulting in a total of eight third data streams. Therefore, the originating end processing module can transmit the third data stream to the receiving end processing module through 8 physical channels.
  • the 8 physical channels can be 8 optical fibers or 8 waves on 1 optical fiber. This is not done here. limited.
  • the originating processing module regards every two coded data streams among the 32 coded data streams as a coded data stream set, and performs channel interleaving on the two coded data stream sets to obtain eight third data streams.
  • a coded data stream set includes coded data stream i and coded data stream i+16, where 0 ⁇ i ⁇ 15, and i is an integer.
  • the originating processing module randomly selects 2 coded data stream sets from the 16 coded data stream sets and performs channel interleaving to obtain a third data stream, and a total of 8 third data streams are obtained.
  • the originating processing module may use any of the following examples to interleave the encoded data stream into the third data stream.
  • the originating processing module can interleave a total of four encoded data streams: encoded data stream 2*j, encoded data stream 2*j+1, encoded data stream 2*j+16, and encoded data stream 2*j+17.
  • the third data stream j where 0 ⁇ j ⁇ 7.
  • a specific interleaving process is to map every 2 consecutive bits in each second FEC codeword to a PAM4.
  • Each second FEC codeword can be mapped to 64 PAM4 symbols, and then encode The data stream 2*j, the encoded data stream 2*j+1, the encoded data stream 2*j+16, and the encoded data stream 2*j+17 are polled and output to the third data stream j according to the PAM4 symbol.
  • another specific interleaving process is to encode the data stream 2*j, the coded data stream 2*j+1, the coded data stream 2*j+16, and the coded data stream 2*j+17 according to 1 bit
  • the polling is output to the third data stream j.
  • the originating processing module may also interleave a total of four encoded data streams, namely encoded data stream j, encoded data stream 8+j, encoded data stream 16+j, and encoded data stream 24+j, into the third data stream j.
  • the specific method may still be the PAM4 symbol polling-based method shown in Figure 10E, or the 1-bit polling-based method shown in Figure 10F, which will not be described again here.
  • each encoded data stream set includes 4 encoded data streams, and the 4 encoded data streams are composed of 2 channel data streams from the first channel data stream set and The other two channel data streams from the second channel data stream set are determined by the four first data streams obtained by channel replacement processing.
  • the four first data streams are respectively subjected to convolution interleaving and second FEC encoding to obtain the following data: A collection of encoded data streams of the aforementioned four encoded data streams.
  • the originating processing module performs channel interleaving on every two coded data stream sets among the 32 coded data streams into one third data stream, resulting in a total of four third data streams. Therefore, the originating end processing module can transmit the third data stream to the receiving end processing module through 4 physical channels.
  • the 4 physical channels can be 4 optical fibers or 4 waves on 1 optical fiber. This is not done here. limited.
  • the originating processing module regards every 4 coded data streams among the 32 coded data streams as a coded data stream set, and performs channel interleaving on the 2 coded data stream sets to obtain 4 third data streams.
  • the originating processing module performs channel interleaving on each set of coded data streams among the 32 coded data streams into one third data stream, resulting in a total of eight third data streams. Therefore, the originating end processing module can transmit the third data stream to the receiving end processing module through 8 physical channels.
  • the 8 physical channels can be 8 optical fibers or 8 waves on 1 optical fiber. This is not done here. limited.
  • the originating processing module regards every 4 coded data streams among the 32 coded data streams as a coded data stream set, and performs channel interleaving on 1 coded data stream set to obtain 8 third data streams.
  • any two encoded data streams in the same encoded data stream set come from the same channel data stream
  • the data of any two encoded data streams in different encoded data stream sets come from different channel data streams.
  • the data from the first channel data stream set is The R/2 channel data streams and the R/2 channel data streams from the second channel data stream set are subjected to channel replacement processing, and each channel data stream in the R/2 channel data streams of the first channel data stream set can be Part of the data is replaced with part of the data of each channel data stream in the R/2 channel data streams of the second channel data stream set to obtain R first data streams, so that the data in the same channel data stream is dispersed to Different first data streams.
  • each of the aforementioned first data streams is separately subjected to convolution interleaving processing and second FEC coding processing to obtain R coded data streams, and then the aforementioned R coded data streams are interleaved into the same third data stream through the channel. . Therefore, the data dispersed into R first data streams through channel replacement is interleaved into the same third data stream through channel interleaving processing. That is to say, even if the data from a certain channel data stream is dispersed to different first data streams through channel replacement, it can still be interleaved into the same third data stream through channel interleaving processing, and then transmitted to the same physical channel. Therefore, the problem of inconsistent transmission delays for the same channel data stream will not be caused, and the end processing module can avoid aligning the channel data stream, effectively reducing the complexity of the end processing module.
  • one of the synchronization methods is to perform self-synchronization of the second FEC codeword by calculating whether the syndrome of the second FEC codeword is 0.
  • a simple solution is to determine that there are T or more second FEC codewords within W consecutive second FEC codewords whose syndromes are 0, which means that the second FEC codeword is synchronized.
  • the second FEC codeword may be a cyclic code, its syndrome will be 0 even in an out-of-synchronization state.
  • a scrambling module can be added to scramble the data stream.
  • the processing methods of adding different scrambling modules are introduced below based on Figure 11A, Figure 13A and Figure 14A respectively.
  • the originating processing module may scramble the encoded data stream after the second FEC encoding and before channel interleaving. In this method, the originating processing module will perform the following steps:
  • Step 1101 Perform channel replacement processing on every R/2 channel data streams from the first channel data stream set and every R/2 channel data streams from the second channel data stream set among the n channel data streams to obtain R For the first data stream, a total of n first data streams are obtained.
  • Step 1102 Perform convolution and interleaving processing on each of the n first data streams to obtain n second data streams.
  • Step 1103 Perform a second FEC encoding process on each of the n second data streams to obtain n encoded data streams.
  • steps 1101 to 1103 are similar to the previous steps 301 to 303.
  • steps 1101 to 1103 are similar to the previous steps 301 to 303.
  • Step 1104 Use a pseudo-random binary sequence with a length of Q*N bits to scramble the Q consecutive second FEC codewords in each coded data stream to obtain n coded data streams after scrambling.
  • N is the length of the second FEC codeword
  • N is an integer greater than 1
  • Q is an integer greater than or equal to 1.
  • the scrambling module uses PN-Q*N pseudo-random noise sequence (pseudo-noise sequence) to scramble the Q encoded codewords.
  • Q is an integer greater than or equal to 8 and less than or equal to 16.
  • the optimal value of Q is 11.
  • the PN-Q*N pseudo-random noise sequence is generated using the scrambling polynomial r(x).
  • the PN-Q*N pseudo-random noise sequence takes Q*N bits as a period, and initializes the scrambling polynomial r(x) as the initial seed at the 0th bit position of the 0th codeword of each Q consecutive inner codewords. .
  • the initial seed is "10101010", and the generated PN-Q*N pseudo-random noise sequence is superimposed on the codeword bits.
  • Step 1105 Channel interleave each set of q coded data streams among the n coded data streams into one third data stream, resulting in a total of m third data streams.
  • step 1105 is similar to the previous step 304.
  • the n coded data streams are n coded data streams that have been scrambled.
  • scrambling is performed on the encoded data stream after the second FEC encoding (ie, inner code encoding), which facilitates the receiving end processing module to perform decoding of the second FEC codeword without adding additional redundant information.
  • Synchronization is beneficial to reducing the probability of mis-synchronization and mis-locking of the second FEC codeword, and improving the reliability of synchronization.
  • FIG. 13A another embodiment of a data processing method with added scrambling processing is shown.
  • the originating processing module can perform scrambling on the third data stream after channel interleaving. In this method, the originating processing module will perform the following steps:
  • Step 1301 Perform channel replacement processing on every R/2 channel data streams from the first channel data stream set and every R/2 channel data streams from the second channel data stream set among the n channel data streams to obtain R For the first data stream, a total of n first data streams are obtained.
  • Step 1302 Perform convolution and interleaving processing on each of the n first data streams to obtain n second data streams.
  • Step 1303 Perform a second FEC encoding process on each of the n second data streams to obtain n encoded data streams.
  • Step 1304 Channel interleave each set of q coded data streams among the n coded data streams into one third data stream, obtaining a total of m third data streams.
  • steps 1301 to 1304 are similar to the previous steps 301 to 304.
  • steps 1301 to 1304 are similar to the previous steps 301 to 304.
  • Step 1305 Use a pseudo-random binary sequence with a length of R*q*Q*N bits to scramble each continuous R*q*Q*N bit in each third data stream to obtain m scrambled bits.
  • the third data stream, the continuous R*q*Q*N bits in the third data stream are the R*q* generated by channel interleaving of Q consecutive second FEC codewords in each of the R*q coded data streams. Q*N bits.
  • each of the Q consecutive second FEC code words in the R*q coded data stream is channel interleaved according to the channel interleaving scheme given in step 304 to generate consecutive R*q*Q*N bits of the third data stream.
  • the transmitting end processing module scrambles the third data stream after channel interleaving, which facilitates the receiving end processing module to synchronize the second FEC codeword without adding additional redundant information, and can Reduce second FEC codeword mis-synchronization and missed lock probability to improve synchronization reliability.
  • the originating processing module may scramble the second data stream before the second FEC encoding.
  • the originating processing module will perform the following steps:
  • Step 1401 Perform channel replacement processing on every R/2 channel data streams from the first channel data stream set and every R/2 channel data streams from the second channel data stream set among the n channel data streams to obtain R For the first data stream, a total of n first data streams are obtained.
  • Step 1402 Perform convolution and interleaving processing on each of the n first data streams to obtain n second data streams.
  • steps 1401 to 1402 are similar to the previous steps 301 to 302.
  • steps 1401 to 1402 are similar to the previous steps 301 to 302.
  • Step 1403 Use a pseudo-random binary sequence with a length of Q*K bits to scramble the Q consecutive second FEC codeword information bits in each second data stream to obtain the scrambled n second data streams.
  • K is the length of the second consecutive FEC codeword information bit
  • K is an integer greater than 1
  • Q is an integer greater than or equal to 1.
  • the scrambling module in this step can use PN-Q*K pseudo-random noise sequences to scramble the information bits of the Q codewords to be encoded.
  • Q is an integer greater than or equal to 8 and less than or equal to 16.
  • BER bit error rate
  • Q is preferably The value is 11.
  • the PN-Q*K pseudo-random noise sequence is generated using the scrambling polynomial r(x).
  • the expression of the polynomial is as shown in the above formula (1), which will not be described again here.
  • Step 1404 Perform a second FEC encoding process on each of the n second data streams to obtain n encoded data streams.
  • the n second data streams are scrambled n second data streams.
  • Step 1405 Channel interleave each set of q coded data streams among the n coded data streams into one third data stream, resulting in a total of m third data streams.
  • steps 1404 to 1405 are similar to the previous steps 303 to 304.
  • steps 1404 to 1405 are similar to the previous steps 303 to 304.
  • scrambling is performed on the second data stream after convolutional interleaving, which facilitates the receiving end processing module to synchronize the second FEC codeword without adding additional redundant information, and can reduce the second data stream.
  • the probability of FEC codeword mis-synchronization and false lock loss improves the reliability of synchronization.
  • the originating processing module performs alignment processing based on the AM sequence, and the AM sequence will be used in the subsequent convolutional interleaving and second FEC encoding processes. Specifically, the originating processing module will perform the following steps:
  • Step 1501 Perform AM sequence-based alignment processing on n channel data streams to obtain n channel data streams aligned based on AM sequences.
  • the channel data stream may be a physical coding sublayer (PCS) channel data stream.
  • the n channel data streams are all data streams encoded by the first FEC, and the n channel data streams are channel data streams that have been identified and locked (alignment lock).
  • the AM sequence is an AM sequence carried in the channel data stream, and the AM sequence is used by the receiving device to synchronize RS codewords and align PCS channels.
  • the sending device can add an AM sequence to the PCS channel data stream every L 1 bit interval. Since the AM sequence is a known sequence, the originating processing module can use the AM sequence to perform channel data alignment processing.
  • the originating processing module can also perform alignment processing based on the AM sequence in channel replacement, convolutional interleaving, and inner code encoding.
  • the receiving processing module can also use the AM sequence to synchronize the inner code.
  • each interval L 1 2785280 bits (that is, 8192 RS codewords, including AM sequences) is inserted into the AM sequence, and the AM sequence includes CM, UP and UM, a total of 3 parts, a total of 15 bytes.
  • the CM part occupies 6 bytes, marked ⁇ CM 0 , CM 1 , CM 2 , CM 3 , CM 4 , CM 5 ⁇ , which is used for RS codeword synchronization by the receiving device.
  • the CM parts of different channel data streams among the 32 channel data streams are the same.
  • the UM part occupies 6 bytes, marked ⁇ UM 0 , UM 1 , UM 2 , UM 3 , UM 4 , UM 5 ⁇ , and is used to carry the channel number to facilitate channel sorting of the channel data stream.
  • the UM part of the AM sequence in different channel data streams is different, which means that the channel numbers of the different channel data streams are different.
  • the UP part occupies 3 bytes and is marked ⁇ UP 0 , UP 1 , UP 2 ⁇ .
  • the UP part is a pad sequence.
  • the UP part of any two channel data streams from channel data stream 0 to channel data stream (n/2)-1 is different, and the UP part of channel data stream n/2 to channel data stream n-1 is different.
  • the UP parts of any two channel data streams are different; the UP parts from channel data stream 0 to channel data stream (n/2)-1 are respectively the same as the UP parts from channel data stream n/2 to channel data stream n-1. same.
  • the UP part of any two channel data streams from channel data stream 0 to channel data stream 15 is different, and the UP part of any two channel data streams from channel data stream 16 to channel data stream 31 is different.
  • the UP parts of the streams are different; the UP parts of channel data stream 0 to channel data stream 15 are the same as the UP parts of channel data stream 16 to channel data stream 31 respectively.
  • Step 1502 Reorder the n channel data streams aligned based on the AM sequence, so that the n channel data streams are sorted according to a preset sorting method.
  • sort n channel data streams according to the preset sorting method.
  • n 32 as an example.
  • the 32 channel data streams after reordering are processed according to the channel data stream.
  • 0 to channel data stream 31 are sorted, where channel data streams 0 to 15 are called the first channel data stream set, and the data of any two channel data streams from channel data stream 0 to channel data stream 15 come from the same first channel data stream set.
  • One FEC codeword, channel data streams 16 to 31 are called the second channel data stream set, and the data of any two channel data streams among channel data stream 16 to channel data stream 31 come from the same first FEC codeword.
  • the data of any one channel data stream in the first channel data stream set and the data of any one channel data stream in the second channel data stream set come from different first FEC codewords.
  • boxes with the same pattern represent symbols of the same first FEC codeword
  • boxes with different patterns represent symbols of different first FEC codewords.
  • step 301 please refer to the introduction to the reordering process in step 301 above, which will not be described again here.
  • Step 1503 Perform channel replacement processing on every R/2 channel data streams from the first channel data stream set and every R/2 channel data streams from the second channel data stream set among the n channel data streams to obtain R For the first data stream, a total of n first data streams are obtained.
  • Each of the n first data streams includes an AM p sequence at an interval of L 1 bits, and the AM p sequence includes 15 bytes.
  • the first 8 bytes of the AM p sequence in each first data stream are the same as the first 8 bytes of the AM sequence in the corresponding channel data stream, and the last 8 bytes of the AM p sequence in each first data stream are the same.
  • the 7 bytes are different from the last 7 bytes of the AM sequence in the corresponding channel data stream, and the last 7 bytes of the AM p sequence in different first data streams are different.
  • the channel data stream corresponding to the first data stream is the channel data stream generated based on the channel replacement process of the first data stream.
  • the channel data stream i 0 and the channel data stream i 1 undergo channel replacement processing to obtain the first data stream i 0 and the first data stream i 1 .
  • the channel data stream corresponding to the first data stream i 0 is the channel data stream i 0 and the channel data stream i 1
  • the channel data stream corresponding to the first data stream i 1 is also the channel data stream i 0 and the channel data stream i 1 .
  • Data stream i 1 .
  • the first 8 bytes of the AM p sequence in the first data stream i 0 are the same as the first 8 bytes of the AM sequence in the channel data stream i 0
  • the first data The first 8 bytes of the AM p sequence in stream i 0 are the same as the first 8 bytes of the AM sequence in channel data stream i 1 .
  • the last 7 bytes of the AM p sequence in the first data stream i 0 are different from the last 7 bytes of the AM sequence in the channel data stream i 0 .
  • the last 7 bytes of the AM p sequence in the first data stream i 0 are different.
  • Bytes are also different from the last 7 bytes of the AM sequence in channel data stream i 1
  • the last 7 bytes of the AM p sequence in any two of the n first data streams are different. same.
  • the first 8 bytes of the AM p sequence in the first data stream are the same as the first 8 bytes of the AM sequence in the channel data stream, specifically referring to the first 8 bytes of the AM p sequence in the first data stream.
  • the 8 bytes are identical to the first 8 bytes of the AM sequence in the channel data stream.
  • the x-th byte of the AM p sequence in the first data stream is the same as the x-th byte of the AM sequence in the channel data stream, where 1 ⁇ x ⁇ 8, and x is an integer.
  • the last 7 bytes of the AM p sequence in the first data stream are different from the last 7 bytes of the AM sequence in the channel data stream.
  • the last 7 bytes of the AM p sequence in the first data stream are different from the last 7 bytes of the AM p sequence in the channel data stream.
  • the last 7 bytes of the AM sequence in the channel data stream are different by at least one byte.
  • the yth byte of the AM p sequence in the first data stream is the same as the AM in the channel data stream.
  • the y-th byte of the sequence is the same, but the z-th byte of the AM p sequence in the first data stream is the same as the z-th byte of the AM sequence in the channel data stream, where 9 ⁇ y ⁇ 15, 9 ⁇ z ⁇ 15, and both y and z are integers, and the values of y and z are different.
  • the 32 channel data streams aligned based on the AM sequence are processed through channel replacement to obtain 32 first data streams.
  • the originating end processing module uses the example introduced in Figure 7A, Figure 7B or Figure 7C to perform channel replacement processing.
  • the length of the AMp sequence is still 120 bits.
  • the first 8 bytes of the AM sequence in the first data stream i (0 ⁇ i ⁇ 32) are consistent with the first 8 bytes of the AM sequence in the channel data stream i (0 ⁇ i ⁇ 32), that is, they are still ⁇ CM 0 , CM 1 , CM 2 , UP 0 , CM 3 , CM 4 , CM 5 , UP 1 ⁇ , and, for all first data streams CM 0 , CM 1 , CM 2 , CM 3 , CM 4 and CM 5 are the same, that is, the CM part of any two first data streams among the 32 first data streams is the same.
  • UP 0 and UP 1 are different for the first data stream 0 to the first data stream 15, but the first data stream 0 to the first data stream 15 are the same as the first data stream 16 to the first data stream 31 respectively. Mark these 8 bytes as CMP .
  • the last 7 bytes of the AM sequence in the first data stream i (0 ⁇ i ⁇ 32) are different from the last 7 bytes of the AM sequence in the channel data stream i (0 ⁇ i ⁇ 32), and, any The last 7 bytes of the AMP sequence in the two first data streams are different from each other. Therefore, the last 7 bytes of the AMP sequence are marked as UMp.
  • Step 1504 Perform convolution and interleaving processing on each of the n first data streams to obtain n second data streams.
  • the originating processing module inputs each consecutive T*L 1 symbol in each first data stream into p delay lines of the convolutional interleaver in units of d symbols, round-robin, Obtain a second data stream, the first t bits of each consecutive T*L 1 symbol are the AM p sequence, the second data stream contains an AM o sequence every L 2 symbols, and the AM o
  • the five consecutive bytes in the CMP sequence are input to the convolutional interleaver at a fixed period.
  • each consecutive T*L symbol in the first data stream is input into the data shown in Figure 8 in a round-robin manner in units of d symbols.
  • T*L 1 can be evenly divided by d*p.
  • the second data stream contains a known sequence of length d symbols every L 2 bits.
  • the aforementioned known sequence is called the AMO sequence, and the AMO sequence is the first d symbols of the AMP sequence.
  • L 2 T*L 1 bit.
  • the 1st convolutional interleaver block is input to the convolutional interleaver delay line 1
  • the 2nd convolutional interleaving block is input to the convolutional interleaver delay line 2
  • the 3rd convolutional interleaving block is input to the convolutional interleaver delay line 2.
  • Interleaver delay line 0 the 4th convolutional interleaving block is input to convolutional interleaver delay line 1, and so on.
  • the format of the second data stream after convolutional interleaving is shown in Figure 20.
  • the known sequence with a length of 40 bits is It is marked as an AMO sequence, and the AMO sequence is the first 5 bytes of the AMP sequence.
  • the AMO sequence contains ⁇ CM 0 , CM 1 , CM 2 , UP 0 , CM 3 ⁇ .
  • Step 1505 Perform a second FEC encoding process on each of the n second data streams to obtain n encoded data streams.
  • the originating processing module performs second FEC encoding on the continuous L 2 symbols in each second data stream to obtain c second FEC codewords.
  • the first d symbols of the continuous L 2 symbols are the AMO sequence
  • the c is L 2 /K
  • the K is the length of the continuous second FEC codeword information bit
  • the K is an integer greater than 1 .
  • the transmitting end processing module needs to synchronize the AMO sequence with the second FEC codeword when performing the second FEC encoding (ie, inner code encoding). (i.e., inner code word) synchronization, that is, the AMO sequence is fixed to a fixed position of the second FEC code word (i.e., inner code word).
  • this application provides an implementation method of fixed AMO sequence. Among them, the AMO sequence is fixed at the first 40 bits of the inner code word.
  • the originating processing module can use the AMO sequence as the starting position to divide every 12 consecutive symbols (i.e.
  • each interval of L3 69632 inner code words in the encoded data stream obtained after the second FEC encoding contains an AMO sequence with a length of 40 bits.
  • Step 1506 Channel interleave each set of q coded data streams among the n coded data streams into one third data stream, resulting in a total of m third data streams.
  • the originating processing module can perform channel interleaving processing in the manner described in the corresponding embodiment in Figure 3 to obtain m third data streams.
  • m 4 or 8.
  • the specific method of selecting the value of m has been introduced in detail in step 304 of the corresponding embodiment in Figure 3, and will not be described again here.
  • FIG 22 it is an example diagram of the third data stream after channel interleaving processing.
  • this fixed sequence is called AM O' sequence, and the length of this AM O' sequence is 32/m*40 bits.
  • the originating processing module can be aligned with the AM sequence during the convolutional interleaving process and the inner code encoding process, so that the encoded data stream or third data can be encoded without adding additional redundant information.
  • the known sequence appears periodically in the stream, so that the receiving end processing module can use this periodic known sequence to synchronize the internal code, which in turn helps reduce the processing complexity of the receiving end.
  • the originating processing module can replace the AM sequence based on the corresponding embodiment in FIG. 15 .
  • the AM sequence in each of the n channel data streams is replaced with an AM * sequence,
  • the first 5 bytes of the AM * sequence are the same in different channel data streams.
  • the first 5 bytes of the AM sequence include the UP sequence, and the first 5 bytes of the AM sequence can be expressed as ⁇ CM 0 , CM 1 , CM 2 , UP 0 , CM 3 ⁇ .
  • UP 0 is the PAD sequence, and different channels have different UP 0 . Therefore, if the receiving end processing module uses the AMO sequence or AMO ' sequence for inner code synchronization, it needs to shield part of the data interleaved by UP 0 in the AMO sequence or AMO ' in the AMO ' sequence, which may increase the probability of false locking. and synchronization complexity.
  • this embodiment proposes a solution that can avoid shielding the UP 0 in the AMO sequence or shielding the partial sequence obtained by interleaving the UP 0 in the AMO sequence when using the AMO sequence or the AMO' sequence for inner code synchronization.
  • Example (b) and example (c) shown in FIG. 23 are examples of two AM * sequences provided by this embodiment.
  • a possible example is shown in example (b) of Figure 23.
  • the originating processing module can move UP 0 in the AM sequence to between CM 5 and UP 1 , leaving other parts unchanged, resulting in the format of the AM * sequence.
  • the first 5 bytes of the AM * sequence are the same for all channels.
  • the originating processing module uses the AM * sequence according to the data processing method given in the corresponding embodiment in Figure 15 to obtain the AMO sequence in the n coded data streams as ⁇ CM 0 , CM 1 , CM 2 , CM 3 , CM 4 ⁇ ,
  • the receiving end processing module can use the complete AMO sequence or AMO ' sequence for inner code synchronization.
  • the originating processing module can convert the AM sequence ⁇ CM 0 , CM 1 , CM 2 , UP 0 , CM 3 , CM 4 , CM 5 , UP 1 ⁇ into Replace with ⁇ CM 0 , CM 1 , CM 3 , CM 4 , CM 5 * , UP 0 , UP 1 ⁇ , other parts remain unchanged.
  • in is 4 bits, for The bits of are inverted, It can be the same as the first 4 bits of CM 2 , or it can be the same as the last 4 bits of CM 2 , or it can be any other sequence.
  • CM 5 * can be the same as CM 5 ; it can also be that the first 4 bits of CM 5 * are the same as the first 4 bits of CM 5 , and the last 4 bits of CM 5 * are opposite to the first 4 bits of CM 5 ; it can also be CM 5
  • the first 4 bits of * are the same as the last 4 bits of CM 5
  • the last 4 bits of CM 5 * are opposite to the first 4 bits of CM 5
  • it can also be other sequences in which the previous and next 4 bits are inverted, which will not be listed here. enumeration, the first 5 bytes of the AM * sequence are the same for all channels.
  • the originating processing module uses the AM * sequence according to the data processing method given in the corresponding embodiment of Figure 15 to obtain the AMO sequence in the n coded data streams as ⁇ CM 0 , CM 1 , CM 3 , CM 4 , ⁇ , then the receiving processing module can use the complete AMO sequence or AMO ' sequence for inner code synchronization.
  • the receiving end processing module since the first 20 bits and the last 20 bits of the AMO sequence are inverted, it is helpful for the receiving end processing module to simplify the internal code synchronization complexity.
  • the sending end processing module can replace the AM sequence, which enables the receiving end processing module to use a long enough known sequence to synchronize the internal code, which is beneficial to reducing the probability of internal code mis-synchronization and missed locking of the receiving end processing module. The probability.
  • the originating processing module can perform replacement of known sequences at other locations in the data sending process based on the embodiment corresponding to FIG. 15 .
  • the originating processing module can perform replacement of known sequences at other locations in the data sending process based on the embodiment corresponding to FIG. 15 .
  • the AMO sequence is replaced with a balanced random sequence of 0 and 1 with a length of 40 bits and good autocorrelation.
  • this embodiment also proposes two AM sequence replacement methods to reduce the number of consecutive identical PAM4 symbols in the third data stream, thereby reducing the problem of clock wander.
  • the originating processing module replaces the AM sequence in each channel data stream from channel data stream 0 to channel data stream (n/2)-1 among the n channel data streams with an AM * sequence, Replace the AM sequence in each channel data stream from channel data stream n/2 to channel data stream n-1 in n channel data streams with sequence.
  • the AM * sequence is the example (b) shown in Figure 23
  • the sequence is the example (a) shown in Figure 24
  • the AM * sequence is the example (c) shown in Figure 23
  • the sequence is the example (b) shown in Fig. 24.
  • the originating processing module can perform replacement of known sequences at other locations in the data sending process based on the embodiment corresponding to FIG. 15 . For example, after channel replacement, replace the CM p part of the AM p sequence in each of the first data streams 0 to 1 of the n first data streams (n/2)-1 with CM p * , replace the CM p part of the AM p sequence in each of the first data streams n/2 to n-1 among the n first data streams with If the CM p * sequence is the first 8 bytes of the AM * sequence shown in example (b) of Figure 23, then The sequence is shown in Figure 24 example (a) The first 8 bytes of the sequence; if the CM p * sequence is the first 8 bytes of the AM * sequence shown in Figure 23 example (c), then The sequence is shown in Figure 24 example (b) The first 8 bytes of the sequence.
  • the sequence can be any balanced random sequence of 0 and 1 with a length of 40 bits and good autocorrelation, and The sequence is Sequence bit inversion, a possible The sequence is the first 5 bytes of the AM * sequence shown in Figure 23 example (b) or Figure 23 example (c).
  • the originating processing module replaces the AM sequence or the AM p sequence or the AM O sequence, so that the AM in the q*R/2 pieces of coded data streams among the q*R pieces of coded data for channel interleaving
  • the O sequence is different from the AMO sequence in the other q*R/2 encoded data streams, which is beneficial to reducing the number of consecutive identical PAM4 symbols in the third data stream, thereby reducing the effect of clock wander.
  • the data processing device 250 includes a channel replacement module 2501, a convolutional interleaving module 2502, an FEC encoding module 2503 and a channel interleaving module 2504.
  • the channel replacement module 2501 is used to perform a process on every R/2 channel data streams from the first channel data stream set and every R/2 channel data streams from the second channel data stream set among the n channel data streams.
  • the channel replacement process obtains R first data streams, and a total of n first data streams are obtained.
  • the n channel data streams are all subjected to the first forward error correction FEC encoding.
  • the data in the first channel data stream set is different from the second channel data.
  • the data in the stream set come from different first FEC codewords.
  • the consecutive a symbols in the channel data stream come from a different first FEC codewords.
  • the consecutive 2a symbols in the first data stream come from 2a different first FEC codewords.
  • n is an integer greater than 1
  • a is an integer greater than 1
  • R is an even number greater than 1 and n is divisible by R.
  • the convolution interleaving module 2502 is used to perform convolution and interleave processing on each of the n first data streams to obtain n second data streams.
  • the continuous b symbols in the channel data stream come from b different In the first FEC codeword, b is an integer greater than 1, and b can be evenly divided by a.
  • the FEC encoding module 2503 performs a second FEC encoding process on each of the n second data streams to obtain n encoded data streams.
  • the n encoded data streams include S encoded data stream sets.
  • the data processing device 250 also includes an alignment module 2505 and a reordering module 2506.
  • alignment module 2505 Used to align n channel data based on RS code or AM sequence.
  • the reordering module 2506 is used to perform channel reordering on the n channel data streams, so that the n channel data streams are arranged in a preset order.
  • the data processing device 260 may include a processor 2601, a memory 2602 and a transceiver 2603.
  • the processor 2601 is coupled to the memory 2602, and the processor 2601 is coupled to the transceiver 2603.
  • the aforementioned transceiver 2603 may also be called a transceiver unit, a transceiver, a transceiver device, etc.
  • the devices used to implement the receiving function in the transceiver unit can be regarded as the receiving unit
  • the devices used in the transceiver unit used to implement the transmitting function can be regarded as the transmitting unit, that is, the transceiver unit includes a receiving unit and a transmitting unit, and the receiving unit also It can be called a receiver, input port, receiving circuit, etc.
  • the sending unit can be called a transmitter, transmitter, or transmitting circuit, etc.
  • the aforementioned processor 2601 can be a central processing unit (CPU), an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof.
  • the above-mentioned PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a general array logic (GAL) or any combination thereof.
  • the processor 2601 may refer to one processor or may include multiple processors, which is not limited here.
  • the aforementioned memory 2602 is mainly used to store software programs and data.
  • the memory 2602 may exist independently and be connected to the processor 2601.
  • the memory 2602 can be integrated with the processor 2601, for example, integrated into one or more chips.
  • the memory 2602 can store program codes for executing the technical solutions of the embodiments of the present application, and the execution is controlled by the processor 2601.
  • Various types of computer program codes that are executed can also be regarded as drivers of the processor 2601.
  • the memory 2602 may include volatile memory (volatile memory), such as random-access memory (RAM); the memory may also include non-volatile memory (non-volatile memory), such as read-only memory (read- only memory (ROM), flash memory (flash memory), hard disk drive (HDD) or solid-state drive (SSD); the memory 2602 may also include a combination of the above types of memory.
  • volatile memory volatile memory
  • non-volatile memory non-volatile memory
  • ROM read-only memory
  • flash memory flash memory
  • HDD hard disk drive
  • SSD solid-state drive
  • the memory 2602 may refer to one memory or may include multiple memories.
  • memory 2602 is used to store various data. Specifically, please refer to the relevant introduction in the previous embodiments, which will not be described again here.
  • computer-readable instructions are stored in the memory 2602, and the computer-readable instructions include multiple software modules, such as the channel replacement module 2501, the convolutional interleaving module 2502, and the FEC encoding module 2503 introduced in Figure 25. and channel interleaving module 2504, alignment module 2505, reordering module 2506, etc.
  • the channel replacement module 2501 the convolutional interleaving module 2502
  • the FEC encoding module 2503 introduced in Figure 25.
  • channel interleaving module 2504 alignment module 2505, reordering module 2506, etc.
  • Step 2701 Obtain f first data streams.
  • the f first data streams are all subjected to the first forward error correction FEC encoding.
  • f is an integer greater than 1.
  • the f first data streams encoded by the first FEC may include a plurality of first FEC codewords. A consecutive data unit in each of the f first data streams comes from a different first FEC codewords, and a is an integer greater than 1.
  • the first FEC encoding can use RS code.
  • the f first data streams after the first FEC encoding can include multiple RS code words. The consecutive a data units in each first data stream come from a different RS codewords, a is an integer greater than 1. It should be noted that in actual applications, other encoding methods may also be used to perform the first FEC encoding, which is not limited by this application.
  • the value of the first FEC code length in this application may be calculated in units of symbols or in units of bits.
  • a symbol may include one or more bits.
  • the first FEC is RS(544,514)
  • one symbol includes 10 bits.
  • a consecutive data units come from a different first FEC codewords, which may be a consecutive symbols. from a different first FEC codeword.
  • first FEC codewords which may be a consecutive symbols. from a different first FEC codeword.
  • bits 0 to 9 in the first data stream come from codeword 0
  • bits 10 to 19 in the first data stream come from codeword 1
  • bits 20 to 29 in the first data stream come from codeword 2
  • the first data Bits 30 to 39 in the stream come from codeword 3.
  • a consecutive data units come from a different first FEC codewords, which may mean that a consecutive bits come from a different first FEC codewords.
  • a consecutive bits come from a different first FEC codewords.
  • bit 0, bit 1, bit 2 and bit 3 respectively come from different first FECs. Codeword.
  • each first data stream contains an AM p2 sequence at an interval of L 2 symbols, where L 2 is an integer greater than 1.
  • L 2 is an integer greater than 1.
  • the first Y bits in each interval of L 2 symbols in each first data stream are an AM p2 sequence.
  • the originating processing module performs reception processing such as AM locking and AM alignment on the data stream received from the AUI interface.
  • reception processing such as AM locking and AM alignment
  • the originating processing module can also multiplex the data stream received from the AUI interface.
  • each first data stream is a data stream obtained by multiplexing based on g PCS channel data streams
  • the aforementioned AM p2 sequence is directly the AM sequence of the g PCS channel data streams that has been multiplexed.
  • the sequence obtained For example, if the originating device can add an AM sequence to the PCS channel data stream at an interval of L 1 bits, then the process of multiplexing g PCS channel data streams can enable g AMs from the g PCS channel data streams.
  • the sequence is multiplexed into an AM p2 sequence. Therefore, the length of an AM p2 sequence is g times the length of an AM sequence.
  • Table 1 it is an example of the AM sequence of each of the 32 PCS channel data streams.
  • i is an integer less than or equal to 7
  • each byte in Table 2 is transmitted from lsb to msb.
  • the first 96 bits of the AM p2 sequence in each first data stream are the same.
  • the originating processing module can obtain the aforementioned f first data streams through any of the following implementation methods:
  • n/e/2 PCS channel data streams from PCS channel data stream 0 to PCS channel data [(n/2)-1] in the originating device and from the PCS channel data stream n/e/2 PCS channel data streams from n/2 to PCS channel data n-1 are multiplexed into one PMA channel data stream.
  • a total of e PMA channel data streams are obtained, and then these e PMA channel data streams are obtained It is sent to the originating processing module through the connection unit interface AUI.
  • every L 2 symbol interval in each PMA channel data stream contains the AM p2 sequence multiplexed by the AM sequence in the PCS channel data stream.
  • the originating processing module receives e PMA channel data streams from the connection unit interface AUI, and performs AM locking on the AM p2 sequence in each PMA channel data stream to obtain f first data streams.
  • e is the number of physical channels included in the AUI interface
  • f is equal to e. That is to say, the e PMA channel data streams directly received by the originating processing module from the e physical channels of the AUI interface are used as e first data streams (that is, f first data streams). Since each PMA channel data stream received through the physical channel of the AUI interface is a data stream that has been multiplexed in the originating device, therefore, the e first data stream (i.e. the f first data stream) received by the originating processing module Each first data stream in one data stream) is also a multiplexed data stream.
  • e 4 or 8.
  • each physical channel transmits a PMA channel data stream
  • the originating processing module receives from the AUI interface
  • the 4 PMA channel data streams serve as 4 first data streams.
  • Each physical channel transmits a PMA channel data stream, and the originating processing module receives 8 PMA channels from the AUI interface.
  • the data streams are as 8 first data streams.
  • each first data stream is a data stream obtained by performing multiplexing processing based on bit granularity or multiplexing processing based on symbol granularity based on g PCS channel data streams. Since the originating processing module treats the received PMA channel data stream as the first data stream, the multiplexing process of the PMA channel data stream is the multiplexing process of the first channel data stream. If each PMA channel data stream received by the originating processing module through the physical channel of the AUI interface is a data stream obtained by performing bit-granularity multiplexing processing on g PCS channel data streams in the originating device, then each first data stream A stream is a data stream obtained by performing multiplexing processing based on bit granularity based on g PCS channel data streams.
  • each PMA channel data stream received by the originating processing module through the physical channel of the AUI interface is a data stream obtained by performing multiplexing processing based on symbol granularity based on g PCS channel data streams in the originating device, then each first data stream The stream is a data stream obtained by multiplexing processing based on symbol granularity based on g PCS channel data streams.
  • the originating device will multiplex every 4 PCS channel data streams among the 32 PCS channel data streams based on symbol granularity. Or based on bit-granularity multiplexing processing, 8 PMA channel data streams are obtained. Then, the originating device sends the aforementioned 8 PMA channel data to the originating processing module through the 8 physical channels of the aforementioned AUI interface. The originating processing module receives the 8 PMA channel data streams through the AUI, and analyzes the AM in each PMA channel data stream. The p2 sequence is locked to obtain 8 first data streams.
  • the aforementioned a data units are a symbols, that is, the consecutive a symbols in each first data stream come from a different first data streams. FEC codeword. If the multiplexing process is a multiplexing process based on bit granularity, the aforementioned a data unit is a bit, that is, the continuous a bits in each first data stream come from a different first FEC codewords.
  • the originating device multiplexes any n/e PCS channel data streams into one PMA channel data stream, obtaining a total of e PMA channel data streams, and then these e PMA channel data streams are obtained It is sent to the originating processing module through the connection unit interface AUI. There is no guarantee that consecutive a symbols on each PMA channel data stream contain a RS codeword.
  • the originating processing module first performs the first demultiplexing process on the e PMA channel data streams received from the connection unit interface AUI, and obtains n PCS channel data streams, where e is the physical data stream contained in the AUI interface.
  • the originating processing module performs AM locking and AM alignment on the AM sequences in the multiple PCS channel data streams, and then performs the first multiplexing process on each g PCS channel data stream in the n PCS channel data streams.
  • obtain the f first data streams the f is equal to n/g, the f is greater than or equal to e, among the g multiplexed data streams, g/2 are from PCS channel data streams 0 to PCS channel data stream [(n/2)-1], and another g/2 from PCS channel data stream n/2 to PCS channel data stream n-1; the AM alignment can also be called deskew (de-skew), at this time, the AM p2 sequence in the first data stream is directly multiplexed from the AM sequence in the PCS channel data stream.
  • g 2 or 4 or 8.
  • the originating processing module first receives 8 PMA channel data streams from the 8 physical channels of the AUI, and performs the first demultiplexing process on the 8 PMA channel data streams to obtain 32 PCS channel data streams. Then, the originating processing module performs AM locking and AM alignment on the 32 PCS channel data streams, and then performs first multiplexing processing on every 4 PCS channel data streams among the 32 PCS channel data streams, resulting in 8 first data streams.
  • two of the four multiplexed PCS channel data streams are from PCS channel data stream 0 to PCS channel data stream 15, and the other two are from PCS channel data stream 16 to PCS channel data stream 31.
  • the originating processing module first receives 8 PMA channel data streams from the 8 physical channels of the AUI, and performs the first demultiplexing process on the 8 PMA channel data streams to obtain 32 PCS channel data streams. Then, the originating processing module performs AM locking and AM alignment on the 32 PCS channel data streams, and then performs first multiplexing processing on every 2 PCS channel data streams among the 32 PCS channel data streams, resulting in 16 first data streams. ;
  • One of the four multiplexed PCS channel data streams comes from PCS channel data stream 0 to PCS channel data stream 15, and the other one comes from PCS channel data stream 16 to PCS channel data stream 31.
  • the PMA channel data stream received by the originating end processing module may be a data stream obtained based on bit-granularity multiplexing processing, or may be a data stream obtained based on symbol-granularity multiplexing processing.
  • bit-granularity multiplexing processing or may be a data stream obtained based on symbol-granularity multiplexing processing.
  • each PMA channel data stream is a data stream obtained by performing bit-granularity-based multiplexing processing on n/e PCS channel data streams
  • the first demultiplexing process is based on bit-granularity-based multiplexing.
  • the originating processing module first receives 8 PMA channel data streams from the 8 physical channels of the AUI.
  • each PMA channel data stream is a data stream obtained based on multiplexing processing with a bit granularity of 4:1 (that is, Every 4 PCS channel data streams among the 32 PCS channel data streams are multiplexed according to bit granularity is 1 PMA channel data stream), then the originating processing module performs demultiplexing processing on each of the 8 PMA channel data streams based on a bit granularity of 1:4, resulting in 32 PCS channel data streams.
  • the originating processing module performs AM locking and AM alignment on the 32 PCS channel data streams
  • the originating processing module multiplexes the 32 PCS channel data streams based on 4:1 symbol granularity (that is, the 32 PCS channel data Every 4 PCS channel data streams in the stream are multiplexed into 1 first data stream according to symbol granularity), resulting in 8 first data streams.
  • each PMA channel data stream is a data stream obtained by symbol-granularity multiplexing based on n/e PCS channel data streams
  • the first demultiplexing process is symbol-based. granular demultiplexing process
  • the originating processing module first receives 8 PMA channel data streams from the 8 physical channels of the AUI.
  • each PMA channel data stream is a data stream obtained based on multiplexing processing with a symbol granularity of 4:1 (that is, Every 4 PCS channel data streams among the 32 PCS channel data streams are multiplexed into 1 PMA channel data stream according to symbol granularity), then the originating processing module performs 1-based processing on each of the 8 PMA channel data streams. :4 symbol granularity demultiplexing processing to obtain 32 PCS channel data streams.
  • the originating processing module performs AM locking and AM alignment on the 32 PCS channel data streams
  • the originating processing module multiplexes the 32 PCS channel data streams based on 2:1 symbol granularity (that is, the 32 PCS channel data Every two PCS channel data streams in the stream are multiplexed into one first data stream according to symbol granularity), resulting in 16 first data streams.
  • the aforementioned first multiplexing process is a multiplexing process based on symbol granularity
  • the aforementioned a data units are a symbols, that is, the consecutive a symbols in each first data stream come from a different The first FEC codeword.
  • the originating processing module when it performs AM locking and AM alignment processing on AM sequences in multiple PCS channel data, it can perform AM locking and AM alignment processing on n PCS channel data streams, that is, n PCS channels are required
  • the AM sequences in the data stream are completely aligned; it can also be performed on AM locking and AM alignment processing for each group of n PCS channel data streams from the same physical channel of the AUI.
  • the PCS channel data flow of the physical channel does not need to be completely aligned.
  • the PCS channel data stream is first reordered, and then the PCS channel data stream is symbol multiplexed.
  • the format of the first data stream is as shown in example (a) of Figure 30.
  • Each continuous 4-bit data comes from a different first FEC codeword, and each The continuous 2720-bit data contains 4 first FEC codewords.
  • the format of the first data stream is as shown in example (b) of Figure 30.
  • the data of each consecutive 4 symbols comes from a different first FEC codeword, and, Each consecutive 272 symbols contains 4 first FEC codewords.
  • Step 2702 Convolve and interleave each consecutive X symbols in each of the f first data streams as a convolutional interleaving block to obtain f second data streams.
  • the second data stream contains one AM o2 sequence every L 3 symbols, and the AM o2 sequence is the first X symbols of the AM p2 sequence.
  • L 3 is an integer greater than 1, and L 3 can be divided by L 2 .
  • the originating processing module inputs each consecutive T*L 2 symbols in each first data stream into p delay lines of the convolutional interleaver in units of X symbols, round-robin, Get the second data stream.
  • the first Y symbols of each consecutive T*L 2 symbols are the AM p2 sequence
  • the L 3 T*L 2
  • the T*L 2 can be evenly divided by X*p.
  • the specific structure of the convolutional interleaver is shown in Figure 32A.
  • the total delay of 800GE service interleaving and deinterleaving is about 52ns.
  • the first 12 convolutional interleaving blocks of the 835584 convolutional interleaving blocks are AMP2 sequences.
  • the continuous 835584 convolution interleave blocks are polled and input into delay line 0 to delay line 2 of the convolution interleaver shown in Figure 32A, that is, the 0th convolution interleave block is input into delay line 0, the 1st convolution interleave block is input into delay line 1, the 2nd convolution interleave block is input into delay line 2, the 3rd convolution block is input into delay line 0, the 4th convolution block is input into delay line 1, the 5th convolution block is input into delay line 2, and so on.
  • the 835584 convolution interleave blocks can be polled and input into the convolution interleaver shown in Figure 32A an integer number of times.
  • the known AMP2 sequence can appear periodically, which is conducive to locking the AMP2 sequence in the receiving device after completing the inner code decoding, and then sending the convolution interleaving block where the AMP2 sequence is located to the required delay line of the deconvolution interleaver, so as to complete the synchronization of deconvolution.
  • the transmitting processing module performs convolution interleaving
  • the AMO2 sequence is output from the delay line 0 of the convolution interleaver shown in FIG32A.
  • the convolution interleave block corresponding to the AMO2 sequence is sent to the delay line 3 of the convolution interleaver of the structure shown in FIG32A, and the subsequent convolution interleave blocks are sent to the delay line 2 and the delay line 0 in turn, and so on.
  • g 8 or 4 or 2.
  • the 7 delay lines include 6Q storage units, 5Q storage units, 4Q storage units, 3Q storage units, 2Q storage units, 1Q storage units and 0 storage units respectively.
  • Each storage unit is used for storage.
  • X 2 symbols (i.e. 20 bits, i.e. one convolutional interleaving block).
  • the symbols are from 14 different RS codewords.
  • the first 24 convolutional interleaving blocks among the 3899392 convolutional interleaving blocks are AM P2 sequences. Then, convert this continuous The 3899392 convolutional interleaving blocks are polling input to delay line 0 to delay line 7 of the convolutional interleaver as shown in Figure 32B, that is, the 0th convolutional interleaving block is input to delay line 0, and the 1st convolutional interleaving block is input to delay line 0.
  • the interleaved block is input to delay line 1, the 2nd convolutional interleaved block is input to delay line 2, the 3rd convolutional block is input to delay line 3, the 4th convolutional block is input to delay line 4, and the 4th convolutional block is input to delay line 4.
  • the 5 convolution blocks are input to delay line 5, the 6th convolution block is input to delay line 6, the 7th convolution block is input to delay line 0, and so on.
  • 3899392 convolutional interleaving blocks can be input into the convolutional interleaver shown in Figure 32B in an integer number of polls.
  • the first data stream undergoes convolutional interleaving After processing the second data stream, the first The specific data is the first 2 symbols of the AMP2 sequence. That is to say, after convolution interleaving processing, the known AM O2 sequence will appear periodically in the first data stream, which is conducive to the receiving device to lock the AM O2 sequence after completing the inner code decoding, and then lock the AM O2 sequence.
  • the convolution interleaving block where the O2 sequence is located is sent to the required delay line of the deconvolution interleaver, and the deconvolution synchronization can be completed.
  • the transmitting end processing module performs convolutional interleaving
  • the AM O2 sequence is output from the delay line 0 of the convolutional interleaver shown in Figure 32B
  • the receiving end module deconvolutionally interleaves
  • the product interleaving block is sent to the delay line 6 of the convolutional interleaver with the structure shown in Figure 32B, and the following convolutional interleaving blocks are sent to the delay line 5 in turn, and so on.
  • the convolutional interleaving delay line 0 to delay line 3 polls the 16 RS symbols output at a time from 16 different RS codewords.
  • L3 L2 .
  • the first 24 convolutional interleaving blocks among the 557056 convolutional interleaving blocks are AMP2 sequences.
  • the continuous 557056 convolutional interleaving blocks are pollingly input to the delay line 0 to delay line 3 of the convolutional interleaver as shown in Figure 32C, that is, the 0th convolutional interleaving block is input to the delay line 0, and The first convolutional interleaving block is input to delay line 1, the second convolutional interleaving block is input to delay line 2, the third convolutional block is input to delay line 0, and so on, 557056 convolutional interleaving blocks can be An integer number of polls are input to the convolutional interleaver shown in Figure 32C.
  • the first data stream undergoes convolutional interleaving processing to obtain After the second data stream, the first The first 4 symbols of the AM P2 sequence. That is to say, after convolutional interleaving processing, the known AM O2 sequence will appear periodically in the first data stream, which is beneficial to the receiving device to lock the AM O2 sequence after completing the inner code decoding, and then lock the AM O2 sequence.
  • the convolution interleaving block where the O2 sequence is located is sent to the required delay line of the deconvolution interleaver, and the deconvolution synchronization can be completed.
  • the transmitting end processing module performs convolutional interleaving
  • the AM O2 sequence is output from the delay line 0 of the convolutional interleaver shown in Figure 32C
  • the receiving end module deconvolutionally interleaves
  • the convolution corresponding to the AM O2 sequence The product interleaving block is sent to the delay line 6 of the convolution interleaver with the structure shown in Figure 32C, and the following convolution interleaving blocks are sent to the delay line 5 in turn, and so on.
  • Step 2703 Use each K consecutive bits in each of the f second data streams as a coding block to perform a second FEC encoding process to obtain f coded data streams.
  • K is the length of the continuous second FEC codeword information bit
  • the K is an integer greater than 1.
  • K 120, 136 or 160.
  • the originating end processing module After the convolutional interleaving process, the originating end processing module performs a second FEC encoding (also called inner code encoding) process on each second data stream. Specifically, the originating processing module performs second FEC encoding on L 3 consecutive symbols in each second data stream to obtain c second FEC codewords. Among them , the first *10)/K, the c is an integer greater than 1.
  • the transmitting end processing module needs to use AMO2 when performing the second FEC encoding (i.e., the inner codeword).
  • the sequence is synchronized with the second FEC codeword (ie, inner codeword), that is, the AM O2 sequence is fixed to a fixed position of the second FEC codeword (ie, inner codeword).
  • Figure 35A, Figure 35B and Figure 35C respectively show several encoding implementation methods of fixed AM O2 sequences provided by this application.
  • the receiving processing module can perform inner encoding based on the AM O2 sequence in the encoded data stream. Codeword synchronization and deconvolutional interleaver synchronization.
  • K 136 bits, that is, the length of the second FEC codeword information bit is 136 bits.
  • the originating processing module uses the AM O2 sequence (i.e., 4 RS symbols) as the starting position to divide each continuous 136 bits in the second data stream into an inner code information block (i.e., the second FEC information block) , then the data between two consecutive AM O2 sequences is divided into 245760 inner code word information blocks. Then, 8 bits of redundant information are added to each inner code information block to obtain a 144-bit inner code word.
  • K 120 bits, that is, the length of the second FEC codeword information bit is 120 bits.
  • the originating processing module uses the AM O2 sequence (i.e., 4 RS symbols) as the starting position to divide each consecutive 120 bits of the second data stream into an inner code information block (i.e., the second FEC information block). Then the data between two consecutive AM O2 sequences is divided into 278528 inner code word information blocks. Then, 8 bits of redundant information are added to each inner code information block to obtain a 128-bit inner code word.
  • K 160 bits, that is, the length of the second FEC codeword information bit is 160 bits.
  • the originating processing module uses the AM O2 sequence (i.e., 4 RS symbols) as the starting position to divide each continuous 160 bits of the second data stream into an inner code information block (i.e., the second FEC information block). Then the data between two consecutive AM O2 sequences is divided into 208896 inner code word information blocks. Then, 16 bits of redundant information are added to each inner code information block to obtain a 176-bit inner code word.
  • the originating processing module can be aligned with the AM p2 sequence during the convolution interleaving process and with the AM o2 sequence during the inner code encoding process. This can be achieved without adding additional redundant information. Known sequences appear periodically in the second data stream and the encoded data stream, so that the receiving end processing module can use this periodic known sequence to synchronize the inner code, which in turn helps reduce the processing complexity of the receiving end.
  • the data processing device 360 includes a reception processing module 3601, a convolutional interleaving module 3602, and an FEC encoding module 3603. Among them, the reception processing module 3601 is used to obtain f first data streams. The f first data streams have all undergone first forward error correction FEC encoding.
  • a consecutive data units in the first data stream come from a different The first FEC codeword, each interval of L 2 symbols in each first data stream contains an AM p2 sequence, the length of the AM p2 sequence is Y symbols, and at least the first X of the AM p2 sequence in the f first data streams symbols are the same, the last (YX) symbols are different from each other, f is an integer greater than 1, a is an integer greater than 1, L 2 is an integer greater than 1, X is an integer.
  • the convolution interleaving module 3602 is used to perform convolution and interleave processing on each consecutive X symbols in each of the f first data streams as a convolution interleave block to obtain f second data streams, and the second The data stream contains an AM o2 sequence every L 3 symbols.
  • the AM o2 sequence is the first X symbols of the AM p2 sequence.
  • L 3 is an integer greater than 1.
  • L 3 can be evenly divided by L 2 .
  • the FEC encoding module 3603 is used to perform the second FEC encoding process on each consecutive K bits in each of the f second data streams as a coding block to obtain f coded data streams. 10 times L 3 can be K is evenly divisible, K is the length of the continuous second FEC codeword information bit, and K is an integer greater than 1.
  • the convolutional interleaving module 3602 is specifically configured to poll and input each consecutive T*L 2 symbols in each first data stream to the convolutional interleaver in units of X symbols. In p delay lines, the second data stream is obtained.
  • the FEC encoding module 3603 is specifically configured to perform second FEC encoding on L 3 consecutive symbols in each second data stream to obtain c second FEC codewords, L 3 consecutive symbols. The first
  • each first data stream is a data stream obtained based on multiplexing of g PCS channel data streams
  • the AM p2 sequence is an AM sequence of g PCS channel data streams that has been multiplexed.
  • the length Y of the AM p2 sequence is g times the length of the AM sequence.
  • the reception processing module 3601 is specifically configured to receive e PMA channel data streams from the connection unit interface AUI, and perform AM locking on the AM p2 sequence in each PMA channel data stream to obtain f first Data stream, e is the number of physical channels included in the AUI interface, and f is equal to e.
  • Each first data stream is obtained by performing bit-granularity-based multiplexing processing or symbol-granularity-based multiplexing processing based on g PCS channel data streams.
  • the a data unit is a bit; if each of the first data streams If the first data stream is multiplexed based on symbol granularity based on the g PCS channel data streams, then the a data units are a symbols.
  • the reception processing module 3601 is specifically configured to perform a first demultiplexing process on e PMA channel data streams received from the connection unit interface AUI, to obtain n PCS channel data streams, where e is the AUI interface.
  • the number of physical channels included perform AM locking and AM alignment on the n PCS channel data streams, and then perform the first multiplexing process on each g PCS channel data stream among the n PCS channel data streams to obtain f first data Flow, f equals n/g, f is greater than or equal to e.
  • each PMA channel data stream is a data stream obtained by performing bit-granularity-based multiplexing processing based on n/e PCS channel data streams.
  • the first demultiplexing process is bit-granularity-based demultiplexing processing.
  • the first multiplexing process is multiplexing based on symbol granularity, and the a data unit is a symbol; or, each PMA channel data stream is multiplexed based on symbol granularity based on n/e PCS channel data streams.
  • the first demultiplexing process is a demultiplexing process based on symbol granularity
  • the first multiplexing process is a multiplexing process based on symbol granularity
  • the a data unit is a bit.
  • the data processing device 370 may include a processor 3701, a memory 3702 and a transceiver 3703. Wherein, the processor 3701 is coupled and connected with the memory 3702, and the processor 3701 is coupled and connected with the transceiver 3703.
  • the aforementioned transceiver 3703 may also be called a transceiver unit, a transceiver, a transceiver device, etc.
  • the devices used to implement the receiving function in the transceiver unit can be regarded as the receiving unit
  • the devices used in the transceiver unit used to implement the transmitting function can be regarded as the transmitting unit, that is, the transceiver unit includes a receiving unit and a transmitting unit, and the receiving unit also It can be called a receiver, input port, receiving circuit, etc.
  • the sending unit can be called a transmitter, transmitter, or transmitting circuit, etc.
  • the aforementioned processor 3701 can be a central processing unit (CPU), an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof.
  • the above-mentioned PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a general array logic (GAL) or any combination thereof.
  • the processor 3701 may refer to one processor or may include multiple processors, which is not limited here.
  • the aforementioned memory 3702 is mainly used to store software programs and data.
  • the memory 3702 may exist independently and be connected to the processor 3701.
  • the memory 3702 can be integrated with the processor 3701, for example, integrated into one or more chips.
  • the memory 3702 can store program codes for executing the technical solutions of the embodiments of the present application, and the execution is controlled by the processor 3701.
  • Various types of computer program codes that are executed can also be regarded as drivers of the processor 3701.
  • the memory 3702 may include volatile memory (volatile memory), such as random-access memory (RAM); the memory may also include non-volatile memory (non-volatile memory), such as read-only memory (read- only memory, ROM), flash memory (flash memory), hard disk drive (hard disk drive, HDD) or solid-state drive (solid-state drive, SSD); the memory 3702 may also include a combination of the above types of memory.
  • volatile memory such as random-access memory (RAM)
  • non-volatile memory such as read-only memory (read- only memory, ROM), flash memory (flash memory), hard disk drive (hard disk drive, HDD) or solid-state drive (solid-state drive, SSD); the memory 3702 may also include a combination of the above types of memory.
  • the memory 3702 may refer to one memory or may include multiple memories.
  • memory 3702 is used to store various data. Specifically, please refer to the relevant introduction in the previous embodiments, which will not be described again here.
  • computer readable instructions are stored in the memory 3702, and the computer readable instructions include multiple software modules, for example, the reception processing module 3601, the convolution interleaving module 3602 and the FEC encoding module introduced in Figure 36. 3603 etc.
  • the reception processing module 3601 the convolution interleaving module 3602
  • the present application provides a computer program product including one or more computer instructions.
  • the processes or functions according to the embodiments of the present application are generated in whole or in part. For example, methods related to the data processing devices in FIG. 3, FIG. 11A, FIG. 13A, FIG. 14A, FIG. 15, and FIG. 27 are implemented.
  • the computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable device.
  • the computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted over a wired connection from a website, computer, server, or data center (for example, coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (for example, infrared, wireless, microwave, etc.) means to transmit to another website, computer, server or data center.
  • the computer-readable storage medium can be any available medium that a computer can store, or a data storage device such as a server or data center integrated with one or more available media.
  • the available media may be magnetic media (e.g., floppy disks, hard disks, tapes), optical media (e.g., digital versatile discs (DVD)), or semiconductor media (e.g., solid state disks (SSD)) wait.
  • this application also provides a computer-readable storage medium, which stores a computer program, and the computer program is executed by the processor to implement the aforementioned Figures 3, 11A, 13A, 14A, 15, and Methods related to the data processing device in 27.
  • the size of the sequence numbers of the above-mentioned processes does not mean the order of execution.
  • the execution order of each process should be determined by its functions and internal logic, and should not be used in the embodiments of the present application.
  • the implementation process constitutes any limitation. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be described again here.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)

Abstract

本申请公开了一种数据处理方法以及数据处理装置，由于，能够将来自第一通道数据流集合的R/2条通道数据流与来自第二通道数据流集合的R/2条通道数据流进行通道置换处理得到R条第一数据流，以使得同一通道数据流中的数据被分散到不同的第一数据流。然后，将基于R条第一数据流获得的R条编码数据流通过信道交织入同一条第三数据流。因此，来自某一通道数据流的数据即使通过通道置换被分散到不同的第一数据流，也能够通过信道交织处理交织入同一条第三数据流，进而被传输到同一物理信道上。因此，不会对同一通道数据流带来传输延迟不一致的问题，可以避免收端处理模块对通道数据流进行对齐处理，有效降低收端处理模块的复杂度。

Description

一种数据处理方法以及数据处理装置
本申请要求于2022年09月15日提交中国国家知识产权局、申请号为202211124570.2、申请名称为“一种数据处理方法以及数据处理装置”的中国专利申请的优先权，以及，要求于2022年11月19日提交中国国家知识产权局、申请号为202211451013.1、申请名称为“一种数据处理方法以及数据处理装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及通信领域，尤其涉及一种数据处理方法以及数据处理装置。
背景技术
在5G、云计算、大数据和人工智能等持续推动下，光通信系统及光传输网(optical transport network，OTN)正朝着大容量和超高速方向发展。采用前向纠错编码(forward error correction，FEC)对传输的数据进行纠错，能够解决传输误码，从接收数据中恢复出发送端发送的原始数据。
当前提出有一种级联FEC的传输方案，发端设备和发端处理模块通过连接单元接口(attachment unit interface，AUI)连接。发端设备对待传输数据进行第一FEC编码，并将第一FEC编码后的数据发送至发端处理模块。发端处理模块先对第一FEC编码后的数据进行级联编码交织再进行第二FEC编码，并将第二FEC编码后的比特序列进行调制映射生成对应的调制符号序列，最后将生成的调制符号序列通过光传输网络传送到接收端。接收端对接收到的调制符号序列进行解调和解码后，可以得到发送端发送的信息。
由于，发端处理模块会收到多路数据流，要分别先对多路数据流先进行卷积交织，再对卷积交织后的每一路数据流进行第二FEC编码，得到多条第二FEC编码后的比特序列，再分别进行调制映射生成对应的多条调制符号序列。然而，当采用直检检测方案时，可能存在多条调制符号序列到达收端处理模块不同步的问题，进而增加了收端处理模块的处理复杂度。
发明内容
本申请提供了一种数据处理方法以及数据处理装置，用于降低收端处理模块的处理复杂度。
第一方面，本申请提供了一种数据处理方法，该数据处理方法应用于发端处理模块中。首先，发端处理模块对n条通道数据流中每R/2条来自第一通道数据流集合的通道数据流与每R/2条来自第二通道数据流集合的通道数据流进行通道置换处理得到R条第一数据流，总共得到n条第一数据流，n条通道数据流都经过第一前向纠错FEC编码，第一通道数据流集合中的数据与第二通道数据流集合中的数据来自不同的第一FEC码字，通道数据流中连续的a个符号来自a个不同的第一FEC码字，第一数据流中连续的2a个符号来自2a个不同的第一FEC码字，n为大于1的整数，a为大于1的整数，R为大于1的偶数且n能被R整除；然后，发端处理模块对n条第一数据流中的每条第一数据流进行卷积交织处理得到n条第二数据流，第二数据流中连续的b个符号来自b个不同的第一FEC码字，b为大于1的整数，b能被a整除；然后，发端处理模块对n条第二数据流中每条第二数据流进行第二FEC编码处理得到n条编码数据流，n条编码数据流包括S个编码数据流集合，每个编码数据流集合包括R条编码数据流，R条编码数据流的数据来自R条进行通道置换的通道数据流，R条进行通道置换的通道数据流包括R/2条来自第一通道数据流集合的通道数据流和R/2条来自第二通道数据流集合的通道数据流，S＝n/R；然后，发端处理模块将n条编码数据流中每q个编码数据流集合进行信道交织为1条第三数据流，总共得到m条第三数据流，其中，m＝S/q，q为大于0的整数，且，S能被q整除。
本实施例中，由于，n条通道数据流中第一通道数据流集合中的数据与第二通道数据流集合中的数据来自不同的第一FEC码字，对来自第一通道数据流集合的R/2条通道数据流与来自第二通道数据流集合的R/2条通道数据流进行通道置换处理，能够将第一通道数据流集合的R/2条通道数据流中每条通道数据流的部分数据与第二通道数据流集合的R/2条通道数据流中每条通道数据流的部分数据进行置换，得到R条第一数据流，以使得同一通道数据流中的数据被分散到不同的第一数据流。然后，再对前述每条第一 数据流分别进行卷积交织处理和第二FEC编码处理，而获得R条编码数据流，在将前述R条编码数据流通过信道交织入同一条第三数据流。因此，通过通道置换而被分散到R条第一数据流中的数据，又通过信道交织处理交织入同一条第三数据流。也就是说，来自某一通道数据流的数据即使通过通道置换被分散到不同的第一数据流，也能够通过信道交织处理交织入同一条第三数据流，进而被传输到同一物理信道上，因此，不会对同一通道数据流带来传输延迟不一致的问题，进而可以避免收端处理模块对通道数据流进行对齐处理，有效降低收端处理模块的复杂度。
可选的，R＝2或4。发端处理模块对n条通道数据流进行通道置换处理可以采用如下任意一种实施方式：
在一种可能的实施方式中，R＝2，发端处理模块可以对n条通道数据流中每1条来自第一通道数据流集合的通道数据流与每1条来自第二通道数据流集合的通道数据流进行通道置换处理得到2条第一数据流，总共得到n条第一数据流。
示例性的，发端处理模块可以对通道数据流i与通道数据流i+(n/2)进行通道置换，得到2条第一数据流，其中，i为大于等于0且小于n/2的整数。其中，通道数据流i来自一个通道数据流集合(例如，第一通道数据流集合)，而通道数据流i+(n/2)来自另一个通道数据流集合(例如，第二通道数据流集合)。例如，n＝32，发端处理模块可以对通道数据流i与通道数据流i+16进行通道置换，得到2条第一数据流，其中，0≤i<16，即通道数据流0到通道数据流15分别与通道数据流16到通道数据流31进行通道置换得到各自对应的2条第一数据流，总共得到32条数据流。
在另一种可能的实施方式中，R＝4，发端处理模块可以对n条通道数据流中每2条来自第一通道数据流集合的通道数据流与每2条来自第二通道数据流集合的通道数据流进行通道置换处理得到4条第一数据流，总共得到n条第一数据流。
示例性的，发端处理模块可以对通道数据流i0、通道数据流i1、通道数据流i2、通道数据流i3进行通道置换，得到4条第一数据流。其中，通道数据流i0、通道数据流i1、通道数据流i2、通道数据流i3中的任意两条通道数据流来自第一通道数据流集合，而另外两条通道数据流来自第二通道数据流集合。例如，通道数据流i0和通道数据流i1来自第一通道数据流集合，通道数据流i2和通道数据流i3来自第二通道数据流集合。其中，n＝32，前述i1＝i0+8，前述i2＝i0+16，前述i3＝i0+24，其中，0≤i0<7，且，i0为整数。例如，发端处理模块可以对通道数据流0、通道数据流8、通道数据流16、通道数据流24进行通道置换，得到4条第一数据流。又例如，发端处理模块可以对通道数据流1、通道数据流9、通道数据流17、通道数据流25进行通道置换，得到4条第一数据流。又例如，发端处理模块可以对通道数据流2、通道数据流10、通道数据流18、通道数据流26进行通道置换，得到4条第一数据流。又例如，发端处理模块可以对通道数据流3、通道数据流11、通道数据流19、通道数据流27进行通道置换，得到4条第一数据流。又例如，发端处理模块可以对通道数据流4、通道数据流12、通道数据流20、通道数据流28进行通道置换，得到4条第一数据流。又例如，发端处理模块可以对通道数据流5、通道数据流13、通道数据流21、通道数据流29进行通道置换，得到4条第一数据流。又例如，发端处理模块可以对通道数据流6、通道数据流14、通道数据流22、通道数据流30进行通道置换，得到4条第一数据流。又例如，发端处理模块可以对通道数据流7、通道数据流15、通道数据流23、通道数据流31进行通道置换，得到4条第一数据流。
可选的，n＝32；R＝2或4；q＝1、2或4；S＝8或16；m＝4或8；q*R＝4或8。发端处理模块将n条编码数据流中每q个编码数据流集合进行信道交织为1条第三数据流，总共得到m条第三数据流，具体可以采用如下任意一种实施方式：
在一种可能的实施方式中，若n＝32，q*R＝4，m＝8，则发端处理模块可以将编码数据流i0、编码数据流i1、编码数据流i0+(n/2)、编码数据流i1+(n/2)共4条编码数据流进行信道交织为1条第三数据流，其中，0≤i0≤15，0≤i1≤15。
在一种示例中，若R＝2，则q＝2，即发端处理模块将32条编码数据流中每2个包含2条编码数据流的编码数据流集合进行信道交织为1条第三数据流，总共得到8条第三数据流。
在另一种示例中，若R＝4，则q＝1，即发端处理模块将32条编码数据流中每1个包含4条编码数据 流的编码数据流集合进行信道交织为1条第三数据流，总共得到8条第三数据流。
在另一种可能的实施方式中，若n＝32，q*R＝8，m＝4，则发端处理模块可以将编码数据流i0、编码数据流i1、编码数据流i2、编码数据流i3、编码数据流i0+(n/2)、编码数据流i1+(n/2)、编码数据流i2+(n/2)和编码数据流i3+(n/2)进行信道交织为1条第三数据流；其中，0≤i0≤15，0≤i1≤15，0≤i2≤15，0≤i3≤15。可选的，i1＝i0+1，i2＝i0+2，i3＝i0+3，其中，i0＝0、4、8或12；或者，i1＝i0+4，i2＝i0+8，i3＝i0+12；其中，i0＝0、1、2或3。
在一种示例中，若R＝2，则q＝4，即发端处理模块将32条编码数据流中每4个包含2条编码数据流的编码数据流集合进行信道交织为1条第三数据流，总共得到4条第三数据流。
在另一种示例中，若R＝4，则q＝2，即发端处理模块将32条编码数据流中每2个包含4条编码数据流的编码数据流集合进行信道交织为1条第三数据流，总共得到4条第三数据流。
本申请中的该数据处理方法还可以对数据进行加扰处理，可以在不需要增加额外的冗余信息的情况下便于收端处理模块进行第二FEC码字的同步，有利于降低第二FEC码字误同步和误失锁的概率，提高同步的可靠性。具体可以采用如下任意一种实施方式进行加扰处理：
在一种可能的实施方式中，发端处理模块发端处理模块将n条编码数据流中每q个编码数据流集合进行信道交织为1条第三数据流，总共得到m条第三数据流之前，该方法还包括：发端处理模块采用长度为Q*N比特的伪随机二进制序列(pseudo random binary sequence，PRBS)对每条编码数据流中的Q个连续第二FEC码字进行加扰处理，得到加扰后的n条编码数据流，N为第二FEC码字长度，N为大于1的整数，Q为大于或等于1的整数。
示例性的，Q为大于等于8或小于等于16的整数。
本实施方式中，对第二FEC编码(即内码编码)后的编码数据流进行加扰处理，有利于降低第二FEC码字误锁定和误失锁的概率。
在另一种可能的实施方式中，发端处理模块将n条编码数据流中每q个编码数据流集合进行信道交织为1条第三数据流，总共得到m条第三数据流之后，该方法还包括：发端处理模块采用长度为R*q*Q*N比特的PRBS序列对每条第三数据流中连续的R*q*Q*N比特进行加扰处理，得到加扰后的m条第三数据流，第三数据流中连续的R*q*Q*N比特为R*q条编码数据流中各连续Q个第二FEC码字进行信道交织而生成的R*q*Q*N比特，N为大于1的整数，Q为大于或等于1的整数。
示例性的，Q为大于等于8或小于等于16的整数。
本实施方式中，对信道交织后的第三数据流进行加扰处理，有利于降低第二FEC码字误锁定和误失锁的概率。
在另一种可能的实施方式中，发端处理模块对n条第二数据流中每条第二数据流进行第二FEC编码处理得到n条编码数据流之前，该方法还包括：发端处理模块采用长度为Q*K比特的PRBS序列对每条第二数据流中的Q个连续第二FEC码字进行加扰处理，得到加扰后的n条第二数据流，K为连续第二FEC码字信息位的长度，K为大于1的整数，Q为大于或等于1的整数。
示例性的，Q为大于等于8或小于等于16的整数。
本实施方式中，对卷积交织后的第二数据流进行加扰处理，有利于降低第二FEC码字误锁定和误失锁的概率。
此外，在一种可能的实施方式中，发端处理模块对n条通道数据流中每R/2条来自第一通道数据流集合的通道数据流与每R/2条来自第二通道数据流集合的通道数据流进行通道置换处理得到R条第一数据流，总共得到n条第一数据流之前，该方法还包括：发端处理模块对n条通道数据流进行通道重排序，以使得所述n条通道数据流按照预设顺序排列。
在一种可能的实施方式中，发端处理模块对n条通道数据流进行通道重排序之前，该方法还包括：发端处理模块对n条通道数据流进行对齐处理，其中，该对齐处理是基于外码符号的对齐处理，或者，基于AM序列的对齐处理。其中，AM序列为通道数据流中携带的AM序列。
在一种可能的实施方式中，n条第一数据流中每条第一数据流每间隔L1个比特包括一条AMp序列，AMp序列包括15个字节；其中，每条第一数据流中的AMp序列的前8个字节与对应的通道数据流中的 AM序列的前8个字节相同，每条第一数据流中的AMp序列的后7个字节与对应的通道数据流中的AM序列的后7个字节不同，不同的第一数据流中的AMp序列的后7个字节各不相同。
在一种可能的实施方式中，发端处理模块对n条第一数据流中的每条第一数据流进行卷积交织处理得到n条第二数据流，包括：发端处理模块将每条第一数据流中的每连续的T*L1个符号以d个符号为单位轮询输入到卷积交织器的p个延迟线中，得到第二数据流，每连续的T*L1个符号的前t个比特为AMp序列，第二数据流每间隔L2符号包含一条AMo序列，AMo序列为AMp序列的前d个符号，L2＝T*L1，T*L1能被d*p整除。
可选的，d＝4；t＝120。
在一种可能的实施方式中，发端处理模块对n条第二数据流中每条第二数据流进行第二FEC编码处理得到n条编码数据流，包括：发端处理模块对每条第二数据流中连续L2符号进行第二FEC编码，得到c个第二FEC码字，连续L2符号的前d个符号为AMo序列，c为L2/K，K为连续第二FEC码字信息位的长度，K为大于1的整数。
本实施方式中，在卷积交织处理过程中和第二FEC编码过程中与AM序列对齐，在不需要增加额外的冗余信息的情况下，可以使得编码数据流或者第三数据流周期性的出现已知序列，使得收端处理模块可以利用这个周期性的已知序列进行内码的同步。
在一种可能的实施方式中，发端处理模块在对齐处理和重排序处理之后，或者，在对齐处理和重排序处理之前，该方法还包括：发端处理模块，将n条通道数据流中每条通道数据流中的AM序列替换为AM*序列，不同的通道数据流中的AM*序列的前5个字节均相同。
本实施方式中，能够将AM序列替换为AM*序列，可以使得收端处理模块采用足够长的已知序列进行内码的同步，降低内码误同步的概率和误失锁的概率。
第二方面，本申请还提供了一种数据处理装置，该数据处理装置位于发端处理模块中。该数据处理装置包括如下功能模块：
通道置换模块，用于对n条通道数据流中每R/2条来自第一通道数据流集合的通道数据流与每R/2条来自第二通道数据流集合的通道数据流进行通道置换处理得到R条第一数据流，总共得到n条第一数据流，n条通道数据流都经过第一前向纠错FEC编码，第一通道数据流集合中的数据与第二通道数据流集合中的数据来自不同的第一FEC码字，通道数据流中连续的a个符号来自a个不同的第一FEC码字，第一数据流中连续的2a个符号来自2a个不同的第一FEC码字，n为大于1的整数，a为大于1的整数，R为大于1的偶数且n能被R整除；
卷积交织模块，用于对n条第一数据流中的每条第一数据流进行卷积交织处理得到n条第二数据流，通道数据流中连续的b个符号来自b个不同的第一FEC码字，b为大于1的整数，b能被a整除；
FEC编码模块，对n条第二数据流中每条第二数据流进行第二FEC编码处理得到n条编码数据流，n条编码数据流包括S个编码数据流集合，每个编码数据流集合包括R条编码数据流，R条编码数据流的数据来自R条进行通道置换的通道数据流，R条进行通道置换的通道数据流包括R/2条来自第一通道数据流集合的通道数据流和R/2条来自第二通道数据流集合的通道数据流，S＝n/R；
信道交织模块，用于将n条编码数据流中每q个编码数据流集合进行信道交织为1条第三数据流，总共得到m条第三数据流，其中，m＝S/q，q为大于0的整数，且，S能被q整除。
在一种可能的实施方式中，当R＝2时，通道置换模块，具体用于对通道数据流i与通道数据流i+(n/2)进行通道置换，得到2条第一数据流，其中，i为大于等于0且小于n/2的整数。
在一种可能的实施方式中，当q＝4时，信道交织模块，具体用于将编码数据流i0、编码数据流i1、编码数据流i2、编码数据流i3、编码数据流i0+(n/2)、编码数据流i1+(n/2)、编码数据流i2+(n/2)和编码数据流i3+(n/2)进行信道交织为1条第三数据流；其中，0≤i0≤15，0≤i1≤15，0≤i2≤15，0≤i3≤15。
可选的，i1＝i0+1，i2＝i0+2，i3＝i0+3；其中，i0＝0、4、8或12；或者，i1＝i0+4，i2＝i0+8，i3＝i0+12；其中，i0＝0、1、2或3。
在一种可能的实施方式中，数据处理装置还包括第一加扰模块，第一加扰模块位于第二FEC编码 模块与信道交织模块之间；第一加扰模块，用于采用长度为Q*N比特的伪随机二进制序列PRBS序列对每条编码数据流中的Q个连续第二FEC码字进行加扰处理，得到加扰后的n条编码数据流，N为第二FEC码字长度，N为大于1的整数，Q为大于或等于1的整数。
在一种可能的实施方式中，数据处理装置还包括第二加扰模块，第二加扰模块位于信道交织模块之后；第二加扰模块，用于采用长度为R*q*Q*N比特的PRBS序列对每条第三数据流中连续的R*q*Q*N比特进行加扰处理，得到加扰后的m条第三数据流，第三数据流中连续的R*q*Q*N比特为R*q条编码数据流中各连续Q个第二FEC码字进行信道交织而生成的R*q*Q*N比特，N为大于1的整数，Q为大于或等于1的整数。
在一种可能的实施方式中，数据处理装置还包括第三加扰模块，第三加扰模块位于卷积交织模块与第二FEC编码模块之间；第三加扰模块，用于采用长度为Q*K比特的PRBS序列对每条第二数据流中的Q个连续第二FEC码字进行加扰处理，得到加扰后的n条第二数据流，K为连续第二FEC码字信息位的长度，K为大于1的整数，Q为大于或等于1的整数。
在一种可能的实施方式中，信道交织模块之前，数据处理装置还包括：对齐处理模块，用于对n条通道数据流进行基于AM序列的对齐处理，AM序列为通道数据流中携带的AM序列。
在一种可能的实施方式中，n条第一数据流中每条第一数据流每间隔L1个比特包括一条AMp序列，AMp序列包括15个字节；其中，每条第一数据流中的AMp序列的前8个字节与对应的通道数据流中的AM序列的前8个字节相同，每条第一数据流中的AMp序列的后7个字节与对应的通道数据流中的AM序列的后7个字节不同，不同的第一数据流中的AMp序列的后7个字节各不相同。
在一种可能的实施方式中，卷积交织模块，具体用于将每条第一数据流中的每连续的T*L1个符号以d个符号为单位轮询输入到卷积交织器的p个延迟线中，得到第二数据流，每连续的T*L1个符号的前t个比特为AMp序列，第二数据流每间隔L2符号包含一条AMo序列，AMo序列为AMp序列的前d个符号，L2＝T*L1，T*L1能被d*p整除。
在一种可能的实施方式中，FEC编码模块，具体用于对每条第二数据流中连续L2符号进行第二FEC编码，得到c个第二FEC码字，连续L2符号的前d个符号为AMo序列，c为L2/K，K为连续第二FEC码字信息位的长度，K为大于1的整数。
在一种可能的实施方式中，数据处理装置还包括：AM序列处理模块，用于将n条通道数据流中每条通道数据流中的AM序列替换为AM*序列，不同的通道数据流中的AM*序列的前5个字节均相同。
在一种可能的实施方式中，Q为大于等于8或小于等于16的整数。
在一种可能的实施方式中，n＝32，R＝2或4，q＝1、2或4。
第三方面，本申请提供了一种数据处理方法，该数据处理方法应用于发端处理模块中。首先，发端处理模块获取f条第一数据流，f条第一数据流都经过第一前向纠错FEC编码，第一数据流中连续的a个数据单位来自a个不同的第一FEC码字，每条第一数据流中每间隔L2个符号包含一个AMp2序列，AMp2序列的长度为Y个符号，f条第一数据流中的AMp2序列的至少前X个符号相同，后(Y-X)个符号互不相同，f为大于1的整数，a为大于1的整数，L2为大于1的整数，X为大于1且小于等于a的整数，Y为大于X的整数。然后，发端处理模块将f条第一数据流中的每条第一数据流中每连续X个符号作为一个卷积交织块进行卷积交织处理得到f条第二数据流，第二数据流每间隔L3个符号包含一条AMo2序列，AMo2序列为AMp2序列的前X个符号，L3为大于1的整数，L3能被L2整除。然后，发端处理模块将f条第二数据流中每条第二数据流中每连续K个比特作为一个编码块进行第二FEC编码处理得到f条编码数据流，10倍L3能被K整除，K为连续的第二FEC码字信息位的长度，K为大于1的整数。
本实施例中，发端处理模块能够在卷积交织处理过程中和AMp2序列对齐，在内码编码处理过程中与AMo2序列对齐，在不需要增加额外的冗余信息的情况下，可以使得第二数据流以及编码数据流周期性的出现已知序列，使得收端处理模块可以利用这个周期性的已知序列进行内码的同步，进而有利于降低收端的处理复杂度。
在一种可能的实施方式中，发端处理模块将f条第一数据流中的每条第一数据流中每连续X个符号作为一个卷积交织块进行卷积交织处理得到f条第二数据流，包括：发端处理模块将每条第一数据流中 的每连续的T*L2个符号以X个符号为单位轮询输入到卷积交织器的p个延迟线中，得到第二数据流，每连续的T*L2个符号的前Y个符号为AMp2序列，L3＝T*L2，T*L2能被X*p整除。
在一种可能的实施方式中，发端处理模块将f条第二数据流中每条第二数据流中每连续K个比特作为一个编码块进行第二FEC编码处理得到f条编码数据流，包括：发端处理模块对每条第二数据流中连续L3个符号进行第二FEC编码，得到c个第二FEC码字，连续L3个符号的前X个符号为AMo2序列，c个第二FEC码字中的第一个第二FEC码字包括AMo2序列，c为(L3*10)/K，c为大于1的整数。
在一种可能的实施方式中，每条第一数据流是基于g条PCS通道数据流进行复用处理而获得的数据流，AMp2序列为g条PCS通道数据流的AM序列经过复用处理而获得的序列，AMp2序列的长度Y为AM序列的长度的g倍。
在一种可能的实施方式中，发端处理模块获取f条第一数据流，包括：发端处理模块从连接单元接口AUI接收e条PMA通道数据流，并对每条PMA通道数据流中的AMp2序列进行AM锁定得到f条第一数据流，e为AUI接口包含的物理通道的数量，f等于e，每条第一数据流是基于g条PCS通道数据流进行基于比特粒度的复用处理或基于符号粒度的复用处理而获得的数据流；其中，若每条所述第一数据流是基于所述g条PCS通道数据流进行基于比特粒度的复用处理，则所述a个数据单位为a个比特；若每条所述第一数据流是基于所述g条PCS通道数据流进行基于符号粒度的复用处理，则所述a个数据单位为a个符号。
在一种可能的实施方式中，发端处理模块获取f条第一数据流，包括：发端处理模块对从连接单元接口AUI接收的e条PMA通道数据流进行第一解复用处理，得到n条PCS通道数据流，e为AUI接口包含的物理通道的数量；然后，发端处理模块对n条PCS通道数据流进行AM锁定和AM对齐后再对n条PCS通道数据流中每g条PCS通道数据流进行第一复用处理，得到f条第一数据流，f等于n/g，f大于或等于e。
在一种可能的实施方式中，每条PMA通道数据流为基于n/e条PCS通道数据流进行基于比特粒度的复用处理而获得的数据流，第一解复用处理为基于比特粒度的解复用处理，第一复用处理为基于符号粒度的复用处理，所述a个数据单位为a个符号；或者，每条PMA通道数据流为基于n/e条PCS通道数据流进行基于符号粒度的复用处理而获得的数据流，第一解复用处理为基于符号粒度的解复用处理，第一复用处理为基于符号粒度的复用处理，所述a个数据单位为a个比特。
在一种可能的实施方式中，f＝4或8或16，X＝2或4，K＝120、136或160。
在一种可能的实施方式中，T＝2或3或7，p＝3或4或7。
在一种可能的实施方式中，g＝2或4或8。
第四方面，本申请提供了一种数据处理装置，该数据处理装置位于发端处理模块中。该数据处理装置包括如下功能模块：
接收处理模块，用于获取f条第一数据流，f条第一数据流都经过第一前向纠错FEC编码，第一数据流中连续的a个数据单位来自a个不同的第一FEC码字，每条第一数据流中每间隔L2个符号包含一个AMp2序列，AMp2序列的长度为Y个符号，f条第一数据流中的AMp2序列的至少前X个符号相同，后(Y-X)个符号互不相同，f为大于1的整数，a为大于1的整数，L2为大于1的整数，X为大于1且小于等于a的整数，Y为大于X的整数。
卷积交织模块，用于将f条第一数据流中的每条第一数据流中每连续X个符号作为一个卷积交织块进行卷积交织处理得到f条第二数据流，第二数据流每间隔L3个符号包含一条AMo2序列，AMo2序列为AMp2序列的前X个符号，L3为大于1的整数，L3能被L2整除。
FEC编码模块，用于将f条第二数据流中每条第二数据流中每连续K个比特作为一个编码块进行第二FEC编码处理得到f条编码数据流，10倍L3能被K整除，K为连续的第二FEC码字信息位的长度，K为大于1的整数。
在一种可能的实施方式中，卷积交织模块，具体用于将每条第一数据流中的每连续的T*L2个符号以X个符号为单位轮询输入到卷积交织器的p个延迟线中，得到第二数据流，每连续的T*L2个符号的前Y个符号为AMp2序列，L3＝T*L2，T*L2能被X*p整除。
在一种可能的实施方式中，FEC编码模块，具体用于对每条第二数据流中连续L3个符号进行第二FEC编码，得到c个第二FEC码字，连续L3个符号的前X个符号为AMo2序列，c个第二FEC码字中的第一个第二FEC码字包括AMo2序列，c为(L3*10)/K，c为大于1的整数。
在一种可能的实施方式中，每条第一数据流是基于g条PCS通道数据流进行复用处理而获得的数据流，AMp2序列为g条PCS通道数据流的AM序列经过复用处理而获得的序列，AMp2序列的长度Y为AM序列的长度的g倍。
在一种可能的实施方式中，接收处理模块，具体用于从连接单元接口AUI接收e条PMA通道数据流，并对每条PMA通道数据流中的AMp2序列进行AM锁定得到f条第一数据流，e为AUI接口包含的物理通道的数量，f等于e，每条第一数据流是基于g条PCS通道数据流进行基于比特粒度的复用处理或基于符号粒度的复用处理而获得的数据流；其中，若每条所述第一数据流是基于所述g条PCS通道数据流进行基于比特粒度的复用处理，则所述a个数据单位为a个比特；若每条所述第一数据流是基于所述g条PCS通道数据流进行基于符号粒度的复用处理，则所述a个数据单位为a个符号。
在一种可能的实施方式中，接收处理模块，具体用于对从连接单元接口AUI接收的e条PMA通道数据流进行第一解复用处理，得到n条PCS通道数据流，e为AUI接口包含的物理通道的数量；以及，对n条PCS通道数据流进行AM锁定和AM对齐后再对n条PCS通道数据流中每g条PCS通道数据流进行第一复用处理，得到f条第一数据流，f等于n/g，f大于或等于e。
在一种可能的实施方式中，每条PMA通道数据流为基于n/e条PCS通道数据流进行基于比特粒度的复用处理而获得的数据流，第一解复用处理为基于比特粒度的解复用处理，第一复用处理为基于符号粒度的复用处理，所述a个数据单位为a个符号；或者，每条PMA通道数据流为基于n/e条PCS通道数据流进行基于符号粒度的复用处理而获得的数据流，第一解复用处理为基于符号粒度的解复用处理，第一复用处理为基于符号粒度的复用处理，所述a个数据单位为a个比特。
在一种可能的实施方式中，f＝4或8或16，X＝2或4，K＝120、136或160。
在一种可能的实施方式中，T＝2或3或7，p＝3或4或7。
在一种可能的实施方式中，g＝2或4或8。
第五方面，本申请提供了一种计算机可读存储介质，计算机可读存储介质存储有计算机程序，其中，计算机程序被硬件执行时能够实现上述第一方面或第三方面中任意一种方法的部分或全部步骤。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例。
图1为本申请实施例应用的一种通信系统示意图；
图2为图1所示通信系统中一种数据传输的过程示意图；
图3为本申请中数据处理方法的一个流程图；
图4为本申请中发端处理模块进行对齐处理和重排序处理的一个示例图；
图5为本申请中数据处理方法的处理流程的一个示例图；
图6为本申请中发端处理模块进行对齐处理的一个示例图；
图7A为本申请中发端处理模块进行通道置换处理的一个示例图；
图7B为本申请中发端处理模块进行通道置换处理的另一个示例图；
图7C为本申请中发端处理模块进行通道置换处理的另一个示例图；
图7D为本申请中发端处理模块进行通道置换处理的另一个示例图；
图8为本申请中对n条通道数据流分别进行卷积交织的一种结构示意图；
图9A为本申请中发端处理模块进行第二FEC编码处理的一个示例图；
图9B为本申请中发端处理模块进行第二FEC编码处理的另一个示例图；
图10A为本申请中发端处理模块进行信道交织处理的一个示例图；
图10B为本申请中发端处理模块进行信道交织处理的另一个示例图；
图10C为本申请中发端处理模块进行信道交织处理的另一个示例图；
图10D为本申请中发端处理模块进行信道交织处理的另一个示例图；
图10E为本申请中发端处理模块进行信道交织处理的另一个示例图；
图10F为本申请中发端处理模块进行信道交织处理的另一个示例图；
图10G为本申请中发端处理模块进行信道交织处理的另一个示例图；
图10H为本申请中发端处理模块进行信道交织处理的另一个示例图；
图11A为本申请中数据处理方法的另一个流程图；
图11B为本申请中数据处理方法的处理流程的另一个示例图；
图12A为本申请中发端处理模块进行加扰处理的一个示例图；
图12B为本申请中发端处理模块进行加扰处理的另一个示例图；
图13A为本申请中数据处理方法的另一个流程图；
图13B为本申请中数据处理方法的处理流程的另一个示例图；
图14A为本申请中数据处理方法的另一个流程图；
图14B为本申请中数据处理方法的处理流程的另一个示例图；
图15为本申请中数据处理方法的另一个流程图；
图16为本申请中通道数据流中的AM序列的一个示例图；
图17为本申请中发端处理模块基于AM序列进行对齐处理和重排序处理的一个示例图；
图18为本申请中发端处理模块基于AM序列进行通道置换处理的一个示例图；
图19为本申请中发端处理模块基于AM序列进行卷积交织处理的一个示例图；
图20为本申请中发端处理模块基于AM序列进行卷积交织处理的另一个示例图；
图21为本申请中发端处理模块基于AM序列进行第二FEC编码处理的一个示例图；
图22为本申请中发端处理模块基于AM序列进行信道交织处理的一个示例图；
图23为本申请中AM*序列的一个示例图；
图24为本申请中AM*序列的另一个示例图；
图25为本申请中数据处理装置的一个实施例示意图；
图26为本申请中数据处理装置的另一个实施例示意图；
图27为本申请中数据处理方法的另一个流程图；
图28为本申请中数据处理方法的流程的一个示例图；
图29A为本申请中获取第一数据流的实现方式的一个示例图；
图29B为本申请中获取第一数据流的实现方式的另一个示例图；
图30为本申请中第一数据流包含的第一FEC码字的图案的示例图；
图31为本申请中复用处理的一个示例图；
图32A为本申请中数据处理方法涉及的卷积交织器的一个示例图；
图32B为本申请中数据处理方法涉及的卷积交织器的另一个示例图；
图32C为本申请中数据处理方法涉及的卷积交织器的另一个示例图；
图33A为本申请中卷积交织块定界的一个示例图；
图33B为本申请中划分卷积交织块定界的另一个示例图；
图33C为本申请中划分卷积交织块定界的另一个示例图；
图34A为本申请中发端处理模块基于AMP2序列对齐进行卷积交织处理的一个示例图；
图34B为本申请中发端处理模块基于AMP2序列对齐进行卷积交织处理的另一个示例图；
图34C为本申请中发端处理模块基于AMP2序列对齐进行卷积交织处理的另一个示例图；
图35A为本申请中发端处理模块基于AMO2序列对齐进行第二FEC编码处理的另一个示例图；
图35B为本申请中发端处理模块基于AMO2序列对齐进行第二FEC编码处理的另一个示例图；
图35C为本申请中发端处理模块基于AMO2序列对齐进行第二FEC编码处理的另一个示例图；
图36为本申请中数据处理装置的另一个实施例示意图；
图37为本申请中数据处理装置的另一个实施例示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”、“第四”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的术语在适当情况下可以互换，以便这里描述的实施例能够以除了在这里图示或描述的内容以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
应理解，本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
图1为本申请实施例应用的一种通信系统示意图。如图1所示，该通信系统包括发端设备01、发端处理模块02、信道传输媒介03、收端处理模块04和收端设备05。以该通信系统是数据中心网络为例，发端设备01和收端设备05可以为交换机或路由器等设备，且发端设备01也称为位于发端的客户侧芯片(host chip)，收端设备05也称为位于收端的客户侧芯片。客户侧芯片有时也称为客户侧设备(host device)。其中，发端设备01与发端处理模块02之间可以通过连接单元接口(attachment unit interface，AUI)连接，收端设备05与收端处理模块04之间可以通过AUI连接。发端处理模块02和收端处理模块04可以为光模块(optical module)、电模块、连接器(connector)或其他在数据发送过程中对数据进行处理的模块。例如，该处理模块可以为800G DR模块(800G DR module，一种800G的直检光模块)。此外，信道传输媒介03可以为光纤。该通信系统中的发端设备01、发端处理模块02、信道传输媒介03、收端处理模块04和收端设备05均可以支持双向传输，也可以支持单向传输，具体此处不做限定。
图2为图1所示通信系统中一种数据传输的过程示意图。如图2所示，从发端设备01向收端设备05传输数据的过程中，发端设备01用于对该数据进行外码编码，然后向发端处理模块02传输经过外码编码的数据。发端处理模块02用于对经过外码编码的数据进行内码编码，得到经过外码编码和内码编码的数据，并将经过外码编码和内码编码的数据传输至信道传输媒介03。信道传输媒介03用于将经过外码编码和内码编码的数据传输至收端处理模块04。收端处理模块04用于对经过外码编码和内码编码的数据进行内码译码，并向收端设备05传输经过内码译码的数据。收端设备05用于对经过内码译码的数据进行外码译码。
应理解，内码中的“内”和外码中的“外”只是基于对数据进行操作的执行主体相对于信道传输媒介03的距离的远近来区分的。对内码进行操作的执行主体较靠近信道传输媒介，对外码进行操作的执行主体较远离信道传输媒介。在本申请实施例中，由于数据从发端设备01发出后经过发端处理模块02传输至信道传输媒介03，然后从信道传输媒介03经过收端处理模块04传输至收端设备05。经发端设备01编码的数据相对于经发端处理模块02编码的数据离信道传输媒介03较远，经收端设备05译码的数据相对于经收端处理模块04译码的数据离信道传输媒介03较远。因此经发端设备01编码的数据称为经过外码编码的数据，经发端处理模块02编码的数据称为经过内码编码的数据，经收端设备05译码的数据称为经过外码译码的数据，经收端处理模块04译码的数据称为经过内码译码的数据。在一种可能的实施方式中，上述的内码编码和外码编码都是采用FEC编码的方式，从而形成一种级联FEC的传输方案。此时，经发端设备01编码的数据称为经过第一FEC编码的数据，经发端处理模块02编码的数据称为经过第二FEC编码的数据，经收端设备05译码的数据称为经过第一FEC译码的数据，经收端处理模块04译码的数据称为经过第二FEC译码的数据。例如，发端设备01可以采用里德-所罗门码(Reed-solomon codes，RS码)进行第一FEC编码(即外码编码)，发端处理模块02可以采用汉明(Hamming)码进行第二FEC编码(即内码编码)。又例如，发端设备01可以采用RS码进行第一FEC编码(即外码编码)，发端处理模块02可以采用博斯-查德胡里-霍昆格姆(Bose–Chaudhuri–Hocquenghem，BCH)码进行第二FEC编码(即内码编码)。
需要说明的是，以上内容是对本申请实施例提供的数据处理方法的应用场景的示例性说明，并不构成对于数据处理方法的应用场景的限定，本领域普通技术人员可知，随着业务需求的改变，其应用场景可以根据应用需求进行调整，本申请实施例对其不做一一列举。
对于上述采用级联FEC的传输方案，本申请设计一种包含“通道置换”和“与通道置换对应的信道交织”的数据处理方案，以实现整体级联FEC方案性能较好，降低收端处理复杂度。
下面结合图3对本申请提出的数据处理方法的主要流程进行介绍，在该方法中，发端处理模块主要执行如下步骤：
步骤301，对n条通道数据流中每R/2条来自第一通道数据流集合的通道数据流与每R/2条来自第二通道数据流集合的通道数据流进行通道置换处理得到R条第一数据流，总共得到n条第一数据流。
本实施例中，通道数据流可以是物理编码子层(physical coding sublayer，PCS)通道数据流。n条通道数据流都是经过第一FEC编码的数据流，也就是上文中介绍的经过外码编码的数据流，其中，n为大于1的整数。经过第一FEC编码的n条通道数据流可以包括多个第一FEC码字。前述n条通道数据流中的每条通道数据流中连续的a个符号来自a个不同的第一FEC码字，所述a为大于1的整数。示例性的，该第一FEC编码可以采用RS码(例如，KP4RS(544，514)码，码长N＝544个符号，一个符号包含10个比特)，经过第一FEC编码后的n条通道数据流可以包括多个RS码字，每条通道数据流中连续的a个符号来自a个不同的RS码字，a为大于0的整数。例如，若a＝2，则每条通道数据流中连续的2个符号来自2个不同的第一FEC码字，即一条通道数据流中第0个符号与第1个符号来自两个不同的第一FEC码字，第1个符号与第2个符号来自两个不同的第一FEC码字，第2个符号与第3个符号来自两个不同的第一FEC码字，以此类推。需要说明的是，在实际应用中也可以采用其他的编码方式进行外码编码，本申请不限制。还需要说明的是，本申请中第一FEC码长取值是以符号为单位来统计的，其中，符号可以包括一个或多个比特。
为便于理解，以发端设备发送1×800GbE业务为例。如图4所示，n＝32且a＝2，第一FEC编码采用KP4RS(544，514)码，码长N＝544个符号，一个符号包含10个比特。发端设备将待传输的800GbE业务数据进行KP4RS(544，514)码第一FEC编码后将每2个RS码字交织分配到PCS通道数据流0～15或者PCS通道数据流16～31，从而使得PCS通道数据流0～15中每条数据流间隔68个符号总共16*68＝1088个符号，其包含了2个RS码码字。每条PCS通道数据流中相邻2个符号来自不同RS码码字，且相邻两条PCS通道数据流的同个位置的2个符号来自不同RS码码字。类似的，PCS通道数据流16～31中每条数据流间隔68个符号总共16*68＝1088个符号，其包含了2个RS码码字。每条PCS通道数据流中相邻2个符号来自不同RS码码字，且相邻两条PCS通道数据流的同个位置的2个符号来自不同RS码码字；且PCS通道数据流0～15包含的RS码字与PCS通道数据流16～31包含的RS码字不同，即PCS通道数据流0～15中的数据与PCS通道数据流16～31中的数据来自不同的RS码字。32条PCS通道数据流经发送设备的PMA层处理后通过连接单元接口800GAUI-8送入发端处理模块。
可选的，该n条通道数据流是经过标识锁定(alignment lock)、通道数据对齐以及通道重排序(lane reorder)等处理而获得的n条通道数据流。例如，如图5所示，发端处理模块的物理媒体附加(physical medium attachment，PMA)子层对来自发送设备的数据进行处理后，可以得到n条经过第一FEC编码(即外码编码)的通道数据流，然后进行标识锁定(alignment lock)和通道数据对齐处理得到对齐的n条通道数据流。然后，根据对齐标识(alignment marker)对n条通道的数据进行通道重排序(lane reorder)处理，使得n条通道的数据能够按照指定的顺序排列。
在一种可能的实施方式中，上述通道数据对齐处理可以是基于AM序列的对齐处理。例如，现有标准定义的通道纠偏处理(lane de-skew)，使得其输出的n条通道数据流的数据是完全对齐的。或者，上述通道数据对齐处理也可以是基于通道符号的对齐处理，使得其输出的n条通道数据流上的数据是基于外码符号对齐，具体可以是基于一个外码符号对齐，也可以是基于多个外码符号对齐。为便于理解，如图6所示，以两条通道数据流为例说明上述通道数据对齐处理的具体操作，假设外码是RS码且一个RS码符号长度为10比特。其中，图6中的场景(a)表明两条通道数据流存在偏差75个比特，AM0和AM1分别是通道数据流0和通道数据流1的对齐标识。图6中的场景(b)是采用现有标准定义的通道纠偏处理 (lane de-skew)，使得其输出后的通道数据流0和通道数据流1不存在偏差。图6中的场景(c)是采用基于1个RS符号对齐处理，使得其输出后的通道数据流0的1个RS符号和通道数据流1的1个RS符号是对齐的，此时两个通道仍存在70比特的偏差。图6中的场景(d)是一种采用基于2个RS符号对齐处理，使得其输出后的通道数据流0的2个RS符号和通道数据流1的2个RS符号是对齐的，此时两个通道仍存在60比特的偏差。本实施例中，以“通道数据对齐处理”是基于通道符号的对齐处理为例进行介绍，在后文图15对应的实施例中，以“通道数据对齐处理”是基于AM序列的对齐处理为例进行介绍。
在一种可能的实施方式中，通道重排序处理是将n条通道数据流按照预设排序方式进行排序，示例性的，该排序方式可以是按照通道数据流0到通道数据流n-1的方式排序，使得通道数据流0到通道数据流(n/2)-1中的任意2条通道数据流的数据来自相同的第一FEC码字，通道数据流n/2到通道数据流n-1中的任意2条通道数据流的数据来自相同的第一FEC码字，并且，通道数据流0到通道数据流(n/2)-1中的任意1条通道数据流与通道数据流n/2到通道数据流n-1中的任意1条通道数据流中的数据来自不同的第一FEC码字。为便于介绍，将n条通道数据流中两部分来自不同第一FEC码字的通道数据流称为两个不同的通道数据流集合。例如，将通道数据流0到通道数据流(n/2)-1共n/2条通道数据流标记为第一通道数据流集合，将通道数据流n/2到通道数据流n-1共n/2条通道数据流标记为第二通道数据流集合。其中，第一通道数据流集合包括的n/2条通道数据流中任意2条通道数据流的数据来自相同的第一FEC码字，第二通道数据流集合包括的n/2条通道数据流中任意2条通道数据流的数据来自相同的第一FEC码字，并且，第一通道数据流集合中的数据中任意1条通道数据流中的数据与第二通道数据流集合中任意1条通道数据流的数据来自不同的第一FEC码字。需要说明的是，通道数据流集合仅仅是对多条通道数据流的一种描述方式，并不是作为数据结构对多条通道数据流进行限定。为便于理解，以n＝32为例，如图4所示，经过重排序处理后的32条通道数据流按照通道数据流0到通道数据流31进行排序，其中，通道数据流0～15被称为第一通道数据流集合，通道数据流0到通道数据流15中的任意2条通道数据流的数据来自相同的第一FEC码字，通道数据流16～31被称为第二通道数据流集合，通道数据流16到通道数据流31中的任意2条通道数据流的数据来自相同的第一FEC码字。第一通道数据流集合中任意一条通道数据流的数据与第二通道数据流集合中任意一条通道数据流的数据来自不同的第一FEC码字。在图4中，相同图案的方框表示同一第一FEC码字的符号，不同的图案的方框表示不同的第一FEC码字的符号。
本步骤中，发端处理模块从n条通道数据流中的第一通道数据流集合中取出R/2条，并且，从n条通道数据流中的第二通道数据流集合中取出R/2条，然后，发端处理模块将来自第一通道数据流集合的R/2条通道数据流与来自第一通道数据流集合的R/2条通道数据流进行通道置换处理，得到R条第一数据流。其中，R为大于1的偶数且n能被R整除。示例性的，R＝2或4。为便于介绍，称经过通道置换处理之后获得的R条第一数据流为一个第一数据流集合。需要说明的是，第一数据流集合仅仅是对多条第一数据流的一种描述方式，并不是作为数据结构对多条第一数据流进行限定。
需要说明的是，发端处理模块不仅是对R条通道数据流进行通道置换处理，而是以R条通道数据流为一组将n条通道数据流均进行通道置换处理，得到n条第一数据流。若n/R＝S，则前述通道置换处理可以理解为发端处理模块将n条通道数据流划分为S组通道数据流，其中，每组通道数据流包括R条来自不同通道数据流集合待进行通道置换处理的通道数据流，即每组通道数据流包括R/2条来自第一通道数据流集合的通道数据流以及R/2条来自第二通道数据流集合的通道数据流，R/2条来自第一通道数据流集合的通道数据流与R/2条来自第二通道数据流集合的通道数据流进行通道置换处理。对n条通道数据流中S组通道数据流进行通道置换处理后，得到S个第一数据流集合，其中每个第一数据流集合包含R条第一数据流，S个第一数据流集合总共有n条第一数据流。需要说明的是，不同组的通道数据流不重复执行通道置换处理，即若第一通道数据流集合中的某一条通道数据流#1被划分到第一组通道数据流中，用于与第二通道数据流集合中的另一条通道数据流#17进行通道置换处理，则该条通道数据流#1不会再次与其他通道数据流进行通道置换处理。例如，当n＝32，R＝2时，S＝16。本示例中，发端处理模块可以将第一道数据流集合中的1条通道数据流和第二通道数据流集合中的1条通道数据流进行通道 置换得到1个第一数据流集合，总共得到16个第一数据流集合，其中每个第一数据流集合包含2条第一数据流。又例如，当n＝32，R＝4时，S＝8。本示例中，发端处理模块可以将第一道数据流集合中的2条通道数据流和第二通道数据流集合中的2条通道数据流进行通道置换得到1个第一数据流集合，总共得到8个第一数据流集合，其中每个第一数据流集合包含4条第一数据流。以此类推，此处不予赘述。
可选的，通道置换的具体处理过程可以是将R/2条来自第一通道数据流集合的通道数据流与R/2条来自第二通道数据流集合的通道数据流每隔Δ个符号置换Δ个符号，得到R条第一数据流，以使得每条第一数据流中每连续2Δ个符号中的前Δ个符号与后Δ个符号分别来自第一通道数据流集合和第二通道数据流集合。其中，所述Δ＝1或2。由于，每条通道数据流每连续a个符号来自a个不同的第一FEC码字，因此，进行通道置换处理后第一数据流每连续的2a个符号来自2a个不同的第一FEC码字，且每连续的2a个符号中的a个符号来自第一通道数据流集合，另外的a个符号来自第二通道数据流集合。以a＝2，第一FEC码字为RS码字为例。每条通道数据流中每连续2个RS符号来自2个不同的RS码字，通道置换处理后每条第一数据流中每连续的4个符号来自4个不同的RS码字，且每连续的4个RS符号中的2个RS符号来自第一通道数据流集合，另外的2个RS符号来自第二通道数据流集合。
在一种可能的实施方式中，R＝2，通道置换的具体处理过程可以是将第一通道数据流与第二通道数据流每隔Δ个符号置换Δ个符号得到2条第一数据流，以使得每条第一数据流中每连续2Δ个符号中的前Δ个符号与后Δ个符号分别来自第一通道数据流和第二通道数据流。其中，第一通道数据流为来自第一通道流数据集合中1条通道数据流，第二通道数据流为来自第二通道流数据集合中的1条通道数据流。其中，所述Δ＝1或2。也就是说，发端处理模块从通道数据流集合0(即通道数据流0到通道数据流(n/2)-1)中任取1条通道数据流i0，从通道数据流集合1(即通道数据流n/2到通道数据流n-1)中任取1条通道数据流i1，通道数据流i0和通道数据流i1每隔Δ个符号置换Δ个符号生成1个第一数据流集合，该第一数据流集合包含2条第一数据流，分别标识为第一数据流i0和第一数据流i1，使得第一数据流每连续的4个符号来自4个不同的码字。可选的，i1＝i0+(n/2)。其中，0≤i0≤(n/2)-1，且，i0为整数；n/2≤i1<n，且，i1为整数。
示例性的，当n＝32时，前述通道置换的具体处理过程可以表示为第一数据流i中的第j个符号来自通道数据流的第j个符号。其中，0≤i≤15，且，i为整数；j≥0，且，j为整数，表示向下取整运算，“％”表示求余运算。
为便于理解，以图7A为例，在图7A的示例(a)中，Δ＝2，即通道数据流i0和通道数据流i1每隔2个RS符号置换2个RS符号生成1个包含第一数据流i0和第一数据流i1的第一数据流集合。本示例中，通道数据流i0和通道数据流i1的前两个RS符号(即第一个RS符号和第二个RS符号)不变，即通道数据流i0中标记为0和2的符号和通道数据流i1中标记为1和3的符号不变，获得的第一数据流i0的前两个RS符号分别为标记为0和2的符号，获得的第一数据流i1的前两个RS符号分别为标记为1和3的符号；通道数据流i0的第三个RS符号与通道数据流i1的第三个RS符号互换，通道数据流i0的第四个RS符号与通道数据流i1的第四个RS符号互换，即通道数据流i0中标记为4和6的符号分别与通道数据流i1中标记为5和7的符号互换，获得的第一数据流i0的第三和第四个RS符号分别为标记为5和7的符号，获得的第一数据流i1的第三和第四个RS符号为标记为4和6的符号。经过通道置换处理后，基于通道数据流i0的前4个RS符号(即“0、2、4、6”)和通道数据流i1的前4个RS符号(即“1、3、5、7”)，获得的第一数据流i0的前4个RS符号为“0、2、5、7”和第一数据流i1的前4个RS符号为“1、3、4、6”。类似的，发端处理模块采用相同的方式基于通道数据流i0的后4个RS符号(即“8、10、12、14”)和通道数据流i1的后4个RS符号(即“9、11、13、15”)，获得的第一数据流i0的后4个RS符号为“8、10、13、15”和第一数据流i1的后4个RS符号为“9、11、12、14”。以此类推，此处不予赘述。在图7A的示例(b)中，Δ＝1，即通道数据流i0和通道数据流i1每隔1个RS符号置换1个RS符号生成1个包含第一数据流i0和第一数据流i1的第一数据流集合。本示例中，通道数据流i0和通道数据流i1的第一个RS符号不变，即通道数据流i0中标记为0的符号和通道数据流i1中标记为1的符号不变；通道数据流i0的第二个RS符号与通道数据流i1的第二个RS符号互换，即通道数据流i0中 标记为2的符号与通道数据流i1中标记为3的符号互换；通道数据流i0和通道数据流i1的第三个RS符号不变，即通道数据流i0中标记为4的符号和通道数据流i1中标记为5的符号不变；通道数据流i0的第四个RS符号与通道数据流i1的第四个RS符号互换，即通道数据流i0中标记为6的符号与通道数据流i1中标记为7的符号互换。经过通道置换处理后，基于通道数据流i0的前4个RS符号(即“0、2、4、6”)和基于通道数据流i1的前4个RS符号(即“1、3、5、7”)，获得的第一数据流i0的前4个RS符号为“0、3、4、7”和第一数据流i1的前4个RS符号为“1、2、5、6”。类似的，发端处理模块采用相同的方式将通道数据流i0的后4个RS符号(即“8、10、12、14”)和通道数据流i1的后4个RS符号(即“9、11、13、15”)，获得的第一数据流i0的后4个RS符号为“8、11、12、15”和第一数据流i1的后4个RS符号为“9、10、13、14”。以此类推，此处不予赘述。
在一种可能的示例中，当n＝32，R＝2时，S＝16。仍旧以通道数据流0到通道数据流15为第一通道数据流集合，通道数据流16到通道数据流31为第二通道数据流集合为例。发端处理模块可以将第一道数据流集合中的通道数据流i与第二通道数据流集合中的通道数据流i+16进行通道置换得到包含第一数据流i和第一数据流i+16的一个第一数据流集合，总共得到16个第一数据流集合。其中，0≤i≤15，且，i为整数。经过通道置换处理之后，如图7B所示，给出了一种Δ＝2的具体示例。在图7B中，通道数据流i和通道数据流i+16每隔2个RS符号置换2个RS符号生成第一数据流i和第一数据流i+16。如图7C所示，给出了一种Δ＝1的具体示例。在图7C中，通道数据流i和通道数据流i+16每隔1个RS符号置换1个符号生成第一数据流i和第一数据流i+16。在前述图7B和图7C所示示例中，第一数据流0和第一数据流16、第一数据流1和第一数据流17、第一数据流2和第一数据流18、第一数据流3和第一数据流19、第一数据流4和第一数据流20、第一数据流5和第一数据流21、第一数据流6和第一数据流22、第一数据流7和第一数据流23、第一数据流8和第一数据流24、第一数据流9和第一数据流25、第一数据流10和第一数据流26、第一数据流11和第一数据流27、第一数据流12和第一数据流28、第一数据流13和第一数据流29、第一数据流14和第一数据流30、第一数据流15和第一数据流31分别属于16个不同的第一数据流集合。
在另一种可能的实施方式中，R＝4，通道置换的具体处理过程可以是从第一通道数据流集合(即通道数据流0到通道数据流(n/2)-1)中任取2条通道数据流(例如，通道数据流i0和通道数据流i1)，从第二通道数据流集合(即通道数据流n/2到通道数据流n-1)中任取2条通道数据流(例如，通道数据流i2和通道数据流i3)，前述4条通道数据流进行通道置换处理生成1个第一数据流集合，该第一数据流集合包含4条第一数据流，分别标识为第一数据流i0、第一数据流i1、第一数据流i2和第一数据流i3，使得第一数据流每连续的4个符号来自4个不同的码字。其中，i0、i1、i2和i3的取值有很多种实现方式，一种可能的实现方式中，0≤i0<7，i1＝i0+8，i2＝i0+16，i3＝i0+24，其中，i0为整数。
需要说明的是，当R＝4时，4条通道数据流进行通道置换的方式有很多种。如图7D所示，是4条通道数据流进行通道置换的两种可能的示例。在一种具体的符号置换方式中，发端处理模块可以将通道数据流i0和/或通道数据流i1中的某一个RS符号与通道数据流i2和/或通道数据流i3中的某一个RS符号置换。例如，在图7D所示的示例(a)中，通道数据流i0的第三个符号(即标识为“8”的符号)与通道数据流i2的第三个符号(即标识为“10”的符号)互换，通道数据流i1的第三个符号(即标识为“9”的符号)与通道数据流i3的第三个符号(即标识为“11”的符号)互换。又例如，在图7D所示的示例(a)中，通道数据流i0的第四个符号(即标识为“12”的符号)与通道数据流i3的第四个符号(即标识为“15”的符号)互换，通道数据流i1的第四个符号(即标识为“13”的符号)与通道数据流i2的第四个符号(即标识为“14”的符号)互换。在另一种具体的符号置换方式中，发端处理模块可以将通道数据流i0与通道数据流i1中的某一个RS符号进行互换，也可以将通道数据流i2与通道数据流i3中的某一个RS符号互换。例如，在图7D所示的示例(a)中，通道数据流i0的第二个符号(即标识为“4”的符号)与通道数据流i1的第二个符号(即标识为“5”的符号)进行互换，通道数据流i2的第二个符号(即标识为“6”的符号)与通道数据流i3的第二个符号(即标识为“7”的符号)进行互换。在另一种具体的符号置换方式中，发端处理模块可以将通道数据流i0、通道数据流i1、通道数据流i2和通道数据流i3中的某一个RS符号进行循环移位。例如，在图7D所示的示例(b)中，通道数据流i0的第四个 符号(即标识为“12”的符号)、通道数据流i1的第四个符号(即标识为“13”的符号)、通道数据流i2的第四个符号(即标识为“14”的符号)以及通道数据流i3的第四个符号(即标识为“15”的符号)分别向通道数据流i1、通道数据流i2、通道数据流i3移动和通道数据流i0移动，以使得在通道置换后的多条第一数据流中的第一数据流i0、第一数据流i1、第一数据流i2以及第一数据流i3的第四个符号分别为“15、12、13、14”。需要说明的是，图7D所示的示例(a)与图7D所示的示例(b)仅仅是通道置换处理的多种置换方式的两种示例，在实际应用中，可以将前述示例中任意一种或多种具体的符号置换的方式进行组合而获得4条通道数据流进行通道置换的实现方式。进行通道置换之后获得的第一数据流每连续的2a个符号来自2a个不同的RS码字，且，每连续的2a个符号中的a个符号来自第一通道数据流集合，另外的a个符号来自第二通道数据流集合。
在一种可能的示例中，当n＝32，R＝4时，S＝8。仍旧以通道数据流0到通道数据流15为第一通道数据流集合，通道数据流16到通道数据流31为第二通道数据流集合为例。发端处理模块可以将通道数据流i0、通道数据流i0+8、通道数据流i0+16、通道数据流i0+24共4条通道数据流进行通道置换，得到包含第一数据流i0、第一数据流i0+8、第一数据流i0+16、第一数据流i0+24共4条第一数据流的一个第一数据流集合j0，总共得到8个第一数据流集合。其中，0≤i0≤6，且，i0为整数；0≤j0≤7，且，j0为整数。
步骤302，对n条第一数据流中的每条第一数据流进行卷积交织处理得到n条第二数据流。
其中，第二数据流中连续的b个符号来自b个不同的第一FEC码字，所述b为大于1的整数，b能被a整除。可选的，b的取值与卷积交织器的延迟线的数量相关。例如，b＝2a×p，其中，p表示卷积交织器中延迟线的数量，p为大于1的整数。
经过通道置换后的n条第一数据流将进入卷积交织器进行卷积交织处理，得到n条第二数据流。如图8所示，为本申请适用的卷积交织器的示例图。在图8所示示例中，第一FEC码字为RS码字，a＝2，卷积交织器包含p＝3条延迟线，3条延迟线分别包括0个存储单元、Q个存储单元、2Q个存储单元，每个存储单元用于存储d＝4个RS符号。在图8所示的示例(a)中，延迟线0的延迟取值为0个RS符号，延迟线1的延迟取值为4Q个RS符号，延迟线2的延迟取值为8Q个符号即无延迟。在图8所示的示例(b)中，延迟线0的延迟取值为8Q个RS符号，延迟线1的延迟取值为4Q个RS符号，延迟线2的延迟取值为0个符号即无延迟。用Sr()表示第一数据流r(0≤r≤31)中连续的4个RS符号，则Sr(3t)、Sr(3t+1)和Sr(3t+2)依次分别输入到图8的示例(a)所示的卷积交织器的延迟线0、延迟线1和延迟线2，同时延迟线0、延迟线1和延迟线2依次分别输出Sr(3t)、Sr(3t-3Q+1)和Sr(3t-6Q+2)。然后，Sr(3t+3)、Sr(3t+4)和Sr(3t+5)依次分别输入到延迟线0、延迟线1和延迟线2，同时延迟线0、延迟线1和延迟线2依次分别输出Sr(3t+3)、Sr(3t-3Q+4)和Sr(3t-6Q+5)、和。结合第一数据流中RS分布规则，则当d(pQ-1)≥68即Q≥6即时，卷积交织的延迟线0、延迟线1和延迟线2轮询1次输出的12个RS符号来自12个不同的RS码字。或者，Sr(3t)、Sr(3t+1)和Sr(3t+2)依次分别输入到图8的示例(b)所示的卷积交织器的延迟线0、延迟线1和延迟线2，同时延迟线0、延迟线1和延迟线2依次分别输出Sr(3t-6Q)、Sr(3t-3Q+1)和Sr(3t+2)，然后，Sr(3t+3)、Sr(3t+4)和Sr(3t+5)依次分别输入到延迟线0、延迟线1和延迟线2，同时延迟线0、延迟线1和延迟线2依次分别输出Sr(3t-6Q+3)、Sr(3t-3Q+4)和Sr(3t+5)。结合第一数据流中RS分布规则，则当d(pQ+1)≥68即Q≥6即时，卷积交织的延迟线0、延迟线1和延迟线2轮询一次输出的12个RS符号来自12个不同的RS码字。
步骤303，对n条第二数据流中每条第二数据流进行第二FEC编码处理得到n条编码数据流。
其中，n条编码数据流中每条编码数据流包括多个第二FEC码字，每个第二FEC码字包括第二FEC信息数据和第二FEC校验数据。其中，第二FEC信息数据是来源于第二数据流的数据，该第二FEC信息数据所在的比特称为信息比特或信息位，第二FEC校验数据是发端处理模块添加的用于校验的冗余数据，该第二FEC校验数据所在的比特称为校验比特或校验位。
图9A为本申请实施例中对n条第二数据流进行第二FEC编码的一种结构示意图。如图9A所示，对n条第二数据流分别进行第二FEC编码(即前文提到的内码编码)得到n条编码数据流。示例性的，对第二数据流i进行第二FEC编码得到编码数据流i，其中，0≤i≤31。如图9B所示，以n＝32，第二 FEC为eHamming(128，120)为例。发端处理模块将每条第二数据流中每连续的12个符号(即120比特)作为一个第二FEC信息数据，对每个第二FEC信息数据进行eHamming(128，120)编码，并且，添加冗余比特，得到128比特长度的第二FEC码字。其中，每个第二FEC的信息位来自12个不同的RS码字。
步骤304，将n条编码数据流中每q个编码数据流集合进行信道交织为1条第三数据流，总共得到m条第三数据流。
其中，n条编码数据流包括S个编码数据流集合，每个编码数据流集合包括R条编码数据流，R条编码数据流的数据来自R条进行通道置换的通道数据流，所述R条进行通道置换的通道数据流包括R/2条来自第一通道数据流集合的通道数据流和R/2条来自第二通道数据流集合的通道数据流。也可以理解为，R条编码数据流由一个第一数据流集合中的R条第一数据流分别经过卷积交织处理和第二FEC编码得到的。需要说明的是，R条编码数据流的数据是指R条编码数据流中的第二FEC信息数据，不包含R条编码数据流中的第二FEC校验数据，即仅有R条编码数据流的第二FEC信息数据来自R条进行通道置换的通道数据流。
其中，S＝n/R，m＝S/q，q为大于0的整数，且，S能被q整除。可选的，n＝32；R＝2或4；q＝1、2或4；S＝8或16；m＝4或8；q*R＝4或8。
在一种可能的实施方式中，若n＝32，q*R＝4，m＝8，则发端处理模块可以将编码数据流i0、编码数据流i1、编码数据流i0+(n/2)、编码数据流i1+(n/2)共4条编码数据流进行信道交织为1条第三数据流，其中，0≤i0≤15，0≤i1≤15。
在一种示例中，若R＝2，则q＝2，即发端处理模块将32条编码数据流中每2个包含2条编码数据流的编码数据流集合进行信道交织为1条第三数据流，总共得到8条第三数据流。
在另一种示例中，若R＝4，则q＝1，即发端处理模块将32条编码数据流中每1个包含4条编码数据流的编码数据流集合进行信道交织为1条第三数据流，总共得到8条第三数据流。
在另一种可能的实施方式中，若n＝32，q*R＝8，m＝4，则发端处理模块可以将编码数据流i0、编码数据流i1、编码数据流i2、编码数据流i3、编码数据流i0+(n/2)、编码数据流i1+(n/2)、编码数据流i2+(n/2)和编码数据流i3+(n/2)进行信道交织为1条第三数据流；其中，0≤i0≤15，0≤i1≤15，0≤i2≤15，0≤i3≤15。可选的，i1＝i0+1，i2＝i0+2，i3＝i0+3，其中，i0＝0、4、8或12；或者，i1＝i0+4，i2＝i0+8，i3＝i0+12；其中，i0＝0、1、2或3。
在一种示例中，若R＝2，则q＝4，即发端处理模块将32条编码数据流中每4个包含2条编码数据流的编码数据流集合进行信道交织为1条第三数据流，总共得到4条第三数据流。
在另一种示例中，若R＝4，则q＝2，即发端处理模块将32条编码数据流中每2个包含4条编码数据流的编码数据流集合进行信道交织为1条第三数据流，总共得到4条第三数据流。
下面将结合示例分别对前述各种实施方式进行详细介绍：
在一种可能的实施方式中，若R＝2，则每个编码数据流集合包括2条编码数据流，2条编码数据流是由来自第一通道数据流集合的1条通道数据流与来自第二通道数据流集合的另1条通道数据流进行通道置换处理而获得的2条第一数据流确定的，该2条第一数据流分别进行卷积交织和第二FEC编码而获得包括前述2条编码数据流的编码数据流集合。本示例中，具体的通道置换处理过程可以参阅前文图7A、图7B以及图7C对应的描述，此处不予赘述。本实施方式中，若n＝32，则S＝n/R＝32/2＝16，即32条编码数据流包括16个编码数据流集合。
在一种本实施方式的一种实现中，若q＝4，则m＝S/q＝16/4＝4。也就是说，发端处理模块将32条编码数据流中每4个编码数据流集合进行信道交织为1条第三数据流，总共得到4条第三数据流。因此，发端处理模块可以通过4个物理信道将第三数据流传输到收端处理模块，其中，4个物理信道可以是4根光纤，也可以1根光纤上的4个波，此处不做限定。如图10A所示，发端处理模块将32条编码数据流中每2条编码数据流作为一个编码数据流集合，并且，将4个编码数据流集合中共8条编码数据流进行信道交织得到4条第三数据流。示例性的，一个编码数据流集合包括编码数据流i和编码数据流i+16，其中，0≤i≤15，且，i为整数。其中，编码数据流i和编码数据流i+16是通道数据流i和通道数据流i+16行通道置换得到的第一数据流集合中的2条第一数据流分别进行卷积交织和内码编码得到的。例如，通 道数据流i和通道数据流i+16进行通道置换得到第一数据流i和第一数据流i+16，然后，第一数据流i和第一数据流i+16分别进行卷积交织得到第二数据流i和第二数据流i+16，然后，第二数据流i和第二数据流i+16分别进行第二FEC编码得到编码数据流i和编码数据流i+16，则将编码数据流i和编码数据流i+16标识为一个编码数据流集合，发端处理模块总共获得16个编码数据流集合。然后，发端处理模块从16个编码数据流集合中，任取4个编码数据流集合进行信道交织得到1条第三数据流，总共得到4条第三数据流。
进一步地，发端处理模块可以采用如下任意一种示例将编码数据流交织为第三数据流。
示例性的，发端处理模块可以将编码数据流4*j，编码数据流4*j+1，编码数据流4*j+2，编码数据流4*j+3，编码数据流4*j+16，编码数据流4*j+17，编码数据流4*j+18，编码数据流4*j+19共8条编码数据流交织得到第三数据流j，其中，0≤j≤3。如图10B所示，一种具体交织过程为将每个第二FEC码字中的每连续2比特映射为一个四电平脉冲幅度调制(4-Level Pulse Amplitude Modulation，PAM4)，其中，S()表示一个PAM4符号。由于一个第二FEC码字为128比特，因此每个第二FEC码字可以映射为64个PAM4符号。发端处理模块将编码数据流4*j，编码数据流4*j+1，编码数据流4*j+2，编码数据流4*j+3，编码数据流4*j+16，编码数据流4*j+17，编码数据流4*j+18，编码数据流4*j+19的数据按照PAM4符号轮询输出到第三数据流中j。如图10C所示，另一种具体交织过程为将编码数据流4*j，编码数据流4*j+1，编码数据流4*j+2，编码数据流4*j+3，编码数据流4*j+16，编码数据流4*j+17，编码数据流4*j+18，编码数据流4*j+19按照1比特轮询输出到第三数据流中j，其中，b()表示编码数据流的1比特数据。
示例性的，发端处理模块也可以将编码数据流j，编码数据流4+j，编码数据流8+j，编码数据流12+j，编码数据流16+j，编码数据流20+j，编码数据流24+j，编码数据流28+j共8条编码数流交织为第三数据流j，其中，0≤j≤3。具体的方式仍可以采用图10B所示的基于PAM4符号轮询的方式，也可以采用图10C所示的基于1比特轮询的方式，此处不予赘述。
在本实施方式的另一种实现中，若q＝2，则m＝S/q＝16/2＝8。也就是说，发端处理模块将32条编码数据流中每2个编码数据流集合进行信道交织为1条第三数据流，总共得到8条第三数据流。因此，发端处理模块可以通过8个物理信道将第三数据流传输到收端处理模块，其中，8个物理信道可以是8根光纤，也可以1根光纤上的8个波，此处不做限定。如图10D所示，发端处理模块将32条编码数据流中每2条编码数据流作为一个编码数据流集合，并且，将2个编码数据流集合进行信道交织得到8条第三数据流。示例性的，一个编码数据流集合包括编码数据流i和编码数据流i+16，其中，0≤i≤15，且，i为整数。其中，关于编码数据流i和编码数据流i+16的介绍请参阅前文图10A对应的描述，此处不予赘述。然后，发端处理模块从16个编码数据流集合中，任取2个编码数据流集合进行信道交织得到1条第三数据流，总共得到8条第三数据流。
进一步地，发端处理模块可以采用如下任意一种示例将编码数据流交织为第三数据流。
示例性的，发端处理模块可以将编码数据流2*j，编码数据流2*j+1，编码数据流2*j+16，编码数据流2*j+17共4条编码数据流交织得到第三数据流j，其中，0≤j≤7。如图10E所示，一种具体交织过程为将每个第二FEC码字中的每连续2比特映射为一个PAM4，每个第二FEC码字可以映射为64个PAM4符号，然后，将编码数据流2*j，编码数据流2*j+1，编码数据流2*j+16，编码数据流2*j+17按照PAM4符号轮询输出到第三数据流中j。如图10F所示，另一种具体交织过程为将编码数据流2*j，编码数据流2*j+1，编码数据流2*j+16，编码数据流2*j+17按照1比特轮询输出到第三数据流中j。
示例性的，发端处理模块也可以将编码数据流j，编码数据流8+j，编码数据流16+j，编码数据流24+j共4条编码数流交织为第三数据流j。具体的方式仍可以采用图10E所示的基于PAM4符号轮询的方式，也可以采用图10F所示的基于1比特轮询的方式，此处不予赘述。
在另一种可能的实施方式中，若R＝4，则每个编码数据流集合包括4条编码数据流，4条编码数据流是由来自第一通道数据流集合的2条通道数据流与来自第二通道数据流集合的另2条通道数据流进行通道置换处理而获得的4条第一数据流确定的，该4条第一数据流分别进行卷积交织和第二FEC编码而获得包括前述4条编码数据流的编码数据流集合。本实例中，具体的通道置换处理过程可以参阅前文 图7D对应的描述，此处不予赘述。本实施方式中，若n＝32，则S＝n/R＝32/4＝8，即32条编码数据流包括8个编码数据流集合。
在一种本实施方式的一种实现中，若q＝2，则m＝S/q＝8/2＝4。也就是说，发端处理模块将32条编码数据流中每2个编码数据流集合进行信道交织为1条第三数据流，总共得到4条第三数据流。因此，发端处理模块可以通过4个物理信道将第三数据流传输到收端处理模块，其中，4个物理信道可以是4根光纤，也可以1根光纤上的4个波，此处不做限定。如图10G所示，发端处理模块将32条编码数据流中每4条编码数据流作为一个编码数据流集合，并且，将2个编码数据流集合进行信道交织得到4条第三数据流。
在本实施方式的另一种实现中，若q＝1，则m＝S/q＝8/1＝8。也就是说，发端处理模块将32条编码数据流中每1个编码数据流集合进行信道交织为1条第三数据流，总共得到8条第三数据流。因此，发端处理模块可以通过8个物理信道将第三数据流传输到收端处理模块，其中，8个物理信道可以是8根光纤，也可以1根光纤上的8个波，此处不做限定。如图10H所示，发端处理模块将32条编码数据流中每4条编码数据流作为一个编码数据流集合，并且，将1个编码数据流集合进行信道交织得到8条第三数据流。
需要说明的是，同一编码数据流集合中的任意两条编码数据流的数据来自于相同的通道数据流，不同的编码数据流集合中的任意两条编码数据流的数据来自不同的通道数据流。
本实施例中，由于，n条通道数据流中第一通道数据流集合中的数据与第二通道数据流集合中的数据来自不同的第一FEC码字，对来自第一通道数据流集合的R/2条通道数据流与来自第二通道数据流集合的R/2条通道数据流进行通道置换处理，能够将第一通道数据流集合的R/2条通道数据流中每条通道数据流的部分数据与第二通道数据流集合的R/2条通道数据流中每条通道数据流的部分数据进行置换，得到R条第一数据流，以使得同一通道数据流中的数据被分散到不同的第一数据流。然后，再对前述每条第一数据流分别进行卷积交织处理和第二FEC编码处理，而获得R条编码数据流，在将前述R条编码数据流通过信道交织入同一条第三数据流。因此，通过通道置换而被分散到R条第一数据流中的数据，又通过信道交织处理交织入同一条第三数据流。也就是说，来自某一通道数据流的数据即使通过通道置换被分散到不同的第一数据流，也能够通过信道交织处理交织入同一条第三数据流，进而被传输到同一物理信道上，因此，不会对同一通道数据流带来传输延迟不一致的问题，进而可以避免收端处理模块对通道数据流进行对齐处理，有效降低收端处理模块的复杂度。
由于收端处理模块在进行第二FEC码字解码前需要进行第二FEC同步，其中一种同步方式为通过计算第二FEC码字的校验子是否为0进行第二FEC码字自同步，简单方案为判断W个连续第二FEC码字内有T个或者以上个第二FEC码字的校验子为0则表示第二FEC码字同步。但是，考虑到第二FEC码字可能是一个循环码，即使在不同步的状态下其校验子也会为0。因此，为了降低误同步的概率和误失锁的概率，提高同步的可靠性，在图3对应的实施例的基础之上，可以增加扰码模块对数据流进行加扰处理。下面分别基于图11A、图13A和图14A对增加了不同的加扰模块的处理方式进行介绍。
如图11A所示，为一种增加了加扰处理的数据处理方法的一种实施例。如图11B所示，发端处理模块在第二FEC编码之后且在信道交织之前可以对编码数据流进行加扰处理。该方法中，发端处理模块将执行如下步骤：
步骤1101，对n条通道数据流中每R/2条来自第一通道数据流集合的通道数据流与每R/2条来自第二通道数据流集合的通道数据流进行通道置换处理得到R条第一数据流，总共得到n条第一数据流。
步骤1102，对n条第一数据流中的每条第一数据流进行卷积交织处理得到n条第二数据流。
步骤1103，对n条第二数据流中每条第二数据流进行第二FEC编码处理得到n条编码数据流。
本实施例中，步骤1101至步骤1103与前文步骤301至步骤303类似，具体请参阅前文步骤301至步骤303中的相关描述，此处不予赘述。
步骤1104，采用长度为Q*N比特的伪随机二进制序列对每条编码数据流中的Q个连续第二FEC码字进行加扰处理，得到加扰后的n条编码数据流。
其中，N为第二FEC码字长度，N为大于1的整数，所述Q为大于或等于1的整数。
示例性的，如图12A所示，为一种加扰处理的示例图。其中，加扰模块使用PN-Q*N伪随机噪声序列(pseudo-noise sequence)，对Q个编码后的码字加扰。可选的，Q为大于等于8且小于等于16的整数。示例性的，当收端处理模块接收的来自发端处理模块的数据的BER(比特错误率)为4.85E-3时，Q的较优取值为11。
可选的，PN-Q*N伪随机噪声序列使用扰码多项式r(x)生成，此多项式的表达式为：
r(x)＝1+x39+x58   (1)
PN-Q*N伪随机噪声序列以Q*N比特为周期，在每Q个连续内码码字的第0个码字的第0比特位置，将扰码多项式r(x)初始化为初始种子。其中，该初始种子为S57＝1，Si-1＝Si XOR 1。或者，该初始种子为“10101010…”，生成的PN-Q*N伪随机噪声序列叠加在码字比特上。
示例性的，以发端处理模块使用汉明码Hamming(128，120)为例。Q＝11个汉明码字，任意一条编码数据流上，间隔1408比特将扰码多项式r(x)初始化为“10101010…”，生成的PN-1408伪随机噪声序列与连续的11个汉明码字进行比特异或，11个码字的具体排列方式如图12B所示。在图12B所示示例中，任意一条编码数据流上，输入加扰模块的码字排列方式，从第0个汉明码字的第0比特开始，直至第10个汉明码字的第127比特，完成第一个周期的汉明码字加扰。在第11个码字第0比特，重新初始化扰码多项式r(x)初始化为“10101010…”，将生成的PN-1408伪随机噪声序列的第0比特与第11个码字的第0比特异或，直到第21个汉明码字的第127比特与PN-1408伪随机噪声序列的第1407比特异或，完成第二个周期的汉明码字加扰。
步骤1105，将n条编码数据流中每q个编码数据流集合进行信道交织为1条第三数据流，总共得到m条第三数据流。
本实施例中，步骤1105与前文步骤304类似，具体请参阅前文步骤304中的相关描述，此处不予赘述。需要注意的是，本步骤中，n条编码数据流是经过加扰处理的n条编码数据流。
本实施例中，对第二FEC编码(即内码编码)后的编码数据流进行加扰处理，在不需要增加额外的冗余信息的情况下便于收端处理模块进行第二FEC码字的同步，有利于降低第二FEC码字误同步和误失锁的概率，提高同步的可靠性。
如图13A所示，为一种增加了加扰处理的数据处理方法的另一种实施例。如图13B所示，发端处理模块在信道交织之后可以对第三数据流进行加扰处理。该方法中，发端处理模块将执行如下步骤：
步骤1301，对n条通道数据流中每R/2条来自第一通道数据流集合的通道数据流与每R/2条来自第二通道数据流集合的通道数据流进行通道置换处理得到R条第一数据流，总共得到n条第一数据流。
步骤1302，对n条第一数据流中的每条第一数据流进行卷积交织处理得到n条第二数据流。
步骤1303，对n条第二数据流中每条第二数据流进行第二FEC编码处理得到n条编码数据流。
步骤1304，将n条编码数据流中每q个编码数据流集合进行信道交织为1条第三数据流，总共得到m条第三数据流。
本实施例中，步骤1301至步骤1304与前文步骤301至步骤304类似，具体请参阅前文步骤301至步骤304中的相关描述，此处不予赘述。
步骤1305，采用长度为R*q*Q*N比特的伪随机二进制序列对每条第三数据流中每连续的R*q*Q*N比特进行加扰处理，得到加扰后的m条第三数据流，所述第三数据流中连续的R*q*Q*N比特为R*q条编码数据流中各连续Q个第二FEC码字进行信道交织而生成的R*q*Q*N比特。具体为根据步骤1304将R*q条编码数据流中各连续Q个第二FEC码字按照步骤304给出的信道交织方案进行信道交织生成第三数据流的连续R*q*Q*N比特，将此连续R*q*Q*N与长度为R*q*Q*N比特的伪随机二进制序列(pseudo random binary sequence，PRBS)进行比特异或得到加扰后的第三数据流。所述N为大于1的整数，所述Q为大于或等于1的整数。
本实施例中，发端处理模块对信道交织后的第三数据流进行加扰处理，在不需要增加额外的冗余信息的情况下便于收端处理模块进行第二FEC码字的同步，且可以降低第二FEC码字误同步和误失锁的 概率，提高同步的可靠性。
如图14A所示，为一种增加了加扰处理的数据处理方法的另一种实施例。如图14B所示，发端处理模块在第二FEC编码之前可以对第二数据流进行加扰处理。该方法中，发端处理模块将执行如下步骤：
步骤1401，对n条通道数据流中每R/2条来自第一通道数据流集合的通道数据流与每R/2条来自第二通道数据流集合的通道数据流进行通道置换处理得到R条第一数据流，总共得到n条第一数据流。
步骤1402，对n条第一数据流中的每条第一数据流进行卷积交织处理得到n条第二数据流。
本实施例中，步骤1401至步骤1402与前文步骤301至步骤302类似，具体请参阅前文步骤301至步骤302中的相关描述，此处不予赘述。
步骤1403，采用长度为Q*K比特的伪随机二进制序列对每条第二数据流中的Q个连续第二FEC码字信息位进行加扰处理，得到加扰后的n条第二数据流。
其中，K为连续第二FEC码字信息位的长度，K为大于1的整数，Q为大于或等于1的整数。
示例性的，本步骤中的加扰模块可以使用PN-Q*K伪随机噪声序列对Q个待编码码字的信息位加扰。可选的，Q为大于等于8且小于等于16的整数。示例性的，当收端处理模块接收的来自发端处理模块的数据的误比特率(bit error rate，BER)(也被称为比特误码率)为4.85E-3时，Q的较优取值为11。
PN-Q*K伪随机噪声序列使用扰码多项式r(x)生成，多项式的表达式如上述公式(1)所示，此处不予赘述。PN-Q*K伪随机噪声序列以Q*K比特为周期，每次在Q个连续内码信息位的的起始比特位置，将扰码多项式r(x)初始化为初始种子。其中，该初始种子为S57＝1，Si-1＝Si XOR 1。或者，该初始种子为“10101010…”，生成的PN-Q*K伪随机噪声序列叠加在码字比特上。
步骤1404，对n条第二数据流中每条第二数据流进行第二FEC编码处理得到n条编码数据流。
需要注意的是，本步骤中，n条第二数据流是经过加扰处理的n条第二数据流。
步骤1405，将n条编码数据流中每q个编码数据流集合进行信道交织为1条第三数据流，总共得到m条第三数据流。
本实施例中，步骤1404至步骤1405与前文步骤303至步骤304类似，具体请参阅前文步骤303至步骤304中的相关描述，此处不予赘述。
本实施例中，对卷积交织后的第二数据流进行加扰处理，在不需要增加额外的冗余信息的情况下便于收端处理模块进行第二FEC码字的同步，可以降低第二FEC码字误同步和误失锁的概率，提高同步的可靠性。
如图15所示，为本申请中数据处理方法的另一种实施例。本实施例中，发端处理模块基于AM序列进行对齐处理，并且，在后续的卷积交织、第二FEC编码过程中均会使用AM序列。具体地，发端处理模块将执行如下步骤：
步骤1501，对n条通道数据流进行基于AM序列的对齐处理，得到基于AM序列对齐的n条通道数据流。
其中，通道数据流可以是物理编码子层(physical coding sublayer，PCS)通道数据流。n条通道数据流都是经过第一FEC编码的数据流，并且，该n条通道数据流是经过标识锁定(alignment lock)的通道数据流。
其中，所述AM序列为所述通道数据流中携带的AM序列，该AM序列用于收端设备进行RS码字的同步和PCS通道对齐。一般地，发送设备能够对PCS通道数据流每间隔L1比特加入一个AM序列。由于，该AM序列是已知序列，因此，发端处理模块可以利用AM序列进行通道数据对齐处理。可选的，该发端处理模块还可以基于AM序列在通道置换、卷积交织以及内码编码等进行对齐处理。此外，收端处理模块也可以利用AM序列进行内码的同步。
如图16所示，为通道数据流中的AM序列的一种示例图。当发端设备的PCS层采用800G PCS ETC模式时，则对应的通道数据流为PCS通道数据流，其中携带的AM序列的位置和格式如图16所示。其 中，每间隔L1＝2785280比特(即8192个RS码字，包含AM序列)插入AM序列，且AM序列包含CM、UP和UM共3部分共15个字节。其中，CM部分占6个字节，标记为{CM0，CM1，CM2，CM3，CM4，CM5}，其用于收端设备进行RS码字同步。在32条通道数据流中不同的通道数据流的CM部分是相同的。UM部分占6个字节，标记为{UM0，UM1，UM2，UM3，UM4，UM5}，用于携带通道号以便于对通道数据流进行通道排序。一般地，不同的通道数据流中AM序列的UM部分不同，代表不同的通道数据流所在的通道号不同。UP部分占3个字节，标记为{UP0，UP1，UP2}，该UP部分为pad序列。一般地，n条通道数据流中，通道数据流0到通道数据流(n/2)-1中任意2条通道数据流的UP部分不同，通道数据流n/2到通道数据流n-1中任意2条通道数据流的UP部分不相同；而通道数据流0到通道数据流(n/2)-1的UP部分分别与通道数据流n/2到通道数据流n-1的UP部分相同。以n＝32为例，32条通道数据流中，通道数据流0到通道数据流15中任意2条通道数据流的UP部分不同，通道数据流16到通道数据流31中任意2条通道数据流的UP部分不相同；通道数据流0到通道数据流15的UP部分分别与通道数据流16到通道数据流31的UP部分相同。
本步骤中，发端处理模块基于AM序列对齐的示例可以参阅前文图6中的示例(b)对应的相关介绍，此处不予赘述。
步骤1502，对n条基于AM序列对齐的通道数据流进行重排序处理，以使得n条通道数据流按照预设排序方式进行排序。
可选的，将n条通道数据流按照预设排序方式进行排序，为便于理解，以n＝32为例，如图17所示，经过重排序处理后的32条通道数据流按照通道数据流0到通道数据流31进行排序，其中，通道数据流0～15被称为第一通道数据流集合，通道数据流0到通道数据流15中的任意2条通道数据流的数据来自相同的第一FEC码字，通道数据流16～31被称为第二通道数据流集合，通道数据流16到通道数据流31中的任意2条通道数据流的数据来自相同的第一FEC码字。第一通道数据流集合中的任意一条通道数据流的数据与第二通道数据流集合中的任意一条通道数据流的数据来自不同的第一FEC码字。在图17中，相同图案的方框表示同一第一FEC码字的符号，不同的图案的方框表示不同的第一FEC码字的符号。
具体地，请参阅前文步骤301中关于重排序处理的介绍，此处不予赘述。
步骤1503，对n条通道数据流中每R/2条来自第一通道数据流集合的通道数据流与每R/2条来自第二通道数据流集合的通道数据流进行通道置换处理得到R条第一数据流，总共得到n条第一数据流。
其中，n条第一数据流中每条第一数据流每间隔L1个比特包括一条AMp序列，该AMp序列包括15个字节。其中，每条第一数据流中的AMp序列的前8个字节与对应的通道数据流中的AM序列的前8个字节相同，每条第一数据流中的AMp序列的后7个字节与对应的通道数据流中的AM序列的后7个字节不同，不同的第一数据流中的AMp序列的后7个字节各不相同。其中，第一数据流对应的通道数据流是基于通道置换处理而生成该第一数据流的通道数据流。例如，通道数据流i0与通道数据流i1进行通道置换处理得到第一数据流i0和第一数据流i1。本示例中，第一数据流i0对应的通道数据流为通道数据流i0和通道数据流i1，并且，第一数据流i1对应的通道数据流也为通道数据流i0和通道数据流i1。以第一数据流i0为例，第一数据流i0中的AMp序列的前8个字节与通道数据流i0中的AM序列的前8个字节相同，并且，第一数据流i0中的AMp序列的前8个字节与通道数据流i1中的AM序列的前8个字节相同。第一数据流i0中的AMp序列的后7个字节与通道数据流i0中的AM序列的后7个字节不同，第一数据流i0中的AMp序列的后7个字节与通道数据流i1中的AM序列的后7个字节也不同，并且，n条第一数据流中任意2条第一数据流中的AMp序列的后7个字节各不相同。
需要说明的是，第一数据流中的AMp序列的前8个字节与通道数据流中的AM序列的前8个字节相同，具体是指第一数据流中的AMp序列的前8个字节与通道数据流中的AM序列的前8个字节完全相同。例如，第一数据流中的AMp序列的第x个字节与通道数据流中的AM序列的第x个字节相同，其中，1≤x≤8，且，x为整数。第一数据流中的AMp序列的后7个字节与通道数据流中的AM序列的后7个字节不同，具体是指第一数据流中的AMp序列的后7个字节与通道数据流中的AM序列的后7个字节存在至少一个字节不同。例如，第一数据流中的AMp序列的第y个字节与通道数据流中的AM 序列的第y个字节相同，但是，第一数据流中的AMp序列的第z个字节与通道数据流中的AM序列的第z个字节相同，其中，9≤y≤15，9≤z≤15，且，y和z均为整数，且，y与z的取值不同。
为便于理解，以n＝32为例介绍进行通道置换前的通道数据流中的AM序列与进行通道置换处理后的第一数据流中的AMp序列之间的区别。如图18所示，基于AM序列对齐的32个通道数据流通过通道置换处理得到32条第一数据流。可选的，发端处理模块采用图7A、图7B或图7C所介绍的示例进行通道置换处理。根据通道置换中数据交换关系可知第一数据流每间隔L1＝278528符号包含一个AMp序列，该AMp序列是AM序列置换后的已知序列。该AMp序列的长度仍为120比特。第一数据流i(0≤i<32)的AMP序列的前8个字节与通道数据流i(0≤i<32)中的AM序列的前8个字节保持一致，即仍为{CM0，CM1，CM2，UP0，CM3，CM4，CM5，UP1}，并且，对于所有第一数据流CM0、CM1、CM2、CM3、CM4以及CM5均相同，即32条第一数据流中任意2条第一数据流的CM部分相同。而UP0和UP1对于第一数据流0到第一数据流15各不相同，但是，第一数据流0到第一数据流15分别与第一数据流16到第一数据流31相同，标记这8个字节为CMP。第一数据流i(0≤i<32)的AMP序列的后面的7个字节与通道数据流i(0≤i<32)中的AM序列的后7个字节不同，且，任意两个第一数据流中AMP序列的后7个字节互不相同，因此，将AMP序列的后7个字节标记为UMp。
关于通道置换的具体介绍请参阅前文步骤301中关于通道置换的描述，此处不予赘述。
步骤1504，对n条第一数据流中的每条第一数据流进行卷积交织处理得到n条第二数据流。
具体地，发端处理模块将每条第一数据流中的每连续的T*L1个符号以d个符号为单位轮询(round-robin)输入到卷积交织器的p个延迟线中，得到第二数据流，所述每连续的T*L1个符号的前t个比特为所述AMp序列，所述第二数据流每间隔L2符号包含一条AMo序列，所述AMo序列为所述AMp序列的前d个符号，所述L2＝T*L1，所述T*L1能被d*p整除。示例性的，d＝4，t＝120。
为了使CMP序列中部分字节在进行卷积交织处理后仍可以在第二数据流中周期性的出现，则CMP中连续的5个字节以固定周期的输入到卷积交织器的中的某一条固定的延迟线。
在一种可能的实施方式中，以AMP序列为起始位置，将第一数据流中每连续T*L1个符号以d个符号为单位轮询(round-robin)输入到图8所示的卷积交织的p条延迟线中。其中，T*L1能被为d*p整除，经过卷积交织后第二数据流每隔L2比特包含长度为d符号的已知序列。为便于介绍，称前述已知序列为AMO序列，该AMO序列为AMP序列的前d个符号。其中，L2＝T*L1比特。根据实施列给出的卷积交织的参数和L1的大小，当T＝3时候，如图19所示，将第一数据流中每连续3个AMP周期的数据以第一个AMP序列为初始位置划分为大小为d＝4个符号的卷积交织，总共包含208896个卷积交织块。然后，将连续208896的卷积交织块轮询(round-robin)输入到卷积交织器的延迟线0、延迟线1和延迟线2中，即将第0个卷积交织块输入到卷积交织器延迟线0，第1个卷积交织块输入到卷积交织器延迟线1，第2个卷积交织块输入到卷积交织器延迟线2，第3个卷积交织块输入到卷积交织器延迟线0，第4个卷积交织块输入到卷积交织器延迟线1，依次类推。经过卷积交织后第二数据流的格式如图20所示，该第二数据流中每间隔L2＝835584符号包含长度为40比特的已知序列，将该长度为40比特的已知序列标记为AMO序列，且，AMO序列为AMP序列的前5个字节，该AMO序列包含{CM0，CM1，CM2，UP0，CM3}。
步骤1505，对n条第二数据流中每条第二数据流进行第二FEC编码处理得到n条编码数据流。
具体地，发端处理模块对每条第二数据流中连续L2符号进行第二FEC编码，得到c个第二FEC码字。其中，连续L2符号的前d个符号为所述AMo序列，所述c为L2/K，所述K为连续第二FEC码字信息位的长度，所述K为大于1的整数。
本步骤中，为了可以使得收端处理模块利用AMO进行第二FEC码字同步，则发端处理模块在进行第二FEC编码(即内码编码)时需要使AMO序列与第二FEC码字(即内码码字)同步，即AMO序列固定为第二FEC码字(即内码码字)的固定位置。如图21所示，为本申请提供的一种固定AMO序列的实现方式。其中，AMO序列固定在内码码字的前40比特。发端处理模块可以将以AMO序列为起始位置将第二数据流每连续的12个符号(即120比特)划分为内码信息块，连续2个AMO序列之间数据划分为整数个内码信息块，对每个内码信息块进行编码添加8比特的冗余信息，得到128比特的码字。于 是，经过第二FEC编码而获得的编码数据流中每间隔L3＝69632个内码码字包含长度为40比特的AMO序列。
步骤1506，将n条编码数据流中每q个编码数据流集合进行信道交织为1条第三数据流，总共得到m条第三数据流。
本步骤中，发端处理模块可以采用图3对应实施例介绍的方式进行信道交织处理，得到m条第三数据流。其中，m＝4或8。关于m的取值的具体方式在图3对应实施例的步骤304中已进行了详细介绍，此处不予赘述。如图22所示，为进行信道交织处理后的第三数据流的示例图。在图22中，第三数据流中每间隔L4＝69632*32/m个内码长度的数据会包含由AMO序列交织的固定序列。为便于介绍，称该固定序列为AMO’序列，该AMO’序列的长度为32/m*40比特。
本实施例中，发端处理模块能够在卷积交织处理过程中和内码编码处理过程中与AM序列对齐，在不需要增加额外的冗余信息的情况下，可以使得编码数据流或者第三数据流周期性的出现已知序列，使得收端处理模块可以利用这个周期性的已知序列进行内码的同步，进而有利于降低收端的处理复杂度。
在一些可能的实施方式中，发端处理模块可以在图15对应的实施例的基础上替换AM序列。例如，在对齐处理和重排序处理之后，或者，在对齐处理和重排序处理之前且AM锁定之后，将n条通道数据流中每条通道数据流中的所述AM序列替换为AM*序列，不同的通道数据流中的AM*序列的前5个字节均相同。
如图23所示的示例(a)，AM序列的前5个字节包括UP序列，AM序列的前5个字节可以表示为{CM0，CM1，CM2，UP0，CM3}。其中，UP0为PAD序列，不同的通道具有不同的UP0。因此，若收端处理模块利用AMO序列或者AMO’序列进行内码同步，需要屏蔽AMO序列中UP0或者AMO’中由UP0交织得到的部分数据，则可能提高误锁定的概率和同步的复杂度。对此，本实施例提出一种可以避免在利用AMO序列或者AMO’序列进行内码同步时屏蔽AMO序列中的UP0或者屏蔽AMO’序列由UP0交织得到的部分序列方案。
如图23的所示的示例(b)和示例(c)是本实施例提供的两种AM*序列的示例。
一种可能的示例如图23的示例(b)所示，发端处理模块可以将AM序列中的UP0移动至CM5和UP1之间，其他部分保持不变，得到的AM*序列的格式如图23的示例(b)所示,对于所有通道的AM*序列的前5个字节是相同的。然后，发端处理模块利用AM*序列按照图15对应实施例给出的数据处理方式得到n条编码数据流中的AMO序列为{CM0，CM1，CM2，CM3，CM4}，则收端处理模块可利用完整的AMO序列或者AMO’序列进行内码同步。
另一种可能的示例如图23的示例(c)所示，发端处理模块可以将AM序列的{CM0，CM1，CM2，UP0，CM3，CM4，CM5，UP1}替换为{CM0，CM1，CM3，CM4，CM5 *，UP0，UP1}，其他部分保持不变。其中，为4比特，为的比特取反，可以与CM2的前4比特相同，也可以与CM2的后4比特相同，还可以是其他任意序列。CM5 *可以与CM5相同；也可以是CM5 *的前4比特与CM5的前4比特相同，而CM5 *的后4比特与CM5的前4比特相反；还可以是CM5 *的前4比特与CM5的后4比特相同，而CM5 *的后4比特与CM5的前4比特相反；还可以是其他前后4比特取反的其他序列，此处不再一一列举，对于所有通道的AM*序列的前5个字节是相同的。然后，发端处理模块利用AM*序列按照图15对应实施例给出的数据处理方式得到n条编码数据流中的AMO序列为{CM0，CM1，CM3，CM4，}，则收端处理模块可利用完整的AMO序列或者AMO’序列进行内码同步。此外，由于AMO序列前20比特与后20比特取反的，因此有利于收端处理模块简化内码同步复杂度。本实施例中，发端处理模块能够替换AM序列，可以使得收端处理模块能够采用足够长的已知序列进行内码的同步，有利于降低收端处理模块内码误同步的概率和误失锁的概率。
在一些可能的实施方式中，发端处理模块可以在图15对应的实施例的基础上在数据发送处理的其他位置进行已知序列的替换。比如在通道置换后将第一数据流中AMp的序列的CMp部分替换为CMp *，其中CMp *的格式如上述的AM*序列的前8个字节相同；或者在卷积交织后或者内码编码后将AMO序列替换为长度为40比特且自相关性很好的0、1平衡的随机序列。
此外，由于每个编码数据流中的AMO是相同的，通过信道交织处理后获得的第三数据流中可能出现连续较多个相同的PAM4符号，进而可能导致时钟漂移(clock wander)问题，从而可能导致收端处理模块的时钟恢复失锁。对此，本实施例又提出了两种AM序列的替换方式，用于降低第三数据流连续相同PAM4符号的数目，从而降低时钟漂移(clock wander)的问题。
一种可能的实施方式中，发端处理模块将n条通道数据流中的通道数据流0到通道数据流(n/2)-1中每条通道数据流中的AM序列替换为AM*序列，将n条通道数据流中的通道数据流n/2到通道数据流n-1中每条通道数据流中的AM序列替换为序列。若AM*序列为图23所示的示例(b)，则序列为图24所示的示例(a)；若AM*序列为图23所示的示例(c)，则序列为图24所示的示例(b)。
在一些可能的实施方式中，发端处理模块可以在图15对应的实施例的基础上在数据发送处理的其他位置进行已知序列的替换。比如在通道置换后将n条第一数据流中的第一数据流0到第一数据流(n/2)-1中每条第一数据流中的AMp序列的CMp部分替换为CMp *，将n条第一数据流中的第一数据流n/2到第一数据流n-1中每条第一数据流中的AMp序列的CMp部分替换为其中若CMp *序列为图23示例(b)所示的AM*序列的前8个字节，则序列为图24示例(a)所示序列的前8个字节；若CMp *序列为图23示例(c)所示的AM*序列的前8个字节，则序列为图24示例(b)所示序列的前8个字节。或者在卷积交织后将n条第二数据流中的第二数据流0到第二数据流(n/2)-1中每条第二数据流中的AMo序列替换为序列，将n条第二数据流中的第二数据流n/2到第二数据流n-1中每条第二数据流中的AMo序列替换为序列。或者在第二FEC编码后将n条编码数据流中的编码数据流0到编码数据流(n/2)-1中每条编码数据流中的AMo序列替换为序列，将n条编码数据流中的编码数据流n/2到编码数据流n-1中每条编码数据流中的AMo序列替换为序列，其中序列可以为任意40比特长度且自相关性很好的0、1平衡的随机序列，而序列为序列比特取反，一种可能的序列为图23示例(b)或者图23示例(c)所示AM*序列的前5个字节。
本实施例中，发端处理模块将AM序列或者AMp序列或者AMO序列进行替换处理，以使得进行信道交织的q*R条的编码数据中的q*R/2条编码数据流中的AMO序列与另外q*R/2条编码数据流中的AMO序列不同，有利于降低第三数据流中连续相同PAM4符号的数目，从而降低产生时钟漂移(clock wander)的效应。
如图25所示，为本实施例提供的一种数据处理装置250的结构示意图。应当理解的是，前述图3、图11A、图13A、图14A以及图15对应的方法实施例中的发端处理模块可以基于本实施例中图25的结构。如图25所示，该数据处理装置250包括通道置换模块2501、卷积交织模块2502、FEC编码模块2503以及信道交织模块2504。其中，通道置换模块2501，用于对n条通道数据流中每R/2条来自第一通道数据流集合的通道数据流与每R/2条来自第二通道数据流集合的通道数据流进行通道置换处理得到R条第一数据流，总共得到n条第一数据流，n条通道数据流都经过第一前向纠错FEC编码，第一通道数据流集合中的数据与第二通道数据流集合中的数据来自不同的第一FEC码字，通道数据流中连续的a个符号来自a个不同的第一FEC码字，第一数据流中连续的2a个符号来自2a个不同的第一FEC码字，n为大于1的整数，a为大于1的整数，R为大于1的偶数且n能被R整除。
卷积交织模块2502，用于对n条第一数据流中的每条第一数据流进行卷积交织处理得到n条第二数据流，通道数据流中连续的b个符号来自b个不同的第一FEC码字，b为大于1的整数，b能被a整除。
FEC编码模块2503，对n条第二数据流中每条第二数据流进行第二FEC编码处理得到n条编码数据流，n条编码数据流包括S个编码数据流集合，每个编码数据流集合包括R条编码数据流，R条编码数据流的数据来自R条进行通道置换的通道数据流，R条进行通道置换的通道数据流包括R/2条来自第一通道数据流集合的通道数据流和R/2条来自第二通道数据流集合的通道数据流，S＝n/R。
信道交织模块2504，用于将n条编码数据流中每q个编码数据流集合进行信道交织为1条第三数据流，总共得到m条第三数据流，其中，m＝S/q，q为大于0的整数，且，S能被q整除。
可选的，该数据处理装置250还包括对齐模块2505以及重排序模块2506。其中，对齐模块2505 用于对n条通道数据进行基于RS码或AM序列的对齐处理。重排序模块2506用于n条通道数据流进行通道重排序，以使得所述n条通道数据流按照预设顺序排列。
其余可以参考上述图3、图11A、图13A、图14A以及图15对应实施例中发端处理模块的方法，此处不再赘述。
如图26所示，为本实施例提供的另一种数据处理装置260的结构示意图。应当理解的是，前述图3、图11A、图13A、图14A以及图15对应的方法实施例中的发端处理模块可以基于本实施例中图26所示的数据处理装置260的结构。如图26所示，该数据处理装置260可以包括处理器2601、存储器2602和收发器2603。其中，该处理器2601与该存储器2602耦合连接，该处理器2601与该收发器2603耦合连接。
其中，前述收发器2603也可以称为收发单元、收发机、收发装置等。可选地，可以将收发单元中用于实现接收功能的器件视为接收单元，将收发单元中用于实现发送功能的器件视为发送单元，即收发单元包括接收单元和发送单元，接收单元也可以称为接收机、输入口、接收电路等，发送单元可以称为发射机、发射器或者发射电路等。
其中，前述处理器2601可以是中央处理器(central processing unit，CPU)、专用集成电路(application-specific integrated circuit，ASIC)、可编程逻辑器件(programmable logic device，PLD)或其组合。上述PLD可以是复杂可编程逻辑器件(complex programmable logic device，CPLD)，现场可编程逻辑门阵列(field-programmable gate array，FPGA)，通用阵列逻辑(generic array logic，GAL)或其任意组合。处理器2601可以是指一个处理器，也可以包括多个处理器，具体此处不做限定。
此外，前述该存储器2602主要用于存储软件程序和数据。存储器2602可以是独立存在，与处理器2601相连。可选地，该存储器2602可以和该处理器2601集成于一体，例如集成于一个或多个芯片之内。其中，该存储器2602能够存储执行本申请实施例的技术方案的程序代码，并由处理器2601来控制执行，被执行的各类计算机程序代码也可被视为是处理器2601的驱动程序。存储器2602可以包括易失性存储器(volatile memory)，例如随机存取存储器(random-access memory，RAM)；存储器也可以包括非易失性存储器(non-volatile memory)，例如只读存储器(read-only memory，ROM)，快闪存储器(flash memory)，硬盘(hard disk drive，HDD)或固态硬盘(solid-state drive，SSD)；存储器2602还可以包括上述种类的存储器的组合。存储器2602可以是指一个存储器，也可以包括多个存储器。示例性的，存储器2602，用于存储各种数据。具体地，请参阅前文实施例中的相关介绍，此处不予赘述。
在一个实现方式中，存储器2602中存储有计算机可读指令，所述计算机可读指令包括多个软件模块，例如，前述图25介绍的通道置换模块2501、卷积交织模块2502、FEC编码模块2503以及信道交织模块2504、对齐模块2505以及重排序模块2506等。具体请参阅前文图25中的相关描述，此处不再赘述。
如图27所示，为本申请中数据处理方法的另一种实施例，可以提高级联码的性能，又可以有效解决收端模块内码同步和解卷积交织器的同步问题。具体地，发端处理模块将执行如下步骤：
步骤2701，获取f条第一数据流。
其中，f条第一数据流都经过第一前向纠错FEC编码。其中，f为大于1的整数。经过第一FEC编码的f条第一数据流可以包括多个第一FEC码字。前述f条第一数据流中的每条第一数据流中连续的a个数据单位来自a个不同的第一FEC码字，所述a为大于1的整数。示例性的，该第一FEC编码可以采用RS码，经过第一FEC编码后的f条第一数据流可以包括多个RS码字，每条第一数据流中连续的a个数据单位来自a个不同的RS码字，a为大于1的整数。需要说明的是，在实际应用中也可以采用其他的编码方式进行第一FEC编码，本申请不限制。
还需要说明的是，本申请中第一FEC码长取值可以是以符号为单位来统计的，也可以是以比特为单位来统计的。其中，符号可以包括一个或多个比特。例如，当第一FEC为RS(544，514)时，一个符号包括10个比特。
在一种可能的示例中，连续的a个数据单位来自a个不同的第一FEC码字，可以是连续的a个符号 来自a个不同的第一FEC码字。以a＝4为例，若第一数据流中连续的4个符号为符号a0、符号a1、符号a2和符号a3，每个符号占用10比特，则符号a0、符号a1、符号a2和符号a3分别来自不同的第一FEC码字。也就是说，第一数据流中的0～9比特、10～19比特、20～29比特以及30～39比特分别来自不同的第一FEC码字。例如，第一数据流中的0～9比特来自码字0，第一数据流中的10～19比特来自码字1，第一数据流中的20～29比特来自码字2，第一数据流中的30～39比特来自码字3。以此类推，此处不予赘述。
在另一种可能的示例中，连续的a个数据单位来自a个不同的第一FEC码字，可以是连续的a个比特来自a个不同的第一FEC码字。以a＝4为例，若第一数据流中连续的4个比特为比特0、比特1、比特2和比特3，则比特0、比特1、比特2和比特3分别来自不同的第一FEC码字。
此外，每条第一数据流中每间隔L2个符号包含一个AMp2序列，其中，L2为大于1的整数。例如，每条第一数据流中每间隔L2个符号中的前Y个比特为一个AMp2序列。
具体地，如图28所示，发端处理模块对从AUI接口接收的数据流进行AM锁定、AM对齐等接收处理。可选的，该发端处理模块还可以对从AUI接口接收的数据流进行复用处理。
可选的，每条第一数据流是基于g条PCS通道数据流进行复用处理后而获得的数据流，而前述AMp2序列直接为该g条PCS通道数据流的AM序列经过复用处理而获得的序列。示例性的，若发端设备能够对PCS通道数据流每间隔L1比特加入一个AM序列，则将g条PCS通道数据流进行复用处理的过程能够使得来自g条PCS通道数据流的g个AM序列复用为一个AMp2序列。因此，一个AMp2序列的长度为一个AM序列的长度的g倍。本示例中，经过复用处理之后，第一数据流中每间隔L2个符号才出现一个AMp2序列，其中，L2等于L1*g。示例性的，g＝2或4或8。
需要说明的是，由于PCS通道数据流的AM序列格式如图16所示，且每条PCS通道对应的AM序列各不相同，当AMp2序列为由PCS通道数据流的AM序列直接复用得到时，每条第一数据流中的各自的AMp2序列不同，但是根据AM序列的格式可知前述f条第一数据流中的各自AMp2序列的至少前X个符号相同，而后(Y-X)个符号互不相同。其中，X为大于1且小于等于a的整数，所述Y为大于所述X的整数。示例性的，如表1所示，为32条PCS通道数据流各自的AM序列的一种示例。如表2所示，当g＝4，且将PCS通道数据流2*i，PCS通道数据流2*i+1，PCS通道数据流2*i+16，PCS通道数据流2*i+17比特复用为一条第一数据流时每条第一数据流的AMp2序列的具体内容。其中，i为小于等于7的整数，且表2中的每个字节的是按照lsb到msb传输的，此时每条第一数据流中AMp2序列的前96比特为相同的。如表3所示，当g＝4，且将PCS通道数据流2*i，PCS通道数据流2*i+1，PCS通道数据流2*i+16，PCS通道数据流2*i+17符号复用为一条第一数据流时每条第一数据流的AMp2序列的具体内容。其中，i为小于等于7的整数，且表3中的每个字节的是按照lsb到msb传输的，此时每条第一数据流中AMp2序列的前96比特为相同的。
表1，PCS通道中的AM序列

表2，第一数据流中AMP2序列一种可能实现
表3，第一数据流中AMP2序列一种可能实现

具体地，发端处理模块可以通过如下任意一种实施方式获得前述f条第一数据流：
在一种可能的实施方式中，发端设备中来自PCS通道数据流0到PCS通道数据[(n/2)-1]中的n/e/2条PCS通道数据数流和来自PCS通道数据流n/2到PCS通道数据n-1中的n/e/2条PCS通道数据数流复用为一条PMA通道数据流，总共得到e条PMA通道数据流，然后将此e条PMA通道数据流通过连接单元接口AUI发送到发端处理模块，此场景下每条PMA通道数据流中每间隔L2个符号包含由PCS通道数据流中的AM序列复用得到的AMp2序列。对应如图29A所示，发端处理模块从连接单元接口AUI接收e条PMA通道数据流，并对每条PMA通道数据流中的AMp2序列进行AM锁定得到f条第一数据流。其中，e为所述AUI接口包含的物理通道的数量，所述f等于所述e。也就是说，发端处理模块直接从AUI接口的e个物理通道接收的e条PMA通道数据流作为e条第一数据流(即f条第一数据流)。由于，通过AUI接口的物理通道接收的每条PMA通道数据流是在发端设备中进行了复用处理的数据流，因此，该发端处理模块收到的e条第一数据流(即f条第一数据流)中的每条第一数据流也是经过复用处理的数据流。
可选的，e＝4或8。示例性的，若e＝4，则f＝4，即发端设备与发端处理模块之间的AUI接口包括4个物理通道，每个物理通道传输一条PMA通道数据流，发端处理模块从AUI接口接收4条PMA通道数据流作为4条第一数据流。若e＝8，则f＝8，即发端设备与发端处理模块之间的AUI接口包括8个物理通道，每个物理通道传输一条PMA通道数据流，发端处理模块从AUI接口接收8条PMA通道数据流作为8条第一数据流。
可选的，每条第一数据流是基于g条PCS通道数据流进行基于比特粒度的复用处理或基于符号粒度的复用处理而获得的数据流。由于，发端处理模块是将收到的PMA通道数据流作为第一数据流，则PMA通道数据流经过的复用处理即为第一通道数据流经过的复用处理。若发端处理模块通过AUI接口的物理通道接收的每条PMA通道数据流在发端设备中是基于g条PCS通道数据流进行基于比特粒度的复用处理而获得的数据流，则每条第一数据流是基于g条PCS通道数据流进行基于比特粒度的复用处理而获得的数据流。若发端处理模块通过AUI接口的物理通道接收的每条PMA通道数据流在发端设备中是基于g条PCS通道数据流进行基于符号粒度的复用处理而获得的数据流，则每条第一数据流是基于g条PCS通道数据流进行基于符号粒度的复用处理而获得的数据流。
示例性的，g＝4且e＝8，若发端设备有32条PCS通道数据流，则发端设备将32条PCS通道数据流中的每4条PCS通道数据流进行基于符号粒度的复用处理或基于比特粒度的复用处理，得到8条PMA通道数据流。然后，发端设备将前述8条PMA通道数据通过前述AUI接口的8个物理通道发送给发端处理模块，发端处理模块通过AUI接收8条PMA通道数据流，并对每条PMA通道数据流中的AMp2序列进行锁定得到8条第一数据流。
需要说明的是，若该复用处理为基于符号粒度的复用处理，则前述a个数据单位为a个符号，即每条第一数据流中连续的a个符号来自a个不同的第一FEC码字。若该复用处理为基于比特粒度的复用处理，则前述a个数据单位为a个比特，即每条第一数据流中连续的a个比特来自a个不同的第一FEC码字。
在另一种可能的实施方式中，发端设备中将任意n/e条PCS通道数据流复用为一条PMA通道数据流，总共得到e条PMA通道数据流，然后将此e条PMA通道数据流通过连接单元接口AUI发送到发端处理模块，每条PMA通道数据流上不保证连续的a个符号包含a个RS码字。对应如图29B所示，发端处理模块先对从连接单元接口AUI接收的e条PMA通道数据流进行第一解复用处理，得到n条PCS通道数据流，其中，e为AUI接口包含的物理通道的数量；然后，该发端处理模块对多条PCS通道数据流中的AM序列进行AM锁定和AM对齐后再对n条PCS通道数据流中每g条PCS通道数据流进行第一复用处理，得到所述f条第一数据流，所述f等于n/g，所述f大于或等于所述e，所述被复用的g条数据流中其中g/2条来自PCS通道数据流0到PCS通道数据流[(n/2)-1]，另外g/2条来自PCS通道数据流n/2到PCS通道数据流n-1；所述的AM对齐也可以称作解偏斜(de-skew)，此时第一数据流中的AMp2序列由PCS通道数据流中的AM序列直接复用得到。
可选的，g＝2或4或8。示例性的，e＝8，n＝32，g＝4，则f＝32/4＝8。本示例中，发端处理模块先对从AUI的8个物理通道接收8条PMA通道数据流，并对该8条PMA通道数据流进行第一解复用处理，得到32条PCS通道数据流。然后，该发端处理模块对32条PCS通道数据流进行AM锁定和AM对齐后再对32条PCS通道数据流中每4条PCS通道数据流进行第一复用处理，得到8条第一数据流，其中被复用的4条PCS通道数据流中的2条来自PCS通道数据流0到PCS通道数据流15，另外2条来自PCS通道数据流16到PCS通道数据流31。示例性的，e＝8，n＝32，g＝2，则f＝32/2＝16。本示例中，发端处理模块先对从AUI的8个物理通道接收8条PMA通道数据流，并对该8条PMA通道数据流进行第一解复用处理，得到32条PCS通道数据流。然后，该发端处理模块对32条PCS通道数据流进行AM锁定和AM对齐后再对32条PCS通道数据流中每2条PCS通道数据流进行第一复用处理，得到16条第一数据流；其中被复用的4条PCS通道数据流中的1条来自PCS通道数据流0到PCS通道数据流15，另外1条来自PCS通道数据流16到PCS通道数据流31。
可选的，发端处理模块收到的PMA通道数据流可能是基于比特粒度的复用处理而获得的数据流，也可能是基于符号粒度的复用处理而获得的数据流。下面分别举例介绍：
在一种可能的示例中，若每条PMA通道数据流为基于n/e条PCS通道数据流进行基于比特粒度的复用处理而获得的数据流，则第一解复用处理为基于比特粒度的解复用处理，并且，第一复用处理为基于符号粒度的复用处理。示例性的，e＝8，n＝32，g＝4，则f＝32/4＝8，n/e＝4。本示例中，发端处理模块先对从AUI的8个物理通道接收8条PMA通道数据流，若每条PMA通道数据流是基于4:1的比特粒度的复用处理而获得的数据流(即将32条PCS通道数据流中每4条PCS通道数据流按照比特粒度复用 为1条PMA通道数据流)，则发端处理模块对该8条PMA通道数据流中每条PMA通道数据流进行基于1:4的比特粒度的解复用处理，得到32条PCS通道数据流。然后，该发端处理模块对32条PCS通道数据流进行AM锁定和AM对齐之后，该发端处理模块对32条PCS通道数据流基于4:1的符号粒度的复用处理(即将32条PCS通道数据流中每4条PCS通道数据流按照符号粒度复用为1条第一数据流)，得到8条第一数据流。
在另一种可能的示例中，若每条PMA通道数据流为基于n/e条PCS通道数据流进行基于符号粒度的复用处理而获得的数据流，则第一解复用处理为基于符号粒度的解复用处理，并且，第一复用处理为基于符号粒度的复用处理。示例性的，e＝8，n＝32，g＝4，则f＝32/4＝8，n/e＝4。本示例中，发端处理模块先对从AUI的8个物理通道接收8条PMA通道数据流，若每条PMA通道数据流是基于4:1的符号粒度的复用处理而获得的数据流(即将32条PCS通道数据流中每4条PCS通道数据流按照符号粒度复用为1条PMA通道数据流)，则发端处理模块对该8条PMA通道数据流中每条PMA通道数据流进行基于1:4的符号粒度的解复用处理，得到32条PCS通道数据流。然后，该发端处理模块对32条PCS通道数据流进行AM锁定和AM对齐之后，该发端处理模块对32条PCS通道数据流基于2:1的符号粒度的复用处理(即将32条PCS通道数据流中每2条PCS通道数据流按照符号粒度复用为1条第一数据流)，得到16条第一数据流。
需要说明的是，由于，前述第一复用处理为基于符号粒度的复用处理，则前述a个数据单位为a个符号，即每条第一数据流中连续的a个符号来自a个不同的第一FEC码字。
需要说明的是，发端处理模块在对多条PCS通道数据中AM序列进行AM锁定和AM对齐处理时，可以是对n条PCS通道数据流进行AM锁定和AM对齐处理，即要求n条PCS通道数据流中的AM序列完全对齐；也可以是对n条PCS通道数据流中的每组来自AUI的同一物理通道的g条PCS通道数据流进行AM锁定和AM对齐处理，来自该AUI的不同的物理通道的PCS通道数据流可以不用完全对齐。可选的，在AM对齐处理后，先对PCS通道数据流进行重排序处理，然后再对PCS通道数据流进行符号复用处理。
为便于理解，以发端设备与发端处理模块之间的AUI接口为800G-AUI8且发端处理模块直接将从AUI接口接收的8条PMA通道数据流作为8条第一数据流为例，f＝e＝8，a＝4。若PMA通道数据流是基于比特粒度的复用，则第一数据流的格式如图30的示例(a)所示，每连续的4比特的数据来自不同的第一FEC码字，且，每连续的2720比特数据包含了4个第一FEC码字。若PMA通道数据流是基于符号粒度的复用，则第一数据流的格式如图30的示例(b)所示，每连续的4个符号的数据来自不同的第一FEC码字，且，每连续的272个符号包含了4个第一FEC码字。如图31所示，若发端设备的PCS层在每个PCS通道数据流中每间隔L1＝278528个符号(即8192个RS码字，包含AM序列)插入AM序列，该AM序列的长度为120比特(即12个符号)，并且，32条PCS通道数据流经过PMA层的4:1比特复用得到8条PMA通道数据流，每条PMA通道数据流每间隔L2＝4*L1＝1114112个符号包含由PCS通道数据流中的AM序列复用而得到的长度为480比特(即48个符号)的AMP2序列。因此，发端处理模块收到的8条第一数据流中每间隔L2＝4*L1＝1114112个符号包含由PCS通道数据流中的AM序列复用而得到的长度为480比特(即48个符号)的AMP2序列。
步骤2702，将f条第一数据流中的每条第一数据流中每连续X个符号作为一个卷积交织块进行卷积交织处理得到f条第二数据流。
其中，第二数据流每间隔L3个符号包含1条AMo2序列，AMo2序列为AMp2序列的前X个符号。其中，L3为大于1的整数，并且，L3能被L2整除。
具体地，发端处理模块将每条第一数据流中的每连续的T*L2个符号以X个符号为单位轮询(round-robin)输入到卷积交织器的p个延迟线中，得到第二数据流。其中，每连续的T*L2个符号的前Y个符号为所述AMp2序列，所述L3＝T*L2，所述T*L2能被X*p整除。
可选的，X＝4或2，T＝2或3或7，p＝3或4或7。下面结合图32A、图32B和图32C所示的三种卷积交织器分别进行介绍：
在一种可能的实施方式中，p＝3，X＝4。如图32A所示，将第一数据流中以AMP2为起始位置的连续 T*L2个符号长度的数据以X＝4个符号(即40比特，标记为一个卷积交织块，图32A中的Sr()表示为一个卷积交织块)为单位轮询(round-robin)输入到图32A所示的卷积交织器的p＝3条延迟线中。其中，延迟线0、延迟线1和延迟线2分别包括2Q个存储单元、Q个存储单元以及0个存储单元，每个存储单元用于存储X＝4个符号(即40比特)。当f＝8，则Q≥23时，卷积交织的延迟线0、延迟线1和延迟线2轮询一次输出的12个RS符号来自12个不同的RS码字。示例性的，若Q＝23，则卷积交织器具体结构如图32A所示，该卷积交织器的交织时延约为46*40*3/2＝2760比特，其等效在1*800GE业务交织和解交织总时延为约52ns。
示例性的，如图33A所示，若T＝3，则L3＝3L2。发端处理模块将第一数据流中每连续3L2个符号长度的数据以第一个AMP2序列为初始位置定界为大小为X＝4个符号(即40比特)的卷积交织块，总共得到835584个卷积交织块。其中，该835584个卷积交织块中的前12个卷积交织块为AMP2序列。然后，将该连续的835584个卷积交织块轮询输入到如图32A所示的卷积交织器的延迟线0到延迟线2，即将第0个卷积交织块输入到延迟线0，将第1个卷积交织块输入到延迟线1，将第2个卷积交织块输入到延迟线2，将第3个卷积块输入到延迟线0，将第4个卷积块输入到延迟线1，将第5个卷积块输入到延迟线2，依次类推，835584个卷积交织块可以整数次轮询输入到图32A所示的卷积交织器中。如图34A所示，由于将每连续3个AMP2序列中的第一个AMP2序列的前X＝4符号固定输入到卷积交织器的延迟线0，则第一数据流经过卷积交织处理后得到第二数据流后，AMP2序列的前X＝4个符号会在第二数据流中间隔L3＝334233符号周期性的出现，标记这个已知符号为AMO2序列，即具体的数据为AMP2序列的前5个字节。也就是说，经过卷积交织处理后，已知的AMO2序列能够周期性出现，有利于收端设备中在完成内码解码后对AMO2序列进行锁定，然后将AMO2序列所在卷积交织块送到解卷积交织器的要求的延迟线中，就可以完成解卷积的同步。比如在发端处理模块进行卷积交织的时候，AMO2序列是从图32A所示卷积交织器的延迟线0输出的，则在收端模块解卷积交织的时候，AMO2序列对应的卷积交织块送到图32A所示结构卷积交织器的延迟线3，而接下来的卷积交织块依次送到延迟线2和延迟线0，依次类推。
在另一种可能的实施方式中，p＝7，X＝2。如图32B所示，将第一数据流中以AMP2为起始位置的连续T*L2符号长度的数据以X＝2个符号(即20比特，标记为一个卷积交织块，图32B中的Sr()表示为一个卷积交织块)为单位轮询(round-robin)输入到图32B所示的卷积交织器的p＝7条延迟线中得到一条第二数据流。
在一种可能的示例中，g＝8或4或2。当g＝8时，每条第一数据是由8条PCS通道数据流进行符号复用处理而获得的；当g＝4时，每条第一数据是由4条PCS通道数据流进行符号复用处理而获得的；当g＝2时，每条第一数据是由2条PCS通道数据流进行符号复用处理而获得的。第一数据流中中每间隔L2＝g*L1包含由PCS通道数据流中AM序列进行符号复用得到长度为g*120比特的AMP2序列。然后，每条第一数据据流中以AMP2序列为起始位置的连续T*L2比特数据以X＝2个符号(即20比特，标记为一个卷积交织块)为单位轮询输入到图32B所示的卷积交织器的p＝7条延迟线中第二数据流。其中，7条延迟线分别包括6Q个存储单元、5Q个存储单元、4Q个存储单元、3Q个存储单元、2Q个存储单元、1Q个存储单元以及0个存储单元，每个存储单元用于存储X＝2个符号(即20比特，即一个卷积交织块)。根据第一数据流中RS符号的分布规律，当g＝2时，即采用2：1的符号复用时，Q大于等于10，卷积交织器的7个延迟线轮询一次输出的14个符号来自14个不同的RS码字；或者，当g＝4时，即采用4:1的符号复用时，Q大于等于20，卷积交织器的7个延迟线轮询一次输出的14个符号来自14个不同的RS码字，或者，当g＝8时，即采用4:1的符号复用时，Q大于等于40，卷积交织器的7个延迟线轮询一次输出的14个符号来自14个不同的RS码字。
示例性的，如图33B所示，若T＝7，则L3＝7L2。发端处理模块将第一数据流中以AMP2序列为起始位置连续7*L2个符号长度的数据以X＝2个符号(即20比特)为单位轮询输入到图32B所示的卷积交织的7条延迟线中。以g＝4为例，其等效为如图33B所示将第一数据流中每连续7个AMP2周期的数据以第一个AMP2序列为初始位置定界为大小为X＝2个符号(即20比特)的卷积交织块，总共得到3899392个卷积交织块。其中，该3899392个卷积交织块中的前24个卷积交织块为AMP2序列。然后，将该连续 的3899392个卷积交织块轮询输入到如图32B所示的卷积交织器的延迟线0到延迟线7，即将第0个卷积交织块输入到延迟线0，将第1个卷积交织块输入到延迟线1，将第2个卷积交织块输入到延迟线2，将第3个卷积块输入到延迟线3，将第4个卷积块输入到延迟线4，将第5个卷积块输入到延迟线5，将第6个卷积块输入到延迟线6，将第7个卷积块输入到延迟线0，依次类推。3899392个卷积交织块可以整数次轮询输入到图32B所示的卷积交织器中。如图34B所示，由于将每连续7个AMP2序列中的第一个AMP2序列的前X＝2符号固定输入到卷积交织器的延迟线0，则第一数据流经过卷积交织处理得到第二数据流后，AMP2序列的前X＝2个符号会在第二数据流中间隔L3＝7*L2符号周期性的出现，标记这个已知符号为AMO2序列，其具体的数据为AMP2序列的前2个符号。也就是说，经过卷积交织处理后，第一数据流中会有已知的AMO2序列周期性出现，有利于收端设备中在完成内码解码后对AMO2序列进行锁定，然后将AMO2序列所在卷积交织块送到解卷积交织器的要求的延迟线中，就可以完成解卷积的同步。例如，在发端处理模块进行卷积交织时，若AMO2序列是从图32B所示卷积交织器的延迟线0输出的，则在收端模块解卷积交织时，AMO2序列对应的卷积交织块送到图32B所示结构卷积交织器的延迟线6，而接下来的卷积交织块依次送到延迟线5，依次类推。
需要说明的是当g＝2时，即第一数据流由2条PCS通道数据流符号复用得到，则对应的L2＝2*L1＝3342336，对应的L3＝7*L2＝6684672个符号。
在另一种可能的实施方式中，p＝4，X＝4。如图32C所示，将第一数据流中以AMP2为起始位置连续T*L2比特数据以X＝4个符号(即40比特，标记为一个卷积交织块)为单位轮询(round-robin)输入到图32C所示的卷积交织器的p＝4条延迟线中。其中，延迟线0、延迟线1、延迟线2和延迟线3分别包括3Q个存储单元、2Q个存储单元、Q个存储单以及0个存储单元，每个存储单元用于存储X＝4个符号(即40比特)。当g＝8，Q≥34时，或g＝4，Q≥17时，或g＝2，Q≥9时，卷积交织的延迟线0到延迟线3轮询一次输出的16个RS符号来自16个不同的RS码字。
示例性的，如图33C所示，若T＝1，则L3＝L2。发端处理模块将第一数据流中每连续L2的数据以第一个AMP2序列为初始位置定界为大小为X＝4个符号(即40比特)的卷积交织块。然后，将该连续的多个卷积交织块轮询输入到如图32C所示的卷积交织器的延迟线0到延迟线3，经过卷积交织处理后每条第二数据流每间隔L3＝L2个符号包含长度为X＝4个符号(即40比特)的已知序列标记为AMO2序列，且AMO2序列为AMP2序列的前40比特。其中，当采用2：1符号复用时，L2＝2*L1＝557056个符号；当采用4:1符号复用时，L2＝4*L1＝1114112个符号。
示例性的，若T＝1，则L3＝L2。发端处理模块将第一数据流中以AMP2序列为起始位置的连续L2符号长度的数据以X＝4个符号(即40比特)为单位轮询输入到图32C所示的卷积交织的4条延迟线中。其等效为如图33C(以g＝8为例)所示将第一数据流中每个AMP2周期的数据以AMP2序列为初始位置定界为大小为X＝4个符号(即40比特)的卷积交织块，总共得到557056个卷积交织块。其中，该557056个卷积交织块中的前24个卷积交织块为AMP2序列。然后，将该连续的557056个卷积交织块轮询输入到如图32C所示的卷积交织器的延迟线0到延迟线3，即将第0个卷积交织块输入到延迟线0，将第1个卷积交织块输入到延迟线1，将第2个卷积交织块输入到延迟线2，将第3个卷积块输入到延迟线0，依次类推，557056个卷积交织块可以整数次轮询输入到图32C所示的卷积交织器中。如图34C所示，由于将每个AMP2序列中的第一个AMP2序列的前X＝4符号固定输入到卷积交织器的延迟线0，则第一数据流经过卷积交织处理得到第二数据流后，AMP2序列的前X＝4个符号会在第二数据流中间隔L3＝L2符号周期性的出现，标记这个已知序列为AMO2序列，其具体的数据为AMP2序列的前4个符号。也就是说，经过卷积交织处理后，第一数据流中会有已知的AMO2序列周期性出现，有利于收端设备中在完成内码解码后对AMO2序列进行锁定，然后将AMO2序列所在卷积交织块送到解卷积交织器的要求的延迟线中，就可以完成解卷积的同步。例如，在发端处理模块进行卷积交织时，若AMO2序列是从图32C所示卷积交织器的延迟线0输出的，则在收端模块解卷积交织时，AMO2序列对应的卷积交织块送到图32C所示结构卷积交织器的延迟线6，而接下来的卷积交织块依次送到延迟线5，依次类推。
步骤2703，将f条第二数据流中每条第二数据流中每连续K个比特作为一个编码块进行第二FEC编码处理得到f条编码数据流。
其中，10倍L3能被K整除，所述K为连续的第二FEC码字信息位的长度，所述K为大于1的整数。可选的，K＝120、136或160。
经过卷积交织处理后，发端处理模块对每条第二数据流分别进行第二FEC编码(也被称为内码编码)处理。具体地，发端处理模块对每条第二数据流中连续L3个符号进行第二FEC编码，得到c个第二FEC码字。其中，连续L3个符号的前X个符号为AMo2序列，所述c个第二FEC码字中的第一个第二FEC码字包括所述AMo2序列，所述c为(L3*10)/K，所述c为大于1的整数。
本步骤中，为了可以使得收端处理模块利用AMO进行内码码字(即第二FEC码字)同步，则发端处理模块在进行第二FEC编码(即内码编码)时需要使AMO2序列与第二FEC码字(即内码码字)同步，即AMO2序列固定为第二FEC码字(即内码码字)的固定位置。图35A、图35B和图35C分别为本申请提供的几种固定AMO2序列的编码实现方式。由于，AMO2序列固定在内码码字的前40个比特，即AMO2序列能够周期性出现在编码数据流中，因此，收端处理模块可以基于编码数据流中的AMO2序列进行内码码字的同步和解卷积交织器的同步。
在一种可能的实施方式中，K＝136比特，即第二FEC码字信息位的长度为136比特。如图35A所示，发端处理模块以AMO2序列(即4个RS符号)为起始位置将第二数据流中每连续的136比特划分为一个内码信息块(即第二FEC信息块)，则连续2个AMO2序列之间的数据划分为245760个内码码字信息块。然后，对每个内码信息块添加8比特的冗余信息，得到144比特的内码码字。第二FEC编码后每间隔L4＝245760个内码码字包含长度为40比特的AMO2序列。
在另一种可能的实施方式中，K＝120比特，即第二FEC码字信息位的长度为120比特。如图35B所示，发端处理模块以AMO2序列(即4个RS符号)为起始位置将第二数据流每连续的120比特划分为一个内码信息块(即第二FEC信息块)，则连续2个AMO2序列之间数据划分为278528个内码码字信息块。然后，对每个内码信息块添加8比特的冗余信息，得到128比特的内码码字。第二FEC编码后每间隔L4＝278528个内码码字包含长度为40比特的AMO2序列。
在另一种可能的实施方式中，K＝160比特，即第二FEC码字信息位的长度为160比特。如图35C所示，发端处理模块以AMO2序列(即4个RS符号)为起始位置将第二数据流每连续的160比特划分为一个内码信息块(即第二FEC信息块)，则连续2个AMO2序列之间数据划分为208896个内码码字信息块。然后，对每个内码信息块添加16比特的冗余信息，得到176比特的内码码字。第二FEC编码后每间隔L4＝208896个内码码字包含长度为40比特的AMO2序列。
本实施例中，发端处理模块能够在卷积交织处理过程中和AMp2序列对齐，在内码编码处理过程中与AMo2序列对齐，在不需要增加额外的冗余信息的情况下，可以使得第二数据流以及编码数据流周期性的出现已知序列，使得收端处理模块可以利用这个周期性的已知序列进行内码的同步，进而有利于降低收端的处理复杂度。
如图36所示，为本实施例提供的一种数据处理装置360的结构示意图。应当理解的是，前述图27对应的方法实施例中的发端处理模块可以基于本实施例中图36的结构。如图36所示，该数据处理装置360包括接收处理模块3601、卷积交织模块3602和、FEC编码模块3603。其中，接收处理模块3601，用于获取f条第一数据流，f条第一数据流都经过第一前向纠错FEC编码，第一数据流中连续的a个数据单位来自a个不同的第一FEC码字，每条第一数据流中每间隔L2个符号包含一个AMp2序列，AMp2序列的长度为Y个符号，f条第一数据流中的AMp2序列的至少前X个符号相同，后(Y-X)个符号互不相同，f为大于1的整数，a为大于1的整数，L2为大于1的整数，X为大于1且小于等于a的整数，Y为大于X的整数。卷积交织模块3602，用于将f条第一数据流中的每条第一数据流中每连续X个符号作为一个卷积交织块进行卷积交织处理得到f条第二数据流，第二数据流每间隔L3个符号包含一条AMo2序列，AMo2序列为AMp2序列的前X个符号，L3为大于1的整数，L3能被L2整除。FEC编码模块3603，用于将f条第二数据流中每条第二数据流中每连续K个比特作为一个编码块进行第二FEC编码处理得到f条编码数据流，10倍L3能被K整除，K为连续的第二FEC码字信息位的长度，K为大于1的整数。
在一种可能的实施方式中，卷积交织模块3602具体用于将每条第一数据流中的每连续的T*L2个符号以X个符号为单位轮询输入到卷积交织器的p个延迟线中，得到第二数据流，每连续的T*L2个符号的前Y个符号为AMp2序列，L3＝T*L2，T*L2能被X*p整除。
在一种可能的实施方式中，FEC编码模块3603具体用于对每条第二数据流中连续L3个符号进行第二FEC编码，得到c个第二FEC码字，连续L3个符号的前X个符号为AMo2序列，c个第二FEC码字中的第一个第二FEC码字包括AMo2序列，c为(L3*10)/K，c为大于1的整数。
在一种可能的实施方式中，每条第一数据流是基于g条PCS通道数据流进行复用处理而获得的数据流，AMp2序列为g条PCS通道数据流的AM序列经过复用处理而获得的序列，AMp2序列的长度Y为AM序列的长度的g倍。
在一种可能的实施方式中，接收处理模块3601具体用于从连接单元接口AUI接收e条PMA通道数据流，并对每条PMA通道数据流中的AMp2序列进行AM锁定得到f条第一数据流，e为AUI接口包含的物理通道的数量，f等于e，每条第一数据流是基于g条PCS通道数据流进行基于比特粒度的复用处理或基于符号粒度的复用处理而获得的数据流；其中，若每条所述第一数据流是基于所述g条PCS通道数据流进行基于比特粒度的复用处理，则所述a个数据单位为a个比特；若每条所述第一数据流是基于所述g条PCS通道数据流进行基于符号粒度的复用处理，则所述a个数据单位为a个符号。
在一种可能的实施方式中，接收处理模块3601具体用于对从连接单元接口AUI接收的e条PMA通道数据流进行第一解复用处理，得到n条PCS通道数据流，e为AUI接口包含的物理通道的数量；对n条PCS通道数据流进行AM锁定和AM对齐后再对n条PCS通道数据流中每g条PCS通道数据流进行第一复用处理，得到f条第一数据流，f等于n/g，f大于或等于e。
可选的，每条PMA通道数据流为基于n/e条PCS通道数据流进行基于比特粒度的复用处理而获得的数据流，第一解复用处理为基于比特粒度的解复用处理，第一复用处理为基于符号粒度的复用处理，所述a个数据单位为a个符号；或者，每条PMA通道数据流为基于n/e条PCS通道数据流进行基于符号粒度的复用处理而获得的数据流，第一解复用处理为基于符号粒度的解复用处理，第一复用处理为基于符号粒度的复用处理，所述a个数据单位为a个比特。
其余可以参考上述图27对应实施例中发端处理模块的方法，此处不再赘述。
如图37所示，为本实施例提供的另一种数据处理装置370的结构示意图。应当理解的是，前述图27对应的方法实施例中的发端处理模块可以基于本实施例中图37所示的数据处理装置370的结构。如图37所示，该数据处理装置370可以包括处理器3701、存储器3702和收发器3703。其中，该处理器3701与该存储器3702耦合连接，该处理器3701与该收发器3703耦合连接。
其中，前述收发器3703也可以称为收发单元、收发机、收发装置等。可选地，可以将收发单元中用于实现接收功能的器件视为接收单元，将收发单元中用于实现发送功能的器件视为发送单元，即收发单元包括接收单元和发送单元，接收单元也可以称为接收机、输入口、接收电路等，发送单元可以称为发射机、发射器或者发射电路等。
其中，前述处理器3701可以是中央处理器(central processing unit，CPU)、专用集成电路(application-specific integrated circuit，ASIC)、可编程逻辑器件(programmable logic device，PLD)或其组合。上述PLD可以是复杂可编程逻辑器件(complex programmable logic device，CPLD)，现场可编程逻辑门阵列(field-programmable gate array，FPGA)，通用阵列逻辑(generic array logic，GAL)或其任意组合。处理器3701可以是指一个处理器，也可以包括多个处理器，具体此处不做限定。
此外，前述该存储器3702主要用于存储软件程序和数据。存储器3702可以是独立存在，与处理器3701相连。可选地，该存储器3702可以和该处理器3701集成于一体，例如集成于一个或多个芯片之内。其中，该存储器3702能够存储执行本申请实施例的技术方案的程序代码，并由处理器3701来控制执行，被执行的各类计算机程序代码也可被视为是处理器3701的驱动程序。存储器3702可以包括易失性存储器(volatile memory)，例如随机存取存储器(random-access memory，RAM)；存储器也可以包括非易失性存储器(non-volatile memory)，例如只读存储器(read-only memory，ROM)，快闪存储器(flash  memory)，硬盘(hard disk drive，HDD)或固态硬盘(solid-state drive，SSD)；存储器3702还可以包括上述种类的存储器的组合。存储器3702可以是指一个存储器，也可以包括多个存储器。示例性的，存储器3702，用于存储各种数据。具体地，请参阅前文实施例中的相关介绍，此处不予赘述。
在一个实现方式中，存储器3702中存储有计算机可读指令，所述计算机可读指令包括多个软件模块，例如，前述图36介绍的接收处理模块3601、卷积交织模块3602和、FEC编码模块3603等。具体请参阅前文图36中的相关描述，此处不再赘述。
此外，本申请提供了一种计算机程序产品，该计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行该计算机程序指令时，全部或部分地产生按照本申请实施例该的流程或功能。例如，实现如前述图3、图11A、图13A、图14A、图15以及图27中的数据处理装置相关的方法。该计算机可以是通用计算机、专用计算机、计算机网络或者其他可编程装置。该计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一计算机可读存储介质传输，例如，该计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如，同轴电缆、光纤、数字用户线(digital subscriber line，DSL))或无线(例如，红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。该计算机可读存储介质可以是计算机能够存储的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。该可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，数字通用光盘(digital versatile disc，DVD))、或者半导体介质(例如固态硬盘(solid state disk，SSD))等。
此外，本申请还提供了一种计算机可读存储介质，该存储介质存储有计算机程序，该计算机程序被处理器执行以实现如前述图3、图11A、图13A、图14A、图15以及图27中的数据处理装置相关的方法。
应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统，装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。

Claims (50)

  1. 一种数据处理方法，其特征在于，包括：
    对n条通道数据流中每R/2条来自第一通道数据流集合的通道数据流与每R/2条来自第二通道数据流集合的通道数据流进行通道置换处理得到R条第一数据流，总共得到n条第一数据流，所述n条通道数据流都经过第一前向纠错FEC编码，所述第一通道数据流集合中的数据与所述第二通道数据流集合中的数据来自不同的第一FEC码字，所述通道数据流中连续的a个符号来自a个不同的第一FEC码字，所述第一数据流中连续的2a个符号来自2a个不同的第一FEC码字，所述n为大于1的整数，所述a为大于1的整数，所述R为大于1的偶数且所述n能被R整除；
    对所述n条第一数据流中的每条第一数据流进行卷积交织处理得到n条第二数据流，所述第二数据流中连续的b个符号来自b个不同的第一FEC码字，所述b为大于1的整数，b能被a整除；
    对所述n条第二数据流中每条第二数据流进行第二FEC编码处理得到n条编码数据流，所述n条编码数据流包括S个编码数据流集合，每个编码数据流集合包括R条编码数据流，所述R条编码数据流的数据来自R条进行通道置换的通道数据流，所述R条进行通道置换的通道数据流包括所述R/2条来自第一通道数据流集合的通道数据流和所述R/2条来自第二通道数据流集合的通道数据流，所述S＝n/R；
    将所述n条编码数据流中每q个编码数据流集合进行信道交织为1条第三数据流，总共得到m条第三数据流，其中，m＝S/q，所述q为大于0的整数，且，所述S能被q整除。
  2. 根据权利要求1所述的方法，其特征在于，所述R＝2；
    对n条通道数据流中每R/2条来自第一通道数据流集合的通道数据流与每R/2条来自第二通道数据流集合的通道数据流进行通道置换处理得到R条第一数据流，总共得到n条第一数据流，包括：
    对通道数据流i与通道数据流i+(n/2)进行通道置换，得到2条第一数据流，其中，i为大于等于0且小于n/2的整数。
  3. 根据权利要求2所述的方法，其特征在于，所述q＝4；
    所述将所述n条编码数据流中每q个编码数据流集合进行信道交织为1条第三数据流，总共得到m条第三数据流，包括：
    将编码数据流i0、编码数据流i1、编码数据流i2、编码数据流i3、编码数据流i0+(n/2)、编码数据流i1+(n/2)、编码数据流i2+(n/2)和编码数据流i3+(n/2)进行信道交织为1条第三数据流；其中，0≤i0≤15，0≤i1≤15，0≤i2≤15，0≤i3≤15。
  4. 根据权利要求3所述的方法，其特征在于，
    i1＝i0+1，i2＝i0+2，i3＝i0+3；其中，i0＝0、4、8或12；
    或者，
    i1＝i0+4，i2＝i0+8，i3＝i0+12；其中，i0＝0、1、2或3。
  5. 根据权利要求1至4中任意一项所述的方法，其特征在于，所述将所述n条编码数据流中每q个编码数据流集合进行信道交织为1条第三数据流，总共得到m条第三数据流之前，所述方法还包括：
    采用长度为Q*N比特的伪随机二进制序列对每条编码数据流中的Q个连续第二FEC码字进行加扰处理，得到加扰后的n条编码数据流，所述N为第二FEC码字长度，所述N为大于1的整数，所述Q为大于或等于1的整数。
  6. 根据权利要求1至4中任意一项所述的方法，其特征在于，所述将所述n条编码数据流中每q个编码数据流集合进行信道交织为1条第三数据流，总共得到m条第三数据流之后，所述方法还包括：
    采用长度为R*q*Q*N比特的伪随机二进制序列对每条第三数据流中连续的R*q*Q*N比特进行加扰处理，得到加扰后的m条第三数据流，所述第三数据流中连续的R*q*Q*N比特为R*q条编码数据流中各连续Q个第二FEC码字进行信道交织而生成的R*q*Q*N比特，所述N为大于1的整数，所述Q为大于或等于1的整数。
  7. 根据权利要求1至4中任意一项所述的方法，其特征在于，所述对n条第二数据流中每条第二数据流进行第二FEC编码处理得到n条编码数据流之前，所述方法还包括：
    采用长度为Q*K比特的伪随机二进制序列对每条第二数据流中的Q个连续第二FEC码字信息位进 行加扰处理，得到加扰后的n条第二数据流，所述K为连续第二FEC码字信息位的长度，所述K为大于1的整数，所述Q为大于或等于1的整数。
  8. 根据权利要求1至4中任意一项所述的方法，其特征在于，所述对n条通道数据流中每R/2条来自第一通道数据流集合的通道数据流与每R/2条来自第二通道数据流集合的通道数据流进行通道置换处理得到R条第一数据流，总共得到n条第一数据流之前，所述方法还包括：
    对所述n条通道数据流进行基于AM序列的对齐处理，所述AM序列为所述通道数据流中携带的AM序列。
  9. 根据权利要求8所述的方法，其特征在于，所述n条第一数据流中每条第一数据流每间隔L1个比特包括一条AMp序列，所述AMp序列包括15个字节；
    其中，每条第一数据流中的AMp序列的前8个字节与对应的通道数据流中的AM序列的前8个字节相同，每条第一数据流中的AMp序列的后7个字节与对应的通道数据流中的AM序列的后7个字节不同，不同的第一数据流中的AMp序列的后7个字节各不相同。
  10. 根据权利要求9所述的方法，其特征在于，所述对所述n条第一数据流中的每条第一数据流进行卷积交织处理得到n条第二数据流，包括：
    将每条所述第一数据流中的每连续的T*L1个符号以d个符号为单位轮询输入到卷积交织器的p个延迟线中，得到第二数据流，所述每连续的T*L1个符号的前t个比特为所述AMp序列，所述第二数据流每间隔L2符号包含一条AMo序列，所述AMo序列为所述AMp序列的前d个符号，所述L2＝T*L1，所述T*L1能被d*p整除。
  11. 根据权利要求10所述的方法，其特征在于，所述对n条第二数据流中每条第二数据流进行第二FEC编码处理得到n条编码数据流，包括：
    对每条所述第二数据流中连续L2符号进行第二FEC编码，得到c个第二FEC码字，所述连续L2符号的前d个符号为所述AMo序列，所述c为L2/K，所述K为连续第二FEC码字信息位的长度，所述K为大于1的整数。
  12. 根据权利要求8至11中任意一项所述的方法，其特征在于，所述方法还包括：
    将所述n条通道数据流中每条通道数据流中的所述AM序列替换为AM*序列，不同的通道数据流中的所述AM*序列的前5个字节均相同。
  13. 根据权利要求5至7中任意一项所述的方法，其特征在于，所述Q为大于等于8或小于等于16的整数。
  14. 根据权利要求1所述的方法，其特征在于，所述n＝32，所述R＝2或4，所述q＝1、2或4。
  15. 一种数据处理装置，其特征在于，包括：
    通道置换模块，用于对n条通道数据流中每R/2条来自第一通道数据流集合的通道数据流与每R/2条来自第二通道数据流集合的通道数据流进行通道置换处理得到R条第一数据流，总共得到n条第一数据流，所述n条通道数据流都经过第一前向纠错FEC编码，所述第一通道数据流集合中的数据与所述第二通道数据流集合中的数据来自不同的第一FEC码字，所述通道数据流中连续的a个符号来自a个不同的第一FEC码字，所述第一数据流中连续的2a个符号来自2a个不同的第一FEC码字，所述n为大于1的整数，所述a为大于1的整数，所述R为大于1的偶数且所述n能被R整除；
    卷积交织模块，用于对所述n条第一数据流中的每条第一数据流进行卷积交织处理得到n条第二数据流，所述通道数据流中连续的b个符号来自b个不同的第一FEC码字，所述b为大于1的整数，b能被a整除；
    FEC编码模块，用于对所述n条第二数据流中每条第二数据流进行第二FEC编码处理得到n条编码数据流，所述n条编码数据流包括S个编码数据流集合，每个编码数据流集合包括R条编码数据流，所述R条编码数据流的数据来自R条进行通道置换的通道数据流，所述R条进行通道置换的通道数据流包括所述R/2条来自第一通道数据流集合的通道数据流和所述R/2条来自第二通道数据流集合的通道数据流，所述S＝n/R；
    信道交织模块，用于将所述n条编码数据流中每q个编码数据流集合进行信道交织为1条第三数据 流，总共得到m条第三数据流，其中，m＝S/q，所述q为大于0的整数，且，所述S能被q整除。
  16. 根据权利要求15所述的数据处理装置，其特征在于，所述R＝2；
    通道置换模块，具体用于对通道数据流i与通道数据流i+(n/2)进行通道置换，得到2条第一数据流，其中，i为大于等于0且小于n/2的整数。
  17. 根据权利要求16所述的数据处理装置，其特征在于，所述q＝4；
    所述信道交织模块，具体用于将编码数据流i0、编码数据流i1、编码数据流i2、编码数据流i3、编码数据流i0+(n/2)、编码数据流i1+(n/2)、编码数据流i2+(n/2)和编码数据流i3+(n/2)进行信道交织为1条第三数据流；其中，0≤i0≤15，0≤i1≤15，0≤i2≤15，0≤i3≤15。
  18. 根据权利要求17所述的数据处理装置，其特征在于，
    i1＝i0+1，i2＝i0+2，i3＝i0+3；其中，i0＝0、4、8或12；
    或者，
    i1＝i0+4，i2＝i0+8，i3＝i0+12；其中，i0＝0、1、2或3。
  19. 根据权利要求15至18中任意一项所述的数据处理装置，其特征在于，所述数据处理装置还包括第一加扰模块，所述第一加扰模块位于所述第二FEC编码模块与所述信道交织模块之间；
    所述第一加扰模块，用于采用长度为Q*N比特的伪随机二进制序列对每条编码数据流中的Q个连续第二FEC码字进行加扰处理，得到加扰后的n条编码数据流，所述N为第二FEC码字长度，所述N为大于1的整数，所述Q为大于或等于1的整数。
  20. 根据权利要求15至18中任意一项所述的数据处理装置，其特征在于，所述数据处理装置还包括第二加扰模块，所述第二加扰模块位于所述信道交织模块之后；
    所述第二加扰模块，用于采用长度为R*q*Q*N比特的伪随机二进制序列对每条第三数据流中连续的R*q*Q*N比特进行加扰处理，得到加扰后的m条第三数据流，所述第三数据流中连续的R*q*Q*N比特为R*q条编码数据流中各连续Q个第二FEC码字进行信道交织而生成的R*q*Q*N比特，所述N为大于1的整数，所述Q为大于或等于1的整数。
  21. 根据权利要求15至18中任意一项所述的数据处理装置，其特征在于，所述数据处理装置还包括第三加扰模块，所述第三加扰模块位于所述卷积交织模块与所述第二FEC编码模块之间；
    所述第三加扰模块，用于采用长度为Q*K比特的伪随机二进制序列对每条第二数据流中的Q个连续第二FEC码字信息位进行加扰处理，得到加扰后的n条第二数据流，所述K为连续第二FEC码字信息位的长度，所述K为大于1的整数，所述Q为大于或等于1的整数。
  22. 根据权利要求15至18中任意一项所述的数据处理装置，其特征在于，所述信道交织模块之前，所述数据处理装置还包括：
    对齐处理模块，用于对所述n条通道数据流进行基于AM序列的对齐处理，所述AM序列为所述通道数据流中携带的AM序列。
  23. 根据权利要求22所述的数据处理装置，其特征在于，所述n条第一数据流中每条第一数据流每间隔L1个比特包括一条AMp序列，所述AMp序列包括15个字节；
    其中，每条第一数据流中的AMp序列的前8个字节与对应的通道数据流中的AM序列的前8个字节相同，每条第一数据流中的AMp序列的后7个字节与对应的通道数据流中的AM序列的后7个字节不同，不同的第一数据流中的AMp序列的后7个字节各不相同。
  24. 根据权利要求23所述的数据处理装置，其特征在于，所述卷积交织模块，具体用于将每条所述第一数据流中的每连续的T*L1个符号以d个符号为单位轮询输入到卷积交织器的p个延迟线中，得到第二数据流，所述每连续的T*L1个符号的前t个比特为所述AMp序列，所述第二数据流每间隔L2符号包含一条AMo序列，所述AMo序列为所述AMp序列的前d个符号，所述L2＝T*L1，所述T*L1能被d*p整除。
  25. 根据权利要求24所述的数据处理装置，其特征在于，所述第二FEC编码模块，具体用于对每条所述第二数据流中连续L2符号进行第二FEC编码，得到c个第二FEC码字，所述连续L2符号的前d个符号为所述AMo序列，所述c为L2/K，所述K为连续第二FEC码字信息位的长度，所述K为大于1 的整数。
  26. 根据权利要求22至25中任意一项所述的数据处理装置，其特征在于，所述数据处理装置还包括：
    AM序列处理模块，用于将所述n条通道数据流中每条通道数据流中的所述AM序列替换为AM*序列，不同的通道数据流中的所述AM*序列的前5个字节均相同。
  27. 根据权利要求19至21中任意一项所述的数据处理装置，其特征在于，所述Q为大于等于8或小于等于16的整数。
  28. 根据权利要求15所述的数据处理装置，其特征在于，所述n＝32，所述R＝2或4，所述q＝1、2或4。
  29. 一种数据处理方法，其特征在于，包括：
    获取f条第一数据流，所述f条第一数据流都经过第一前向纠错FEC编码，所述第一数据流中连续的a个数据单位来自a个不同的第一FEC码字，每条所述第一数据流中每间隔L2个符号包含一个AMp2序列，所述AMp2序列的长度为Y个符号，所述f条第一数据流中的AMp2序列的至少前X个符号相同，后(Y-X)个符号互不相同，所述f为大于1的整数，所述a为大于1的整数，所述L2为大于1的整数，所述X为大于1且小于等于a的整数，所述Y为大于所述X的整数；
    将所述f条第一数据流中的每条第一数据流中每连续X个符号作为一个卷积交织块进行卷积交织处理得到f条第二数据流，所述第二数据流每间隔L3个符号包含一条AMo2序列，所述AMo2序列为所述AMp2序列的前X个符号，所述L3为大于1的整数，所述L3能被L2整除；
    将所述f条第二数据流中每条第二数据流中每连续K个比特作为一个编码块进行第二FEC编码处理得到f条编码数据流，10倍所述L3能被所述K整除，所述K为连续的第二FEC码字信息位的长度，所述K为大于1的整数。
  30. 根据权利要求29所述的方法，其特征在于，所述将所述f条第一数据流中的每条第一数据流中每连续X个符号作为一个卷积交织块进行卷积交织处理得到f条第二数据流，包括：
    将每条所述第一数据流中的每连续的T*L2个符号以X个符号为单位轮询输入到卷积交织器的p个延迟线中，得到第二数据流，所述每连续的T*L2个符号的前Y个符号为所述AMp2序列，所述L3＝T*L2，所述T*L2能被X*p整除。
  31. 根据权利要求30所述的方法，其特征在于，所述将所述f条第二数据流中每条第二数据流中每连续K个比特作为一个编码块进行第二FEC编码处理得到f条编码数据流，包括：
    对每条所述第二数据流中连续L3个符号进行第二FEC编码，得到c个第二FEC码字，所述连续L3个符号的前X个符号为所述AMo2序列，所述c个第二FEC码字中的第一个第二FEC码字包括所述AMo2序列，所述c为(L3*10)/K，所述c为大于1的整数。
  32. 根据权利要求29至31中任意一项所述的方法，其特征在于，每条所述第一数据流是基于g条PCS通道数据流进行复用处理而获得的数据流，所述AMp2序列为所述g条PCS通道数据流的AM序列经过复用处理而获得的序列，所述AMp2序列的长度Y为所述AM序列的长度的g倍。
  33. 根据权利要求32所述的方法，其特征在于，所述获取f条第一数据流，包括：
    从连接单元接口AUI接收e条PMA通道数据流，并对每条所述PMA通道数据流中的AMp2序列进行AM锁定得到所述f条第一数据流，所述e为所述AUI接口包含的物理通道的数量，所述f等于所述e，每条所述第一数据流是基于所述g条PCS通道数据流进行基于比特粒度的复用处理或基于符号粒度的复用处理而获得的数据流；
    其中，若每条所述第一数据流是基于所述g条PCS通道数据流进行基于比特粒度的复用处理，则所述a个数据单位为a个比特；若每条所述第一数据流是基于所述g条PCS通道数据流进行基于符号粒度的复用处理，则所述a个数据单位为a个符号。
  34. 根据权利要求32所述的方法，其特征在于，所述获取f条第一数据流，包括：
    对从连接单元接口AUI接收的e条PMA通道数据流进行第一解复用处理，得到n条PCS通道数据流，所述e为所述AUI接口包含的物理通道的数量；
    对所述n条PCS通道数据流进行AM锁定和AM对齐后再对所述n条PCS通道数据流中每g条PCS 通道数据流进行第一复用处理，得到所述f条第一数据流，所述f等于n/g，所述f大于或等于所述e。
  35. 根据权利要求34所述的方法，其特征在于，
    每条所述PMA通道数据流为基于所述n/e条PCS通道数据流进行基于比特粒度的复用处理而获得的数据流，所述第一解复用处理为基于比特粒度的解复用处理，所述第一复用处理为基于符号粒度的复用处理，所述a个数据单位为a个符号；或者，
    每条所述PMA通道数据流为基于所述n/e条PCS通道数据流进行基于符号粒度的复用处理而获得的数据流，所述第一解复用处理为基于符号粒度的解复用处理，所述第一复用处理为基于符号粒度的复用处理，所述a个数据单位为a个符号。
  36. 根据权利要求29至35中任意一项所述的方法，其特征在于，所述f＝4或8或16，所述X＝2或4，所述K＝120、136或160。
  37. 根据权利要求30至36中任意一项所述的方法，其特征在于，所述T＝2或3或7，所述p＝3或4或7。
  38. 根据权利要求32至37中任意一项所述的方法，其特征在于，所述g＝2或4或8。
  39. 一种数据处理装置，其特征在于，包括：
    接收处理模块，用于获取f条第一数据流，所述f条第一数据流都经过第一前向纠错FEC编码，所述第一数据流中连续的a个数据单位来自a个不同的第一FEC码字，每条所述第一数据流中每间隔L2个符号包含一个AMp2序列，所述AMp2序列的长度为Y个符号，所述f条第一数据流中的AMp2序列的至少前X个符号相同，后(Y-X)个符号互不相同，所述f为大于1的整数，所述a为大于1的整数，所述L2为大于1的整数，所述X为大于1且小于等于a的整数，所述Y为大于所述X的整数；
    卷积交织模块，用于将所述f条第一数据流中的每条第一数据流中每连续X个符号作为一个卷积交织块进行卷积交织处理得到f条第二数据流，所述第二数据流每间隔L3个符号包含一条AMo2序列，所述AMo2序列为所述AMp2序列的前X个符号，所述L3为大于1的整数，所述L3能被L2整除；
    FEC编码模块，用于将所述f条第二数据流中每条第二数据流中每连续K个比特作为一个编码块进行第二FEC编码处理得到f条编码数据流，10倍所述L3能被所述K整除，所述K为连续的第二FEC码字信息位的长度，所述K为大于1的整数。
  40. 根据权利要求39所述的数据处理装置，其特征在于，所述卷积交织模块，具体用于将每条所述第一数据流中的每连续的T*L2个符号以X个符号为单位轮询输入到卷积交织器的p个延迟线中，得到第二数据流，所述每连续的T*L2个符号的前Y个符号为所述AMp2序列，所述L3＝T*L2，所述T*L2能被X*p整除。
  41. 根据权利要求40所述的数据处理装置，其特征在于，所述FEC编码模块，具体用于对每条所述第二数据流中连续L3个符号进行第二FEC编码，得到c个第二FEC码字，所述连续L3个符号的前X个符号为所述AMo2序列，所述c个第二FEC码字中的第一个第二FEC码字包括所述AMo2序列，所述c为(L3*10)/K，所述c为大于1的整数。
  42. 根据权利要求39至41中任意一项所述的数据处理装置，其特征在于，每条所述第一数据流是基于g条PCS通道数据流进行复用处理而获得的数据流，所述AMp2序列为所述g条PCS通道数据流的AM序列经过复用处理而获得的序列，所述AMp2序列的长度Y为所述AM序列的长度的g倍。
  43. 根据权利要求42所述的数据处理装置，其特征在于，所述接收处理模块，具体用于从连接单元接口AUI接收e条PMA通道数据流，并对每条所述PMA通道数据流中的AMp2序列进行AM锁定得到所述f条第一数据流，所述e为所述AUI接口包含的物理通道的数量，所述f等于所述e，每条所述第一数据流是基于所述g条PCS通道数据流进行基于比特粒度的复用处理或基于符号粒度的复用处理而获得的数据流；
    其中，若每条所述第一数据流是基于所述g条PCS通道数据流进行基于比特粒度的复用处理，则所述a个数据单位为a个比特；若每条所述第一数据流是基于所述g条PCS通道数据流进行基于符号粒度的复用处理，则所述a个数据单位为a个符号。
  44. 根据权利要求42所述的数据处理装置，其特征在于，所述接收处理模块，具体用于对从连接单 元接口AUI接收的e条PMA通道数据流进行第一解复用处理，得到n条PCS通道数据流，所述e为所述AUI接口包含的物理通道的数量；以及，对所述n条PCS通道数据流进行AM锁定和AM对齐后再对所述n条PCS通道数据流中每g条PCS通道数据流进行第一复用处理，得到所述f条第一数据流，所述f等于n/g，所述f大于或等于所述e。
  45. 根据权利要求44所述的数据处理装置，其特征在于，
    每条所述PMA通道数据流为基于所述n/e条PCS通道数据流进行基于比特粒度的复用处理而获得的数据流，所述第一解复用处理为基于比特粒度的解复用处理，所述第一复用处理为基于符号粒度的复用处理，所述a个数据单位为a个符号；或者，
    每条所述PMA通道数据流为基于所述n/e条PCS通道数据流进行基于符号粒度的复用处理而获得的数据流，所述第一解复用处理为基于符号粒度的解复用处理，所述第一复用处理为基于符号粒度的复用处理，所述a个数据单位为a个符号。
  46. 根据权利要求39至45中任意一项所述的数据处理装置，其特征在于，所述f＝4或8或16，所述X＝2或4，所述K＝120、136或160。
  47. 根据权利要求40至46中任意一项所述的数据处理装置，其特征在于，所述T＝2或3或7，所述p＝3或4或7。
  48. 根据权利要求42至47中任意一项所述的数据处理装置，其特征在于，所述g＝2或4或8。
  49. 一种数据处理装置，其特征在于，包括处理器和存储器；
    其中，存储器存储有计算机程序；
    所述处理器调用所述计算机程序以使得所述数据处理装置执行如权利要求1至14中任意一项所述的方法，或者，执行如权利要求29至38中任意一项所述的方法。
  50. 一种计算机可读存储介质，存储有指令，当所述指令在计算机上运行时，使得计算机执行如权利要求1至14中任意一项所述的方法，或者，执行如权利要求29至38中任意一项所述的方法。
PCT/CN2023/118196 2022-09-15 2023-09-12 一种数据处理方法以及数据处理装置 WO2024055954A1 (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN202211124570.2 2022-09-15
CN202211124570 2022-09-15
CN202211451013.1A CN117713992A (zh) 2022-09-15 2022-11-19 一种数据处理方法以及数据处理装置
CN202211451013.1 2022-11-19

Publications (1)

Publication Number Publication Date
WO2024055954A1 true WO2024055954A1 (zh) 2024-03-21

Family

ID=90142977

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/118196 WO2024055954A1 (zh) 2022-09-15 2023-09-12 一种数据处理方法以及数据处理装置

Country Status (2)

Country Link
CN (1) CN117713992A (zh)
WO (1) WO2024055954A1 (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5592492A (en) * 1994-05-13 1997-01-07 Lsi Logic Corporation Convolutional interleaving/de-interleaving method and apparatus for data transmission
CN110830171A (zh) * 2013-12-17 2020-02-21 华为技术有限公司 接收数据的方法及设备，以及发送数据的方法及设备
WO2020227976A1 (zh) * 2019-05-15 2020-11-19 华为技术有限公司 一种数据传输方法和装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5592492A (en) * 1994-05-13 1997-01-07 Lsi Logic Corporation Convolutional interleaving/de-interleaving method and apparatus for data transmission
CN110830171A (zh) * 2013-12-17 2020-02-21 华为技术有限公司 接收数据的方法及设备，以及发送数据的方法及设备
WO2020227976A1 (zh) * 2019-05-15 2020-11-19 华为技术有限公司 一种数据传输方法和装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
LIU LONGWEN, LIU ZHI: "On several key issues in channel coding", CATV TECHNOLOGY, vol. 3, 31 March 2007 (2007-03-31), pages 53 - 56, XP093146632, DOI: 10.16045/j.cnki.catvtec.2007.03.015 *

Also Published As

Publication number Publication date
CN117713992A (zh) 2024-03-15

Similar Documents

Publication Publication Date Title
CN101529775B (zh) 与64b/66b加扰兼容的多链路传输的前向纠错编码
JP2715900B2 (ja) 並列データ伝送装置
CA3072857C (en) Forward error correction with compression coding
WO2022088709A1 (zh) 一种以太网的编码方法及装置
US20100262887A1 (en) High Integrity Data Network System and Method
US11936475B2 (en) Method, apparatus, and system for improving reliability of data transmission involving an ethernet device
US20220321255A1 (en) Multi-wire permuted forward error correction
US20230224194A1 (en) Data encoding method, data decoding method, and communication apparatus
Luyi et al. Forward error correction
WO2024055954A1 (zh) 一种数据处理方法以及数据处理装置
US11804855B2 (en) Pipelined forward error correction for vector signaling code channel
WO2020114318A1 (zh) 一种编码方法、解码方法及装置
WO2023246477A1 (zh) 一种数据处理方法及数据处理装置
WO2023143130A1 (zh) 一种数据处理方法和数据处理装置
WO2024087758A1 (zh) 一种数据处理方法和数据处理装置
WO2023029880A1 (zh) 一种数据交织方法及数据交织装置
WO2023015863A1 (zh) 数据传输的方法、装置、设备、系统及可读存储介质
CN112543080A (zh) 误码率检测的方法和装置
CN116781233A (zh) 一种数据处理方法及第二通信装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23864686

Country of ref document: EP

Kind code of ref document: A1