WO2020215445A1 - 一种氧化镓半导体叠层结构及其制备方法 - Google Patents

一种氧化镓半导体叠层结构及其制备方法 Download PDF

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WO2020215445A1
WO2020215445A1 PCT/CN2019/089460 CN2019089460W WO2020215445A1 WO 2020215445 A1 WO2020215445 A1 WO 2020215445A1 CN 2019089460 W CN2019089460 W CN 2019089460W WO 2020215445 A1 WO2020215445 A1 WO 2020215445A1
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gallium oxide
oxide semiconductor
layer
phase
silicon substrate
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French (fr)
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陈梓敏
王钢
陈伟驱
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中山大学
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02491—Conductive materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02551—Group 12/16 materials
    • H01L21/02554—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body

Definitions

  • the invention belongs to the field of semiconductor materials and device preparation, and mainly relates to a growth method capable of realizing high-quality gallium oxide semiconductors on a silicon substrate and semiconductor devices prepared based on the same.
  • Gallium oxide (Ga 2 O 3 ) has five phases of ⁇ , ⁇ , ⁇ , ⁇ , and ⁇ , of which ⁇ phase is the stable phase, followed by the ⁇ phase, followed by the ⁇ phase, and the ⁇ and ⁇ phases have poor stability.
  • Ga 2 O 3 semiconductor is an ideal electronic device material, with high voltage resistance, high temperature resistance, and device power
  • the vertical structure is a more ideal device structure than the horizontal structure.
  • Ga 2 O 3 power devices with vertical structure can be prepared (IEEE Electron Device Letters 39, 869-872, 2018), but ⁇ -Ga 2 O 3 substrate size is small Moreover, the cost is high, which is not conducive to the commercialization of gallium oxide semiconductor materials and devices.
  • Patent application documents CN106415845A and CN106796891A use sapphire as a substrate for Ga 2 O 3 growth, and disclose an ⁇ -phase Ga 2 O 3 laminated structure with excellent crystallinity and corresponding semiconductor vertical structure devices; however, on the one hand, sapphire is not An ideal substrate for electronic devices is not as good as a silicon substrate in terms of price, size, and thermal conductivity. On the other hand, the production of ⁇ -Ga 2 O 3 vertical devices on a sapphire substrate requires peeling off the sapphire substrate. The stripping of the sapphire substrate is a difficult and costly process step.
  • the ⁇ 111> crystal orientation of silicon (Si) material has hexagonal symmetry and can be used as a heteroepitaxial substrate for ⁇ -phase or ⁇ -phase Ga 2 O 3 .
  • Si substrate to grow Ga 2 O 3 the preparation of Ga 2 O 3 semiconductor devices can be compatible with the existing Si-based semiconductor process, and the cost of preparing Ga 2 O 3 semiconductor materials can be effectively reduced; and, since n-type Si is conductive Excellent performance, it can be used as a bottom electrode without substrate stripping, which is beneficial to the preparation of vertical structure devices.
  • the invention aims at the existing gallium oxide semiconductor material and vertical device structure on the silicon substrate, overcomes the deficiencies in the growth technology, and provides a gallium oxide semiconductor stacked structure and a preparation method thereof.
  • the stacked structure contains pure phase ⁇ -Ga 2 O 3 or pure phase ⁇ -Ga 2 O 3 semiconductor crystalline film, the substrate used is a Si(111) substrate, and a high-quality ⁇ -Ga 2 O 3 semiconductor crystalline film is grown by introducing a metal insertion layer.
  • a stacked structure of gallium oxide semiconductor comprising a silicon substrate and a gallium oxide semiconductor layer grown on the silicon substrate; a metal insertion layer is arranged between the silicon substrate and the gallium oxide semiconductor layer; the silicon The substrate surface and the silicon (111) crystal plane have an off angle of 0°-10°; the crystal structure of the metal insertion layer is hexagonal phase or cubic phase; and the gallium oxide semiconductor layer is epsilon phase or alpha phase gallium oxide.
  • the metal insertion layer is one or more of cubic phase tungsten, molybdenum, iridium, rhodium, vanadium, chromium, platinum, palladium, iron, nickel, copper, gold, silver, aluminum, or hexagonal
  • rhenium, ruthenium, hafnium, zirconium, titanium, and cobalt is one or more of cubic phase tungsten, molybdenum, iridium, rhodium, vanadium, chromium, platinum, palladium, iron, nickel, copper, gold, silver, aluminum, or hexagonal
  • rhenium, ruthenium, hafnium, zirconium, titanium, and cobalt are examples of aluminum tungsten, molybdenum, iridium, rhodium, vanadium, chromium, platinum, palladium, iron, nickel, copper, gold, silver, aluminum, or hexagonal
  • the ⁇ 001> crystal orientation of the hexagonal phase metal and the silicon ⁇ 111> crystal orientation have an off angle of 0°-10°.
  • the ⁇ 111> crystal orientation of the cubic phase metal and the silicon ⁇ 111> crystal orientation have an off angle of 0°-10°.
  • the thickness of the metal insertion layer is 2 to 2000 nm.
  • the thickness of the gallium oxide semiconductor layer does not exceed 100 ⁇ m.
  • a method for preparing a gallium oxide semiconductor laminated structure as described above includes the following steps:
  • S3 Depositing a gallium oxide semiconductor layer, the deposited gallium oxide is ⁇ -phase or ⁇ -phase gallium oxide with hexagonal symmetry.
  • the gallium oxide semiconductor layer further contains a dopant, and the dopant is one or more of the seven elements of tin, silicon, germanium, magnesium, zinc, iron, and nitrogen.
  • the semiconductor device is a Schottky barrier diode, a field effect transistor, a PN junction diode, a PNP and NPN transistor, or an insulated gate double-click transistor.
  • Si has a diamond structure, and its (111) crystal plane has hexagonal symmetry, which can be used for the growth of ⁇ -phase or ⁇ -phase gallium oxide that also has hexagonal symmetry; more specifically, the surface of the Si substrate can also interact with (111) crystals.
  • the plane has an off angle of 0°-10°, and the present invention preferably has an off angle of 0.1°-2°; the thickness of the substrate can be 100-2000 ⁇ m, and the present invention is preferably 300-1500 ⁇ m.
  • the metal insertion layer may contain one of tungsten, rhenium, molybdenum, iridium, ruthenium, hafnium, rhodium, vanadium, chromium, zirconium, platinum, titanium, palladium, iron, cobalt, nickel, copper, gold, silver, and aluminum Or multiple.
  • the metal insertion layer may be a single-layer structure or a multi-layer structure formed of different metals, and the total thickness is 10-1000 nm, preferably 10-500 nm.
  • the preparation methods that can be used for the metal insertion layer include DC magnetron sputtering, AC magnetron sputtering, thermal evaporation, and electron beam evaporation. After the metal insertion layer is deposited on the silicon substrate, thermal annealing can also be performed to further improve the crystalline quality of the metal layer.
  • the gallium oxide semiconductor layer is deposited on the metal insertion layer, and the gallium oxide is pure ⁇ -phase Ga 2 O 3 or pure ⁇ -phase Ga 2 O 3 semiconductor; more specifically, the crystal orientations of the gallium oxide are ⁇ -Ga 2 O 3 ⁇ 001> or ⁇ -Ga 2 O 3 ⁇ 001> crystals that also have hexagonal symmetry. And allow an off angle of 0°-10° with the Si ⁇ 111> crystal orientation, preferably an off angle of 0°-1°.
  • the thickness of the gallium oxide semiconductor layer does not exceed 100 ⁇ m, and preferably does not exceed 10 ⁇ m.
  • the gallium oxide semiconductor layer may contain a dopant, and the dopant is a mixture of one or more of the seven elements of tin, silicon, germanium, magnesium, zinc, iron, and nitrogen.
  • the dopant is a mixture of one or more of the seven elements of tin, silicon, germanium, magnesium, zinc, iron, and nitrogen.
  • some additional and unintentional impurity elements are introduced. This process is called unintentional doping.
  • the so-called dopant in the present invention does not refer to the introduction of these unintentional doping. ⁇ impurities.
  • the so-called doping in the present invention refers to the process of artificially introducing impurities during the growth process; the concentration of these impurity elements in the crystal film is in the range of 1 ⁇ 10 15 to 1 ⁇ 10 20 cm -3 .
  • These dopants include one or more of the seven elements of tin, silicon, germanium, magnesium, zinc, iron, and nitrogen.
  • tin, silicon, and germanium are n-type dopants that can make Ga 2 O 3
  • the semiconductor layer has electronic conductivity; magnesium, zinc, and nitrogen are p-type dopants, which can make the ⁇ -Ga 2 O 3 semiconductor crystal film have hole conductivity; magnesium and iron can also be used as compensatory dopants to make The Ga 2 O 3 semiconductor crystal film forms a high resistance state.
  • the gallium oxide semiconductor layer can be a single-layer structure or a multi-layer structure; it can be a single layer containing any one or more dopants, or a single layer that does not contain deliberate doping, or It is a multilayer structure formed by superimposing these two single layers in any order.
  • a semiconductor device comprising a structure in which the above-mentioned silicon substrate, a metal insertion layer, and a gallium oxide semiconductor layer are superimposed from the bottom up.
  • the semiconductor device has a vertical device structure, that is, when the device is in normal operation, the underlying silicon substrate serves as one of the paths for current flow.
  • the present invention has the following beneficial effects: by introducing a metal insertion layer, the present invention prevents the Si surface from being oxidized to form silicon oxide during the deposition of gallium oxide on the one hand, and on the other hand, the metal layer can realize gallium oxide.
  • the excellent electrical contact with the silicon substrate results in a high-quality ⁇ -Ga 2 O 3 or ⁇ -Ga 2 O 3 semiconductor crystal film deposited on the Si(111) substrate.
  • the invention solves the problem that the high-quality Ga 2 O 3 crystalline film is difficult to prepare on the Si substrate, and the structure can also be used to prepare semiconductor devices with a vertical structure.
  • FIG. 1 is a schematic diagram of the intrinsic ⁇ -Ga 2 O 3 semiconductor laminated structure of the silicon substrate of Embodiment 1;
  • Example 2 is an X-ray diffraction pattern of the intrinsic ⁇ -Ga 2 O 3 semiconductor stack on the silicon substrate of Example 1;
  • Fig. 3 is a schematic diagram of the laminated structure of the intrinsic ⁇ -Ga 2 O 3 semiconductor two-step growth method on the silicon substrate of the present invention
  • FIG. 4 is a schematic diagram of the N-type ⁇ -Ga 2 O 3 semiconductor laminated structure on a silicon substrate of the present invention
  • FIG. 5 is a schematic diagram of the ⁇ -Ga 2 O 3 semiconductor Schottky barrier diode of the present invention.
  • FIG. 6 is a schematic diagram of the horizontal gate structure ⁇ -Ga 2 O 3 semiconductor field effect transistor of the present invention.
  • FIG. 7 is a schematic diagram of the recessed gate structure ⁇ -Ga 2 O 3 semiconductor field effect transistor of the present invention.
  • Fig. 8 is a schematic diagram of the ⁇ -Ga 2 O 3 semiconductor NPN bipolar transistor of the present invention.
  • MOCVD metal organic chemical vapor deposition
  • Step 1 Si(111) substrate 1 is cleaned to remove the surface oxide layer.
  • Step 2 Using an electron beam evaporation method, deposit a 100 nm gold insertion layer 102 on the cleaned Si(111) substrate 1.
  • Step 3 Feed the substrate into the reaction chamber of the MOCVD equipment, and let the tray rotate at a speed of 750 rpm to prepare for epitaxial growth of the gallium oxide film.
  • Step 4 The reaction chamber is heated to 550°C, and the pressure is controlled at 80 Torr.
  • Step 5 Immerse the bubbling bottle containing triethylgallium and deionized water in two constant temperature water tanks, and control the temperature of the bubbling bottle to 25°C and 25°C through the constant temperature water tank, and pass the mass flowmeter and pressure gauge. Control the pressure of the two bubbling bottles to 320 Torr and 280 Torr.
  • Step 6 After the temperature of the reaction chamber stabilizes at 550°C, simultaneously pour argon carrier gas into the bubbling bottle of triethylgallium and deionized water, and let these argon carrier gas flow into the reaction chamber at a flow rate of 30 sccm. And 800sccm; controlling the growth time, a 300nm intrinsic ⁇ -Ga 2 O 3 semiconductor crystal film 103 is grown on the surface of the substrate.
  • Step 7 Stop growing, take samples after cooling down to room temperature, and complete the preparation of high-quality gallium oxide epitaxial film.
  • FIG. 1 a schematic diagram of the intrinsic ⁇ -Ga 2 O 3 semiconductor laminated structure of the silicon substrate in Embodiment 1.
  • the thickness of the metal insertion layer is 100 nm
  • the thickness of the gallium oxide semiconductor layer is 200 nm
  • Torr is the pressure unit
  • sccm is the volume flow unit.
  • an X-ray diffraction pattern of a comparative sample (below) is also given; the difference between this sample and Example 1 is that it does not contain a gold intercalation layer.
  • the comparative sample has low diffraction intensity at the ⁇ -Ga 2 O 3 diffraction peak position, indicating that the crystalline quality of the ⁇ -Ga 2 O 3 layer is extremely poor because it does not contain a gold insertion layer.
  • MOCVD metal organic chemical vapor deposition
  • Steps 1 to 6 are the same as in Example 1.
  • Step 7 Stop the carrier gas containing triethylgallium from flowing into the reaction chamber, keep the carrier gas of deionized water flowing into the reaction chamber, reduce the growth pressure to 10 Torr, and increase the growth temperature to 640° C. and keep it stable.
  • Step 8 Re-flow the argon carrier gas containing triethylgallium into the reaction chamber at a flow rate of 20sccm and 1500sccm; control the growth time, and grow a 1000nm intrinsic ⁇ -Ga 2 O 3 high temperature layer 203A on the surface of the substrate .
  • Step 9 Stop growing, take samples after cooling down to room temperature, and complete the preparation of high-quality gallium oxide epitaxial film.
  • FIG. 3 a schematic diagram of a stacked structure of an intrinsic ⁇ -Ga 2 O 3 semiconductor on a silicon substrate by a two-step growth method.
  • the total thickness of the metal insertion layer is 100 nm
  • the thickness of the gallium oxide semiconductor layer is 1100 nm.
  • MOCVD metal organic chemical vapor deposition
  • Step 1 Si(111) substrate 1 is cleaned to remove the surface oxide layer.
  • Step 2 Using a thermal evaporation method, deposit a 100nm aluminum metal insertion layer 302 on the cleaned Si(111) substrate 1.
  • Step 3 Use rapid annealing to anneal metal aluminum for 20 minutes in a nitrogen environment at 600°C.
  • Step 4 Lower the temperature to room temperature in a nitrogen environment and take out the sample.
  • Step 5 The substrate is fed into the reaction chamber of the CVD equipment, and the reaction chamber is heated to 500° C. to prepare for epitaxial growth of the gallium oxide film.
  • Step 6 Immerse the bubbling bottle containing triethylgallium, tetradimethylaminotin, and deionized water in three constant temperature water tanks, and control the temperature of the three bubbling bottles to 25°C through the constant temperature water tank and pass the mass flow Gauge and pressure gauge to control the pressure of the three bubbling bottles to 320 Torr, 280 Torr, and 280 Torr.
  • Step 7 After the temperature of the reaction chamber stabilizes at 500°C, simultaneously pour argon carrier gas into the bubbling bottle of triethylgallium and deionized water, and let these argon carrier gas flow into the reaction chamber at a flow rate of 30 sccm. And 800sccm; control the growth time, grow a 1000nm intrinsic ⁇ -Ga 2 O 3 semiconductor crystal film 303A on the surface of the substrate.
  • Step 8 Keep other conditions unchanged, pass argon carrier gas into the bubbling bottle of tetradimethylaminotin, and let these argon carrier gas flow into the reaction chamber at a flow rate of 20sccm; control the growth time, on the substrate surface A 1000 nm N-type ⁇ -Ga 2 O 3 semiconductor crystal film 303B doped with tin was grown.
  • Step 9 Stop growing, take samples after cooling down to room temperature, and complete the preparation of high-quality gallium oxide epitaxial film.
  • FIG. 4 is a schematic diagram of an N-type ⁇ -Ga 2 O 3 semiconductor laminated structure on a silicon substrate.
  • the thickness of the metal insertion layer is 100 nm
  • the thickness of the gallium oxide semiconductor layer is 2000 nm.
  • MOCVD metal organic chemical vapor deposition
  • Step 1 Cleaning the Si(111) substrate to remove the surface oxide layer.
  • Step 2 Using an electron beam evaporation method, deposit a 300nm molybdenum metal insertion layer 402 on the cleaned Si(111) substrate 1.
  • Step 3 Re-feed the substrate into the reaction chamber of the MOCVD equipment, and let the tray rotate at a speed of 750 rpm to prepare for epitaxial growth of the gallium oxide film.
  • Step 4 The reaction chamber is heated to 600°C and the pressure is controlled at 30 Torr.
  • Step 5 Immerse the bubbling bottle containing triethylgallium and deionized water in a constant temperature water tank, and control the temperature of the two bubbling bottles to 25°C through the constant temperature water tank, and control the two through a mass flow meter and a pressure gauge.
  • the pressure of the bubbling bottle is 320 Torr and 280 Torr.
  • Step 6 After the temperature of the reaction chamber stabilizes at 600°C, simultaneously pour argon carrier gas into the bubbling bottle of triethylgallium and deionized water, and let these argon carrier gas flow into the reaction chamber at a flow rate of 30 sccm. At the same time, 2sccm of germane was passed into the reaction chamber; the growth time was controlled, and a 1000nm germanium-doped N-type ⁇ -Ga 2 O 3 semiconductor crystal film 403 was grown on the surface of the substrate.
  • Step 7 Stop growing, take samples after cooling down to room temperature, and complete the preparation of high-quality gallium oxide epitaxial film.
  • Step 8 Prepare an ohmic contact electrode 404B on the back of the silicon substrate.
  • Step 9 Prepare a Schottky contact electrode 404A as shown in FIG. 4 on the upper surface of the N-type ⁇ -Ga 2 O 3 semiconductor layer to form a Schottky barrier diode with a vertical structure.
  • Fig. 5 a schematic diagram of an ⁇ -Ga 2 O 3 semiconductor Schottky barrier diode.
  • the total thickness of the metal insertion layer is 300 nm
  • the thickness of the gallium oxide semiconductor layer is 1000 nm.
  • MOCVD metal organic chemical vapor deposition
  • Step 1 Si(111) substrate 1 is cleaned to remove the surface oxide layer.
  • Step 2 Using an electron beam evaporation method, deposit a 200nm titanium insertion layer 502 on the cleaned Si(111) substrate 1.
  • Step 3 Re-feed the substrate into the reaction chamber of the MOCVD equipment, and let the tray rotate at a speed of 750 rpm to prepare for epitaxial growth of the gallium oxide film.
  • Step 4 The reaction chamber is heated to 600°C, and the pressure is controlled at 30 Torr.
  • Step 5 Immerse the bubbling bottle containing triethylgallium and deionized water in two constant temperature water tanks, control the temperature of the two bubbling bottles to 25°C through the constant temperature water tank, and pass the mass flowmeter and pressure gauge, Control the pressure of the two bubbling bottles to 320 Torr and 280 Torr.
  • Step 6 After the temperature of the reaction chamber stabilizes at 600°C, simultaneously pour argon carrier gas into the bubbling bottle of triethylgallium and deionized water, and let these argon carrier gas flow into the reaction chamber at a flow rate of 30 sccm. At the same time, 2sccm of silane was passed into the reaction chamber; the growth time was controlled, and a 3000nm silicon-doped N-type ⁇ -Ga 2 O 3 semiconductor crystal film 503A was grown on the surface of the substrate.
  • Step 7 Stop growing, take samples after cooling down to room temperature, and complete the preparation of high-quality gallium oxide epitaxial film.
  • Step 8 As shown in Figure 6, ion implantation is used to form a magnesium-implanted P-type ⁇ -Ga 2 O 3 layer 503B in a specific area in the N-type ⁇ -Ga 2 O 3 and silicon implants heavily doped N-type ⁇ -Ga 2 O 3 layer 503C; and then prepare 100 nm aluminum oxide gate dielectric 504D, gate electrode 504C, 400 nm silicon dioxide gate protection layer 504E, and source electrode 504B on the ⁇ -Ga 2 O 3 layer.
  • Step 9 Fabricate a drain electrode 504A on the back of the silicon substrate to complete the preparation of the vertical structure ⁇ -Ga 2 O 3 field effect transistor.
  • FIG. 6 a schematic diagram of a horizontal gate structure ⁇ -Ga 2 O 3 semiconductor field effect transistor.
  • the thickness of the metal insertion layer is 200 nm
  • the thickness of the gallium oxide semiconductor layer is 3000 nm.
  • MOCVD metal organic chemical vapor deposition
  • Steps 1 to 4 are the same as in Example 5.
  • Step 5 Immerse the bubbling bottle containing magnesium ocene, triethylgallium, and deionized water in a constant temperature water tank, control the temperature of the three bubbling bottles to 25°C through the constant temperature water tank, and pass the mass flowmeter and pressure Control the pressure of the three bubbling bottles as 320 Torr, 320 Torr and 280 Torr.
  • Step 6 After the temperature of the reaction chamber stabilizes at 600°C, simultaneously pour argon carrier gas into the bubbling bottle of triethylgallium and deionized water, and let these argon carrier gas flow into the reaction chamber at a flow rate of 30 sccm. At the same time, 2sccm of silane was introduced into the reaction chamber; the growth time was controlled, and a 2000nm germanium-doped N-type ⁇ -Ga 2 O 3 semiconductor crystal film 603A was grown on the surface of the substrate.
  • Step 7 Stop passing silane; at the same time, pass argon carrier gas into the magnesiumocene bubbling bottle, and let these argon carrier gas flow into the reaction chamber, the flow rate is 20sccm; control the growth time, A 4000nm magnesium-doped P-type ⁇ -Ga 2 O 3 semiconductor crystal film 603B is grown on the bottom surface.
  • Step 8 Stop the growth, take samples after cooling down to room temperature to complete the preparation of high-quality gallium oxide epitaxial films.
  • Step 9 7, ion implantation method to form a heavily doped N-type germanium implantation ⁇ -Ga 2 O 3 layer in a specific area of 603C 2 O 3 P-type ⁇ -Ga; then ⁇ -Ga 2 O A recessed gate structure is formed on the three layers by wet etching; then a 100nm aluminum oxide gate dielectric 604E, a gate electrode 604C, a 400nm silicon dioxide gate protection layer 604D, and a source electrode 604B are respectively prepared.
  • Step 10 Fabricate a drain electrode 604A on the back of the silicon substrate to complete the preparation of the vertical structure ⁇ -Ga 2 O 3 field effect transistor.
  • FIG. 7 a schematic diagram of a recessed gate structure ⁇ -Ga 2 O 3 semiconductor field effect transistor.
  • the thickness of the metal insertion layer is 200 nm
  • the thickness of the gallium oxide semiconductor layer is 6000 nm.
  • MOCVD metal organic chemical vapor deposition
  • Step 1 Si(111) substrate 1 is cleaned to remove the surface oxide layer.
  • Step 2 Using a thermal evaporation method, deposit 500nm of metallic vanadium on the cleaned Si(111) substrate 1.
  • Step 3 Lower the temperature to room temperature in a nitrogen environment and take out the sample.
  • Step 4 The substrate is sent into the reaction chamber of the CVD equipment, and the reaction chamber is heated to 500° C. to prepare for epitaxial growth of the gallium oxide film.
  • Step 5 After the temperature of the reaction chamber stabilizes at 500°C, sequentially grow a 1000nm tin-doped N-type ⁇ -Ga 2 O 3 semiconductor layer 703A, a 400nm iron-doped P-type ⁇ -Ga 2 O 3 semiconductor layer 703B, The 200nm tin doped N-type ⁇ -Ga 2 O 3 semiconductor layer 703C.
  • Step 6 Take samples after cooling down to room temperature to complete the preparation of the epitaxial structure of the high-quality ⁇ -Ga 2 O 3 device.
  • Step 7 As shown in Figure 8, a collector 704A is formed on the metal insertion layer, a base 704B is formed on the P-type ⁇ -Ga 2 O 3 layer, and the emitter is formed on the N-type ⁇ -Ga 2 O 3 layer on the top layer. ⁇ 704C.
  • FIG. 8 a schematic diagram of an ⁇ -Ga 2 O 3 semiconductor NPN bipolar transistor.
  • the thickness of the metal insertion layer is 500 nm
  • the thickness of the gallium oxide semiconductor layer is 1600 nm.

Abstract

本发明提供了一种氧化镓半导体的叠层结构及其制备方法，包括硅衬底和生长在所述硅衬底上的氧化镓半导体层，所述硅衬底和氧化镓半导体层之间设置有金属插入层；所述硅衬底表面与硅(111)晶面存在0°～10°的偏离角；所述金属插入层是立方相的钨、钼、铱、铑、钒、铬、铂、钯、铁、镍、铜、金、银、铝中的一种或多种，或者是六方相的铼、钌、铪、锆、钛、钴中的一种或多种；所述氧化镓半导体层为具有六方对称性的ε相或α相氧化镓，厚度不超过50μm。本发明通过引入金属插入层，解决了高质量Ga 2O 3结晶膜难于在Si衬底上制备的问题，该结构同时还可以用于制备具有垂直结构的半导体器件。

Description

一种氧化镓半导体叠层结构及其制备方法 技术领域
本发明属于半导体材料与器件制备领域，主要涉及在能在硅衬底上实现高质量氧化镓半导体的生长方法及基于此制备的半导体器件。
背景技术
氧化镓(Ga 2O 3)具有β、ε、α、γ、δ五种相，其中β相是稳定相，ε相次之，α相又次之，而γ、δ相稳定性差。由于不同相Ga 2O 3均具有4.7～5.4eV的超宽禁带宽度和高临界击穿电场，因此，Ga 2O 3半导体是理想的电子器件材料，具有耐高电压、耐高温、器件功率大、热损耗低、寄生效应小的优点；特别是在ε-Ga 2O 3中，由于极化效应和二维电子气的存在，ε-Ga 2O 3还能用于制作高频电子器件(Applied Physics Letters,112,162101,2018)。
在制备Ga 2O 3半导体功率电子器件的过程中，为使器件能够工作在大功率大电流的应用场合，垂直结构相比起水平结构是更理想的器件结构。采用β相Ga 2O 3晶体作为同质衬底，可以制备具有垂直结构的Ga 2O 3功率器件(IEEE Electron Device Letters 39,869-872,2018)，但是，β-Ga 2O 3衬底尺寸小且成本高昂，不利于氧化镓半导体材料与器件的商用化进程。专利申请文件CN106415845A和CN106796891A通过采用蓝宝石作为Ga 2O 3生长的衬底，公开了一种结晶性优异的α相Ga 2O 3层叠结构和相应的半导体垂直结构器件；但是，一方面，蓝宝石不是电子器件的理想衬底，其在价格、尺寸、导热性上均不如硅材料衬底，另一方面，在蓝宝石衬底上制作α-Ga 2O 3垂直器件，需要对蓝宝石衬底进行剥离，而蓝宝石衬底的剥离是一道难度大、成本高的工艺步骤。硅(Si)材料的<111>晶向具有六方对称性，可以作为ε相或α相Ga 2O 3的异质外延衬底。采用Si衬底生长Ga 2O 3，可以将Ga 2O 3半导体器件的制备兼容到现有的Si基半导体工艺中，有效降低Ga 2O 3半导体材料的制备成本；并且，由于n型Si导电性能优良，其可以作为底电极而无需进行衬底剥离，有利于垂直结构器件的制备。
但采用Si作为衬底生长Ga 2O 3薄膜并制备相应的垂直结构器件，面临两方面的难题：一是生长的初期很容易在单晶Si表面形成一层非晶态的氧化硅，这一层非晶态的氧化硅晶 向一致性差，因而会严重降低后续生长的Ga 2O 3薄膜质量；其次，由于Ga 2O 3导电性差，其很难和n型Si形成良好的欧姆接触，会导致所制备的垂直结构器件具有过高的接触电阻，严重降低器件的工作效率。因此，目前迫切需要一种硅衬底上生长氧化镓的新技术新工艺，以解决以上两方面问题。
发明内容
本发明针对现有硅衬底氧化镓半导体材料和垂直器件结构，克服生长技术上存在的不足，提供一种氧化镓半导体叠层结构及其制备方法，该叠层结构含有纯相的ε-Ga 2O 3或纯相的α-Ga 2O 3半导体结晶膜，所采用的衬底为Si(111)衬底，通过引入金属插入层，生长高质量α-Ga 2O 3半导体结晶膜。
为实现上述发明目的，本发明提供的技术方案如下：
一种氧化镓半导体的叠层结构，包括硅衬底和生长在所述硅衬底上的氧化镓半导体层；所述硅衬底和氧化镓半导体层之间设置有金属插入层；所述硅衬底表面与硅(111)晶面存在0°～10°的偏离角；所述金属插入层的晶体结构为六方相或者立方相；所述氧化镓半导体层为ε相或α相氧化镓。
优选地，所述金属插入层是立方相的钨、钼、铱、铑、钒、铬、铂、钯、铁、镍、铜、金、银、铝中的一种或多种，或者是六方相的铼、钌、铪、锆、钛、钴中的一种或多种；
优选地，所述六方相金属的<001>晶向与硅<111>晶向存在0°～10°的偏离角。
优选地，所述立方相金属的<111>晶向与硅<111>晶向存在0°～10°的偏离角。
优选地，所述金属插入层厚度为2～2000nm。
优选地，所述氧化镓半导体层的厚度不超过100μm。
一种如上述所述的一种氧化镓半导体叠层结构的制备方法，该方法包括如下步骤：
S1：硅衬底清洗，去除表面氧化层；
S2：沉积金属插入层；
S3：沉积氧化镓半导体层，所沉积的氧化镓为具有六方对称性的ε相或α相氧化镓。
优选地，所述氧化镓半导体层还含有掺杂剂，所述掺杂剂是锡、硅、锗、镁、锌、铁、氮七种元素中的一种或多种。
一种具有上述所述的一种氧化镓半导体叠层结构的半导体器件，所述半导体器件为垂直结构器件。
优选地，所述半导体器件为肖特基势垒二极管、场效应晶体管、PN结二极管、PNP和NPN三极管或绝缘栅双击晶体管。
Si具有金刚石结构，而其(111)晶面具有六方对称性，可用于同样具有六方对称性的ε相或α相氧化镓的生长；更具体的，Si衬底表面还可以和(111)晶面存在0°～10°的偏离角，本发明优选0.1°～2°的偏离角；衬底的厚度可为100～2000μm，本发明优选300～1500μm。
在Si(111)衬底上沉积金属插入层，一方面防止Si表面在沉积氧化镓的过程中被氧化形成氧化硅，另一方面金属层可以实现氧化镓和硅衬底之间的优良电学接触。所述金属插入层可以含有钨、铼、钼、铱、钌、铪、铑、钒、铬、锆、铂、钛、钯、铁、钴、镍、铜、金、银、铝中的一种或多种。所述金属插入层可以是单层结构，也可以是不同金属形成的多层结构，并且总厚度为10～1000nm，优选10～500nm。所述金属插入层可以采用的制备方法包括直流磁控溅射、交流磁控溅射、热蒸发、电子束蒸发。所述金属插入层在硅衬底上沉积之后，还可以进行热退火，进一步提高金属层的结晶质量。
所述金属插入层在沉积后，仍能保持来自Si(111)衬底的六方对称性；因此，在所述金属插入层上进行氧化镓半导体层的沉积，氧化镓为纯ε相Ga 2O 3或纯α相Ga 2O 3半导体；更具体的，所述氧化镓的晶向分别为同样具有六方对称性的ε-Ga 2O 3<001>或α-Ga 2O 3<001>晶向；且允许与Si<111>晶向存在0°～10°的偏离角，优选0°～1°的偏离角。所述氧化镓半导体层厚度不超过100μm，优选不超过10μm。
所述氧化镓半导体层可以含有掺杂剂，所述掺杂剂是锡、硅、锗、镁、锌、铁、氮七种元素中的一种或多种的混合。沉积氧化镓半导体层的过程中，会额外的、非故意的引入一些杂质元素，这一过程被称为非故意掺杂，而本发明所谓的掺杂剂，并不指这些非故意掺杂引入的杂质。本发明所谓掺杂，是指生长过程中人为有意引入杂质的过程；这些杂质元素在结晶膜中浓度为1×10 15～1×10 20cm -3范围。这些掺杂剂包括锡、硅、锗、镁、锌、铁、氮七种元素中的一种或多种的混合：其中，锡、硅、锗是n型掺杂剂，可以使Ga 2O 3半导体层具有电子导电能力；镁、锌、氮是p型掺杂剂，可以使ε-Ga 2O 3半导体结晶膜具有空穴导电能力；镁和铁还可以作为补偿性掺杂剂，使Ga 2O 3半导体结晶膜形成高阻态。
所述氧化镓半导体层可以是单层结构，也可以是多层结构；其可以是含有任意一种或多种掺杂剂的单层，也可以是不含有故意掺杂的单层，还可以是这两种单层按照任意顺序叠加而成的多层结构。
一种半导体器件，所述器件包含有上述硅衬底、金属插入层、氧化镓半导体层自下而 上叠加而成的结构。所述半导体器件为垂直器件结构，亦即器件在正常工作时，底层的硅衬底作为电流流通的路径之一。
本发明的有益效果：
与现有技术相比，本发明取得的有益效果为：本发明通过引入金属插入层，一方面防止Si表面在沉积氧化镓的过程中被氧化形成氧化硅，另一方面金属层可以实现氧化镓和硅衬底之间的优良电学接触，得到了在Si(111)衬底上沉积的高质量ε-Ga 2O 3或α-Ga 2O 3半导体结晶膜。本发明解决了高质量Ga 2O 3结晶膜难于在Si衬底上制备的问题，该结构同时还可以用于制备具有垂直结构的半导体器件。
附图说明
图1是实施例1的硅衬底本征ε-Ga 2O 3半导体叠层结构示意图；
图2是实施例1硅衬底本征ε-Ga 2O 3半导体叠层的X射线衍射图谱；
图3是本发明的硅衬底本征ε-Ga 2O 3半导体两步生长法叠层结构示意图；
图4是本发明的硅衬底N型α-Ga 2O 3半导体叠层结构示意图；
图5是本发明的ε-Ga 2O 3半导体肖特基势垒二极管示意图；
图6是本发明的水平栅结构ε-Ga 2O 3半导体场效应晶体管示意图；
图7是本发明的凹栅结构ε-Ga 2O 3半导体场效应晶体管示意图；
图8是本发明的α-Ga 2O 3半导体NPN双极晶体管示意图。
附图中的标记所对应的技术特征为：
1Si (111)衬底
102 金插入层
103 本征ε-Ga 2O 3半导体结晶膜
203A 本征ε-Ga 2O 3高温层
302 铝金属插入层
303A 本征α-Ga 2O 3半导体结晶膜
303B 锡掺杂的N型α-Ga 2O 3半导体结晶膜
402 钼金属插入层
403 锗掺杂的N型ε-Ga 2O 3半导体结晶膜
404A 肖特基接触电极
404B 欧姆接触电极
502 钛金属插入层
503A 硅掺杂的N型ε-Ga 2O 3半导体结晶膜
503B 镁注入P型ε-Ga 2O 3层
503C 硅注入重掺N型ε-Ga 2O 3层
504A 漏电极
504B 源电极
504C 栅电极
504D 氧化铝栅介质
504E 二氧化硅栅保护层
603A 锗掺杂的N型ε-Ga 2O 3半导体结晶膜
603B 镁掺杂的P型ε-Ga 2O 3半导体结晶膜
603C 锗注入重掺N型ε-Ga 2O 3层
604A 漏电极
604B 源电极
604C 栅电极
604D 二氧化硅栅保护层
604E 氧化铝栅介质
702 金属钒插入层
703A 锡掺杂N型α-Ga 2O 3半导体层
703B 铁掺杂P型α-Ga 2O 3半导体层
703C 锡掺杂N型α-Ga 2O 3半导体层
704A 集电极
704B 基极
704C 发射极
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合说明书附图和具体实 施例，对本发明进一步详细说明，但本发明要求的保护范围并不局限于实施例。
实施例1
金属有机化学气相沉积(MOCVD)方法制备含有高质量ε-Ga 2O 3半导体结晶膜的叠层结构。
步骤1：Si(111)衬底1清洗，去除表面氧化层。
步骤2：利用电子束蒸发方法，在清洗后的Si(111)衬底1上沉积100nm的金插入层102。
步骤3：将衬底送入MOCVD设备的反应室，并让托盘旋转，转速为750转/分，准备进行氧化镓膜的外延生长。
步骤4：反应室升温至550℃，气压控制在80Torr。
步骤5：将装有三乙基镓、去离子水的鼓泡瓶沉浸在两个恒温水槽中，通过恒温水槽将鼓泡瓶温度控制为25℃、25℃，并通过质量流量计和压力计，控制两个鼓泡瓶的压力为320Torr、280Torr。
步骤6：待反应室温度稳定在550℃后，同时向三乙基镓和去离子水的鼓泡瓶通入氩气载气，并让这些氩气载气流入反应室中，流量分别为30sccm和800sccm；控制生长时间，在衬底表面生长出300nm的本征ε-Ga 2O 3半导体结晶膜103。
步骤7：停止生长，降温至室温后取样，完成高质量氧化镓外延膜的制备。
参见图1，实施例1硅衬底本征ε-Ga 2O 3半导体叠层结构示意图。本例中金属插入层的厚度为100nm，氧化镓半导体层的厚度为200nm，Torr为压强单位，sccm为体积流量单位。
参见图2，实施例1硅衬底本征ε-Ga 2O 3半导体叠层结构的X射线衍射图谱(在上)；该样品在ε-Ga 2O 3衍射峰位处具有较强的衍射强度，说明通过引入金插入层，实现了高质量的硅衬底ε-Ga 2O 3结晶膜。作为对比，同时还给出了一个对比样品的X射线衍射图谱(在下)；该样品与实施例1的差别在于不含金插入层。对比样品在ε-Ga 2O 3衍射峰位处的衍射强度低，说明由于不含有金插入层，其ε-Ga 2O 3层的结晶质量极差。
实施例2
金属有机化学气相沉积(MOCVD)方法制备含有高质量ε-Ga 2O 3半导体结晶膜的叠层结构。
步骤1～6与实施例1相同。
步骤7：停止含有三乙基镓的载气通入反应室，保持去离子水的载气通入反应室，将生长气压降低至10Torr，生长温度升高至640℃，并保持稳定。
步骤8：再次将含有三乙基镓的氩气载气流入反应室中，流量分别为20sccm和1500sccm；控制生长时间，在衬底表面生长出1000nm的本征ε-Ga 2O 3高温层203A。
步骤9：停止生长，降温至室温后取样，完成高质量氧化镓外延膜的制备。
参见图3，硅衬底本征ε-Ga 2O 3半导体两步生长法叠层结构示意图。本例中金属插入层的总厚度为100nm，氧化镓半导体层的厚度为1100nm。
实施例3
金属有机化学气相沉积(MOCVD)方法制备含有高质量α-Ga 2O 3半导体结晶膜的叠层结构。
步骤1：Si(111)衬底1清洗，去除表面氧化层。
步骤2：利用热蒸发方法，在清洗后的Si(111)衬底1上沉积100nm的铝金属插入层302。
步骤3：采用快速退火，在600℃氮气环境下对金属铝退火20分钟。
步骤4：在氮气环境下降温至室温，取出样品。
步骤5：将衬底送入CVD设备的反应室，反应室升温至500℃，准备进行氧化镓膜的外延生长。
步骤6：将装有三乙基镓、四二甲氨基锡、去离子水的鼓泡瓶沉浸在三个恒温水槽中，通过恒温水槽将三个鼓泡瓶温度控制为25℃，并通过质量流量计和压力计，控制三个鼓泡瓶的压力为320Torr、280Torr、280Torr。
步骤7：待反应室温度稳定在500℃后，同时向三乙基镓和去离子水的鼓泡瓶通入氩气载气，并让这些氩气载气流入反应室中，流量分别为30sccm和800sccm；控制生长时间，在衬底表面生长出1000nm的本征α-Ga 2O 3半导体结晶膜303A。
步骤8：保持其他条件不变，向四二甲氨基锡的鼓泡瓶通入氩气载气，并让这些氩气载气流入反应室中，流量为20sccm；控制生长时间，在衬底表面生长出1000nm含有锡掺杂的N型α-Ga 2O 3半导体结晶膜303B。
步骤9：停止生长，降温至室温后取样，完成高质量氧化镓外延膜的制备。
参见图4，硅衬底N型α-Ga 2O 3半导体叠层结构示意图。本例中金属插入层的厚度为 100nm，氧化镓半导体层的厚度为2000nm。通过引入铝插入层，防止硅衬底表面氧化而形成非晶氧化硅层，从而提高后续生长α-Ga 2O 3半导体结晶膜的结晶质量。
实施例4
金属有机化学气相沉积(MOCVD)方法制备含有高质量ε-Ga 2O 3半导体结晶膜的叠层结构。
步骤1：Si(111)衬底清洗，去除表面氧化层。
步骤2：利用电子束蒸发方法，在清洗后的Si(111)衬底1上沉积300nm的钼金属插入层402。
步骤3：将衬底重新送入MOCVD设备的反应室，并让托盘旋转，转速为750转/分，准备进行氧化镓膜的外延生长。
步骤4：反应室升温至600℃，压控制在30Torr。
步骤5：将装有三乙基镓、去离子水的鼓泡瓶沉浸在恒温水槽中，通过恒温水槽将两个鼓泡瓶温度控制为25℃，并通过质量流量计和压力计，控制两个鼓泡瓶的压力为320Torr、280Torr。
步骤6：待反应室温度稳定在600℃后，同时向三乙基镓和去离子水的鼓泡瓶通入氩气载气，并让这些氩气载气流入反应室中，流量分别为30sccm和800sccm；与此同时，向反应室中通入2sccm的锗烷；控制生长时间，在衬底表面生长出1000nm的锗掺杂的N型ε-Ga 2O 3半导体结晶膜403。
步骤7：停止生长，降温至室温后取样，完成高质量氧化镓外延膜的制备。
步骤8：在硅衬底背部制备欧姆接触电极404B。
步骤9：在N型ε-Ga 2O 3半导体层的上表面制备如图4的肖特基接触电极404A，形成具有垂直结构的肖特基势垒二极管。
参见图5，ε-Ga 2O 3半导体肖特基势垒二极管示意图。本例中金属插入层的总厚度为300nm，氧化镓半导体层的厚度为1000nm。通过引入钼金属插入层，防止硅衬底表面氧化而形成非晶氧化硅层，从而提高后续生长ε-Ga 2O 3半导体结晶膜的结晶质量。
实施例5
金属有机化学气相沉积(MOCVD)方法制备含有高质量ε-Ga 2O 3半导体结晶膜的叠层 结构。
步骤1：Si(111)衬底1清洗，去除表面氧化层。
步骤2：利用电子束蒸发方法，在清洗后的Si(111)衬底1上沉积200nm的钛金属插入层502。
步骤3：将衬底重新送入MOCVD设备的反应室，并让托盘旋转，转速为750转/分，准备进行氧化镓膜的外延生长。
步骤4：反应室升温至600℃，气压控制在30Torr。
步骤5：将装有三乙基镓、去离子水的鼓泡瓶沉浸在两个个恒温水槽中，通过恒温水槽将两个鼓泡瓶温度控制为25℃，并通过质量流量计和压力计，控制两个个鼓泡瓶的压力为320Torr、280Torr。
步骤6：待反应室温度稳定在600℃后，同时向三乙基镓和去离子水的鼓泡瓶通入氩气载气，并让这些氩气载气流入反应室中，流量分别为30sccm和800sccm；与此同时，向反应室中通入2sccm的硅烷；控制生长时间，在衬底表面生长出3000nm的硅掺杂的N型ε-Ga 2O 3半导体结晶膜503A。
步骤7：停止生长，降温至室温后取样，完成高质量氧化镓外延膜的制备。
步骤8：如图6所示，采用离子注入方法，在N型ε-Ga 2O 3中的特定区域形成镁注入P型ε-Ga 2O 3层503B和硅注入重掺N型ε-Ga 2O 3层503C；然后在ε-Ga 2O 3层上分别制备100nm的氧化铝栅介质504D、栅电极504C、400nm的二氧化硅栅保护层504E、源电极504B。
步骤9：在硅衬底背部制作漏电极504A，完成垂直结构的ε-Ga 2O 3场效应晶体管制备。
参见图6，水平栅结构ε-Ga 2O 3半导体场效应晶体管示意图。本例中金属插入层的厚度为200nm，氧化镓半导体层的厚度为3000nm。通过引入钛金属插入层，防止硅衬底表面氧化而形成非晶氧化硅层，从而提高后续生长ε-Ga 2O 3半导体结晶膜的结晶质量。
实施例6
金属有机化学气相沉积(MOCVD)方法制备含有高质量ε-Ga 2O 3半导体结晶膜的叠层结构。
步骤1～4与实施例5相同。
步骤5：将装有二茂镁、三乙基镓、去离子水的鼓泡瓶沉浸在恒温水槽中，通过恒温水 槽将三个鼓泡瓶温度控制为25℃，并通过质量流量计和压力计，控制三个鼓泡瓶的压力为320Torr、320Torr、280Torr。
步骤6：待反应室温度稳定在600℃后，同时向三乙基镓和去离子水的鼓泡瓶通入氩气载气，并让这些氩气载气流入反应室中，流量分别为30sccm和800sccm；与此同时，向反应室中通入2sccm的硅烷；控制生长时间，在衬底表面生长出2000nm的锗掺杂的N型ε-Ga 2O 3半导体结晶膜603A。
步骤7：停止通入硅烷；与此同时，向二茂镁的鼓泡瓶通入氩气载气，并让这些氩气载气流入反应室中，流量分别为20sccm；控制生长时间，在衬底表面生长出4000nm的镁掺杂的P型ε-Ga 2O 3半导体结晶膜603B。
步骤8：停止生长，降温至室温后取样，完成高质量氧化镓外延膜的制备。
步骤9：如图7所示，采用离子注入方法，在P型ε-Ga 2O 3中的特定区域形成锗注入重掺N型ε-Ga 2O 3层603C；然后在ε-Ga 2O 3层上通过湿法腐蚀形成凹栅结构；而后分别制备100nm的氧化铝栅介质604E、栅电极604C、400nm的二氧化硅栅保护层604D、源电极604B。
步骤10：在硅衬底背部制作漏电极604A，完成垂直结构的ε-Ga 2O 3场效应晶体管制备。
参见图7，凹栅结构ε-Ga 2O 3半导体场效应晶体管示意图。本例中金属插入层的厚度为200nm，氧化镓半导体层的厚度为6000nm。
实施例7
金属有机化学气相沉积(MOCVD)方法制备含有高质量α-Ga 2O 3半导体结晶膜的叠层结构。
步骤1：Si(111)衬底1清洗，去除表面氧化层。
步骤2：利用热蒸发方法，在清洗后的Si(111)衬底1上沉积500nm的金属钒。
步骤3：在氮气环境下降温至室温，取出样品。
步骤4：将衬底送入CVD设备的反应室，反应室升温至500℃，准备进行氧化镓膜的外延生长。
步骤5：待反应室温度稳定在500℃后，依次分别生长1000nm的锡掺杂N型α-Ga 2O 3半导体层703A、400nm的铁掺杂P型α-Ga 2O 3半导体层703B、200nm的锡掺杂N型α-Ga 2O 3半导体层703C。
步骤6：降温至室温后取样，完成高质量α-Ga 2O 3器件外延结构的制备。
步骤7：如图8所示，在金属插入层上形成集电极704A，在P型α-Ga 2O 3层上形成基极704B、在顶层的N型α-Ga 2O 3层上形成发射极704C。
参见图8，α-Ga 2O 3半导体NPN双极晶体管示意图。本例中金属插入层的厚度为500nm，氧化镓半导体层的厚度为1600nm。通过引入钒插入层，防止硅衬底表面氧化而形成非晶氧化硅层；因此可以提高后续生长α-Ga 2O 3半导体结晶膜的结晶质量，从而制备高质量的晶体管器件。
根据上述说明书的揭示和教导，本发明所属领域的技术人员还可以对上述实施方式进行变更和修改。因此，本发明并不局限于上面揭示和描述的具体实施方式，对发明的一些修改和变更也应当落入本发明的权利要求的保护范围内。此外，尽管本说明书中使用了一些特定的术语，但这些术语只是为了方便说明，并不对本发明构成任何限制。

Claims (10)

  1. 一种氧化镓半导体的叠层结构，包括硅衬底和生长在所述硅衬底上的氧化镓半导体层，其特征在于：所述硅衬底和氧化镓半导体层之间设置有金属插入层；所述硅衬底表面与硅(111)晶面存在0°～10°的偏离角；所述金属插入层的晶体结构为六方相或立方相；所述氧化镓半导体层为ε相或α相氧化镓。
  2. 根据权利要求1所述的一种氧化镓半导体叠层结构，其特征在于：所述金属插入层是立方相的钨、钼、铱、铑、钒、铬、铂、钯、铁、镍、铜、金、银、铝中的一种或多种，或者是六方相的铼、钌、铪、锆、钛、钴中的一种或多种。
  3. 根据权利要求1所述的一种氧化镓半导体叠层结构，其特征在于：所述六方相金属的<001>晶向与硅<111>晶向存在0°～10°的偏离角。
  4. 根据权利要求1所述的一种氧化镓半导体叠层结构，其特征在于：所述立方相金属的<111>晶向与硅<111>晶向存在0°～10°的偏离角。
  5. 根据权利要求1所述的一种氧化镓半导体叠层结构，其特征在于：所述金属插入层厚度为2～2000nm。
  6. 根据权利要求1所述的一种氧化镓半导体叠层结构，其特征在于：所述氧化镓半导体层的厚度不超过100μm。
  7. 一种如权利要求1-6任意一项所述的一种氧化镓半导体叠层结构的制备方法，其特征在于：该方法包括如下步骤：
    S1：硅衬底清洗，去除表面氧化层；
    S2：沉积金属插入层；
    S3：沉积氧化镓半导体层，所沉积的氧化镓为具有六方对称性的ε相或α相氧化镓。
  8. 根据权利要求7所述一种氧化镓半导体叠层结构的制备方法，其特征在于：所述氧化镓半导体层还含有掺杂剂，所述掺杂剂是锡、硅、锗、镁、锌、铁、氮七种元素中的一种或多种。
  9. 一种具有权利要求1-6任意一项所述的一种氧化镓半导体叠层结构的半导体器件，其特征在于：所述半导体器件为垂直结构器件。
  10. 如权利要求9所述的一种氧化镓半导体叠层结构的的半导体器件，其特征在于，所述半导体器件为肖特基势垒二极管、场效应晶体管、PN结二极管、PNP和NPN三极管或绝缘栅双击晶体管。
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