WO2020211200A1 - 显示面板以及显示装置 - Google Patents

显示面板以及显示装置 Download PDF

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Publication number
WO2020211200A1
WO2020211200A1 PCT/CN2019/096488 CN2019096488W WO2020211200A1 WO 2020211200 A1 WO2020211200 A1 WO 2020211200A1 CN 2019096488 W CN2019096488 W CN 2019096488W WO 2020211200 A1 WO2020211200 A1 WO 2020211200A1
Authority
WO
WIPO (PCT)
Prior art keywords
terminal group
display area
signal terminal
bump
driving chip
Prior art date
Application number
PCT/CN2019/096488
Other languages
English (en)
French (fr)
Inventor
卢延涛
刘广辉
王超
Original Assignee
武汉华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US16/631,298 priority Critical patent/US11092860B1/en
Publication of WO2020211200A1 publication Critical patent/WO2020211200A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13456—Cell terminals located on one side of the display only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/56—Substrates having a particular shape, e.g. non-rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/05—Flexible printed circuits [FPCs]
    • H05K2201/053—Tails
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/05—Flexible printed circuits [FPCs]
    • H05K2201/056—Folded around rigid support or component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09027—Non-rectangular flat PCB, e.g. circular
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10128—Display
    • H05K2201/10136—Liquid Crystal display [LCD]

Definitions

  • This application relates to the field of display technology, and in particular to a display panel and a display device.
  • the screen-to-body ratio is constantly increasing, and the area of the non-display area of the display (the frame below) is also getting smaller and smaller.
  • the distance d keeps decreasing.
  • circuit elements such as driver chips, wiring, terminals, etc. need to be arranged in the non-display area, in order to ensure the normal function of these circuit elements, sufficient area needs to be reserved, and the distance d between the lower frame and the edge of the display area cannot be less than the predetermined value , The existing display panel setting method cannot meet the development trend of full-screen technology.
  • the existing display panels have technical problems that cannot meet the development trend of full screens, and need to be improved.
  • the present application provides a display panel and a display device to alleviate the technical problem of the existing display panel that cannot meet the development trend of a full screen.
  • An embodiment of the present application provides a display panel, which includes an array substrate, a driving chip, and a flexible circuit board.
  • the array substrate includes a display area and a non-display area, and the driving chip and the flexible circuit board are bound to the non-display area.
  • At least two bumps are formed on the side of the non-display area away from the display area, and recesses are formed between adjacent bumps;
  • a part of the flexible circuit board is bent to the back of the array substrate via the edge of the recess; the driving chip is located between the edge of the non-display area and the edge of the display area.
  • the bump includes at least one first bump and at least one second bump, and the driving chip is located between the edge of the first bump and the display area. Between the edges.
  • the driving chip is located outside the first bump; or, the driving chip is completely or partially disposed in the first bump.
  • the shape of the bump includes one or more of rectangle, trapezoid, arc, and triangle.
  • GOA traces are provided in the array substrate, and the GOA traces include inclined sections located in the non-display area and directed to the driving chip, and the GOA traces The inclined section of is connected to the driving chip; the non-display area is provided with a plurality of signal terminal groups for connecting to the flexible circuit board.
  • the signal terminal group includes a main signal terminal group and a secondary signal terminal group, wherein the main signal terminal group is located between the secondary signal terminal group and the driving chip.
  • the secondary signal terminal group is separated from the main signal terminal group, and the primary signal terminal is completely or partially located in the first bump, and the secondary signal terminal group The signal terminal is located outside the first bump.
  • the flexible circuit board includes a main body section and a connecting section, and the connecting section includes a first section corresponding to the main signal terminal group and a corresponding connection point.
  • the first block and the second block are arranged in a staggered manner.
  • the signal terminal group further includes a virtual terminal group, and the virtual terminal group is located at one of the inclined sections of the secondary signal terminal group away from the driver chip and the GOA trace. side.
  • the non-display area is also provided with a test terminal group, a conversion terminal group, and an identification terminal group, and at least one of the test terminal group, the conversion terminal group, and the identification terminal group Located between the edge of the second bump and the edge of the display area.
  • test terminal group the conversion terminal group and the identification terminal group are arranged in at least two rows.
  • An embodiment of the present application provides a display device including a display panel, the display panel including an array substrate, a driving chip, and a flexible circuit board, the array substrate including a display area and a non-display area, the driving chip and the flexible circuit board Bound to one side of the non-display area;
  • At least two bumps are formed on the side of the non-display area away from the display area, and recesses are formed between adjacent bumps;
  • a part of the flexible circuit board is bent to the back of the array substrate through the edge of the recess, and the driving chip is located between the edge of the non-display area and the edge of the display area.
  • the bump includes at least one first bump and at least one second bump, and the driving chip is located between the edge of the first bump and the display area. Between the edges.
  • the driving chip is located outside the first bump; or, the driving chip is completely or partially disposed in the first bump.
  • the shape of the bump includes one or more of a rectangle, a trapezoid, a circular arc, and a triangle.
  • GOA traces are provided in the array substrate, and the GOA traces include inclined sections located in the non-display area and directed to the driving chip, and the GOA traces The inclined section of is connected to the driving chip; the non-display area is provided with a plurality of signal terminal groups for connecting to the flexible circuit board.
  • the signal terminal group includes a main signal terminal group and a secondary signal terminal group, and the main signal terminal group is located between the secondary signal terminal group and the driving chip.
  • the secondary signal terminal group is separated from the main signal terminal group, and the primary signal terminal is completely or partially located in the first bump, and the secondary signal terminal The signal terminal is located outside the first bump.
  • the flexible circuit board includes a main body section and a connecting section, and the connecting section includes a first section corresponding to the main signal terminal group and a corresponding connection point.
  • the first block and the second block are arranged in a staggered manner.
  • the signal terminal group further includes a virtual terminal group, and the virtual terminal group is located at one of the inclined sections of the secondary signal terminal group away from the driver chip and the GOA trace. side.
  • the present application provides a display panel and a display device.
  • the array substrate of the display panel is provided with at least two bumps as extensions on the side of the non-display area away from the display area, and recesses are formed between the bumps.
  • the driver chip is arranged in the space between the edge of the display area and the edge of the non-display area, which increases the distance between the driver chip and the edge of the display area and the edge of the non-display area, and avoids The area of the non-display area of the high-screen-to-body ratio display is compressed, and the drive chip is too close to the display area and the edge of the substrate, resulting in poor electrical properties after the drive chip is pressed and the technical defects of poor liquid crystal cell sealing; at the same time, the flexible circuit board
  • the bending section is located in the recesses on both sides of the bump, and the bending radius of the bending section does not exceed the edge of the bump, so it does not increase the width of the non-display area, maintain
  • Fig. 1 is a schematic diagram of a conventional display panel.
  • FIG. 2 is a structural diagram of a display panel provided by an embodiment of the application.
  • FIG 3 is a schematic cross-sectional view of a display panel A-A' provided by an embodiment of the application.
  • FIG. 4 is a schematic diagram of comparison between a display panel provided by an embodiment of the application and an existing display panel.
  • FIG. 5 is a schematic diagram of the first type of bumps of the display panel provided by an embodiment of the application.
  • FIG. 6 is a schematic diagram of the second type of bumps of the display panel provided by an embodiment of the application.
  • FIG. 7 is a schematic diagram of a third type of bump of a display panel provided by an embodiment of the application.
  • FIG. 8 is a schematic diagram of a first terminal arrangement of a display panel provided by an embodiment of the application.
  • FIG. 9 is a schematic diagram of a first type of flexible circuit board of a display panel provided by an embodiment of the application.
  • FIG. 10 is a schematic diagram of the second terminal arrangement of the display panel provided by the embodiment of the application.
  • FIG. 11 is a schematic diagram of a second type of flexible circuit board of a display panel provided by an embodiment of the application.
  • FIG. 12 is a schematic diagram of a third terminal arrangement of a display panel provided by an embodiment of the application.
  • FIG. 13 is a schematic diagram of the fourth terminal arrangement of the display panel provided by the embodiment of the application.
  • the display panel provided by the present application includes an array substrate 101 and a color filter substrate 102 disposed opposite to the array substrate 101; the surface of the array substrate 101 defines a display area 103, The display area 103 is defined by a sealant, a liquid crystal layer is arranged in the sealant, and the color filter substrate 102 and the array substrate 101 are combined by the sealant.
  • the area outside the display area 103 and the edge of the array substrate 101 forms a non-display area 104.
  • the non-display area 104 is provided with signal traces, and is also bound with a driver chip 105, a flexible circuit board 106, etc. Electronic component.
  • the color filter substrate 102 is shorter than the array substrate 101, and the color filter substrate 102 is higher than the surface of the array substrate 101.
  • the projection of the lower edge of the color filter substrate 102 on the surface of the array substrate 101 The area between the edges of the array substrate 101 forms a stepped area, the stepped area is located in the non-display area 104, and the drive chip 105, the flexible circuit board 106 and other electronic components are located in the non-display area 104 In the step area, the signal trace extends from the step area to the entire non-display area 104 and the display area 103.
  • At least two bumps 107 are reserved at the end of the array substrate 101 far away from the display area 103, and a recess 108 is formed between adjacent bumps 107; the driving chip 105 is arranged in The lower edge of the bump 107 is between the edge of the non-display area 104 and the edge of the display area 103, thereby raising the height of the upper side of the driving chip 105 from the edge of the display area 103, and the driving The height of the lower side of the chip 105 from the lower edge of the bump 107.
  • the bump 107 includes at least one first bump 107a and at least one second bump 107b, the first bump 107a is located in the middle of the end of the array substrate 101, and the driving The chip 105 is disposed between the lower edge of the first bump 107 a and the edge of the display area 103.
  • the flexible circuit board 106 includes a connection section connected to the non-display area 104, a main body section bent to the back of the display panel, and a bending section connecting the connection section and the main body section Section, the bending section is bent to the back of the array substrate through the edge of the recess. That is, the bending section is located in the concave portion, and the bending radius of the bending section is less than or equal to the height of the first bump 107 a, that is, the bending section does not exceed the concave portion 108.
  • the bending section is bent by the edge of the concave portion on at least one side of the first bump 107a, or may be bent by the concave portion on at least one side of the second bump 107b. The edges are completely bent.
  • the first bump 107a is arranged according to the number of driving chips, and the positions of the first bump 107a and the driving chip are not limited to the middle position of the non-display area, for example, The first bump 107a can also be arranged close to any side of the non-display area.
  • the second bumps 107b are arranged according to the number of the first bumps 107a to increase the contact area between the bumps 107 and the display device housing, so that the force of the display panel is uniform.
  • the second bump 107b and the first bump 107a are not limited to the staggered arrangement.
  • the second bump 107b may only have a supporting function, and no circuit element is provided in its area, or it may be used as a setting area of the circuit element.
  • the circuit element may be a circuit element required by a display panel, such as a switching terminal. It can also be fingerprint recognition, camera and other circuit components not required by the display panel.
  • the embodiment of the present application expands the space on the upper and lower sides of the driving chip 105 without increasing the overall height of the non-display area 104, which not only solves the space around the driving chip 105
  • the problem is that the narrow non-display area of the prior art display panel is also maintained.
  • FIG. 4 (1) in FIG. 4 is a display panel provided by this application, and (2) in FIG. 4 is a display panel in the prior art; both include an array substrate 101, a color film substrate 102, and a display area 103 ,
  • the height D of the bump 107 also includes the height D of the bump 107, The height E between the lower edge of the driving chip 105 and the edge of the bump 107, and the height/figure between the lower edge of the color filter substrate 102 and the edge of the recessed portion of the non-display area 104 in FIG. 4 (1)
  • the height F between the lower edge of the color filter substrate 102 and the edge of the flexible circuit board 106.
  • the total height of the non-display area height A+height F+height D, wherein the value of height A and height F are equivalent, and the difference between height A and height F is less than 50um, and height D is greater than height
  • the difference between B and height F, for example, height D is 5 to 6 times the difference between height B and height F, so as to ensure that height C and height E are not less than 100um.
  • Table 1 the specific setting method is shown in Table 1 below:
  • the unit of height is microns.
  • the height of the bump is increased, and the driving chip is lowered, so that the height A between the lower edge of the display area and the edge of the color filter substrate, and the driving chip
  • the height C between the upper edge and the edge of the color filter substrate is increased, and the height F between the lower edge of the color filter substrate and the edge of the recessed portion of the non-display area is reduced compared with the prior art
  • the combined height of the non-display area and the bent section of the flexible circuit board after bending in the embodiment of the present application is smaller than the prior art, further shortening the height of the non-display area.
  • the distance between the side of the driver chip close to the display area and the edge of the display area is set to be greater than The distance between the side of the driving chip close to the first bump and the edge of the first bump.
  • the setting positions of the driving chip can be various and can be designed according to needs.
  • the driving chip is disposed in the non-display area and located outside the first bump.
  • the driving chip is completely or partially disposed in the first bump.
  • the shape of the bump 107 can be various, and it can be one or more of rectangle, trapezoid, arc, and triangle.
  • the shape of each bump 107 can be all the same, or All are different, and can also be partly the same, which are set according to the circuit layout in actual design.
  • the shape of the second bump located on the first side is rectangular, the shape of the first bump located at the middle position is trapezoidal or arc shape, and the shape of the second bump located on the second side The shape is triangle and so on.
  • the display panel provided by the present application includes an array substrate 101, a color filter substrate 102, a display area 103, and bumps 107 formed at the end of the array substrate 101, so The non-display area 104 of the array substrate 101 is provided with a driving chip 105.
  • the bump 107 includes two symmetrically arranged short sides connecting the edges of the non-display area 104, and a long side connecting the other ends of the two sides; for example, as shown in FIG. 5, the short side is A straight side, and the short side and the edge of the non-display area 104 are perpendicular to each other. At this time, the surface shape of the bump 107 is rectangular.
  • the bump 107 includes two symmetrically arranged short sides connecting the edges of the non-display area 104, and a long side connecting the other ends of the two sides; as shown in FIG. 6,
  • the difference between the display panel provided in this application and FIG. 5 is that the short side is a straight side, and the included angle formed between the short side and the edge of the non-display area 104 is a non-right angle, that is, the included angle is greater than Or less than 90 degrees, the surface shape of the bump 107 is trapezoidal.
  • the difference between the display panel provided by the present application and FIGS. 5 and 6 is that the bump 107 includes an outer arc edge, and both ends of the outer arc edge It is connected to the edge of the non-display area 104, and the end of the outer arc side presents an inner arc transition.
  • the display panel provided by the present application includes an array substrate 101, a color filter substrate 102, a non-display area 104 located in a non-display area of the array substrate 101, and a display panel disposed in the non-display area 104.
  • the driving chip 105 and the fan-out wiring 801 connected to the driving chip 105, for example, the fan-out wiring 801 is used to transmit display data signals to the display area 103;
  • the non-display area 104 is provided with at least one set GOA (gate drive circuit) traces 802.
  • GOA gate drive circuit
  • the inclined section of the GOA trace 802 is connected to the driving chip 105 to input the Gate signal, and the GOA trace
  • the parallel section of the line 802 connects the scan lines of each pixel row to output the Gate signal.
  • the non-display area 104 is provided with a plurality of signal terminal groups for connecting to the flexible circuit board.
  • the signal terminal groups include at least a main signal terminal group 803 and a secondary signal terminal group 804, for example, the main signal terminal
  • the group 803 includes pixel data signals and gate signals.
  • the sub-signal terminal group 804 includes power signals, etc.; wherein the main signal terminal group 803 is located between the sub-signal terminal group 804 and the driving chip 105 to reduce signal transmission delay.
  • the main signal terminal group 803 is arranged close to the driving chip 105, and the secondary signal terminal group 804 is away from the driving chip 105 and the inclination of the GOA trace 802 Segment settings.
  • the inclined section of the GOA trace 802 connected to the driver chip 105 moves downward at the same time, thus compressing the terminal setting space. If the terminal is too close to the GOA trace 802, the impedance will increase. , It will cause signal distortion and affect the display quality. Therefore, in the embodiment of the present application, the terminal is at least partially arranged away from the GOA wiring 802.
  • the secondary signal terminal group 804 and the main signal terminal group 803 are arranged separately, and the primary signal terminal is completely or partially located in the first bump 107a, and the secondary signal The terminal is located outside the bump 107, thereby effectively controlling the distance between the terminal and the GOA trace 802 and reducing impedance.
  • the flexible circuit board includes a main body section 1061, and a connection section for connecting the signal terminal group, and the connection section includes a first area corresponding to the main signal terminal group 803.
  • the block 1062 and the second block 1063 corresponding to the secondary signal terminal group 804, the first block 1062 and the second block 1063 are arranged in a staggered manner.
  • the terminals are closely arranged, and the main signal terminal group 803 and the secondary signal terminal group 804 are both arranged outside the first bump 107a, thereby The space compression of the first bump 107a is avoided, and the area of each terminal in the main signal terminal group 803 is equivalent to the area of each terminal of the secondary signal terminal group 804 to ensure stable connection of signal contact points.
  • the height of each terminal of the main signal terminal group 4071 is less than the height of each terminal of the secondary signal terminal group 4072, and the width of each terminal of the main signal terminal group 4071 is greater than The width of each terminal of the secondary signal terminal group 4072 is reduced by reducing the height of the terminal close to the GOA trace 802 to maintain the distance from the GOA trace 802, thereby reducing the generation between the terminal and the GOA trace 802 ⁇ impedance.
  • the height of each terminal in the main signal terminal group 803 ranges from the terminal away from the driver chip 105 and the inclined section of the GOA trace 802 to the terminal near the driver chip 105 and the The terminals of the inclined section of the GOA trace 802 decrease; and the width of each terminal in the main signal terminal group 804 ranges from the terminal of the inclined section of the driver chip 105 and the GOA trace 802 to closer The terminals of the driving chip 105 and the inclined section of the GOA trace 802 are increased to ensure that the distance between each terminal and the GOA trace 802 is equal.
  • the flexible circuit board includes a main body section 1061 and a connecting section 1064 for connecting the terminals.
  • the end of the connecting section 1064 has a regular geometric shape.
  • the connecting section 1064 A first connection area and a second connection area are provided at the ends of the, the first connection area covers and connects to the main signal terminal group, and the second connection area covers and connects to the secondary signal terminal group.
  • the signal terminal group further includes a dummy terminal group located on the side of the secondary signal terminal group 4072 away from the driving chip 406 and the inclined section of the GOA trace 409 .
  • the terminals in the virtual terminal group do not transmit signals, and are used to increase the binding area between the panel and the flexible circuit board, enhance the connection and fixing effect, and then can support the flexible circuit board to ensure the flatness of the display panel.
  • the display panel provided by the present application includes an array substrate 101, a color filter substrate 102, and a non-display area 104 located in a non-display area of the array substrate 101, which is disposed
  • the test terminal group 805, the conversion terminal group 806, and the identification terminal group 806 in the non-display area 104, and at least one of the test terminal group 805, the conversion terminal group 806, and the identification terminal group 807 is located on the second bump Between the edge of 107b and the edge of the display area 103.
  • the terminals in the test terminal group 805, the conversion terminal group 806, and the identification terminal group 807 can be arranged in the same row between the edge of the second bump 107b and the edge of the display area 103, or can be arranged in multiple rows on the second bump Between the edge of 107b and the edge of the display area 103.
  • test terminal The group 805, the conversion terminal group 806, and the identification terminal group 807 are arranged in at least two rows.
  • the terminals in the test terminal group 805 are used to test the performance of the display panel by inputting test signals to the terminals in the test terminal group 805 after the array substrate is prepared into a display panel.
  • the terminals in the conversion terminal group 806 are used to coat conductive silver glue, which is used to connect the ground wire (not shown) in the non-display area 101 of the array substrate and the color film substrate opposite to the array substrate in the display panel.
  • the conductive layer plays a role of anti-static.
  • the terminals in the identification terminal group 807 are used to record related information of the array substrate, and are used for alignment.
  • the embodiment of the application further provides a display device.
  • the display device provided in the embodiment of the application includes a display panel, the display panel including an array substrate, a display area provided on the surface of the array substrate, and Formed in a non-display area of the array substrate that does not cover a portion of the display area, and a driver chip and a flexible circuit board are bound to the non-display area;
  • a bump is formed at one end of the non-display area away from the display area, and a recess is formed between adjacent bumps; the bump includes at least one first bump and at least one second bump, so The driving chip is located between the edge of the first bump and the edge of the display area;
  • a part of the flexible circuit board is bent to the back of the array substrate through the edge of the concave portion on at least one side of the first bump.
  • the distance between the side of the driving chip close to the display area and the edge of the display area is greater than that of the driving chip close to the second The distance between one side of a bump and the edge of the first bump.
  • the driving chip is located outside the first bump; or, the driving chip is completely or partially disposed in the first bump .
  • the bump in the display device provided by the embodiment of the present application, includes two symmetrically arranged short sides connecting the edges of the non-display area, and a second side connecting the other ends of the two sides.
  • Long side; the short side and the edge of the non-display area are perpendicular to each other, or the angle formed between the short side and the edge of the non-display area is a non-right angle.
  • the bump in the display device provided in the embodiment of the present application, includes an outer arc edge, both ends of the outer arc edge are connected to the edge of the non-display area, and the The end of the outer arc side is in an inner arc transition.
  • GOA traces are provided in the array substrate, and the GOA traces include inclined lines located in the non-display area and directed to the driving chip. Section, the inclined section of the GOA trace is connected to the drive chip; the non-display area is provided with a plurality of signal terminal groups for connecting to the flexible circuit board, and the signal terminal group includes a main signal terminal group and The secondary signal terminal group, wherein the main signal terminal group is located between the secondary signal terminal group and the driving chip.
  • the secondary signal terminal group and the main signal terminal group are arranged separately, and the main signal terminal is completely or partially located in the first signal terminal group.
  • the secondary signal terminal is located outside the first bump.
  • the flexible circuit board includes a main body section and a connecting section, and the connecting section includes a first terminal corresponding to the main signal terminal group.
  • a block and a second block corresponding to the secondary signal terminal group, the first block and the second block are arranged in a staggered manner.
  • a virtual terminal group is further provided in the non-display area, and the virtual terminal group is located in the secondary signal terminal group away from the driving chip and the driving chip.
  • One side of the inclined section of the GOA trace is further provided in the non-display area, and the virtual terminal group is located in the secondary signal terminal group away from the driving chip and the driving chip.
  • the non-display area is also provided with a test terminal group, a conversion terminal group, and an identification terminal group.
  • the test terminal group, the conversion terminal group and the identification terminal group At least one of the terminal groups is located between the edge of the second bump and the edge of the display area.
  • the test terminal group, the conversion terminal group, and the identification terminal group are arranged in at least two rows.
  • the present application provides a display panel and a display device.
  • the array substrate of the display panel is provided with at least two bumps as extensions on the side of the non-display area away from the display area, and recesses are formed between the bumps.
  • the driver chip is arranged in the space between the edge of the display area and the edge of the non-display area, which increases the distance between the driver chip and the edge of the display area and the edge of the non-display area, and avoids The area of the non-display area of the high-screen-to-body ratio display is compressed, and the drive chip is too close to the display area and the edge of the substrate, resulting in poor electrical properties after the drive chip is pressed and the technical defects of poor liquid crystal cell sealing; at the same time, the flexible circuit board
  • the bending section is located in the recesses on both sides of the bump, and the bending radius of the bending section does not exceed the edge of the bump, so it does not increase the width of the non-display area, maintain

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Abstract

一种显示面板以及显示装置，显示面板的阵列基板（101）在非显示区（104）远离显示区（103）的一侧设置有至少两个凸块（107）作为延伸部，凸块（107）之间形成凹陷部（108），驱动芯片（105）设置于显示区（103）边缘与非显示区（104）边缘之间的空间内，增加了驱动芯片（105）与显示区（103）边缘及非显示区（104）边缘之间的距离，柔性电路板（106）的弯折区段位于凹陷部（108）内，不会增加非显示区（104）宽度。

Description

显示面板以及显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板以及显示装置。
 背景技术
随着全面屏技术的发展，显示屏屏占比在不断地提高，显示器的非显示区（如下边框）的面积也越来越小，如图1所示，下边框到显示区边缘之间的距离d不断减小。
由于需要在非显示区内设置驱动芯片、走线、端子等电路元件，为了保证这些电路元件的正常功能，需要预留足够的面积，下边框到显示区边缘之间的距离d不能小于预定值，现有显示面板的设置方式不能满足全面屏技术的发展趋势。
即，现有显示面板存在不能满足全面屏发展趋势的技术问题，需要改进。
 技术问题
本申请提供一种显示面板以及显示装置，以缓解现有显示面板存在的不能满足全面屏发展趋势的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供一种显示面板，其包括阵列基板、驱动芯片以及柔性电路板，所述阵列基板包括显示区以及非显示区 ，所述驱动芯片以及柔性电路板绑定在所述非显示区的一侧；
所述非显示区远离所述显示区的一侧形成有至少两个凸块 ，相邻凸块之间形成凹陷部；
其中，所述柔性电路板的部分区段经所述凹陷部边缘弯折至所述阵列基板的背部；所述驱动芯片位于所述非显示区边缘与所述显示区边缘之间。
在本申请实施例提供的显示面板中，所述凸块包括至少一个第一凸块、以及至少一个第二凸块，所述驱动芯片位于所述第一凸块的边缘与所述显示区的边缘之间。
在本申请实施例提供的显示面板中，所述驱动芯片位于所述第一凸块之外；或者，所述驱动芯片完全或部分设置于所述第一凸块内。
在本申请实施例提供的显示面板中，所述凸块的形状包括矩形、梯形、圆弧形、三角形中的一种或几种。
在本申请实施例提供的显示面板中，所述阵列基板内设置有GOA走线，所述GOA走线包括位于所述非显示区内且指向所述驱动芯片的倾斜段，所述GOA走线的倾斜段连接所述驱动芯片；所述非显示区内设置有多个用以连接所述柔性电路板的信号端子组。
在本申请实施例提供的显示面板中，所述信号端子组包括主信号端子组和次信号端子组，其中，所述主信号端子组位于所述次信号端子组和所述驱动芯片之间。
在本申请实施例提供的显示面板中，所述次信号端子组与所述主信号端子组之间分离设置，且所述主信号端子完全或部分位于所述第一凸块内，所述次信号端子位于所述第一凸块之外。
在本申请实施例提供的显示面板中，所述柔性电路板包括主体区段以及用连接区段，所述连接区段包括对应连接所述主信号端子组的第一区块、以及对应连接所述次信号端子组的第二区块，所述第一区块与所述第二区块错位设置。
在本申请实施例提供的显示面板中，所述信号端子组还包括虚拟端子组，所述虚拟端子组位于所述次信号端子组远离所述驱动芯片和所述GOA走线的倾斜段的一侧。
在本申请实施例提供的显示面板中，所述非显示区内还设置有测试端子组、转换端子组和识别端子组，所述测试端子组、转换端子组和识别端子组中的至少一种位于所述第二凸块的边缘与所述显示区的边缘之间。
在本申请实施例提供的显示面板中，所述测试端子组、转换端子组和识别端子组设置在至少两行。
本申请实施例提供一种显示装置，其包括显示面板，所述显示面板包括阵列基板、驱动芯片以及柔性电路板，所述阵列基板包括显示区以及非显示区，所述驱动芯片以及柔性电路板绑定在所述非显示区的一侧；
所述非显示区远离所述显示区的一侧形成有至少两个凸块，相邻凸块之间形成凹陷部；
其中，所述柔性电路板的部分区段经所述凹陷部边缘弯折至所述阵列基板的背部，所述驱动芯片位于所述非显示区边缘与所述显示区边缘之间。
在本申请实施例提供的显示装置中，所述凸块包括至少一个第一凸块、以及至少一个第二凸块，所述驱动芯片位于所述第一凸块的边缘与所述显示区的边缘之间。
在本申请实施例提供的显示装置中，所述驱动芯片位于所述第一凸块之外；或者，所述驱动芯片完全或部分设置于所述第一凸块内。
在本申请实施例提供的显示装置中，所述凸块的形状包括矩形、梯形、圆弧形、三角形中的一种或几种。
在本申请实施例提供的显示装置中，所述阵列基板内设置有GOA走线，所述GOA走线包括位于所述非显示区内且指向所述驱动芯片的倾斜段，所述GOA走线的倾斜段连接所述驱动芯片；所述非显示区内设置有多个用以连接所述柔性电路板的信号端子组。
在本申请实施例提供的显示装置中，所述信号端子组包括主信号端子组和次信号端子组，所述主信号端子组位于所述次信号端子组和所述驱动芯片之间。
在本申请实施例提供的显示装置中，所述次信号端子组与所述主信号端子组之间分离设置，且所述主信号端子完全或部分位于所述第一凸块内，所述次信号端子位于所述第一凸块之外。
在本申请实施例提供的显示装置中，所述柔性电路板包括主体区段以及用连接区段，所述连接区段包括对应连接所述主信号端子组的第一区块、以及对应连接所述次信号端子组的第二区块，所述第一区块与所述第二区块错位设置。
在本申请实施例提供的显示装置中，所述信号端子组还包括虚拟端子组，所述虚拟端子组位于所述次信号端子组远离所述驱动芯片和所述GOA走线的倾斜段的一侧。
 有益效果
本申请提供一种显示面板以及显示装置，该显示面板的阵列基板在非显示区远离显示区的一侧设置有至少两个凸块作为延伸部，凸块之间形成凹陷部，相较于现有的显示面板，本申请提供的显示面板中驱动芯片设置于显示区边缘与非显示区边缘之间的空间内，增加了驱动芯片与显示区边缘及非显示区边缘之间的距离，避免了高屏占比显示屏非显示区面积被压缩导致的驱动芯片距离显示区和基板边缘过近，产生的驱动芯片压合后电性不良及液晶成盒密封不良的技术缺陷；同时，柔性电路板的弯折区段位于凸块两侧的凹陷部内，弯折区段的弯折半径不超出凸块边缘，因此不会增加非显示区宽度，保持显示设备的屏占比，缓解了现有显示面板存在的不能满足全面屏发展趋势的技术问题。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1现有显示面板的示意图。
图2为本申请实施例提供的显示面板的结构图。
图3为本申请实施例提供的显示面板A-A’剖面示意图。
图4为本申请实施例提供的显示面板与现有显示面板的对比示意图。
图5为本申请实施例提供的显示面板的第一种凸块示意图。
图6为本申请实施例提供的显示面板的第二种凸块示意图。
图7为本申请实施例提供的显示面板的第三种凸块示意图。
图8为本申请实施例提供的显示面板的第一种端子设置示意图。
图9为本申请实施例提供的显示面板的第一种柔性电路板示意图。
图10为本申请实施例提供的显示面板的第二种端子设置示意图。
图11为本申请实施例提供的显示面板的第二种柔性电路板示意图。
图12为本申请实施例提供的显示面板的第三种端子设置示意图。
图13为本申请实施例提供的显示面板的第四种端子设置示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
针对现有显示面板存在的不能满足全面屏发展趋势的技术问题，本申请实施例可以缓解。
如图2以及图3所示，本申请提供的显示面板，包括阵列基板101、以及与所述阵列基板101相对设置的彩膜基板102；所述阵列基板101表面定义有显示区103，所述显示区103通过框胶限定，所述框胶内设置有液晶层，所述彩膜基板102与所述阵列基板101通过所述框胶相结合。
所述显示区103外与所述阵列基板101边缘之间的区域形成非显示区104，所述非显示区104内布设有信号走线、还绑定有驱动芯片105、柔性电路板106等其它电子元件。
所述彩膜基板102短于所述阵列基板101，且所述彩膜基板102高于所述阵列基板101表面，所述彩膜基板102下侧边缘在所述阵列基板101表面的投影与所述阵列基板101边缘之间的区域形成台阶区域，所述台阶区域位于所述非显示区104内，且所述驱动芯片105、所述柔性电路板106等其他电子元件位于所述非显示区104的一侧，即台阶区域内，所述信号走线从所述台阶区域延伸至整个所述非显示区104及所述显示区103内。
在切割显示面板母版时，在所述阵列基板101远离所述显示区103的一端预留至少两个凸块107，相邻凸块107之间形成凹陷部108；所述驱动芯片105设置于所述凸块107的下侧边缘，即非显示区104边缘与所述显示区103边缘之间，从而抬升了所述驱动芯片105上侧距离所述显示区103边缘的高度，以及所述驱动芯片105下侧距离所述凸块107下侧边缘的高度。
在一种实施例中，所述凸块107包括至少一个第一凸块107a、以及至少一个第二凸块107b，第一凸块107a位于所述阵列基板101端部的中间位置，所述驱动芯片105设置于所述第一凸块107a的下侧边缘与所述显示区103的边缘之间。
所述柔性电路板106包括连接于所述非显示区104内的连接区段、弯折至所述显示面板背部的主体区段、以及连接所述连接区段与所述主体区段的弯折区段，所述弯折区段经所述凹陷部边缘弯折至所述阵列基板的背部。即所述弯折区段位于所述凹陷部内，所述弯折区段的弯折半径小于或等于所述第一凸块107a的高度，即弯折区段没有超出凹陷部108。
在一种实施例中，所述弯折区段经所述第一凸块107a的至少一侧的凹陷部边缘完成弯折，也可以经所述第二凸块107b的至少一侧的凹陷部边缘完成弯折。
在本申请实施例中，所述第一凸块107a根据驱动芯片的数量设置，且所述第一凸块107a和所述驱动芯片的位置不局限于所述非显示区的中间位置，例如，所述第一凸块107a还可以靠近所述非显示区的任意一侧设置。
在本申请实施例中，所述第二凸块107b根据所述第一凸块107a的数量设置，用于增大凸块107与显示装置壳体的接触面积，使得显示面板的受力均匀。第二凸块107b和第一凸块107a不局限于交错设置的方式。
在本申请实施例中，第二凸块107b可以仅具备支撑作用，其区域内不设置电路元件，也可以作为电路元件的设置区，电路元件可以是显示面板所需要的电路元件，例如转换端子等，也可以是指纹识别、摄像头等其他非显示面板所需要的电路元件。
因此，相较于现有技术的显示面板，本申请实施例扩宽了所述驱动芯片105上下两侧的空间，同时也没有增加非显示区104整体高度，不仅解决了驱动芯片105周围的空间问题，还保持了现有技术的显示面板的窄非显示区。
如图4所示，图4中（1）为本申请提供的显示面板，图4中（2）为现有技术的显示面板；两者均包括阵列基板101、彩膜基板102、显示区103、驱动芯片105以及柔性电路板106，所述阵列基板101包括非显示区104，所述非显示区104包括所述显示区103下侧边缘与所述彩膜基板102边缘之间的高度A、所述驱动芯片105的高度B、所述驱动芯片105上侧边缘与所述彩膜基板102边缘之间的高度C，图4中（1）还包括所述凸块107的高度D、所述驱动芯片105下侧边缘与所述凸块107边缘之间的高度E、图4中（1）所述彩膜基板102下侧边缘与所述非显示区104凹陷部边缘之间的高度/图4中（2）所述彩膜基板102下侧边缘与所述柔性电路板106边缘之间的高度F。
在本申请实施例中，所述非显示区的总高度=高度A+高度F+高度D，其中，高度A与高度F的值相当，且高度A与高度F的差值小于50um，高度D大于高度B与高度F的差值，例如，高度D为高度B与高度F差值的5至6倍，从而确保高度C与高度E不低于100um。例如，具体设置方式参考如下表1所示：
  A B C D E F
图4中（1） 700 780 200 400 120 700
图4中（2） 540 780 80 0 0 860
表1
在表1中，高度的单位为微米。
由表1可知，本申请实施例的显示面板，增加了凸块的高度，驱动芯片下调，使得所述显示区下侧边缘与所述彩膜基板边缘之间的高度A、以及所述驱动芯片上侧边缘与所述彩膜基板边缘之间的高度C均有提升，且所述彩膜基板下侧边缘与所述非显示区凹陷部边缘之间的高度F相对现有技术有减小，在柔性电路板弯折半径相同的情况下，本申请实施例中非显示区与弯折后的所述柔性电路板的弯折区段的组合高度小于现有技术，进一步缩短非显示区高度。
在一种实施例中，为了预留足够的空间布设GOA走线、扇出走线以及端子，所述驱动芯片靠近所述显示区的一侧与所述显示区边缘之间的距离，设置为大于所述驱动芯片靠近所述第一凸块的一侧与所述第一凸块边缘之间的距离。
所述驱动芯片的设置位置可以是多种多样的，可以根据需要进行设计。
在一种实施例中，所述驱动芯片设置于所述非显示区内，且位于所述第一凸块之外。
在一种实施例中，所述驱动芯片完全或部分设置于所述第一凸块内。
在一种实施例中，凸块107的形状可以是多种多样的，可以是矩形、梯形、圆弧形、三角形中的一种或几种，各凸块107的形状可以全部相同，也可以全部不同，还可以部分相同，在实际设计时根据电路布局设置。
在一种实施例中，位于第一侧边的第二凸块的形状为矩形，位于中间位置的第一凸块的形状为梯形或者圆弧形，位于第二侧边的第二凸块的形状为三角形等等。
在一种实施例中，如图5所示，本申请提供的显示面板，包括阵列基板101、彩膜基板102、显示区103、以及形成于所述阵列基板101端部的凸块107，所述阵列基板101的非显示区104内设置有驱动芯片105。
所述凸块107包括连接所述非显示区104边缘的两条对称设置的短边，以及连接两条所述侧边另一端的长边；例如，如图5所示，所述短边为直边，且所述短边与所述非显示区104边缘之间相互垂直，此时，所述凸块107的表面形状为矩形。
在一种实施例中，所述凸块107包括连接所述非显示区104边缘的两条对称设置的短边，以及连接两条所述侧边另一端的长边；如图6所示，本申请提供的显示面板与图5的区别为：所述短边为直边，且所述短边与所述非显示区104边缘之间形成的夹角为非直角，即所述夹角大于或小于90度，所述凸块107的表面形状为梯形。
在一种实施例中，如图7所示，本申请提供的显示面板与图5、图6的区别为：所述凸块107包括一外圆弧边，所述外圆弧边的两端连接于所述非显示区104边缘，且所述外圆弧边的端部呈内圆弧过渡。
现针对柔性电路板的端子设置方式进行说明。
如图8所示，本申请提供的显示面板，包括阵列基板101、彩膜基板102、以及位于所述阵列基板101的非显示区的非显示区104、设置于所述非显示区104内的驱动芯片105以及连接所述驱动芯片105的扇出走线801，例如，所述扇出走线801用于传输显示数据信号至所述显示区103内；所述非显示区104内设置有至少一组GOA（栅极驱动电路）走线802，以两组相对称的GOA走线802为例进行说明，两组所述GOA走线802均包括位于所述显示区103外侧且平行于所述显示区103边缘的平行段，以及位于所述非显示区104内且指向所述驱动芯片105的倾斜段，所述GOA走线802的倾斜段连接所述驱动芯片105以输入Gate信号，所述GOA走线802的平行段连接各像素行的扫描线以输出Gate信号。
所述非显示区104内设置有多个用以连接所述柔性电路板的信号端子组，所述信号端子组至少包括主信号端子组803和次信号端子组804，例如，所述主信号端子组803包括像素数据信号和栅极信号，所述次信号端子组804包括电源信号等；其中，主信号端子组803位于次信号端子组804和驱动芯片105之间，以降低信号传输的延迟。
在一种实施例中，如图8所示，所述主信号端子组803靠近所述驱动芯片105设置，所述次信号端子组804远离所述驱动芯片105和所述GOA走线802的倾斜段设置。由于驱动芯片105相对下移，连接所述驱动芯片105的所述GOA走线802的倾斜段同时下移，从而压缩了端子的设置空间，端子距离所述GOA走线802过近则会增加阻抗，会导致信号失真，影响显示品质，因此，本申请实施例将端子至少部分远离所述GOA走线802设置。
在一种实施例中，所述次信号端子组804与所述主信号端子组803之间分离设置，且所述主信号端子完全或部分位于所述第一凸块107a内，所述次信号端子位于所述凸块107之外，从而有效控制端子与所述GOA走线802的距离，降低阻抗。
如图9所示，所述柔性电路板包括主体区段1061，以及用于连接所述信号端子组的连接区段，所述连接区段包括对应连接所述主信号端子组803的第一区块1062、以及对应连接所述次信号端子组804的第二区块1063，所述第一区块1062与所述第二区块1063错位设置。
如图10所示，与图8的信号端子排布方式相比，各端子紧密排列，所述主信号端子组803与所述次信号端子组804均设置于第一凸块107a之外，从而避免对第一凸块107a的空间压缩，且所述主信号端子组803中的各个端子的面积，与所述次信号端子组804的各个端子的面积相当，以保证信号接触点的稳定连接。
在一种实施例中，所述主信号端子组4071的各端子的高度，小于所述次信号端子组4072的各端子的高度，并且，所述主信号端子组4071的各端子的宽度，大于所述次信号端子组4072的各端子的宽度，通过降低靠近所述GOA走线802的端子的高度来保持与所述GOA走线802间的距离，从而降低端子与GOA走线802之间产生的阻抗。
在一种实施例中，所述主信号端子组803中的各端子的高度，自远离所述驱动芯片105和所述GOA走线802的倾斜段的端子，至靠近所述驱动芯片105和所述GOA走线802的倾斜段的端子递减；并且，所述主信号端子组804中的各端子的宽度，自远离所述驱动芯片105和所述GOA走线802的倾斜段的端子，至靠近所述驱动芯片105和所述GOA走线802的倾斜段的端子递增，从而保证各端子与GOA走线802间的距离相等。
如图11所示，所述柔性电路板包括主体区段1061，以及用于连接所述端子的连接区段1064，所述连接区段1064的端部为规则几何形状，所述连接区段1064的端部设置有第一连接区域和第二连接区域，所述第一连接区域覆盖且连接所述主信号端子组，所述第二连接区域覆盖且连接所述次信号端子组。
在一种实施例中，所述信号端子组还包括虚拟端子组，所述虚拟端子组位于所述次信号端子组4072远离所述驱动芯片406和所述GOA走线409的倾斜段的一侧。虚拟端子组内的端子不传输信号，用于增大面板与柔性电路板之间的绑定面积，增强连接固定效果，进而可以对柔性电路板进行支撑，保证显示面板的平整。
现针对第二凸块上的电路设置进行说明。
在一种实施例中，如图12所示，本申请提供的显示面板，包括阵列基板101、彩膜基板102、以及位于所述阵列基板101的非显示区的非显示区104、设置于所述非显示区104内的测试端子组805、转换端子组806和识别端子组806，所述测试端子组805、转换端子组806和识别端子组807中的至少一种位于所述第二凸块107b的边缘与所述显示区103的边缘之间。
测试端子组805、转换端子组806和识别端子组807中的端子可以同行设置于第二凸块107b的边缘与所述显示区103的边缘之间，也可以分多行设置于第二凸块107b的边缘与所述显示区103的边缘之间。
在一种实施例中，为了增大测试端子组805、转换端子组806和识别端子组806之间的缝隙，如图13所示，在本申请实施例提供的显示面板中，所述测试端子组805、转换端子组806和识别端子组807设置在至少两行。
测试端子组805中的端子用于阵列基板在制备成显示面板后，通过对测试端子组805中的端子输入测试信号以对显示面板进行性能测试。转换端子组806中的端子用于涂布导电银胶，导电银胶用于连接阵列基板非显示区101中的接地线（未示出）和显示面板中与阵列基板对置的彩膜基板中的导电层以起到防静电作用。识别端子组807中的端子用于记录阵列基板的相关信息，以及用于对位等。
在一种实施例中，本申请实施例还提供了一种显示装置，本申请实施例提供的显示装置包括显示面板，该显示面板包括阵列基板、设置于所述阵列基板表面的显示区、以及形成于所述阵列基板未覆盖所述显示区部分的非显示区，所述非显示区内绑定有驱动芯片以及柔性电路板；
其中，所述非显示区远离所述显示区的一端形成有凸块，相邻凸块之间形成凹陷部；所述凸块包括至少一个第一凸块、以及至少一个第二凸块，所述驱动芯片位于所述第一凸块的边缘与所述显示区的边缘之间；
所述柔性电路板的部分区段经所述第一凸块至少一侧的凹陷部边缘弯折至所述阵列基板的背部。
在一种实施例中，在本申请实施例提供的显示装置中，所述驱动芯片靠近所述显示区的一侧与所述显示区边缘之间的距离，大于所述驱动芯片靠近所述第一凸块的一侧与所述第一凸块边缘之间的距离。
在一种实施例中，在本申请实施例提供的显示装置中，所述驱动芯片位于所述第一凸块之外；或者，所述驱动芯片完全或部分设置于所述第一凸块内。
在一种实施例中，在本申请实施例提供的显示装置中，所述凸块包括连接所述非显示区边缘的两条对称设置的短边，以及连接两条所述侧边另一端的长边；所述短边与所述非显示区边缘之间相互垂直，或者，所述短边与所述非显示区边缘之间形成的夹角为非直角。
在一种实施例中，在本申请实施例提供的显示装置中，所述凸块包括一外圆弧边，所述外圆弧边的两端连接于所述非显示区边缘，且所述外圆弧边的端部呈内圆弧过渡。
在一种实施例中，在本申请实施例提供的显示装置中，所述阵列基板内设置有GOA走线，所述GOA走线包括位于所述非显示区内且指向所述驱动芯片的倾斜段，所述GOA走线的倾斜段连接所述驱动芯片；所述非显示区内设置有多个用以连接所述柔性电路板的信号端子组，所述信号端子组包括主信号端子组和次信号端子组，其中，所述主信号端子组位于所述次信号端子组和所述驱动芯片之间。
在一种实施例中，在本申请实施例提供的显示装置中，所述次信号端子组与所述主信号端子组之间分离设置，且所述主信号端子完全或部分位于所述第一凸块内，所述次信号端子位于所述第一凸块之外。
在一种实施例中，在本申请实施例提供的显示装置中，所述柔性电路板包括主体区段以及用连接区段，所述连接区段包括对应连接所述主信号端子组的第一区块、以及对应连接所述次信号端子组的第二区块，所述第一区块与所述第二区块错位设置。
在一种实施例中，在本申请实施例提供的显示装置中，所述非显示区内还设置有虚拟端子组，所述虚拟端子组位于所述次信号端子组远离所述驱动芯片和所述GOA走线的倾斜段的一侧。
在一种实施例中，在本申请实施例提供的显示装置中，所述非显示区内还设置有测试端子组、转换端子组和识别端子组，所述测试端子组、转换端子组和识别端子组中的至少一种位于所述第二凸块的边缘与所述显示区的边缘之间。
在一种实施例中，在本申请实施例提供的显示装置中，所述测试端子组、转换端子组和识别端子组设置在至少两行。
根据上述实施例可知：
本申请提供一种显示面板以及显示装置，其显示面板的阵列基板在非显示区远离显示区的一侧设置有至少两个凸块作为延伸部，凸块之间形成凹陷部，相较于现有的显示面板，本申请提供的显示面板中驱动芯片设置于显示区边缘与非显示区边缘之间的空间内，增加了驱动芯片与显示区边缘及非显示区边缘之间的距离，避免了高屏占比显示屏非显示区面积被压缩导致的驱动芯片距离显示区和基板边缘过近，产生的驱动芯片压合后电性不良及液晶成盒密封不良的技术缺陷；同时，柔性电路板的弯折区段位于凸块两侧的凹陷部内，弯折区段的弯折半径不超出凸块边缘，因此不会增加非显示区宽度，保持显示设备的屏占比，缓解了现有显示面板存在的不能满足全面屏发展趋势的技术问题。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种显示面板，其包括阵列基板、驱动芯片以及柔性电路板，所述阵列基板包括显示区以及非显示区，所述驱动芯片以及柔性电路板绑定在所述非显示区的一侧；
    所述非显示区远离所述显示区的一侧形成有至少两个凸块，相邻凸块之间形成凹陷部；
    其中，所述柔性电路板的部分区段经所述凹陷部边缘弯折至所述阵列基板的背部，所述驱动芯片位于所述非显示区边缘与所述显示区边缘之间。
  2. 根据权利要求1所述的显示面板，其中，所述凸块包括至少一个第一凸块、以及至少一个第二凸块，所述驱动芯片位于所述第一凸块的边缘与所述显示区的边缘之间。
  3. 根据权利要求2所述的显示面板，其中，所述驱动芯片位于所述第一凸块之外；或者，所述驱动芯片完全或部分设置于所述第一凸块内。
  4. 根据权利要求1所述的显示面板，其中，所述凸块的形状包括矩形、梯形、圆弧形、三角形中的一种或几种。
  5. 根据权利要求1所述的显示面板，其中，所述阵列基板内设置有GOA走线，所述GOA走线包括位于所述非显示区内且指向所述驱动芯片的倾斜段，所述GOA走线的倾斜段连接所述驱动芯片；所述非显示区内设置有多个用以连接所述柔性电路板的信号端子组。
  6. 根据权利要求5所述的显示面板，其中，所述信号端子组包括主信号端子组和次信号端子组，所述主信号端子组位于所述次信号端子组和所述驱动芯片之间。
  7. 根据权利要求6所述的显示面板，其中，所述次信号端子组与所述主信号端子组之间分离设置，且所述主信号端子完全或部分位于所述第一凸块内，所述次信号端子位于所述第一凸块之外。
  8. 根据权利要求7所述的显示面板，其中，所述柔性电路板包括主体区段以及用连接区段，所述连接区段包括对应连接所述主信号端子组的第一区块、以及对应连接所述次信号端子组的第二区块，所述第一区块与所述第二区块错位设置。
  9. 根据权利要求6所述的显示面板，其中，所述信号端子组还包括虚拟端子组，所述虚拟端子组位于所述次信号端子组远离所述驱动芯片和所述GOA走线的倾斜段的一侧。
  10. 根据权利要求1所述的显示面板，其中，所述非显示区内还设置有测试端子组、转换端子组和识别端子组，所述测试端子组、转换端子组和识别端子组中的至少一种位于所述第二凸块的边缘与所述显示区的边缘之间。
  11. 根据权利要求10所述的显示面板，其中，所述测试端子组、转换端子组和识别端子组设置在至少两行。
  12. 一种显示装置，其包括显示面板，所述显示面板包括阵列基板、驱动芯片以及柔性电路板，所述阵列基板包括显示区以及非显示区，所述驱动芯片以及柔性电路板绑定在所述非显示区的一侧；
    所述非显示区远离所述显示区的一侧形成有至少两个凸块，相邻凸块之间形成凹陷部；
    其中，所述柔性电路板的部分区段经所述凹陷部边缘弯折至所述阵列基板的背部，所述驱动芯片位于所述非显示区边缘与所述显示区边缘之间。
  13. 根据权利要求12所述的显示装置，其中，所述凸块包括至少一个第一凸块、以及至少一个第二凸块，所述驱动芯片位于所述第一凸块的边缘与所述显示区的边缘之间。
  14. 根据权利要求13所述的显示装置，其中，所述驱动芯片位于所述第一凸块之外；或者，所述驱动芯片完全或部分设置于所述第一凸块内。
  15. 根据权利要求12所述的显示装置，其中，所述凸块的形状包括矩形、梯形、圆弧形、三角形中的一种或几种。
  16. 根据权利要求12所述的显示装置，其中，所述阵列基板内设置有GOA走线，所述GOA走线包括位于所述非显示区内且指向所述驱动芯片的倾斜段，所述GOA走线的倾斜段连接所述驱动芯片；所述非显示区内设置有多个用以连接所述柔性电路板的信号端子组。
  17. 根据权利要求16所述的显示装置，其中，所述信号端子组包括主信号端子组和次信号端子组，所述主信号端子组位于所述次信号端子组和所述驱动芯片之间。
  18. 根据权利要求17所述的显示装置，其中，所述次信号端子组与所述主信号端子组之间分离设置，且所述主信号端子完全或部分位于所述第一凸块内，所述次信号端子位于所述第一凸块之外。
  19. 根据权利要求18所述的显示装置，其中，所述柔性电路板包括主体区段以及用连接区段，所述连接区段包括对应连接所述主信号端子组的第一区块、以及对应连接所述次信号端子组的第二区块，所述第一区块与所述第二区块错位设置。
  20. 根据权利要求17所述的显示装置，其中，所述信号端子组还包括虚拟端子组，所述虚拟端子组位于所述次信号端子组远离所述驱动芯片和所述GOA走线的倾斜段的一侧。
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