WO2020206792A1 - Goa电路及显示面板 - Google Patents

Goa电路及显示面板 Download PDF

Info

Publication number
WO2020206792A1
WO2020206792A1 PCT/CN2019/086230 CN2019086230W WO2020206792A1 WO 2020206792 A1 WO2020206792 A1 WO 2020206792A1 CN 2019086230 W CN2019086230 W CN 2019086230W WO 2020206792 A1 WO2020206792 A1 WO 2020206792A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
electrically connected
signal
node
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/086230
Other languages
English (en)
French (fr)
Inventor
张留旗
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US16/980,907 priority Critical patent/US11138939B2/en
Publication of WO2020206792A1 publication Critical patent/WO2020206792A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Program-control systems
    • G05B19/02—Program-control systems electric
    • G05B19/04—Program control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Program control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0423—Input/output
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/21—Pc I-O input output
    • G05B2219/21119—Circuit for signal adaption, voltage level shift, filter noise
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Definitions

  • This application relates to the field of display technology, in particular to a GOA circuit and a display panel.
  • GOA full name in English: Gate Driver on Array, full name in Chinese: integrated gate drive circuit
  • GOA full name in English: Gate Driver on Array, full name in Chinese: integrated gate drive circuit
  • the signal output by the GOA circuit requires two pulse waveforms: one is a positive pulse waveform, which can be generated by a conventional GOA circuit; the other is a negative pulse waveform.
  • the existing GOA circuit generates a negative pulse waveform signal, and its circuit design is relatively complicated.
  • the purpose of the embodiments of the present application is to provide a GOA circuit and a display panel, which can solve the technical problem that the existing GOA circuit generates a negative pulse waveform signal and its circuit design is relatively complicated.
  • An embodiment of the present application provides a GOA circuit, including: multi-level cascaded GOA units, each level of GOA unit includes: multi-level cascaded GOA units, each level of GOA unit includes: input module, first output Module, second output module, pull-down module, inverting module, sustaining module and bootstrap capacitor;
  • the input module is connected to the first clock signal and the upper level transmission signal, and is electrically connected to the first node and the second node, and is used to transfer the upper level to the upper level under the control of the first clock signal. Output the signal to the first node;
  • the first output module is connected to a second clock signal and is electrically connected to the first node for outputting a transmission signal of the current stage under the control of the potential of the first node;
  • the second output module is connected to a third reference low-level signal and is electrically connected to the first node for outputting a scan signal of the current level under the control of the potential of the first node;
  • the pull-down module is connected to the next level transmission signal, the first reference low level signal, and the second reference low level signal, and is electrically connected to the first node and the current level transmission signal for Under the control of the next-level transmission signal, the potential of the first node is pulled down to the potential of the first reference low-level signal, and the potential of the current-level transmission signal is pulled down to the The potential of the second reference low-level signal;
  • the inverting module is connected to the reference high-level signal and the first reference low-level signal, and is electrically connected to the third node and the first node, and is configured to respond to the reference high-level signal and the first node.
  • the first reference low level signal and the potential of the first node control the potential of the third node;
  • the maintenance module accesses the first reference low level signal, the reference high level signal, and the second reference low level signal, and is electrically connected to the first node and the third node ,
  • the current-level transmission signal and the current-level scanning signal are used to maintain the potential of the first node and the current-level transmission signal under the control of the potential of the third node.
  • One end of the bootstrap capacitor is electrically connected to the first node, and the other end of the bootstrap capacitor is electrically connected to the current stage for signal transmission;
  • the transmission signal of the current level is a positive pulse signal
  • the scanning signal of the current level is a negative pulse signal
  • the GOA circuit further includes: a seventeenth transistor, an eighteenth transistor, and a nineteenth transistor;
  • the gate of the seventeenth transistor is electrically connected to the current level transmitting signal
  • the drain of the seventeenth transistor is electrically connected to the second node
  • the source of the seventeenth transistor is The drain of the eighteenth transistor and the drain of the nineteenth transistor are electrically connected
  • the gate of the eighteenth transistor is electrically connected to the first node
  • the source of the eighteenth transistor The electrode is electrically connected to the second clock signal
  • the gate of the nineteenth transistor is electrically connected to the third node
  • the source of the nineteenth transistor is electrically connected to the second reference low Level signal
  • the potential of the first reference low level signal is less than the potential of the second reference low level signal, and the potential of the second reference level signal is equal to the potential of the third reference low level signal.
  • the input module includes: a second transistor and a third transistor;
  • the gate of the second transistor and the gate of the third transistor are both electrically connected to the first clock signal, and the source of the second transistor is electrically connected to the upper-level transmission signal,
  • the drain of the second transistor and the source of the third transistor are both electrically connected to the second node, and the drain of the third transistor is electrically connected to the first node.
  • the first output module includes: a fourth transistor
  • the gate of the fourth transistor is electrically connected to the first node, the source of the fourth transistor is electrically connected to the second clock signal, and the drain of the fourth transistor is electrically connected to the Describe the transmission signal at this level.
  • the second output module includes: a fifth transistor
  • the gate of the fifth transistor is electrically connected to the first node, the source of the fifth transistor is electrically connected to the third reference low level signal, and the drain of the fifth transistor is electrically connected Connect to the scan signal of the current level.
  • the pull-down module includes: a sixth transistor, a seventh transistor, and an eighth transistor;
  • the gate of the sixth transistor, the gate of the seventh transistor, and the gate of the eighth transistor are all electrically connected to the next-stage transmission signal, and the source of the sixth transistor is electrically connected Connected to the second reference low level signal, the drain of the sixth transistor is electrically connected to the current-level transmission signal, and the drain of the seventh transistor is electrically connected to the first node, The source of the seventh transistor is electrically connected to the drain of the eighth transistor, and the source of the eighth transistor is electrically connected to the first reference low level signal.
  • the inverter module includes: a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor;
  • the gate and source of the ninth transistor and the source of the eleventh transistor are all electrically connected to the reference high-level signal, and the drain of the ninth transistor and the source of the eleventh transistor are The gate and the drain of the tenth transistor are electrically connected, the drain of the eleventh transistor and the drain of the twelfth transistor are both electrically connected to the third node, and the tenth transistor The gate of the twelfth transistor and the gate of the twelfth transistor are both electrically connected to the first node, and the source of the tenth transistor and the source of the twelfth transistor are both electrically connected to the first node. A reference low-level signal.
  • the sustain module includes: a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor;
  • the gate of the thirteenth transistor, the gate of the fourteenth transistor, the gate of the fifteenth transistor, and the gate of the sixteenth transistor are all electrically connected to the third node,
  • the source of the thirteenth transistor is electrically connected to the reference high level signal
  • the drain of the thirteenth transistor is electrically connected to the scan signal of the current stage
  • the source of the fourteenth transistor Is electrically connected to the second reference low level signal
  • the drain of the fourteenth transistor is electrically connected to the current-level transmission signal
  • the drain of the sixteenth transistor is electrically connected to the fifteenth
  • the source of the transistor is electrically connected
  • the drain of the fifteenth transistor is electrically connected to the first node
  • the source of the sixteenth transistor is electrically connected to the first reference low level signal.
  • An embodiment of the present application also provides a GOA circuit, including: multi-level cascaded GOA units, each level of GOA unit includes: multi-level cascaded GOA units, each level of GOA unit includes: input module, first Output module, second output module, pull-down module, inverting module, sustaining module and bootstrap capacitor;
  • the input module is connected to the first clock signal and the upper level transmission signal, and is electrically connected to the first node and the second node, and is used to transfer the upper level to the upper level under the control of the first clock signal. Output the signal to the first node;
  • the first output module is connected to a second clock signal and is electrically connected to the first node for outputting a transmission signal of the current stage under the control of the potential of the first node;
  • the second output module is connected to a third reference low-level signal and is electrically connected to the first node for outputting a scan signal of the current level under the control of the potential of the first node;
  • the pull-down module is connected to the next level transmission signal, the first reference low level signal, and the second reference low level signal, and is electrically connected to the first node and the current level transmission signal for Under the control of the next-level transmission signal, the potential of the first node is pulled down to the potential of the first reference low-level signal, and the potential of the current-level transmission signal is pulled down to the The potential of the second reference low-level signal;
  • the inverting module is connected to the reference high-level signal and the first reference low-level signal, and is electrically connected to the third node and the first node, and is configured to respond to the reference high-level signal and the first node.
  • the first reference low level signal and the potential of the first node control the potential of the third node;
  • the maintenance module accesses the first reference low level signal, the reference high level signal, and the second reference low level signal, and is electrically connected to the first node and the third node ,
  • the current-level transmission signal and the current-level scanning signal are used to maintain the potential of the first node and the current-level transmission signal under the control of the potential of the third node.
  • One end of the bootstrap capacitor is electrically connected to the first node, and the other end of the bootstrap capacitor is electrically connected to the current stage for signal transmission;
  • the transmission signal of the current level is a positive pulse signal
  • the scanning signal of the current level is a negative pulse signal
  • the input module includes: a second transistor and a third transistor;
  • the gate of the second transistor and the gate of the third transistor are both electrically connected to the first clock signal, and the source of the second transistor is electrically connected to the upper-level transmission signal,
  • the drain of the second transistor and the source of the third transistor are both electrically connected to the second node, and the drain of the third transistor is electrically connected to the first node.
  • the first output module includes: a fourth transistor
  • the gate of the fourth transistor is electrically connected to the first node, the source of the fourth transistor is electrically connected to the second clock signal, and the drain of the fourth transistor is electrically connected to the Describe the transmission signal at this level.
  • the second output module includes: a fifth transistor
  • the gate of the fifth transistor is electrically connected to the first node, the source of the fifth transistor is electrically connected to the third reference low level signal, and the drain of the fifth transistor is electrically connected Connect to the scan signal of the current level.
  • the pull-down module includes: a sixth transistor, a seventh transistor, and an eighth transistor;
  • the gate of the sixth transistor, the gate of the seventh transistor, and the gate of the eighth transistor are all electrically connected to the next-stage transmission signal, and the source of the sixth transistor is electrically connected Connected to the second reference low level signal, the drain of the sixth transistor is electrically connected to the current-level transmission signal, and the drain of the seventh transistor is electrically connected to the first node, The source of the seventh transistor is electrically connected to the drain of the eighth transistor, and the source of the eighth transistor is electrically connected to the first reference low level signal.
  • the inverter module includes: a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor;
  • the gate and source of the ninth transistor and the source of the eleventh transistor are all electrically connected to the reference high-level signal, and the drain of the ninth transistor and the source of the eleventh transistor are The gate and the drain of the tenth transistor are electrically connected, the drain of the eleventh transistor and the drain of the twelfth transistor are both electrically connected to the third node, and the tenth transistor The gate of the twelfth transistor and the gate of the twelfth transistor are both electrically connected to the first node, and the source of the tenth transistor and the source of the twelfth transistor are both electrically connected to the first node. A reference low-level signal.
  • the sustain module includes: a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor;
  • the gate of the thirteenth transistor, the gate of the fourteenth transistor, the gate of the fifteenth transistor, and the gate of the sixteenth transistor are all electrically connected to the third node,
  • the source of the thirteenth transistor is electrically connected to the reference high level signal
  • the drain of the thirteenth transistor is electrically connected to the scan signal of the current stage
  • the source of the fourteenth transistor Is electrically connected to the second reference low level signal
  • the drain of the fourteenth transistor is electrically connected to the current-level transmission signal
  • the drain of the sixteenth transistor is electrically connected to the fifteenth
  • the source of the transistor is electrically connected
  • the drain of the fifteenth transistor is electrically connected to the first node
  • the source of the sixteenth transistor is electrically connected to the first reference low level signal.
  • the GOA circuit further includes: a seventeenth transistor, an eighteenth transistor, and a nineteenth transistor;
  • the gate of the seventeenth transistor is electrically connected to the current level transmitting signal
  • the drain of the seventeenth transistor is electrically connected to the second node
  • the source of the seventeenth transistor is The drain of the eighteenth transistor and the drain of the nineteenth transistor are electrically connected, the gate of the eighteenth transistor is electrically connected to the first node, and the source of the eighteenth transistor
  • the electrode is electrically connected to the second clock signal
  • the gate of the nineteenth transistor is electrically connected to the third node
  • the source of the nineteenth transistor is electrically connected to the second reference low Level signal.
  • the potential of the first reference low-level signal is less than the potential of the second reference low-level signal, and the potential of the second reference-level signal is equal to the third Refer to the potential of the low level signal.
  • An embodiment of the present application also provides a display panel, which transmits signals at the first node, the third node, the current level, and the current level scan signal, which is used for potential control at the third node Next, maintaining the potential of the first node and the potential of the current-level transmission signal at the potential of the first reference low-level signal, and maintaining the potential of the current-level scanning signal at the reference high The potential of the level signal;
  • One end of the bootstrap capacitor is electrically connected to the first node, and the other end of the bootstrap capacitor is electrically connected to the current stage for signal transmission;
  • the transmission signal of the current level is a positive pulse signal
  • the scanning signal of the current level is a negative pulse signal
  • the input module includes: a second transistor and a third transistor;
  • the gate of the second transistor and the gate of the third transistor are both electrically connected to the first clock signal, and the source of the second transistor is electrically connected to the upper-level transmission signal,
  • the drain of the second transistor and the source of the third transistor are both electrically connected to the second node, and the drain of the third transistor is electrically connected to the first node.
  • the first output module includes: a fourth transistor
  • the gate of the fourth transistor is electrically connected to the first node, the source of the fourth transistor is electrically connected to the second clock signal, and the drain of the fourth transistor is electrically connected to the Describe the transmission signal at this level.
  • the second output module includes: a fifth transistor
  • the gate of the fifth transistor is electrically connected to the first node, the source of the fifth transistor is electrically connected to the third reference low level signal, and the drain of the fifth transistor is electrically connected Connect to the scan signal of the current level.
  • the GOA circuit and display panel provided by the embodiments of the present application adopt a relatively simple circuit design and can simultaneously output a positive pulse waveform signal and a negative pulse waveform signal.
  • FIG. 1 is a schematic structural diagram of a GOA circuit provided by an embodiment of the application.
  • FIG. 2 is a schematic diagram of the first circuit of a GOA unit in the GOA circuit provided by the embodiment of the application;
  • FIG. 3 is a signal timing diagram of a GOA unit in the GOA circuit provided by an embodiment of the application;
  • FIG. 4 is a schematic diagram of a second circuit of a GOA unit in the GOA circuit provided by the embodiment of the application.
  • FIG. 5 is a schematic structural diagram of a display panel provided by an embodiment of the application.
  • the transistors used in all the embodiments of this application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistor used here are symmetrical, the source and drain can be interchanged of. In the embodiments of the present application, in order to distinguish the two poles of the transistor except the gate, one of the poles is called the source and the other is called the drain. According to the form in the figure, it is stipulated that the middle end of the switching transistor is the gate, the signal input end is the source, and the output end is the drain. In addition, the transistors used in the embodiments of the present application are all N-type transistors, where the N-type transistor is turned on when the gate is at a high level, and turned off when the gate is at a low level.
  • FIG. 1 is a schematic structural diagram of a GOA circuit provided by an embodiment of the application.
  • the GOA circuit 10 provided by the embodiment of the present application includes multi-stage cascaded GOA units 20.
  • Each GOA unit 20 is used to output a negative pulse waveform scanning signal and a negative pulse waveform grade transmission signal.
  • the first-level GOA unit 20 is connected to the start signal STV, and then the second-level GOA unit 20, the third-level GOA unit 20, ..., the last-level GOA unit 20 are sequentially Pass start.
  • the n-1 level GOA unit When the n-1 level GOA unit is working, the n-1 level GOA unit outputs a negative pulse waveform scanning signal and a negative pulse waveform grade transmission signal, which are used to control the light-emitting diodes in the light-emitting diode display panel. Subsequently, the stage transmission signal of the n-1th stage GOA unit activates the nth stage GOA unit, and the nth stage GOA unit outputs a scanning signal with a negative pulse waveform and a stage transmission signal with a negative pulse waveform. Finally, the stage transmission signal of the nth stage GOA unit activates the n+1 stage GOA unit, and the n+1 stage GOA unit outputs a scanning signal with a negative pulse waveform and a stage transmission signal with a negative pulse waveform.
  • FIG. 2 is a schematic diagram of a first circuit of a GOA unit in the GOA circuit provided by an embodiment of the application.
  • the GOA circuit includes: an input module 101, a first output module 102, a second output module 103, a pull-down module 104, an inverter module 105, a sustain module 106, and a bootstrap capacitor Cb.
  • the input module 101 accesses the first clock signal CLK and the upper level transmission signal Gout(n-1), and is electrically connected to the first node Q(n) and the second node L(n) for Under the control of the first clock signal CLK, the upper stage transmission signal Gout(n-1) is output to the first node Q(n).
  • the first output module 102 is connected to the second clock signal CK, and is electrically connected to the first node Q(n), for outputting the current-level transmission signal Cout( n).
  • the second output module 103 is connected to the third reference low level signal VGL3, and is electrically connected to the first node Q(n), for outputting the current level scanning signal under the control of the potential of the first node Q(n) G(n).
  • the pull-down module 104 is connected to the next level transmission signal Cout(n+1), the first reference low level signal VGL1 and the second reference low level signal VGL2, and is electrically connected to the first node Q(n) And the current level transmission signal Cout(n), which is used to pull down the potential of the first node Q(n) to the first reference low level signal VGL1 under the control of the next level transmission signal Cout(n+1) And pull down the potential of the transmission signal Cout(n) of the current stage to the potential of the second reference low level signal VGL2.
  • the inverting module 105 is connected to the reference high level signal VGH and the first reference low level signal VGL1, and is electrically connected to the third node K(n) and the first node Q(n), and is used for according to the reference high The level signal VGH, the first reference low level signal VGL1, and the potential of the first node Q(n) control the potential of the third node K(n).
  • the maintenance module 106 accesses the first reference low level signal VGL1, the reference high level signal VGH, and the second reference low level signal VGL2, and is electrically connected to the first node Q(n) and the third node K( n), the transmission signal Cout(n) of this level and the scanning signal G(n) of this level are used to control the potential of the first node Q(n) and the level of the third node K(n).
  • the potential of the level transfer signal Cout(n) is maintained at the potential of the first reference low level signal VGL1, and the potential of the current level scanning signal G(n) is maintained at the potential of the reference high level signal VGH.
  • One end of the bootstrap capacitor Cb is electrically connected to the first node Q(n), and the other end of the bootstrap capacitor Cb is electrically connected to the transmission signal Cout(n) of the current stage.
  • the input module 101 includes: a second transistor T2 and a third transistor T3; the gate of the second transistor T2 and the gate of the third transistor T3 are both electrically connected to the first clock signal CLK, and the second transistor
  • the source of T2 is electrically connected to the upper level transmission signal Cout(n-1)
  • the drain of the second transistor T2 and the source of the third transistor T3 are both electrically connected to the second node L(n)
  • the drain of the three transistor T3 is electrically connected to the first node Q(n).
  • the first output module 102 includes: a fourth transistor T4; the gate of the fourth transistor T4 is electrically connected to the first node Q(n), and the source of the fourth transistor T4 is electrically connected to the second node. With the clock signal CK, the drain of the fourth transistor T4 is electrically connected to the transmission signal Cout(n) of the current stage.
  • the second output module 103 includes: a fifth transistor T5; the gate of the fifth transistor T5 is electrically connected to the first node Q(n), and the source of the fifth transistor T5 is electrically connected to the third node. With reference to the low-level signal VGL3, the drain of the fifth transistor T5 is electrically connected to the scan signal G(n) of the current level.
  • the pull-down module 104 includes: a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8; the gate of the sixth transistor T6, the gate of the seventh transistor T7, and the gate of the eighth transistor T8 are all
  • the source of the sixth transistor T6 is electrically connected to the second reference low-level signal VGL2, and the drain of the sixth transistor T6 is electrically connected to the current stage.
  • the level transmission signal Cout(n) the drain of the seventh transistor T7 is electrically connected to the first node Q(n), the source of the seventh transistor T7 is electrically connected to the drain of the eighth transistor T8, and the eighth transistor T8 The source of is electrically connected to the first reference low level signal VGL1.
  • the inverting module 105 includes: a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, and a twelfth transistor T12; the gate and source of the ninth transistor T9, and the eleventh transistor T11
  • the sources of the ninth transistor T9, the gate of the eleventh transistor T11, and the drain of the tenth transistor T10 are electrically connected to the reference high-level signal VGH
  • the drain of the eleventh transistor T11 is electrically connected
  • Both the electrode and the drain of the twelfth transistor T12 are electrically connected to the third node K(n)
  • the gate of the tenth transistor T10 and the gate of the twelfth transistor T12 are both electrically connected to the first node Q(n)
  • the source of the tenth transistor T10 and the source of the twelfth transistor T12 are electrically connected to the first reference low level signal VGL1.
  • the maintenance module 106 includes: a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, and a sixteenth transistor T16; the gate of the thirteenth transistor T13 and the gate of the fourteenth transistor T14 The gate, the gate of the fifteenth transistor T15 and the gate of the sixteenth transistor T16 are all electrically connected to the third node K(n), and the source of the thirteenth transistor T13 is electrically connected to the reference high level signal VGH, the drain of the thirteenth transistor T13 is electrically connected to the scan signal G(n) of this stage, the source of the fourteenth transistor T14 is electrically connected to the second reference low level signal VGL2, and the source of the fourteenth transistor T14 The drain is electrically connected to the transmission signal Cout(n) of the current stage, the drain of the sixteenth transistor T16 is electrically connected to the source of the fifteenth transistor T15, and the drain of the fifteenth transistor T15 is electrically connected to the A node Q(n).
  • the potential of the first reference low level signal VGL1 is less than the potential of the second reference low level signal VGL2, and the potential of the second reference level signal VGL2 is equal to the potential of the third reference low level signal VGL3.
  • the current level transmission signal of the GOA circuit provided by the embodiment of the present application is a positive pulse signal
  • the current level scan signal is a negative pulse signal. That is, the GOA provided by the embodiment of the present application can simultaneously output a positive pulse waveform signal and a negative pulse waveform signal.
  • FIG. 3 is a signal timing diagram of a GOA circuit in the GOA circuit provided by the embodiment of the application.
  • the period of the first clock signal CLK is the same as the period of the second clock signal CK, and the polarity of the first clock signal CLK is opposite to the polarity of the second clock signal CK.
  • the potential of the first reference low level signal VGL1 is less than the potential of the second reference low level signal VGL2.
  • the first clock signal CLK is at a high potential, and the second transistor T2 and the third transistor T3 are turned on at this time.
  • the upper stage transmission signal Gout(n -1) At this time, it is a high potential, so that the potential of the first node Q(n) is raised, and the fourth transistor T4 and the fifth transistor T5 are turned on; at this time, because the second clock signal CK is at a low potential, the current level
  • the transmission signal Cout(n) is a low potential; the potential of the scan signal G(n) of this level is equal to the potential of the third reference low level signal VGL3, that is, the scan signal G(n) of this level is a low potential.
  • the first clock signal CLK is at a low potential
  • the first transistor T1, the second transistor T2, and the third transistor T3 are turned off at this time, and the potential of the first node Q(n) continues to be maintained at a high potential.
  • the fourth transistor T4 and the fifth transistor T5 are still on.
  • the second clock signal CK is at a high potential. Therefore, the transmission signal Cout(n) of the current stage is at a high potential, and the potential of the scan signal G(n) of the current stage is still equal to the potential of the third reference low level signal VGL3. That is, the scanning signal G(n) of this stage is at a low level.
  • the transmission signal Cout(n) of the current stage is at a high potential, under the action of the bootstrap capacitor Cb, the potential of the first node Q(n) is further raised to ensure that the fourth transistor T4 and the first The five transistor T5 is turned on and the transmission signal Cout(n) of this stage is a high potential signal, and the scanning signal G(n) of this stage is a low potential.
  • the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned on, and the first node Q(n ) Is connected to the first reference low level signal VGL1, and the current stage transmission signal Cout(n) is connected to the second reference low level signal VGL2. That is, at this time, the potential of the transmission signal Cout(n) of the current stage is pulled down to the potential of the second reference low level signal VGL2, and the potential of the first node Q(n) is pulled down to the first reference low level signal The potential of VGL1.
  • the potential of the first node Q(n) is low, the tenth transistor T10 and the twelfth transistor T12 are turned off, and the high potential of the reference high-level signal VGH is output to the second node L(n) , So that the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, and the sixteenth transistor T16 are turned on, and the potential of the first node Q(n) is maintained at the potential of the first reference low level signal VGL1,
  • the potential of the transmission signal Cout(n) of the current stage is maintained at the potential of the second reference low level signal VGL2, and the potential of the scan signal G(n) of the current stage is maintained at the potential of the reference high level signal VGH.
  • FIG. 4 is a schematic diagram of a second type of circuit of a GOA unit in the GOA circuit provided by an embodiment of the application.
  • the difference between the circuit shown in FIG. 4 and the circuit shown in FIG. 2 is that the GOA circuit shown in FIG. 4 also includes: a seventeenth transistor T17, an eighteenth transistor T18, and a nineteenth transistor T19.
  • the gate of the seventeenth transistor T17 is electrically connected to the level transmission signal Cout(n)
  • the drain of the seventeenth transistor T17 is electrically connected to the second node L(n)
  • the The source, the drain of the eighteenth transistor T18, and the drain of the nineteenth transistor T19 are electrically connected.
  • the gate of the eighteenth transistor T18 is electrically connected to the first node Q(n).
  • the source is electrically connected to the second clock signal CK
  • the gate of the nineteenth transistor T19 is electrically connected to the third node K(n)
  • the source of the nineteenth transistor T19 is electrically connected to the second reference low level Signal VGL2.
  • a seventeenth transistor T17, an eighteenth transistor T18, and a nineteenth transistor T19 are added to expand the functions of the GOA circuit and make the GOA circuit more secure and stable.
  • FIG. 5 is a schematic structural diagram of a display panel provided by an embodiment of the application.
  • the display panel includes a display area 100 and a GOA circuit 200 integratedly arranged on the edge of the display area 100; wherein the structure and principle of the GOA circuit 200 are similar to the GOA circuit described above, and will not be repeated here.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种GOA电路（10）及显示面板，GOA电路（10）包括：多级级联的GOA单元（20），每一级GOA单元（20）均包括：输入模块（101）、第一输出模块（102）、第二输出模块（103）、下拉模块（104）、反相模块（105）、维持模块（106）以及自举电容（Cb）。本发明提供的GOA电路（10）及显示面板采用较为简单的电路设计可同时输出正脉冲波形信号和负脉冲波形信号。

Description

GOA电路及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种GOA电路及显示面板。
 背景技术
GOA( 英文全称：Gate Driver on Array ，中文全称：集成栅极驱动电路)技术将栅极驱动电路集成在显示面板的阵列基板上，从而可以省掉栅极驱动集成电路部分，以从材料成本和制作工艺两方面降低产品成本。
在有机发光二极管显示面板中，GOA电路输出的信号需要两种脉冲波形：一种为正脉冲波形，该波形可以使用常规的GOA电路产生；另一种为负脉冲波形。然而，现有的GOA电路为生成负脉冲波形的信号，其电路设计较为复杂。
 技术问题
本申请实施例的目的在于提供一种GOA电路及显示面板，能够解决现有的GOA电路为生成负脉冲波形的信号，其电路设计较为复杂的技术问题。
 技术解决方案
本申请实施例提供一种GOA电路，包括：多级级联的GOA单元，每一级GOA单元均包括：多级级联的GOA单元，每一级GOA单元均包括：输入模块、第一输出模块、第二输出模块、下拉模块、反相模块、维持模块以及自举电容；
所述输入模块接入第一时钟信号以及上一级级传信号，并电性连接于第一节点以及第二节点，用于在所述第一时钟信号的控制下将所述上一级级传信号输出至所述第一节点；
所述第一输出模块接入第二时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级级传信号；
所述第二输出模块接入第三参考低电平信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级扫描信号；
所述下拉模块接入下一级级传信号、第一参考低电平信号以及第二参考低电平信号，并电性连接于所述第一节点以及所述本级级传信号，用于在所述下一级级传信号的控制下，将所述第一节点的电位下拉至所述第一参考低电平信号的电位，以及将所述本级级传信号的电位下拉至所述第二参考低电平信号的电位；
所述反相模块接入参考高电平信号以及所述第一参考低电平信号，并电性连接于第三节点以及所述第一节点，用于根据所述参考高电平信号、所述第一参考低电平信号以及所述第一节点的电位控制所述第三节点的电位；
所述维持模块接入所述第一参考低电平信号、所述参考高电平信号以及所述第二参考低电平信号，并电性连接于所述第一节点、所述第三节点、所述本级级传信号以及所述本级扫描信号，用于在所述第三节点的电位控制下，将所述第一节点的电位以及所述本级级传信号的电位维持在所述第一参考低电平信号的电位，以及将所述本级扫描信号的电位维持在所述参考高电平信号的电位；
所述自举电容的一端电性连接于所述第一节点，所述自举电容的另一端电性连接于所述本级级传信号；
其中，所述本级级传信号为正脉冲信号，所述本级扫描信号为负脉冲信号；
所述GOA电路还包括：第十七晶体管、第十八晶体管以及第十九晶体管；
所述第十七晶体管的栅极电性连接于所述本级级传信号，所述第十七晶体管的漏极电性连接于所述第二节点，所述第十七晶体管的源极、所述第十八晶体管的漏极以及所述第十九晶体管的漏极电性连接，所述第十八晶体管的栅极电性连接于所述第一节点，所述第十八晶体管的源极电性连接于所述第二时钟信号，所述第十九晶体管的栅极电性连接于所述第三节点，所述第十九晶体管的源极电性连接于所述第二参考低电平信号；
所述第一参考低电平信号的电位小于所述第二参考低电平信号的电位，且所述第二参考电平信号的电位等于所述第三参考低电平信号的电位。
在本申请所述的GOA电路中，所述输入模块包括：第二晶体管以及第三晶体管；
所述第二晶体管的栅极以及所述第三晶体管的栅极均电性连接于所述第一时钟信号，所述第二晶体管的源极电性连接于所述上一级级传信号，所述第二晶体管的漏极与所述第三晶体管的源极均与所述第二节点电性连接，所述第三晶体管的漏极电性连接于所述第一节点。
在本申请所述的GOA电路中，所述第一输出模块包括：第四晶体管；
所述第四晶体管的栅极电性连接于所述第一节点，所述第四晶体管的源极电性连接于所述第二时钟信号，所述第四晶体管的漏极电性连接于所述本级级传信号。
在本申请所述的GOA电路中，所述第二输出模块包括：第五晶体管；
所述第五晶体管的栅极电性连接于所述第一节点，所述第五晶体管的源极电性连接于所述第三参考低电平信号，所述第五晶体管的漏极电性连接于所述本级扫描信号。
在本申请所述的GOA电路中，所述下拉模块包括：第六晶体管、第七晶体管以及第八晶体管；
所述第六晶体管的栅极、所述第七晶体管的栅极以及所述第八晶体管的栅极均电性连接于所述下一级级传信号，所述第六晶体管的源极电性连接于所述第二参考低电平信号，所述第六晶体管的漏极电性连接于所述本级级传信号，所述第七晶体管的漏极电性连接于所述第一节点，所述第七晶体管的源极与所述第八晶体管的漏极电性连接，所述第八晶体管的源极电性连接于所述第一参考低电平信号。
在本申请所述的GOA电路中，所述反相模块包括：第九晶体管、第十晶体管、第十一晶体管以及第十二晶体管；
所述第九晶体管的栅极、源极以及所述第十一晶体管的源极均电性连接于所述参考高电平信号，所述第九晶体管的漏极、所述第十一晶体管的栅极以及所述第十晶体管的漏极电性连接，所述第十一晶体管的漏极以及所述第十二晶体管的漏极均电性连接于所述第三节点，所述第十晶体管的栅极以及所述第十二晶体管的栅极均电性连接于所述第一节点，所述第十晶体管的源极以及所述第十二晶体管的源极均电性连接于所述第一参考低电平信号。
在本申请所述的GOA电路中，所述维持模块包括：第十三晶体管、第十四晶体管、第十五晶体管以及第十六晶体管；
所述第十三晶体管的栅极、所述第十四晶体管的栅极、所述第十五晶体管的栅极以及所述第十六晶体管的栅极均电性连接于所述第三节点，所述第十三晶体管的源极电性连接于所述参考高电平信号，所述第十三晶体管的漏极电性连接于所述本级扫描信号，所述第十四晶体管的源极电性连接于所述第二参考低电平信号，所述第十四晶体管的漏极电性连接于所述本级级传信号，所述第十六晶体管的漏极与所述第十五晶体管的源极电性连接，所述第十五晶体管的漏极电性连接于所述第一节点，所述第十六晶体管的源极电性连接于所述第一参考低电平信号。
本申请实施例还提供一种GOA电路，包括：多级级联的GOA单元，每一级GOA单元均包括：多级级联的GOA单元，每一级GOA单元均包括：输入模块、第一输出模块、第二输出模块、下拉模块、反相模块、维持模块以及自举电容；
所述输入模块接入第一时钟信号以及上一级级传信号，并电性连接于第一节点以及第二节点，用于在所述第一时钟信号的控制下将所述上一级级传信号输出至所述第一节点；
所述第一输出模块接入第二时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级级传信号；
所述第二输出模块接入第三参考低电平信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级扫描信号；
所述下拉模块接入下一级级传信号、第一参考低电平信号以及第二参考低电平信号，并电性连接于所述第一节点以及所述本级级传信号，用于在所述下一级级传信号的控制下，将所述第一节点的电位下拉至所述第一参考低电平信号的电位，以及将所述本级级传信号的电位下拉至所述第二参考低电平信号的电位；
所述反相模块接入参考高电平信号以及所述第一参考低电平信号，并电性连接于第三节点以及所述第一节点，用于根据所述参考高电平信号、所述第一参考低电平信号以及所述第一节点的电位控制所述第三节点的电位；
所述维持模块接入所述第一参考低电平信号、所述参考高电平信号以及所述第二参考低电平信号，并电性连接于所述第一节点、所述第三节点、所述本级级传信号以及所述本级扫描信号，用于在所述第三节点的电位控制下，将所述第一节点的电位以及所述本级级传信号的电位维持在所述第一参考低电平信号的电位，以及将所述本级扫描信号的电位维持在所述参考高电平信号的电位；
所述自举电容的一端电性连接于所述第一节点，所述自举电容的另一端电性连接于所述本级级传信号；
其中，所述本级级传信号为正脉冲信号，所述本级扫描信号为负脉冲信号。
在本申请所述的GOA电路中，所述输入模块包括：第二晶体管以及第三晶体管；
所述第二晶体管的栅极以及所述第三晶体管的栅极均电性连接于所述第一时钟信号，所述第二晶体管的源极电性连接于所述上一级级传信号，所述第二晶体管的漏极与所述第三晶体管的源极均与所述第二节点电性连接，所述第三晶体管的漏极电性连接于所述第一节点。
在本申请所述的GOA电路中，所述第一输出模块包括：第四晶体管；
所述第四晶体管的栅极电性连接于所述第一节点，所述第四晶体管的源极电性连接于所述第二时钟信号，所述第四晶体管的漏极电性连接于所述本级级传信号。
在本申请所述的GOA电路中，所述第二输出模块包括：第五晶体管；
所述第五晶体管的栅极电性连接于所述第一节点，所述第五晶体管的源极电性连接于所述第三参考低电平信号，所述第五晶体管的漏极电性连接于所述本级扫描信号。
在本申请所述的GOA电路中，所述下拉模块包括：第六晶体管、第七晶体管以及第八晶体管；
所述第六晶体管的栅极、所述第七晶体管的栅极以及所述第八晶体管的栅极均电性连接于所述下一级级传信号，所述第六晶体管的源极电性连接于所述第二参考低电平信号，所述第六晶体管的漏极电性连接于所述本级级传信号，所述第七晶体管的漏极电性连接于所述第一节点，所述第七晶体管的源极与所述第八晶体管的漏极电性连接，所述第八晶体管的源极电性连接于所述第一参考低电平信号。
在本申请所述的GOA电路中，所述反相模块包括：第九晶体管、第十晶体管、第十一晶体管以及第十二晶体管；
所述第九晶体管的栅极、源极以及所述第十一晶体管的源极均电性连接于所述参考高电平信号，所述第九晶体管的漏极、所述第十一晶体管的栅极以及所述第十晶体管的漏极电性连接，所述第十一晶体管的漏极以及所述第十二晶体管的漏极均电性连接于所述第三节点，所述第十晶体管的栅极以及所述第十二晶体管的栅极均电性连接于所述第一节点，所述第十晶体管的源极以及所述第十二晶体管的源极均电性连接于所述第一参考低电平信号。
在本申请所述的GOA电路中，所述维持模块包括：第十三晶体管、第十四晶体管、第十五晶体管以及第十六晶体管；
所述第十三晶体管的栅极、所述第十四晶体管的栅极、所述第十五晶体管的栅极以及所述第十六晶体管的栅极均电性连接于所述第三节点，所述第十三晶体管的源极电性连接于所述参考高电平信号，所述第十三晶体管的漏极电性连接于所述本级扫描信号，所述第十四晶体管的源极电性连接于所述第二参考低电平信号，所述第十四晶体管的漏极电性连接于所述本级级传信号，所述第十六晶体管的漏极与所述第十五晶体管的源极电性连接，所述第十五晶体管的漏极电性连接于所述第一节点，所述第十六晶体管的源极电性连接于所述第一参考低电平信号。
在本申请所述的GOA电路中，所述GOA电路还包括：第十七晶体管、第十八晶体管以及第十九晶体管；
所述第十七晶体管的栅极电性连接于所述本级级传信号，所述第十七晶体管的漏极电性连接于所述第二节点，所述第十七晶体管的源极、所述第十八晶体管的漏极以及所述第十九晶体管的漏极电性连接，所述第十八晶体管的栅极电性连接于所述第一节点，所述第十八晶体管的源极电性连接于所述第二时钟信号，所述第十九晶体管的栅极电性连接于所述第三节点，所述第十九晶体管的源极电性连接于所述第二参考低电平信号。
在本申请所述的GOA电路中，所述第一参考低电平信号的电位小于所述第二参考低电平信号的电位，且所述第二参考电平信号的电位等于所述第三参考低电平信号的电位。
本申请实施例还提供一种显示面板，于所述第一节点、所述第三节点、所述本级级传信号以及所述本级扫描信号，用于在所述第三节点的电位控制下，将所述第一节点的电位以及所述本级级传信号的电位维持在所述第一参考低电平信号的电位，以及将所述本级扫描信号的电位维持在所述参考高电平信号的电位；
所述自举电容的一端电性连接于所述第一节点，所述自举电容的另一端电性连接于所述本级级传信号；
其中，所述本级级传信号为正脉冲信号，所述本级扫描信号为负脉冲信号。
在本申请所述的显示面板中，所述输入模块包括：第二晶体管以及第三晶体管；
所述第二晶体管的栅极以及所述第三晶体管的栅极均电性连接于所述第一时钟信号，所述第二晶体管的源极电性连接于所述上一级级传信号，所述第二晶体管的漏极与所述第三晶体管的源极均与所述第二节点电性连接，所述第三晶体管的漏极电性连接于所述第一节点。
在本申请所述的显示面板中，所述第一输出模块包括：第四晶体管；
所述第四晶体管的栅极电性连接于所述第一节点，所述第四晶体管的源极电性连接于所述第二时钟信号，所述第四晶体管的漏极电性连接于所述本级级传信号。
在本申请所述的显示面板中，所述第二输出模块包括：第五晶体管；
所述第五晶体管的栅极电性连接于所述第一节点，所述第五晶体管的源极电性连接于所述第三参考低电平信号，所述第五晶体管的漏极电性连接于所述本级扫描信号。
 有益效果
本申请实施例提供的GOA电路及显示面板，采用较为简单的电路设计可同时输出正脉冲波形信号和负脉冲波形信号。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的GOA电路的结构示意图；
图2为本申请实施例提供的GOA电路中一GOA单元的第一种电路示意图；
图3为本申请实施例提供的GOA电路中一GOA单元的信号时序图；
图4为本申请实施例提供的GOA电路中一GOA单元的第二种电路示意图；以及
图5为本申请实施例提供的显示面板的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请所有实施例中采用的晶体管可以为薄膜晶体管或场效应管或其他特性相同的器件，由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本申请实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。按附图中的形态规定开关晶体管的中间端为栅极、信号输入端为源极、输出端为漏极。此外本申请实施例所采用的晶体管均为N 型晶体管，其中，N 型晶体管为在栅极为高电平时导通，在栅极为低电平时截止。
请参阅图1，图1为本申请实施例提供的GOA电路的结构示意图。如图1所示，本申请实施例提供的GOA电路10包括多级级联的GOA单元20。每一级GOA单元20均用于输出一负脉冲波形的扫描信号以及一负脉冲波形的级传信号。其中，当该GOA电路10工作时，第一级GOA单元20接入起始信号STV，随后，第二级GOA单元20、第三级GOA单元20，……，最后一级GOA单元20依次级传启动。
例如，以级联的第n-1级GOA单元、第n级GOA单元和第n+1级GOA单元为例。当第n-1级GOA单元工作时，第n-1级GOA单元输出负脉冲波形的扫描信号以及负脉冲波形的级传信号，用于在发光二极管显示面板中控制发光二极管发光。随后，第n-1级GOA单元的级传信号启动第n级GOA单元，第n级GOA单元输出负脉冲波形的扫描信号以及负脉冲波形的级传信号。最后，第n级GOA单元的级传信号启动第n+1级GOA单元，第n+1级GOA单元输出负脉冲波形的扫描信号以及负脉冲波形的级传信号。
进一步的，请参阅图2，图2为本申请实施例提供的GOA电路中一GOA单元的第一种电路示意图。如图2所示，该GOA电路包括：输入模块101、第一输出模块102、第二输出模块103、下拉模块104、反相模块105、维持模块106以及自举电容Cb。
其中，输入模块101接入第一时钟信号CLK以及上一级级传信号Gout（n-1），并电性连接于第一节点Q（n）以及第二节点L（n），用于在第一时钟信号CLK的控制下将上一级级传信号Gout（n-1）输出至第一节点Q（n）。
其中，第一输出模块102接入第二时钟信号CK，并电性连接于第一节点Q（n），用于在第一节点Q（n）的电位控制下输出本级级传信号Cout（n）。
其中，第二输出模块103接入第三参考低电平信号VGL3，并电性连接于第一节点Q（n），用于在第一节点Q（n）的电位控制下输出本级扫描信号G（n）。
其中，下拉模块104接入下一级级传信号Cout（n+1）、第一参考低电平信号VGL1以及第二参考低电平信号VGL2，并电性连接于第一节点Q（n）以及本级级传信号Cout（n），用于在下一级级传信号Cout（n+1）的控制下，将第一节点Q（n）的电位下拉至第一参考低电平信号VGL1的电位，以及将本级级传信号Cout（n）的电位下拉至第二参考低电平信号VGL2的电位。
其中，反相模块105接入参考高电平信号VGH以及第一参考低电平信号VGL1，并电性连接于第三节点K（n）以及第一节点Q（n），用于根据参考高电平信号VGH、第一参考低电平信号VGL1以及第一节点Q（n）的电位控制第三节点K（n）的电位。
其中，维持模块106接入第一参考低电平信号VGL1、参考高电平信号VGH以及第二参考低电平信号VGL2，并电性连接于第一节点Q（n）、第三节点K（n）、本级级传信号Cout（n）以及本级扫描信号G（n），用于在第三节点K（n）的电位控制下，将第一节点Q（n）的电位以及本级级传信号Cout（n）的电位维持在第一参考低电平信号VGL1的电位，以及将本级扫描信号G（n）的电位维持在参考高电平信号VGH的电位。
其中，自举电容Cb的一端电性连接于第一节点Q（n），自举电容Cb的另一端电性连接于本级级传信号Cout（n）。
在一些实施例中，输入模块101包括：第二晶体管T2以及第三晶体管T3；第二晶体管T2的栅极以及第三晶体管T3的栅极均电性连接于第一时钟信号CLK，第二晶体管T2的源极电性连接于上一级级传信号Cout（n-1），第二晶体管T2的漏极与第三晶体管T3的源极均与第二节点L（n）电性连接，第三晶体管T3的漏极电性连接于第一节点Q（n）。
在一些实施例中，第一输出模块102包括：第四晶体管T4；第四晶体管T4的栅极电性连接于第一节点Q（n），第四晶体管T4的源极电性连接于第二时钟信号CK，第四晶体管T4的漏极电性连接于本级级传信号Cout（n）。
在一些实施例中，第二输出模块103包括：第五晶体管T5；第五晶体管T5的栅极电性连接于第一节点Q（n），第五晶体管T5的源极电性连接于第三参考低电平信号VGL3，第五晶体管T5的漏极电性连接于本级扫描信号G（n）。
在一些实施例中，下拉模块104包括：第六晶体管T6、第七晶体管T7以及第八晶体管T8；第六晶体管T6的栅极、第七晶体管T7的栅极以及第八晶体管T8的栅极均电性连接于下一级级传信号Cout（n+1），第六晶体管T6的源极电性连接于第二参考低电平信号VGL2，第六晶体管T6的漏极电性连接于本级级传信号Cout（n），第七晶体管T7的漏极电性连接于第一节点Q（n），第七晶体管T7的源极与第八晶体管T8的漏极电性连接，第八晶体管T8的源极电性连接于第一参考低电平信号VGL1。
在一些实施例中，反相模块105包括：第九晶体管T9、第十晶体管T10、第十一晶体管T11以及第十二晶体管T12；第九晶体管T9的栅极、源极以及第十一晶体管T11的源极均电性连接于参考高电平信号VGH，第九晶体管T9的漏极、第十一晶体管T11的栅极以及第十晶体管T10的漏极电性连接，第十一晶体管T11的漏极以及第十二晶体管T12的漏极均电性连接于第三节点K（n），第十晶体管T10的栅极以及第十二晶体管T12的栅极均电性连接于第一节点Q（n），第十晶体管T10的源极以及第十二晶体管T12的源极均电性连接于第一参考低电平信号VGL1。
在一些实施例中，维持模块106包括：第十三晶体管T13、第十四晶体管T14、第十五晶体管T15以及第十六晶体管T16；第十三晶体管T13的栅极、第十四晶体管T14的栅极、第十五晶体管T15的栅极以及第十六晶体管T16的栅极均电性连接于第三节点K（n），第十三晶体管T13的源极电性连接于参考高电平信号VGH，第十三晶体管T13的漏极电性连接于本级扫描信号G（n），第十四晶体管T14的源极电性连接于第二参考低电平信号VGL2，第十四晶体管T14的漏极电性连接于本级级传信号Cout（n），第十六晶体管T16的漏极与第十五晶体管T15的源极电性连接，第十五晶体管T15的漏极电性连接于第一节点Q（n），第十六晶体管T16的源极电性连接于第一参考低电平信号VGL1。
在一些实施例中，第一参考低电平信号VGL1的电位小于第二参考低电平信号VGL2的电位，且第二参考电平信号VGL2的电位等于第三参考低电平信号VGL3的电位。
需要说明的是，本申请实施例提供的GOA电路的本级级传信号为正脉冲信号，本级扫描信号为负脉冲信号。也即，本申请实施例提供的GOA可同时输出正脉冲波形信号和负脉冲波形信号。
具体的，请结合图2、图3，图3为本申请实施例提供的GOA电路中一GOA电路的信号时序图。其中，第一时钟信号CLK的周期与第二时钟信号CK的周期相同，且第一时钟信号CLK的极性与第二时钟信号CK的极性相反。第一参考低电平信号VGL1的电位小于第二参考低电平信号VGL2的电位。
在第一时间段t1，第一时钟信号CLK为高电位，第二晶体管T2以及第三晶体管T3此时打开，由于此时第二晶体管T2的源极输入的上一级级传信号Gout（n-1）此时为高电位，使得第一节点Q（n）的电位被抬高，第四晶体管T4和第五晶体管T5打开；此时由于第二时钟信号CK为低电位，因此本级级传信号Cout（n）为低电位；本级扫描信号G（n）的电位等于第三参考低电平信号VGL3的电位，也即，本级扫描信号G（n）为低电位。
在第二时间段t2，第一时钟信号CLK为低电位，第一晶体管T1、第二晶体管T2以及第三晶体管T3此时关闭，第一节点Q（n）的电位继续保持为高电位，第四晶体管T4和第五晶体管T5依然打开。此时第二时钟信号CK为高电位，因此，本级级传信号Cout（n）为高电位，本级扫描信号G（n）的电位仍等于第三参考低电平信号VGL3的电位，也即，本级扫描信号G（n）为低电位。
同时，在本阶段，由于本级级传信号Cout（n）为高电位，在自举电容Cb的作用下，将第一节点Q（n）的电位进一步抬高，保证第四晶体管T4和第五晶体管T5的打开以及本级级传信号Cout（n）为高电位信号、本级扫描信号G（n）为低电位。
在第三时间段t3，由于下一级级传信号Cout（n+1）为高电位信号，使得第六晶体管T6、第七晶体管T7和第八晶体管T8开启，直接将第一节点Q（n）与第一参考低电平信号VGL1连通，以及将本级级传信号Cout（n）与第二参考低电平信号VGL2连通。也即，此时，本级级传信号Cout（n）的电位被下拉至第二参考低电平信号VGL2的电位，第一节点Q（n）的电位被下拉至第一参考低电平信号VGL1的电位。
在第四时间段t3，第一节点Q（n）的电位为低电位，第十晶体管T10和第十二晶体管T12关闭，参考高电平信号VGH的高电位输出至第二节点L（n），从而使得第十三晶体管T13、第十四晶体管T14、第十五晶体管T15以及第十六晶体管T16打开，第一节点Q（n）的电位维持在第一参考低电平信号VGL1的电位，本级级传信号Cout（n）的电位维持在第二参考低电平信号VGL2的电位，以及本级扫描信号G（n）的电位维持在参考高电平信号VGH的电位。
另外，请参阅图4，图4为本申请实施例提供的GOA电路中一GOA单元的第二种电路示意图。其中，图4所示的电路与图2所示的电路的区别在于：图4所示的GOA电路还包括：第十七晶体管T17、第十八晶体管T18以及第十九晶体管T19。
其中，第十七晶体管T17的栅极电性连接于本级级传信号Cout（n），第十七晶体管T17的漏极电性连接于第二节点L（n），第十七晶体管T17的源极、第十八晶体管T18的漏极以及第十九晶体管T19的漏极电性连接，第十八晶体管T18的栅极电性连接于第一节点Q（n），第十八晶体管T18的源极电性连接于第二时钟信号CK，第十九晶体管T19的栅极电性连接于第三节点K（n），第十九晶体管T19的源极电性连接于第二参考低电平信号VGL2。
需要说明的是，本申请实施例通过增加第十七晶体管T17、第十八晶体管T18以及第十九晶体管T19，从而扩展GOA电路的功能，使得GOA电路更加安全、稳定。
请参阅图5，图5为本申请实施例提供的显示面板的结构示意图。如图5所示，该显示面板包括显示区域100以及集成设置在显示区域100边缘上的GOA电路200；其中，该GOA电路200与上述的GOA电路的结构和原理类似，这里不再赘述。
以上仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种GOA电路，其包括：多级级联的GOA单元，每一级GOA单元均包括：多级级联的GOA单元，每一级GOA单元均包括：输入模块、第一输出模块、第二输出模块、下拉模块、反相模块、维持模块以及自举电容；
    所述输入模块接入第一时钟信号以及上一级级传信号，并电性连接于第一节点以及第二节点，用于在所述第一时钟信号的控制下将所述上一级级传信号输出至所述第一节点；
    所述第一输出模块接入第二时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级级传信号；
    所述第二输出模块接入第三参考低电平信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级扫描信号；
    所述下拉模块接入下一级级传信号、第一参考低电平信号以及第二参考低电平信号，并电性连接于所述第一节点以及所述本级级传信号，用于在所述下一级级传信号的控制下，将所述第一节点的电位下拉至所述第一参考低电平信号的电位，以及将所述本级级传信号的电位下拉至所述第二参考低电平信号的电位；
    所述反相模块接入参考高电平信号以及所述第一参考低电平信号，并电性连接于第三节点以及所述第一节点，用于根据所述参考高电平信号、所述第一参考低电平信号以及所述第一节点的电位控制所述第三节点的电位；
    所述维持模块接入所述第一参考低电平信号、所述参考高电平信号以及所述第二参考低电平信号，并电性连接于所述第一节点、所述第三节点、所述本级级传信号以及所述本级扫描信号，用于在所述第三节点的电位控制下，将所述第一节点的电位以及所述本级级传信号的电位维持在所述第一参考低电平信号的电位，以及将所述本级扫描信号的电位维持在所述参考高电平信号的电位；
    所述自举电容的一端电性连接于所述第一节点，所述自举电容的另一端电性连接于所述本级级传信号；
    其中，所述本级级传信号为正脉冲信号，所述本级扫描信号为负脉冲信号；
    所述GOA电路还包括：第十七晶体管、第十八晶体管以及第十九晶体管；
    所述第十七晶体管的栅极电性连接于所述本级级传信号，所述第十七晶体管的漏极电性连接于所述第二节点，所述第十七晶体管的源极、所述第十八晶体管的漏极以及所述第十九晶体管的漏极电性连接，所述第十八晶体管的栅极电性连接于所述第一节点，所述第十八晶体管的源极电性连接于所述第二时钟信号，所述第十九晶体管的栅极电性连接于所述第三节点，所述第十九晶体管的源极电性连接于所述第二参考低电平信号；
    所述第一参考低电平信号的电位小于所述第二参考低电平信号的电位，且所述第二参考电平信号的电位等于所述第三参考低电平信号的电位。
  2. 根据权利要求1所述的GOA电路，其中，所述输入模块包括：第二晶体管以及第三晶体管；
    所述第二晶体管的栅极以及所述第三晶体管的栅极均电性连接于所述第一时钟信号，所述第二晶体管的源极电性连接于所述上一级级传信号，所述第二晶体管的漏极与所述第三晶体管的源极均与所述第二节点电性连接，所述第三晶体管的漏极电性连接于所述第一节点。
  3. 根据权利要求1所述的GOA电路，其中，所述第一输出模块包括：第四晶体管；
    所述第四晶体管的栅极电性连接于所述第一节点，所述第四晶体管的源极电性连接于所述第二时钟信号，所述第四晶体管的漏极电性连接于所述本级级传信号。
  4. 根据权利要求1所述的GOA电路，其中，所述第二输出模块包括：第五晶体管；
    所述第五晶体管的栅极电性连接于所述第一节点，所述第五晶体管的源极电性连接于所述第三参考低电平信号，所述第五晶体管的漏极电性连接于所述本级扫描信号。
  5. 根据权利要求1所述的GOA电路，其中，所述下拉模块包括：第六晶体管、第七晶体管以及第八晶体管；
    所述第六晶体管的栅极、所述第七晶体管的栅极以及所述第八晶体管的栅极均电性连接于所述下一级级传信号，所述第六晶体管的源极电性连接于所述第二参考低电平信号，所述第六晶体管的漏极电性连接于所述本级级传信号，所述第七晶体管的漏极电性连接于所述第一节点，所述第七晶体管的源极与所述第八晶体管的漏极电性连接，所述第八晶体管的源极电性连接于所述第一参考低电平信号。
  6. 根据权利要求1所述的GOA电路，其中，所述反相模块包括：第九晶体管、第十晶体管、第十一晶体管以及第十二晶体管；
    所述第九晶体管的栅极、源极以及所述第十一晶体管的源极均电性连接于所述参考高电平信号，所述第九晶体管的漏极、所述第十一晶体管的栅极以及所述第十晶体管的漏极电性连接，所述第十一晶体管的漏极以及所述第十二晶体管的漏极均电性连接于所述第三节点，所述第十晶体管的栅极以及所述第十二晶体管的栅极均电性连接于所述第一节点，所述第十晶体管的源极以及所述第十二晶体管的源极均电性连接于所述第一参考低电平信号。
  7. 根据权利要求1所述的GOA电路，其中，所述维持模块包括：第十三晶体管、第十四晶体管、第十五晶体管以及第十六晶体管；
    所述第十三晶体管的栅极、所述第十四晶体管的栅极、所述第十五晶体管的栅极以及所述第十六晶体管的栅极均电性连接于所述第三节点，所述第十三晶体管的源极电性连接于所述参考高电平信号，所述第十三晶体管的漏极电性连接于所述本级扫描信号，所述第十四晶体管的源极电性连接于所述第二参考低电平信号，所述第十四晶体管的漏极电性连接于所述本级级传信号，所述第十六晶体管的漏极与所述第十五晶体管的源极电性连接，所述第十五晶体管的漏极电性连接于所述第一节点，所述第十六晶体管的源极电性连接于所述第一参考低电平信号。
  8. 一种GOA电路，其包括：多级级联的GOA单元，每一级GOA单元均包括：多级级联的GOA单元，每一级GOA单元均包括：输入模块、第一输出模块、第二输出模块、下拉模块、反相模块、维持模块以及自举电容；
    所述输入模块接入第一时钟信号以及上一级级传信号，并电性连接于第一节点以及第二节点，用于在所述第一时钟信号的控制下将所述上一级级传信号输出至所述第一节点；
    所述第一输出模块接入第二时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级级传信号；
    所述第二输出模块接入第三参考低电平信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级扫描信号；
    所述下拉模块接入下一级级传信号、第一参考低电平信号以及第二参考低电平信号，并电性连接于所述第一节点以及所述本级级传信号，用于在所述下一级级传信号的控制下，将所述第一节点的电位下拉至所述第一参考低电平信号的电位，以及将所述本级级传信号的电位下拉至所述第二参考低电平信号的电位；
    所述反相模块接入参考高电平信号以及所述第一参考低电平信号，并电性连接于第三节点以及所述第一节点，用于根据所述参考高电平信号、所述第一参考低电平信号以及所述第一节点的电位控制所述第三节点的电位；
    所述维持模块接入所述第一参考低电平信号、所述参考高电平信号以及所述第二参考低电平信号，并电性连接于所述第一节点、所述第三节点、所述本级级传信号以及所述本级扫描信号，用于在所述第三节点的电位控制下，将所述第一节点的电位以及所述本级级传信号的电位维持在所述第一参考低电平信号的电位，以及将所述本级扫描信号的电位维持在所述参考高电平信号的电位；
    所述自举电容的一端电性连接于所述第一节点，所述自举电容的另一端电性连接于所述本级级传信号；
    其中，所述本级级传信号为正脉冲信号，所述本级扫描信号为负脉冲信号。
  9. 根据权利要求8所述的GOA电路，其中，所述输入模块包括：第二晶体管以及第三晶体管；
    所述第二晶体管的栅极以及所述第三晶体管的栅极均电性连接于所述第一时钟信号，所述第二晶体管的源极电性连接于所述上一级级传信号，所述第二晶体管的漏极与所述第三晶体管的源极均与所述第二节点电性连接，所述第三晶体管的漏极电性连接于所述第一节点。
  10. 根据权利要求8所述的GOA电路，其中，所述第一输出模块包括：第四晶体管；
    所述第四晶体管的栅极电性连接于所述第一节点，所述第四晶体管的源极电性连接于所述第二时钟信号，所述第四晶体管的漏极电性连接于所述本级级传信号。
  11. 根据权利要求8所述的GOA电路，其中，所述第二输出模块包括：第五晶体管；
    所述第五晶体管的栅极电性连接于所述第一节点，所述第五晶体管的源极电性连接于所述第三参考低电平信号，所述第五晶体管的漏极电性连接于所述本级扫描信号。
  12. 根据权利要求8所述的GOA电路，其中，所述下拉模块包括：第六晶体管、第七晶体管以及第八晶体管；
    所述第六晶体管的栅极、所述第七晶体管的栅极以及所述第八晶体管的栅极均电性连接于所述下一级级传信号，所述第六晶体管的源极电性连接于所述第二参考低电平信号，所述第六晶体管的漏极电性连接于所述本级级传信号，所述第七晶体管的漏极电性连接于所述第一节点，所述第七晶体管的源极与所述第八晶体管的漏极电性连接，所述第八晶体管的源极电性连接于所述第一参考低电平信号。
  13. 根据权利要求8所述的GOA电路，其中，所述反相模块包括：第九晶体管、第十晶体管、第十一晶体管以及第十二晶体管；
    所述第九晶体管的栅极、源极以及所述第十一晶体管的源极均电性连接于所述参考高电平信号，所述第九晶体管的漏极、所述第十一晶体管的栅极以及所述第十晶体管的漏极电性连接，所述第十一晶体管的漏极以及所述第十二晶体管的漏极均电性连接于所述第三节点，所述第十晶体管的栅极以及所述第十二晶体管的栅极均电性连接于所述第一节点，所述第十晶体管的源极以及所述第十二晶体管的源极均电性连接于所述第一参考低电平信号。
  14. 根据权利要求8所述的GOA电路，其中，所述维持模块包括：第十三晶体管、第十四晶体管、第十五晶体管以及第十六晶体管；
    所述第十三晶体管的栅极、所述第十四晶体管的栅极、所述第十五晶体管的栅极以及所述第十六晶体管的栅极均电性连接于所述第三节点，所述第十三晶体管的源极电性连接于所述参考高电平信号，所述第十三晶体管的漏极电性连接于所述本级扫描信号，所述第十四晶体管的源极电性连接于所述第二参考低电平信号，所述第十四晶体管的漏极电性连接于所述本级级传信号，所述第十六晶体管的漏极与所述第十五晶体管的源极电性连接，所述第十五晶体管的漏极电性连接于所述第一节点，所述第十六晶体管的源极电性连接于所述第一参考低电平信号。
  15. 根据权利要求8所述的GOA电路，其中，所述GOA电路还包括：第十七晶体管、第十八晶体管以及第十九晶体管；
    所述第十七晶体管的栅极电性连接于所述本级级传信号，所述第十七晶体管的漏极电性连接于所述第二节点，所述第十七晶体管的源极、所述第十八晶体管的漏极以及所述第十九晶体管的漏极电性连接，所述第十八晶体管的栅极电性连接于所述第一节点，所述第十八晶体管的源极电性连接于所述第二时钟信号，所述第十九晶体管的栅极电性连接于所述第三节点，所述第十九晶体管的源极电性连接于所述第二参考低电平信号。
  16. 根据权利要求8所述的GOA电路，其中，所述第一参考低电平信号的电位小于所述第二参考低电平信号的电位，且所述第二参考电平信号的电位等于所述第三参考低电平信号的电位。
  17. 一种显示面板，其包括GOA电路，所述GOA电路包括：多级级联的GOA单元，每一级GOA单元均包括：多级级联的GOA单元，每一级GOA单元均包括：输入模块、第一输出模块、第二输出模块、下拉模块、反相模块、维持模块以及自举电容；
    所述输入模块接入第一时钟信号以及上一级级传信号，并电性连接于第一节点以及第二节点，用于在所述第一时钟信号的控制下将所述上一级级传信号输出至所述第一节点；
    所述第一输出模块接入第二时钟信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级级传信号；
    所述第二输出模块接入第三参考低电平信号，并电性连接于所述第一节点，用于在所述第一节点的电位控制下输出本级扫描信号；
    所述下拉模块接入下一级级传信号、第一参考低电平信号以及第二参考低电平信号，并电性连接于所述第一节点以及所述本级级传信号，用于在所述下一级级传信号的控制下，将所述第一节点的电位下拉至所述第一参考低电平信号的电位，以及将所述本级级传信号的电位下拉至所述第二参考低电平信号的电位；
    所述反相模块接入参考高电平信号以及所述第一参考低电平信号，并电性连接于第三节点以及所述第一节点，用于根据所述参考高电平信号、所述第一参考低电平信号以及所述第一节点的电位控制所述第三节点的电位；
    所述维持模块接入所述第一参考低电平信号、所述参考高电平信号以及所述第二参考低电平信号，并电性连接于所述第一节点、所述第三节点、所述本级级传信号以及所述本级扫描信号，用于在所述第三节点的电位控制下，将所述第一节点的电位以及所述本级级传信号的电位维持在所述第一参考低电平信号的电位，以及将所述本级扫描信号的电位维持在所述参考高电平信号的电位；
    所述自举电容的一端电性连接于所述第一节点，所述自举电容的另一端电性连接于所述本级级传信号；
    其中，所述本级级传信号为正脉冲信号，所述本级扫描信号为负脉冲信号。
  18. 根据权利要求17所述的显示面板，其中，所述输入模块包括：第二晶体管以及第三晶体管；
    所述第二晶体管的栅极以及所述第三晶体管的栅极均电性连接于所述第一时钟信号，所述第二晶体管的源极电性连接于所述上一级级传信号，所述第二晶体管的漏极与所述第三晶体管的源极均与所述第二节点电性连接，所述第三晶体管的漏极电性连接于所述第一节点。
  19. 根据权利要求17所述的显示面板，其中，所述第一输出模块包括：第四晶体管；
    所述第四晶体管的栅极电性连接于所述第一节点，所述第四晶体管的源极电性连接于所述第二时钟信号，所述第四晶体管的漏极电性连接于所述本级级传信号。
  20. 根据权利要求17所述的显示面板，其中，所述第二输出模块包括：第五晶体管；
    所述第五晶体管的栅极电性连接于所述第一节点，所述第五晶体管的源极电性连接于所述第三参考低电平信号，所述第五晶体管的漏极电性连接于所述本级扫描信号。
PCT/CN2019/086230 2019-04-10 2019-05-09 Goa电路及显示面板 Ceased WO2020206792A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/980,907 US11138939B2 (en) 2019-04-10 2019-05-09 Gate driver on array (GOA) circuit and display apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910283268.3 2019-04-10
CN201910283268.3A CN110007628B (zh) 2019-04-10 2019-04-10 Goa电路及显示面板

Publications (1)

Publication Number Publication Date
WO2020206792A1 true WO2020206792A1 (zh) 2020-10-15

Family

ID=67170617

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/086230 Ceased WO2020206792A1 (zh) 2019-04-10 2019-05-09 Goa电路及显示面板

Country Status (3)

Country Link
US (1) US11138939B2 (zh)
CN (1) CN110007628B (zh)
WO (1) WO2020206792A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110706631A (zh) * 2019-09-03 2020-01-17 深圳市华星光电半导体显示技术有限公司 显示驱动电路
CN111402829B (zh) * 2020-04-10 2021-07-27 苏州华星光电技术有限公司 Goa电路、显示面板
KR102733296B1 (ko) * 2020-12-17 2024-11-21 엘지디스플레이 주식회사 게이트 구동 회로 및 게이트 구동회로를 포함하는 표시 장치
CN114495793B (zh) * 2022-02-14 2023-08-22 深圳市华星光电半导体显示技术有限公司 Goa电路及显示面板
CN114758635B (zh) 2022-04-27 2023-07-25 Tcl华星光电技术有限公司 Goa电路及显示面板
CN120220562A (zh) * 2023-12-26 2025-06-27 武汉华星光电半导体显示技术有限公司 栅极驱动单元及显示装置

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103680450A (zh) * 2013-12-18 2014-03-26 友达光电股份有限公司 一种可实现信号双向传输的驱动电路及其移位寄存器
CN103928005A (zh) * 2014-01-27 2014-07-16 深圳市华星光电技术有限公司 用于共同驱动栅极和公共电极的goa单元、驱动电路及阵列
CN104091577A (zh) * 2014-07-15 2014-10-08 深圳市华星光电技术有限公司 应用于2d-3d信号设置的栅极驱动电路
CN104409058A (zh) * 2014-11-14 2015-03-11 深圳市华星光电技术有限公司 一种扫描驱动电路
CN104537991A (zh) * 2014-12-30 2015-04-22 深圳市华星光电技术有限公司 正反向扫描的栅极驱动电路
CN105206237A (zh) * 2015-10-10 2015-12-30 武汉华星光电技术有限公司 应用于In Cell型触控显示面板的GOA电路
CN105469754A (zh) * 2015-12-04 2016-04-06 武汉华星光电技术有限公司 降低馈通电压的goa电路
CN109416902A (zh) * 2017-04-13 2019-03-01 京东方科技集团股份有限公司 移位寄存器电路及其驱动方法、阵列基板上栅极驱动器电路和触摸感应显示面板

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2006315037C1 (en) * 2005-11-18 2013-05-02 Ichnos Sciences SA Anti-alpha2 integrin antibodies and their uses
CN101510411B (zh) * 2009-03-05 2011-01-19 友达光电股份有限公司 显示装置及其修复方法
CN101944321B (zh) * 2010-09-26 2012-11-21 友达光电股份有限公司 栅极驱动脉冲补偿电路以及显示装置
CN102820007B (zh) * 2012-08-27 2014-10-15 京东方科技集团股份有限公司 阵列基板行驱动电路、显示面板及显示装置
CN104157259B (zh) * 2014-09-10 2016-06-22 深圳市华星光电技术有限公司 基于igzo制程的栅极驱动电路
CN104505048A (zh) * 2014-12-31 2015-04-08 深圳市华星光电技术有限公司 一种goa电路及液晶显示装置
CN104867438B (zh) * 2015-06-24 2018-02-13 合肥鑫晟光电科技有限公司 移位寄存器单元及其驱动方法、移位寄存器和显示装置
CN109285504B (zh) * 2017-07-20 2020-07-24 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路
CN109493783B (zh) * 2018-12-21 2020-10-13 深圳市华星光电半导体显示技术有限公司 Goa电路及显示面板
US10950155B1 (en) * 2020-03-27 2021-03-16 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. GOA circuit and display panel

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103680450A (zh) * 2013-12-18 2014-03-26 友达光电股份有限公司 一种可实现信号双向传输的驱动电路及其移位寄存器
CN103928005A (zh) * 2014-01-27 2014-07-16 深圳市华星光电技术有限公司 用于共同驱动栅极和公共电极的goa单元、驱动电路及阵列
CN104091577A (zh) * 2014-07-15 2014-10-08 深圳市华星光电技术有限公司 应用于2d-3d信号设置的栅极驱动电路
CN104409058A (zh) * 2014-11-14 2015-03-11 深圳市华星光电技术有限公司 一种扫描驱动电路
CN104537991A (zh) * 2014-12-30 2015-04-22 深圳市华星光电技术有限公司 正反向扫描的栅极驱动电路
CN105206237A (zh) * 2015-10-10 2015-12-30 武汉华星光电技术有限公司 应用于In Cell型触控显示面板的GOA电路
CN105469754A (zh) * 2015-12-04 2016-04-06 武汉华星光电技术有限公司 降低馈通电压的goa电路
CN109416902A (zh) * 2017-04-13 2019-03-01 京东方科技集团股份有限公司 移位寄存器电路及其驱动方法、阵列基板上栅极驱动器电路和触摸感应显示面板

Also Published As

Publication number Publication date
US11138939B2 (en) 2021-10-05
US20210158761A1 (en) 2021-05-27
CN110007628A (zh) 2019-07-12
CN110007628B (zh) 2022-02-01

Similar Documents

Publication Publication Date Title
WO2020206792A1 (zh) Goa电路及显示面板
CN106683631B (zh) 一种igzo薄膜晶体管的goa电路及显示装置
CN103117091B (zh) 移位缓存器及其驱动方法
CN102682699B (zh) 栅极驱动电路及显示器
WO2022007147A1 (zh) Goa电路以及显示面板
WO2016188287A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路和显示装置
US10121442B2 (en) Driving methods and driving devices of gate driver on array (GOA) circuit
WO2020164193A1 (zh) Goa 电路及显示面板
WO2022011836A1 (zh) Goa电路以及显示面板
WO2020206816A1 (zh) Goa 电路及显示面板
WO2020215435A1 (zh) Goa电路及显示面板
WO2021147990A1 (zh) 移位寄存器、栅极驱动电路、显示装置和栅极驱动方法
WO2014166251A1 (zh) 移位寄存器单元及栅极驱动电路
WO2021203485A1 (zh) Goa 电路及显示面板
US10825412B2 (en) Liquid crystal panel including GOA circuit and driving method thereof
CN106951123A (zh) 触控驱动单元及其驱动方法、触控驱动电路、显示装置
WO2020220565A1 (zh) 一种goa电路及显示装置
WO2020124822A1 (zh) Goa 电路及显示面板
WO2021103164A1 (zh) 一种 goa 电路及液晶显示面板
WO2020206796A1 (zh) Goa电路及显示面板
WO2020077897A1 (zh) Goa 驱动电路及显示面板
WO2018107533A1 (zh) 一种栅极驱动电路及驱动方法、显示装置
WO2018161527A1 (zh) 移位寄存器、栅极驱动电路、显示面板及驱动方法
WO2023206624A1 (zh) Goa电路及显示面板
WO2020199284A1 (zh) Goa电路及显示面板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19924184

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19924184

Country of ref document: EP

Kind code of ref document: A1