WO2023206624A1 - Goa电路及显示面板 - Google Patents

Goa电路及显示面板 Download PDF

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Publication number
WO2023206624A1
WO2023206624A1 PCT/CN2022/092709 CN2022092709W WO2023206624A1 WO 2023206624 A1 WO2023206624 A1 WO 2023206624A1 CN 2022092709 W CN2022092709 W CN 2022092709W WO 2023206624 A1 WO2023206624 A1 WO 2023206624A1
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WO
WIPO (PCT)
Prior art keywords
transistor
node
level
signal
electrode
Prior art date
Application number
PCT/CN2022/092709
Other languages
English (en)
French (fr)
Inventor
贾莎莎
Original Assignee
惠州华星光电显示有限公司
Tcl华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 惠州华星光电显示有限公司, Tcl华星光电技术有限公司 filed Critical 惠州华星光电显示有限公司
Priority to US17/779,150 priority Critical patent/US20240169950A1/en
Publication of WO2023206624A1 publication Critical patent/WO2023206624A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • This application relates to the field of display technology, and specifically to a GOA circuit and a display panel.
  • GOA GateDriver on Array, integrated gate drive circuit
  • the purpose of the embodiments of the present application is to provide a GOA circuit and a display panel.
  • the GOA circuit has a simple structure, can reduce the circuit layout space while ensuring the circuit function, increase the aperture ratio of the display panel, and meet the requirements of narrow borders and high height of the display panel. resolution requirements.
  • embodiments of the present application provide a GOA circuit, including multi-level cascaded GOA units.
  • Each level of GOA unit includes: a pull-up control module, an output module, a stage transmission module, a pull-down module and a pull-down maintenance module; so
  • the pull-up control module is connected to the upper-level transmission signal and the reference high-level signal, and is electrically connected to the first node.
  • the pull-up control module is used to control the upper-level transmission signal.
  • the potential of the first node is raised to the potential of the reference high level; the output module is connected to the first clock signal and is electrically connected to the first node and the scanning signal of this level, The output module is used to output the scanning signal of this level under the potential control of the first node; the level transmission module is connected to the first clock signal and is electrically connected to the first node and The level transmission signal of the current level, the level transmission module is used to output the level transmission signal of the current level under the potential control of the first node; the pull-down module is connected to the next level scanning signal, the level transmission signal of the current level transmits the signal, the scanning signal of this level, the first reference low level signal and the second reference low level signal, and is electrically connected to the first node and the second node, and the pull-down module is used to perform the next The control of the level scanning signal pulls down the potential of the first node, the second node and the level transmission signal of the current level to the potential of the first reference low level signal, and pulls down the level scanning signal to the
  • the pull-down maintenance module is used to enable the pull-down maintenance module under the control of the reset signal and the second clock signal.
  • the potential of the first node and the second node is maintained at the potential of the first reference low-level signal, and the potential of the current-level scanning signal is maintained at the potential of the second reference low-level signal.
  • the GOA unit further includes a bootstrap capacitor, and both ends of the bootstrap capacitor are electrically connected to the first node and the scanning signal of this level respectively, so The bootstrap capacitor is used to raise the potential of the first node twice to ensure the normal output of the scanning signal of this level.
  • the pull-up control module includes a first transistor, the gate of the first transistor is connected to the upper-level transmission signal, and the third transistor of the first transistor An electrode is connected to the reference high level signal, and a second electrode of the first transistor is electrically connected to the first node.
  • the output module includes a second transistor, the gate of the second transistor is electrically connected to the first node, and the first electrode of the second transistor is connected to The first clock signal is input, and the second electrode of the second transistor is electrically connected to the scanning signal of this level.
  • the cascade transmission module includes a third transistor, the gate of the third transistor is electrically connected to the first node, and the first electrode of the third transistor The first clock signal is connected, and the second electrode of the third transistor is electrically connected to the current stage transmission signal.
  • the pull-down module includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor, and the gate of the fourth transistor is connected to the current level of the current transistor.
  • the first electrode of the fourth transistor is electrically connected to the scanning signal of this level, the second electrode of the fourth transistor is electrically connected to the second node;
  • the gate electrode of the fifth transistor is connected to The next-level scanning signal is input, the first electrode of the fifth transistor is electrically connected to the current-level scanning signal, and the second electrode of the fifth transistor is connected to the second reference low-level signal;
  • the gate of the sixth transistor is connected to the next-level scan signal, the first electrode of the sixth transistor is electrically connected to the first node, and the second electrode of the sixth transistor is electrically connected to The second node;
  • the gate of the seventh transistor is connected to the next-level scanning signal, the first electrode of the seventh transistor is electrically connected to the second node, and the gate of the seventh transistor is electrically connected to the second node.
  • the pull-down holding module includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor. and a fifteenth transistor, the gate of the eighth transistor is electrically connected to the third node, the first electrode of the eighth transistor is electrically connected to the first node, and the second electrode of the eighth transistor is electrically connected to the second node; the gate of the ninth transistor is electrically connected to the third node, the first electrode of the ninth transistor is electrically connected to the second node, and the gate of the ninth transistor is electrically connected to the third node.
  • the second electrode of the ninth transistor is connected to the first reference low level signal; the gate of the tenth transistor is electrically connected to the third node, and the first electrode of the tenth transistor is electrically connected to the third node.
  • the second electrode of the tenth transistor is connected to the second reference low level signal; the gate electrode of the eleventh transistor and the first electrode of the eleventh transistor are both connected to The second clock signal, the second electrode of the eleventh transistor is electrically connected to the fourth node; the gate of the twelfth transistor is electrically connected to the fourth node, and the twelfth transistor
  • the first electrode of the twelfth transistor is connected to the second clock signal, the second electrode of the twelfth transistor is electrically connected to the third node; the gate of the thirteenth transistor is electrically connected to the fifth node, The first electrode of the thirteenth transistor is electrically connected to the fourth node, and the second electrode of the thirteenth transistor is connected to the first reference low level signal; the gate of the fourteenth transistor
  • the potential of the first clock signal is opposite to the potential of the second clock signal.
  • a start signal is input into the pull-up control module of the first-level GOA unit and the pull-down module of the last-level GOA unit.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the The seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor , the fifteenth transistor is a transistor of the same type.
  • the present application provides a display panel, which includes a display area and a GOA circuit integrated on the display area.
  • the GOA circuit includes: multi-level cascaded GOA units, each level of GOA unit including : Pull-up control module, output module, level transmission module, pull-down module and pull-down maintenance module; the pull-up control module is connected to the upper level level transmission signal and the reference high-level signal, and is electrically connected to the first node , the pull-up control module is used to pull up the potential of the first node to the potential of the reference high level under the control of the upper level transmission signal; the output module is connected to the first A clock signal is electrically connected to the first node and the scanning signal of this level, and the output module is used to output the scanning signal of this level under the potential control of the first node; the level transmission module , access the first clock signal, and be electrically connected to the first node and the level transmission signal of this level.
  • the level transmission module is used to output the level transmission signal of this level under the potential control of the first node. Transmit signals; the pull-down module is connected to the next level scanning signal, the current level transmission signal, the current level scanning signal, the first reference low level signal and the second reference low level signal, and electrically Connected to the first node and the second node, the pull-down module is used to pull down the potential of the first node, the second node and the current level transmission signal to The potential of the first reference low-level signal is lowered to the potential of the current-level scanning signal to the potential of the second reference low-level signal; the pull-down maintenance module is connected to the reset signal and the second clock signal, the current-level scanning signal, the first reference low-level signal and the second reference low-level signal, and are electrically connected to the first node and the second node, and the pull-down maintain The module is configured to maintain the potential of the first node and the second node at the potential of the first reference low level signal under the control of the reset signal and the second clock signal,
  • the GOA unit further includes a bootstrap capacitor, and both ends of the bootstrap capacitor are electrically connected to the first node and the scanning signal of this level respectively, so The bootstrap capacitor is used to raise the potential of the first node twice to ensure the normal output of the scanning signal of this level.
  • the pull-up control module includes a first transistor, the gate of the first transistor is connected to the upper-level transmission signal, and the third transistor of the first transistor An electrode is connected to the reference high level signal, and a second electrode of the first transistor is electrically connected to the first node.
  • the output module includes a second transistor, the gate of the second transistor is electrically connected to the first node, and the first electrode of the second transistor is connected to The first clock signal is input, and the second electrode of the second transistor is electrically connected to the scanning signal of this level.
  • the cascade transmission module includes a third transistor, the gate of the third transistor is electrically connected to the first node, and the first electrode of the third transistor The first clock signal is connected, and the second electrode of the third transistor is electrically connected to the current stage transmission signal.
  • the pull-down module includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor, and the gate of the fourth transistor is connected to the current level of the current transistor.
  • the first electrode of the fourth transistor is electrically connected to the scanning signal of this level, the second electrode of the fourth transistor is electrically connected to the second node;
  • the gate electrode of the fifth transistor is connected to The next-level scanning signal is input, the first electrode of the fifth transistor is electrically connected to the current-level scanning signal, and the second electrode of the fifth transistor is connected to the second reference low-level signal;
  • the gate of the sixth transistor is connected to the next-level scan signal, the first electrode of the sixth transistor is electrically connected to the first node, and the second electrode of the sixth transistor is electrically connected to The second node;
  • the gate of the seventh transistor is connected to the next-level scanning signal, the first electrode of the seventh transistor is electrically connected to the second node, and the gate of the seventh transistor is electrically connected to the second node.
  • the pull-down holding module includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor. and a fifteenth transistor, the gate of the eighth transistor is electrically connected to the third node, the first electrode of the eighth transistor is electrically connected to the first node, and the second electrode of the eighth transistor is electrically connected to the second node; the gate of the ninth transistor is electrically connected to the third node, the first electrode of the ninth transistor is electrically connected to the second node, and the gate of the ninth transistor is electrically connected to the third node.
  • the second electrode of the ninth transistor is connected to the first reference low level signal; the gate of the tenth transistor is electrically connected to the third node, and the first electrode of the tenth transistor is electrically connected to the third node.
  • the second electrode of the tenth transistor is connected to the second reference low level signal; the gate electrode of the eleventh transistor and the first electrode of the eleventh transistor are both connected to The second clock signal, the second electrode of the eleventh transistor is electrically connected to the fourth node; the gate of the twelfth transistor is electrically connected to the fourth node, and the twelfth transistor
  • the first electrode of the twelfth transistor is connected to the second clock signal, the second electrode of the twelfth transistor is electrically connected to the third node; the gate of the thirteenth transistor is electrically connected to the fifth node, The first electrode of the thirteenth transistor is electrically connected to the fourth node, and the second electrode of the thirteenth transistor is connected to the first reference low level signal; the gate of the fourteenth transistor
  • the potential of the first clock signal is opposite to the potential of the second clock signal.
  • a start signal is input into the pull-up control module of the first-level GOA unit and the pull-down module of the last-level GOA unit.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the The seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor , the fifteenth transistor is a transistor of the same type.
  • the embodiment of the present application provides a GOA circuit including multi-level cascaded GOA units.
  • Each level of GOA unit includes: a pull-up control module, an output module, a transfer module, pull-down module and pull-down maintenance module.
  • the GOA circuit has a simple structure, can reduce the circuit layout space while ensuring the circuit function, increase the aperture ratio of the display panel, and meet the requirements of narrow frame and high resolution of the display panel.
  • Figure 1 is a schematic structural diagram of a GOA circuit provided by an embodiment of the present application.
  • Figure 2 is a schematic structural diagram of a first implementation of a GOA unit in the GOA circuit provided by the embodiment of the present application;
  • Figure 3 is a circuit schematic diagram of a first implementation of a GOA unit in the GOA circuit provided by the embodiment of the present application;
  • Figure 4 is a schematic structural diagram of a second implementation of a GOA unit in the GOA circuit provided by the embodiment of the present application;
  • Figure 5 is a circuit schematic diagram of a second implementation mode of a GOA unit in the GOA circuit provided by the embodiment of the present application;
  • Figure 6 is a signal timing diagram of a GOA unit in the GOA circuit provided by the embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • Embodiments of the present application provide a GOA circuit and a display panel.
  • the GOA circuit has a simple structure, can reduce the circuit layout space while ensuring the circuit function, increase the aperture ratio of the display panel, and meet the needs of narrow borders and high resolution of the display panel. Require.
  • the GOA circuit has a simple structure, can reduce the circuit layout space while ensuring the circuit function, increase the aperture ratio of the display panel, and meet the needs of narrow borders and high resolution of the display panel. Require.
  • the transistors used in all embodiments of this application can be thin film transistors, field effect transistors, or other devices with the same characteristics. Since the sources and drains of the transistors used here are symmetrical, their sources and drains are interchangeable. of. In the embodiment of the present application, in order to distinguish the two electrodes of the transistor except the gate electrode, one of the source electrode and the drain electrode is called the first electrode, and the other of the source electrode and the drain electrode is called the second electrode. . According to the form in the drawing, the middle terminal of the switching transistor is the gate, the signal input terminal is the first electrode, and the output terminal is the second electrode. In addition, the transistors used in the embodiments of the present application are N-type transistors or P-type transistors.
  • the N-type transistor is turned on when the gate is at a high potential and is turned off when the gate is at a low potential; the P-type transistor is turned off when the gate is at a low potential. It is turned on when the gate is at a high potential and turned off when the gate is at a high potential.
  • Figure 1 is a schematic structural diagram of a GOA circuit provided by an embodiment of the present application.
  • the GOA circuit provided by the embodiment of the present application includes multi-level cascaded GOA units.
  • Figure 1 takes the cascaded N-1th level GOA unit, Nth level GOA unit and N+1th level GOA unit as an example.
  • the scanning signal output by the N-th level GOA unit is high potential, which is used to turn on the transistor switch of each pixel in a row of the display panel, and conduct the data signal to the pixel electrode in each pixel.
  • Charging; the Nth level transmission signal is used to control the work of the N+1th level GOA unit; when the N+1th level GOA unit is working, the scanning signal output by the N+1th level GOA unit is high potential, and at the same time the Nth level GOA unit The scanning signal output by the level GOA unit is low potential.
  • FIG. 2 is a schematic structural diagram of a first implementation of a GOA unit in the GOA circuit provided by the embodiment of the present application.
  • the GOA unit includes: a pull-up control module 101, an output module 102, a stage transmission module 103, a pull-down module 104, and a pull-down maintenance module 105.
  • the pull-up control module 101 is connected to the upper-level transmission signal ST(N-1) and the reference high-level signal VGH, and is electrically connected to the first node Q.
  • the pull-up control module 101 is used to Under the control of the stage transmission signal ST(N-1), the potential of the first node Q is raised to the reference high level potential.
  • the output module 102 is connected to the first clock signal CK and is electrically connected to the first node Q and the scanning signal G(N) of the current level.
  • the output module 102 is used to output the current level under the potential control of the first node Q. Scan signal G(N).
  • the level transmission module 103 is connected to the first clock signal CK and is electrically connected to the first node Q and the current level level transmission signal ST(N).
  • the level transmission module 103 is used to control the potential of the first node Q. Output the level transmission signal ST(N).
  • the pull-down module 104 is connected to the next-level scanning signal G(N+1), the current-level transmission signal ST(N), the current-level scanning signal G(N), the first reference low-level signal VSSQ and the second Referring to the low-level signal VSSG and electrically connected to the first node Q and the second node P, the pull-down module 104 is used to pull down the first node Q and the second node under the control of the next-level scanning signal G(N+1). P and the current stage transmit the signal ST(N) to the potential of the first reference low-level signal VSSQ, and pull down the current-stage scanning signal G(N) to the potential of the second reference low-level signal VSSG.
  • the pull-down sustain module 105 is connected to the reset signal RESET, the second clock signal CKN+1, the scanning signal G(N) of this stage, the first reference low-level signal VSSQ and the second reference low-level signal VSSG, and is powered on.
  • the pull-down maintenance module 105 is used to maintain the potential of the first node Q and the second node P at the first level under the control of the reset signal RESET and the second clock signal CKN+1.
  • the potential of the reference low-level signal VSSQ is maintained at the potential of the current level scanning signal G(N) at the potential of the second reference low-level signal VSSG.
  • the GOA unit also includes a bootstrap capacitor C st .
  • the two ends of the bootstrap capacitor C st are electrically connected to the first node Q and the scanning signal G(N) of this level respectively.
  • the bootstrap capacitor C st is used for the second lifting of the second level.
  • the potential of a node Q ensures the normal output of the scanning signal G(N) of this level.
  • the GOA circuit provided by this application has a simple structure, can reduce the circuit layout space while ensuring the circuit function, increase the aperture ratio of the display panel, and meet the requirements of narrow frame and high resolution of the display panel.
  • the GOA circuit of the present application is placed inside the display area, the number of signals is simple, which can reduce crosstalk between signals. At the same time, it can be matched with high-mobility devices, and the number of devices is small and the size is small, so it can be greatly reduced.
  • the GOA circuit design space is increased, so that the size of key components can be increased. For example, the size of the components in the output module 102 can be increased to ensure the thrust of a large-size high-definition narrow-frame LCD panel.
  • FIG. 3 is a circuit schematic diagram of a first implementation mode of a GOA unit in the GOA circuit provided by the embodiment of the present application.
  • the pull-up control module 101 includes a first transistor T1.
  • the gate of the first transistor T1 is connected to the upper level transmission signal ST(N-1), and the first electrode of the first transistor T1 is connected to the reference The high level signal VGH, the second electrode of the first transistor T1 is electrically connected to the first node Q.
  • the output module 102 includes a second transistor T2.
  • the gate of the second transistor T2 is electrically connected to the first node Q.
  • the first electrode of the second transistor T2 is connected to the first clock signal CK.
  • the electrode is electrically connected to the scanning signal G(N) of this level.
  • the cascade transmission module 103 includes a third transistor T3.
  • the gate of the third transistor T3 is electrically connected to the first node Q.
  • the first electrode of the third transistor T3 is connected to the first clock signal CK.
  • the two electrodes are electrically connected to the current stage transmission signal ST(N).
  • the pull-down module 104 includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7.
  • the gate of the fourth transistor T4 is connected to the stage transmission signal ST(N) of the current stage.
  • the first electrode is electrically connected to the scanning signal G(N) of this level
  • the second electrode of the fourth transistor T4 is electrically connected to the second node P
  • the gate of the fifth transistor T5 is connected to the scanning signal G(N) of the next level.
  • the first electrode of the fifth transistor T5 is electrically connected to the current level scanning signal G(N), the second electrode of the fifth transistor T5 is connected to the second reference low level signal VSSG; the gate of the sixth transistor T6
  • the first electrode of the sixth transistor T6 is electrically connected to the first node Q, and the second electrode of the sixth transistor T6 is electrically connected to the second node P;
  • the gate of the seventh transistor T7 is connected to the next-level scanning signal G(N+1), the first electrode of the seventh transistor T7 is electrically connected to the second node P, and the second electrode of the seventh transistor T7 is connected to the first reference Low level signal VSSQ.
  • the pull-down holding module 105 includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, and a fifteenth transistor.
  • T15 the gate of the eighth transistor T8 is electrically connected to the third node M
  • the first electrode of the eighth transistor T8 is electrically connected to the first node Q
  • the second electrode of the eighth transistor T8 is electrically connected to the second node.
  • the gate of the ninth transistor T9 is electrically connected to the third node M, the first electrode of the ninth transistor T9 is electrically connected to the second node P, and the second electrode of the ninth transistor T9 is connected to the first reference low voltage.
  • flat signal VSSQ the gate of the tenth transistor T10 is electrically connected to the third node M, the first electrode of the tenth transistor T10 is electrically connected to the scanning signal G(N) of this level, and the second electrode of the tenth transistor T10 is electrically connected to the third node M.
  • the second reference low level signal VSSG is input; the gate of the eleventh transistor T11 and the first electrode of the eleventh transistor T11 are both connected to the second clock signal CKN+1, and the second electrode of the eleventh transistor T11 is electrically Connected to the fourth node N; the gate of the twelfth transistor T12 is electrically connected to the fourth node N, the first electrode of the twelfth transistor T12 is connected to the second clock signal CKN+1, and the gate of the twelfth transistor T12 is connected to the fourth node N.
  • the two electrodes are electrically connected to the third node M; the gate of the thirteenth transistor T13 is electrically connected to the fifth node S, and the first electrode of the thirteenth transistor T13 is electrically connected to the fourth node N.
  • the second electrode of T13 is connected to the first reference low level signal VSSQ; the gate of the fourteenth transistor T14 is electrically connected to the fifth node S, and the first electrode of the fourteenth transistor T14 is electrically connected to the third node M.
  • the second electrode of the fourteenth transistor T14 is connected to the first reference low level signal VSSQ; the gate of the fifteenth transistor T15 is connected to the reset signal RESET, and the first electrode of the fifteenth transistor T15 is electrically connected to the fifth At node S, the second electrode of the fifteenth transistor T15 is connected to the first reference low level signal VSSQ.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 are transistors of the same type.
  • the potential of the first clock signal CK is opposite to the potential of the second clock signal CKN+1.
  • the start signal STV is input into the pull-up control module 101 of the first-level GOA unit and the pull-down module 104 of the last-level GOA unit.
  • FIG. 4 is a schematic structural diagram of a second implementation mode of a GOA unit in the GOA circuit provided by the embodiment of the present application. As shown in FIG. 4 , both the pull-down module 104 and the pull-down sustain module 105 are connected to the first reference low-level signal VSSQ.
  • the pull-down module 104 accesses the next-level scanning signal G(N+1), the current-level transmission signal ST(N), the current-level scanning signal G(N), and the first reference low-level signal VSSQ, and electrically Sexually connected to the first node Q and the second node P, the pull-down module 104 is used to pull down the first node Q, the second node P, and the present-level transmission signal ST( N) and the potential of the current level scanning signal G(N) to the potential of the first reference low level signal VSSQ.
  • the pull-down sustain module 105 is connected to the reset signal RESET, the second clock signal CKN+1, the scanning signal G(N) of this stage, and the first reference low level signal VSSQ, and is electrically connected to the first node Q, the second Node P, the pull-down holding module 105 is used to maintain the potential of the first node Q, the second node P and the current level scanning signal G(N) at the first reference under the control of the reset signal RESET and the second clock signal CKN+1.
  • the potential of the low-level signal VSSQ is connected to the reset signal RESET, the second clock signal CKN+1, the scanning signal G(N) of this stage, and the first reference low level signal VSSQ, and is electrically connected to the first node Q, the second Node P, the pull-down holding module 105 is used to maintain the potential of the first node Q, the second node P and the current level scanning signal G(N) at the first reference under the control of the reset signal RESET and the second clock signal CKN+1
  • the pull-up control module 101 is connected to the upper-level transmission signal ST(N-1) and the reference high-level signal VGH, and is electrically connected to the first node Q.
  • the pull-up control module 101 is used to Under the control of the stage transmission signal ST(N-1), the potential of the first node Q is raised to the reference high level potential.
  • the output module 102 is connected to the first clock signal CK and is electrically connected to the first node Q and the scanning signal G(N) of the current level.
  • the output module 102 is used to output the current level under the potential control of the first node Q. Scan signal G(N).
  • the level transmission module 103 is connected to the first clock signal CK and is electrically connected to the first node Q and the current level level transmission signal ST(N).
  • the level transmission module 103 is used to control the potential of the first node Q. Output the level transmission signal ST(N).
  • the GOA unit also includes a bootstrap capacitor C st .
  • the two ends of the bootstrap capacitor C st are electrically connected to the first node Q and the scanning signal G(N) of this level respectively.
  • the bootstrap capacitor C st is used for the second lifting of the second level.
  • the potential of a node Q ensures the normal output of the scanning signal G(N) of this level.
  • the pull-down sustain module 105 and the pull-down module 104 provided by the embodiment of the present application are both electrically connected to the first reference low-level signal VSSQ, which can further simplify the structure of the GOA circuit, reduce the number of signals, and further reduce the number of signals.
  • the crosstalk between them also reduces the GOA circuit design space, increases the aperture ratio of the display panel, and meets the requirements of narrow borders and high resolution of the display panel.
  • the pull-down module 104 includes a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 and a seventh transistor T7 .
  • the gate of the fourth transistor T4 is connected to the current stage transmission signal ST(N).
  • the first electrode of the fourth transistor T4 is electrically connected to the scanning signal G(N) of this level, the second electrode of the fourth transistor T4 is electrically connected to the second node P; the gate of the fifth transistor T5 is connected to the next level of scanning.
  • the first electrode of the fifth transistor T5 is electrically connected to the scanning signal G(N) of this level, and the second electrode of the fifth transistor T5 is connected to the first reference low level signal VSSQ;
  • the pull-down holding module 105 includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, and a fifteenth transistor.
  • T15 the gate of the eighth transistor T8 is electrically connected to the third node M
  • the first electrode of the eighth transistor T8 is electrically connected to the first node Q
  • the second electrode of the eighth transistor T8 is electrically connected to the second node.
  • the gate of the ninth transistor T9 is electrically connected to the third node M, the first electrode of the ninth transistor T9 is electrically connected to the second node P, and the second electrode of the ninth transistor T9 is connected to the first reference low voltage.
  • flat signal VSSQ the gate of the tenth transistor T10 is electrically connected to the third node M, the first electrode of the tenth transistor T10 is electrically connected to the scanning signal G(N) of this level, and the second electrode of the tenth transistor T10 is electrically connected to the third node M.
  • the first reference low level signal VSSQ is input; the gate of the eleventh transistor T11 and the first electrode of the eleventh transistor T11 are both connected to the second clock signal CKN+1, and the second electrode of the eleventh transistor T11 is electrically Connected to the fourth node N; the gate of the twelfth transistor T12 is electrically connected to the fourth node N, the first electrode of the twelfth transistor T12 is connected to the second clock signal CKN+1, and the gate of the twelfth transistor T12 is connected to the fourth node N.
  • the two electrodes are electrically connected to the third node M; the gate of the thirteenth transistor T13 is electrically connected to the fifth node S, and the first electrode of the thirteenth transistor T13 is electrically connected to the fourth node N.
  • the second electrode of T13 is connected to the first reference low level signal VSSQ; the gate of the fourteenth transistor T14 is electrically connected to the fifth node S, and the first electrode of the fourteenth transistor T14 is electrically connected to the third node M.
  • the second electrode of the fourteenth transistor T14 is connected to the first reference low level signal VSSQ; the gate of the fifteenth transistor T15 is connected to the reset signal RESET, and the first electrode of the fifteenth transistor T15 is electrically connected to the fifth At node S, the second electrode of the fifteenth transistor T15 is connected to the first reference low level signal VSSQ.
  • the pull-up control module 101 includes a first transistor T1.
  • the gate of the first transistor T1 is connected to the upper level transmission signal ST(N-1), and the first electrode of the first transistor T1 is connected to the reference high level signal. VGH, the second electrode of the first transistor T1 is electrically connected to the first node Q.
  • the output module 102 includes a second transistor T2.
  • the gate of the second transistor T2 is electrically connected to the first node Q.
  • the first electrode of the second transistor T2 is connected to the first clock signal CK.
  • the electrode is electrically connected to the scanning signal G(N) of this level.
  • the cascade transmission module 103 includes a third transistor T3.
  • the gate of the third transistor T3 is electrically connected to the first node Q.
  • the first electrode of the third transistor T3 is connected to the first clock signal CK.
  • the two electrodes are electrically connected to the current stage transmission signal ST(N).
  • the potential of the first clock signal CK is opposite to the potential of the second clock signal CKN+1. Further, during operation, the start signal STV is input into the pull-up control module 101 of the first-level GOA unit and the pull-down module 104 of the last-level GOA unit.
  • FIG. 6 is a signal timing diagram of a GOA unit in the GOA circuit provided by the embodiment of the present application.
  • Figure 6 shows the GOA circuit of a set of clock control signals within one frame.
  • the high-frequency signal with a duty cycle of 50/50 is used.
  • clock signals with different duty cycles can be set as needed.
  • multiple sets of high-frequency clock signals can also be designed according to the load of the LCD panel. Specifically, the reset signal RESET is turned on to cause the first node Q to discharge.
  • the start signal STV is input into the pull-up control module 101 of the first-level GOA unit and the pull-down module 104 of the last-level GOA unit for charging the first node Q.
  • the start signal STV of the GOA circuit is responsible for starting the first-level GOA circuit, and the start signal STV of the N+1-th level GOA circuit is generated by the current-level level transmission signal ST(N) in the level transmission module 103 of the N-th level GOA circuit. ) is responsible for generating the signal, so that the GOA drive circuit can be turned on step by step to realize line scan driving.
  • the first clock signal CK and the second clock signal CKN+1 have opposite potentials.
  • the second clock signal CKN+1 is used to pull down the potential of the first node Q and the scanning signal G(N) of this level.
  • the first clock signal CK and the second clock signal CKN+1 are a set of high-frequency clock signals with the same high and low potentials and opposite phases.
  • the pulse width, period and high and low potentials of the clock signals mainly depend on the scanning signal of the liquid crystal display panel.
  • the first transistor T1 is turned on under the control of the ST(N-1) signal of the upper-level GOA circuit and the output signal G(N-1) signal of the upper-level Gate corresponding to the first electrode of the first transistor T1. level GOA circuit.
  • the potential rise of the waveform of the first node Q twice is mainly to ensure the normal output of the scanning signal G(N) of this level, and the first node Q is also responsible for closing the pull-down maintenance module 105 during the action of the Gate waveform output.
  • the potential of the first reference low level signal VSSQ and the second reference low level signal VSSG directly determines the potential of the first node Q and this stage.
  • the first reference low-level signal VSSQ and the second reference low-level signal VSSG are both DC negative voltage sources. Their main function is to keep the first node Q and the current level scanning signal G(N) in a stable off state during the non-output period. .
  • FIG. 7 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • the display panel includes a display area 100 and a GOA circuit 10 integrated in the display area 100 .
  • the structure and principle of the GOA circuit 10 are similar to the above-mentioned GOA circuit 10 and will not be described again here.

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Abstract

一种GOA电路（10）及显示面板，包括多级级联的GOA单元，每一级GOA单元均包括：上拉控制模块（101）、输出模块（102）、级传模块（103）、下拉模块（104）以及下拉维持模块（105）；GOA电路（10）结构简单，能够在保证电路功能的情况下缩小电路布局的空间，增加显示面板的开口率，满足显示面板窄边框及高分辨率的要求。

Description

GOA电路及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种GOA电路及显示面板。
 背景技术
现有液晶拼接屏需实现源极驱动侧及栅极驱动侧双边的侧印和印刷电路板的绑定，拼接时其单板模组仍需实现双边拼接，使得拼接风险及单板制程难度大，驱动和模组成本较高。
GOA(GateDriver on Array，集成栅极驱动电路)技术将栅极驱动电路集成在显示面板的阵列基板上，从而可以省掉栅极驱动集成电路部分。
因此，如何提供一种GOA电路，通过将该GOA电路集成于显示区域，使液晶拼接屏只需要单边侧印及拼接，并在保证电路功能的情况下缩小电路布局的空间，增加显示面板的开口率，满足显示面板窄边框及高分辨率的要求是现有面板厂家需要努力攻克的难关。
 技术问题
本申请实施例的目的在于提供一种GOA路及显示面板，该GOA电路结构简单，能够在保证电路功能的情况下缩小电路布局的空间，增加显示面板的开口率，满足显示面板窄边框及高分辨率的要求。
 技术解决方案
一方面，本申请实施例提供一种GOA电路，包括多级级联的GOA单元，每一级GOA单元均包括：上拉控制模块、输出模块、级传模块、下拉模块以及下拉维持模块；所述上拉控制模块，接入上一级级传信号以及参考高电平信号，并电性连接于第一节点，所述上拉控制模块用于在所述上一级级传信号的控制下将所述第一节点的电位拉高至所述参考高电平的电位；所述输出模块，接入第一时钟信号，并电性连接于所述第一节点以及所述本级扫描信号，所述输出模块用于在所述第一节点的电位控制下输出所述本级扫描信号；所述级传模块，接入所述第一时钟信号，并电性连接于所述第一节点以及本级级传信号，所述级传模块用于在所述第一节点的电位控制下输出所述本级级传信号；所述下拉模块，接入下一级扫描信号、所述本级级传信号、所述本级扫描信号、第一参考低电平信号以及第二参考低电平信号，并电性连接于第一节点、第二节点，所述下拉模块用于在所述下一级扫描信号的控制下拉低所述第一节点、所述第二节点以及所述本级级传信号的电位至所述第一参考低电平信号的电位，并拉低所述本级扫描信号的电位至所述第二参考低电平信号的电位；所述下拉维持模块，接入复位信号、第二时钟信号、所述本级扫描信号、所述第一参考低电平信号以及所述第二参考低电平信号，并电性连接于所述第一节点、所述第二节点，所述下拉维持模块用于在所述复位信号以及所述第二时钟信号的控制下使所述第一节点以及所述第二节点的电位保持在所述第一参考低电平信号的电位，并使所述本级扫描信号的电位保持在所述第二参考低电平信号的电位。
可选地，在本申请的一些实施例中，所述GOA单元还包括自举电容，所述自举电容的两端分别电性连接于所述第一节点与所述本级扫描信号，所述自举电容用于二次抬升所述第一节点的电位，确保所述本级扫描信号正常输出。
可选地，在本申请的一些实施例中，所述上拉控制模块包括第一晶体管，所述第一晶体管的栅极接入所述上一级级传信号，所述第一晶体管的第一电极接入所述参考高电平信号，所述第一晶体管的第二电极电性连接于所述第一节点。
可选地，在本申请的一些实施例中，所述输出模块包括第二晶体管，所述第二晶体管的栅极电性连接于所述第一节点，所述第二晶体管的第一电极接入所述第一时钟信号，所述第二晶体管的第二电极电性连接于所述本级扫描信号。
可选地，在本申请的一些实施例中，所述级传模块包括第三晶体管，所述第三晶体管的栅极电性连接于所述第一节点，所述第三晶体管的第一电极接入所述第一时钟信号，所述第三晶体管的第二电极电性连接于本级级传信号。
可选地，在本申请的一些实施例中，所述下拉模块包括第四晶体管、第五晶体管、第六晶体管以及第七晶体管，所述第四晶体管的栅极接入所述本级级传信号，所述第四晶体管的第一电极电性连接于所述本级扫描信号，所述第四晶体管的第二电极电性连接于所述第二节点；所述第五晶体管的栅极接入所述下一级扫描信号，所述第五晶体管的第一电极电性连接于所述本级扫描信号，所述第五晶体管的第二电极接入所述第二参考低电平信号；所述第六晶体管的栅极接入所述下一级扫描信号，所述第六晶体管的第一电极电性连接于所述第一节点，所述第六晶体管的第二电极电性连接于所述第二节点；所述第七晶体管的栅极接入所述下一级扫描信号，所述第七晶体管的第一电极电性连接于所述第二节点，所述第七晶体管的第二电极接入所述第一参考低电平信号。
可选地，在本申请的一些实施例中，所述下拉维持模块包括第八晶体管、第九晶体管、第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管以及第十五晶体管，所述第八晶体管的栅极电性连接于第三节点，所述第八晶体管的第一电极电性连接于所述第一节点，所述第八晶体管的第二电极电性连接于所述第二节点；所述第九晶体管的栅极电性连接于所述第三节点，所述第九晶体管的第一电极电性连接于所述第二节点，所述第九晶体管的第二电极接入所述第一参考低电平信号；所述第十晶体管的栅极电性连接于所述第三节点，所述第十晶体管的第一电极电性连接于所述本级扫描信号，所述第十晶体管的第二电极接入所述第二参考低电平信号；所述第十一晶体管的栅极和所述第十一晶体管的第一电极均接入所述第二时钟信号，所述第十一晶体管的第二电极电性连接于第四节点；所述第十二晶体管的栅极电性连接于所述第四节点，所述第十二晶体管的第一电极接入所述第二时钟信号，所述第十二晶体管的第二电极电性连接于所述第三节点；所述第十三晶体管的栅极电性连接于第五节点，所述第十三晶体管的第一电极电性连接于所述第四节点，所述第十三晶体管的第二电极接入所述第一参考低电平信号；所述第十四晶体管的栅极电性连接于所述第五节点，所述第十四晶体管的第一电极电性连接于所述第三节点，所述第十四晶体管的第二电极接入所述第一参考低电平信号；所述第十五晶体管的栅极接入所述复位信号，所述第十五晶体管的第一电极电性连接于所述第五节点，所述第十五晶体管的第二电极接入所述第一参考低电平信号。
可选地，在本申请的一些实施例中，所述第一时钟信号的电位与所述第二时钟信号的电位相反。
可选地，在本申请的一些实施例中，工作时，启动信号输入第一级GOA单元的所述上拉控制模块中以及最后一级GOA单元的所述下拉模块中。
可选地，在本申请的一些实施例中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第八晶体管、所述第九晶体管、所述第十晶体管、所述第十一晶体管、所述第十二晶体管、所述第十三晶体管、所述第十四晶体管、所述第十五晶体管为同类型晶体管。
另一方面，本申请提供一种显示面板，其包括显示区域以及集成设置在所述显示区域上的GOA电路，所述GOA电路包括：多级级联的GOA单元，每一级GOA单元均包括：上拉控制模块、输出模块、级传模块、下拉模块以及下拉维持模块；所述上拉控制模块，接入上一级级传信号以及参考高电平信号，并电性连接于第一节点，所述上拉控制模块用于在所述上一级级传信号的控制下将所述第一节点的电位拉高至所述参考高电平的电位；所述输出模块，接入第一时钟信号，并电性连接于所述第一节点以及所述本级扫描信号，所述输出模块用于在所述第一节点的电位控制下输出所述本级扫描信号；所述级传模块，接入所述第一时钟信号，并电性连接于所述第一节点以及本级级传信号，所述级传模块用于在所述第一节点的电位控制下输出所述本级级传信号；所述下拉模块，接入下一级扫描信号、所述本级级传信号、所述本级扫描信号、第一参考低电平信号以及第二参考低电平信号，并电性连接于第一节点、第二节点，所述下拉模块用于在所述下一级扫描信号的控制下拉低所述第一节点、所述第二节点以及所述本级级传信号的电位至所述第一参考低电平信号的电位，并拉低所述本级扫描信号的电位至所述第二参考低电平信号的电位；所述下拉维持模块，接入复位信号、第二时钟信号、所述本级扫描信号、所述第一参考低电平信号以及所述第二参考低电平信号，并电性连接于所述第一节点、所述第二节点，所述下拉维持模块用于在所述复位信号以及所述第二时钟信号的控制下使所述第一节点以及所述第二节点的电位保持在所述第一参考低电平信号的电位，并使所述本级扫描信号的电位保持在所述第二参考低电平信号的电位。
可选地，在本申请的一些实施例中，所述GOA单元还包括自举电容，所述自举电容的两端分别电性连接于所述第一节点与所述本级扫描信号，所述自举电容用于二次抬升所述第一节点的电位，确保所述本级扫描信号正常输出。
可选地，在本申请的一些实施例中，所述上拉控制模块包括第一晶体管，所述第一晶体管的栅极接入所述上一级级传信号，所述第一晶体管的第一电极接入所述参考高电平信号，所述第一晶体管的第二电极电性连接于所述第一节点。
可选地，在本申请的一些实施例中，所述输出模块包括第二晶体管，所述第二晶体管的栅极电性连接于所述第一节点，所述第二晶体管的第一电极接入所述第一时钟信号，所述第二晶体管的第二电极电性连接于所述本级扫描信号。
可选地，在本申请的一些实施例中，所述级传模块包括第三晶体管，所述第三晶体管的栅极电性连接于所述第一节点，所述第三晶体管的第一电极接入所述第一时钟信号，所述第三晶体管的第二电极电性连接于本级级传信号。
可选地，在本申请的一些实施例中，所述下拉模块包括第四晶体管、第五晶体管、第六晶体管以及第七晶体管，所述第四晶体管的栅极接入所述本级级传信号，所述第四晶体管的第一电极电性连接于所述本级扫描信号，所述第四晶体管的第二电极电性连接于所述第二节点；所述第五晶体管的栅极接入所述下一级扫描信号，所述第五晶体管的第一电极电性连接于所述本级扫描信号，所述第五晶体管的第二电极接入所述第二参考低电平信号；所述第六晶体管的栅极接入所述下一级扫描信号，所述第六晶体管的第一电极电性连接于所述第一节点，所述第六晶体管的第二电极电性连接于所述第二节点；所述第七晶体管的栅极接入所述下一级扫描信号，所述第七晶体管的第一电极电性连接于所述第二节点，所述第七晶体管的第二电极接入所述第一参考低电平信号。
可选地，在本申请的一些实施例中，所述下拉维持模块包括第八晶体管、第九晶体管、第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管以及第十五晶体管，所述第八晶体管的栅极电性连接于第三节点，所述第八晶体管的第一电极电性连接于所述第一节点，所述第八晶体管的第二电极电性连接于所述第二节点；所述第九晶体管的栅极电性连接于所述第三节点，所述第九晶体管的第一电极电性连接于所述第二节点，所述第九晶体管的第二电极接入所述第一参考低电平信号；所述第十晶体管的栅极电性连接于所述第三节点，所述第十晶体管的第一电极电性连接于所述本级扫描信号，所述第十晶体管的第二电极接入所述第二参考低电平信号；所述第十一晶体管的栅极和所述第十一晶体管的第一电极均接入所述第二时钟信号，所述第十一晶体管的第二电极电性连接于第四节点；所述第十二晶体管的栅极电性连接于所述第四节点，所述第十二晶体管的第一电极接入所述第二时钟信号，所述第十二晶体管的第二电极电性连接于所述第三节点；所述第十三晶体管的栅极电性连接于第五节点，所述第十三晶体管的第一电极电性连接于所述第四节点，所述第十三晶体管的第二电极接入所述第一参考低电平信号；所述第十四晶体管的栅极电性连接于所述第五节点，所述第十四晶体管的第一电极电性连接于所述第三节点，所述第十四晶体管的第二电极接入所述第一参考低电平信号；所述第十五晶体管的栅极接入所述复位信号，所述第十五晶体管的第一电极电性连接于所述第五节点，所述第十五晶体管的第二电极接入所述第一参考低电平信号。
可选地，在本申请的一些实施例中，所述第一时钟信号的电位与所述第二时钟信号的电位相反。
可选地，在本申请的一些实施例中，工作时，启动信号输入第一级GOA单元的所述上拉控制模块中以及最后一级GOA单元的所述下拉模块中。
可选地，在本申请的一些实施例中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第八晶体管、所述第九晶体管、所述第十晶体管、所述第十一晶体管、所述第十二晶体管、所述第十三晶体管、所述第十四晶体管、所述第十五晶体管为同类型晶体管。
 有益效果
在本申请实施例提供的GOA电路及显示面板中，本申请实施例提供一种GOA电路，包括多级级联的GOA单元，每一级GOA单元均包括：上拉控制模块、输出模块、级传模块、下拉模块以及下拉维持模块。该GOA电路结构简单，能够在保证电路功能的情况下缩小电路布局的空间，增加显示面板的开口率，满足显示面板窄边框及高分辨率的要求。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的GOA电路的结构示意图；
图2为本申请实施例提供的GOA电路中一GOA单元的第一种实施方式的结构示意图；
图3为本申请实施例提供的GOA电路中一GOA单元的第一种实施方式的电路示意图；
图4为本申请实施例提供的GOA电路中一GOA单元的第二种实施方式的结构示意图；
图5为本申请实施例提供的GOA电路中一GOA单元的第二种实施方式的电路示意图；
图6为本申请实施例提供的GOA电路中一GOA单元的信号时序图；
图7为本申请实施例提供的显示面板的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请实施例提供一种GOA电路及显示面板，该GOA电路结构简单，能够在保证电路功能的情况下缩小电路布局的空间，增加显示面板的开口率，满足显示面板窄边框及高分辨率的要求。以下分别进行详细说明。需说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。另外，在本申请的描述中，术语“包括”是指“包括但不限于”。术语“第一”、“第二”、“第三”等仅仅作为标示使用，其用于区别不同对象，而不是用于描述特定顺序。
本申请所有实施例中采用的晶体管可以为薄膜晶体管或场效应管或其他特性相同的器件，由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本申请实施例中，为区分晶体管除栅极之外的两极，将源极与漏极中的一者称为第一电极，将源极和漏极中的另一者称为第二电极。按附图中的形态规定开关晶体管的中间端为栅极、信号输入端为第一电极、输出端为第二电极。此外本申请实施例所采用的晶体管为N型晶体管或P型晶体管，其中，N型晶体管为在栅极为高电位时导通，在栅极为低电位时截止；P型晶体管为在栅极为低电位时导通，在栅极为高电位时截止。
请参阅图1，图1为本申请实施例提供的GOA电路的结构示意图。如图1所示，本申请实施例提供的GOA电路包括多级级联的GOA单元。图1以级联的第N-1级GOA单元、第N级GOA单元和第N+1级GOA单元为例。
当第N级GOA单元工作时，第N级GOA单元输出的扫描信号为高电位，用于打开显示面板中一行中每个像素的晶体管开关，并通过数据信号对每个像素中的像素电极进行充电；第N级级传信号用于控制第N+1级GOA单元的工作；当第N+1级GOA单元工作时，第N+1级GOA单元输出的扫描信号为高电位，同时第N级GOA单元输出的扫描信号为低电位。
请参阅图2，图2为本申请实施例提供的GOA电路中一GOA单元的第一种实施方式的结构示意图。如图2所示，该GOA单元包括：上拉控制模块101、输出模块102、级传模块103、下拉模块104、下拉维持模块105。
其中，上拉控制模块101接入上一级级传信号ST(N-1)以及参考高电平信号VGH，并电性连接于第一节点Q，上拉控制模块101用于在上一级级传信号ST(N-1)的控制下将第一节点Q的电位拉高至参考高电平的电位。
其中，输出模块102，接入第一时钟信号CK，并电性连接于第一节点Q以及本级扫描信号G(N)，输出模块102用于在第一节点Q的电位控制下输出本级扫描信号G(N)。
其中，级传模块103，接入第一时钟信号CK，并电性连接于第一节点Q以及本级级传信号ST(N)，级传模块103用于在第一节点Q的电位控制下输出本级级传信号ST(N)。
其中，下拉模块104，接入下一级扫描信号G(N+1)、本级级传信号ST(N)、本级扫描信号G(N)、第一参考低电平信号VSSQ以及第二参考低电平信号VSSG，并电性连接于第一节点Q、第二节点P，下拉模块104用于在下一级扫描信号G(N+1)的控制下拉低第一节点Q、第二节点P以及本级级传信号ST(N)至第一参考低电平信号VSSQ的电位，并拉低本级扫描信号G(N)至第二参考低电平信号VSSG的电位。
其中，下拉维持模块105，接入复位信号RESET、第二时钟信号CKN+1、本级扫描信号G(N)、第一参考低电平信号VSSQ以及第二参考低电平信号VSSG，并电性连接于第一节点Q、第二节点P，下拉维持模块105用于在复位信号RESET以及第二时钟信号CKN+1的控制下使第一节点Q以及第二节点P的电位保持在第一参考低电平信号VSSQ的电位，并使本级扫描信号G(N)的电位保持在第二参考低电平信号VSSG的电位。
其中，GOA单元还包括自举电容C st，自举电容C st的两端分别电性连接于第一节点Q与本级扫描信号G(N)，自举电容C st用于二次抬升第一节点Q的电位，确保本级扫描信号G(N)正常输出。
本申请提供的GOA电路结构简单，能够在保证电路功能的情况下缩小电路布局的空间，增加显示面板的开口率，满足显示面板窄边框及高分辨率的要求。
另外，由于将本申请的GOA电路放置于显示区内部，信号数目简单，可以减少信号之间的串扰，同时可搭配高迁移率的器件，且器件数量较少，尺寸较小，因而大幅度减少了GOA电路设计空间，从而可以加大关键器件的大小，比如可以增大输出模块102中器件的大小，从而保证大尺寸高清窄边框液晶显示面板的推力。
请参阅图3，图3为本申请实施例提供的GOA电路中一GOA单元的第一种实施方式的电路示意图。如图3所示，上拉控制模块101包括第一晶体管T1，第一晶体管T1的栅极接入上一级级传信号ST(N-1)，第一晶体管T1的第一电极接入参考高电平信号VGH，第一晶体管T1的第二电极电性连接于第一节点Q。
其中，输出模块102包括第二晶体管T2，第二晶体管T2的栅极电性连接于第一节点Q，第二晶体管T2的第一电极接入第一时钟信号CK，第二晶体管T2的第二电极电性连接于本级扫描信号G(N)。
其中，级传模块103包括第三晶体管T3，第三晶体管T3的栅极电性连接于第一节点Q，第三晶体管T3的第一电极接入第一时钟信号CK，第三晶体管T3的第二电极电性连接于本级级传信号ST(N)。
其中，下拉模块104包括第四晶体管T4、第五晶体管T5、第六晶体管T6以及第七晶体管T7，第四晶体管T4的栅极接入本级级传信号ST(N)，第四晶体管T4的第一电极电性连接于本级扫描信号G(N)，第四晶体管T4的第二电极电性连接于第二节点P；第五晶体管T5的栅极接入下一级扫描信号G(N+1)，第五晶体管T5的第一电极电性连接于本级扫描信号G(N)，第五晶体管T5的第二电极接入第二参考低电平信号VSSG；第六晶体管T6的栅极接入下一级扫描信号G(N+1)，第六晶体管T6的第一电极电性连接于第一节点Q，第六晶体管T6的第二电极电性连接于第二节点P；第七晶体管T7的栅极接入下一级扫描信号G(N+1)，第七晶体管T7的第一电极电性连接于第二节点P，第七晶体管T7的第二电极接入第一参考低电平信号VSSQ。
其中，下拉维持模块105包括第八晶体管T8、第九晶体管T9、第十晶体管T10、第十一晶体管T11、第十二晶体管T12、第十三晶体管T13、第十四晶体管T14以及第十五晶体管T15，第八晶体管T8的栅极电性连接于第三节点M，第八晶体管T8的第一电极电性连接于第一节点Q，第八晶体管T8的第二电极电性连接于第二节点P；第九晶体管T9的栅极电性连接于第三节点M，第九晶体管T9的第一电极电性连接于第二节点P，第九晶体管T9的第二电极接入第一参考低电平信号VSSQ；第十晶体管T10的栅极电性连接于第三节点M，第十晶体管T10的第一电极电性连接于本级扫描信号G(N)，第十晶体管T10的第二电极接入第二参考低电平信号VSSG；第十一晶体管T11的栅极和第十一晶体管T11的第一电极均接入第二时钟信号CKN+1，第十一晶体管T11的第二电极电性连接于第四节点N；第十二晶体管T12的栅极电性连接于第四节点N，第十二晶体管T12的第一电极接入第二时钟信号CKN+1，第十二晶体管T12的第二电极电性连接于第三节点M；第十三晶体管T13的栅极电性连接于第五节点S，第十三晶体管T13的第一电极电性连接于第四节点N，第十三晶体管T13的第二电极接入第一参考低电平信号VSSQ；第十四晶体管T14的栅极电性连接于第五节点S，第十四晶体管T14的第一电极电性连接于第三节点M，第十四晶体管T14的第二电极接入第一参考低电平信号VSSQ；第十五晶体管T15的栅极接入复位信号RESET，第十五晶体管T15的第一电极电性连接于第五节点S，第十五晶体管T15的第二电极接入第一参考低电平信号VSSQ。
其中，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9、第十晶体管T10、第十一晶体管T11、第十二晶体管T12、第十三晶体管T13、第十四晶体管T14、第十五晶体管T15为同类型晶体管。
其中，第一时钟信号CK的电位与第二时钟信号CKN+1的电位相反。
具体地，工作时，启动信号STV输入第一级GOA单元的上拉控制模块101中以及最后一级GOA单元的下拉模块104中。
具体的，请参阅图4，图4为本申请实施例提供的GOA电路中一GOA单元的第二种实施方式的结构示意图。如图4所示，下拉模块104与下拉维持模块105均接入第一参考低电平信号VSSQ。
具体地，下拉模块104接入下一级扫描信号G(N+1)、本级级传信号ST(N)、本级扫描信号G(N)、第一参考低电平信号VSSQ，并电性连接于第一节点Q、第二节点P，下拉模块104用于在下一级扫描信号G(N+1)的控制下拉低第一节点Q、第二节点P、本级级传信号ST(N)以及本级扫描信号G(N)的电位至第一参考低电平信号VSSQ的电位。
其中，下拉维持模块105接入复位信号RESET、第二时钟信号CKN+1、本级扫描信号G(N)、第一参考低电平信号VSSQ，并电性连接于第一节点Q、第二节点P，下拉维持模块105用于在复位信号RESET以及第二时钟信号CKN+1的控制下使第一节点Q、第二节点P以及本级扫描信号G(N)的电位保持在第一参考低电平信号VSSQ的电位。
其中，上拉控制模块101接入上一级级传信号ST(N-1)以及参考高电平信号VGH，并电性连接于第一节点Q，上拉控制模块101用于在上一级级传信号ST(N-1)的控制下将第一节点Q的电位拉高至参考高电平的电位。
其中，输出模块102，接入第一时钟信号CK，并电性连接于第一节点Q以及本级扫描信号G(N)，输出模块102用于在第一节点Q的电位控制下输出本级扫描信号G(N)。
其中，级传模块103，接入第一时钟信号CK，并电性连接于第一节点Q以及本级级传信号ST(N)，级传模块103用于在第一节点Q的电位控制下输出本级级传信号ST(N)。
其中，GOA单元还包括自举电容C st，自举电容C st的两端分别电性连接于第一节点Q与本级扫描信号G(N)，自举电容C st用于二次抬升第一节点Q的电位，确保本级扫描信号G(N)正常输出。
需要说明的是，本申请实施例提供的下拉维持模块105和下拉模块104均电性连接于第一参考低电平信号VSSQ，从而可以进一步简化GOA电路的结构，减少信号数目，进而进一步减少信号之间的串扰，同时减少了GOA电路设计空间，增加显示面板的开口率，满足显示面板窄边框及高分辨率的要求。
具体的，请参阅图5，图5为本申请实施例提供的GOA电路中一GOA单元的第二种实施方式的电路示意图。如图5所示，下拉模块104包括第四晶体管T4、第五晶体管T5、第六晶体管T6以及第七晶体管T7，第四晶体管T4的栅极接入本级级传信号ST(N)，第四晶体管T4的第一电极电性连接于本级扫描信号G(N)，第四晶体管T4的第二电极电性连接于第二节点P；第五晶体管T5的栅极接入下一级扫描信号G(N+1)，第五晶体管T5的第一电极电性连接于本级扫描信号G(N)，第五晶体管T5的第二电极接入第一参考低电平信号VSSQ；第六晶体管T6的栅极接入下一级扫描信号G(N+1)，第六晶体管T6的第一电极电性连接于第一节点Q，第六晶体管T6的第二电极电性连接于第二节点P；第七晶体管T7的栅极接入下一级扫描信号G(N+1)，第七晶体管T7的第一电极电性连接于第二节点P，第七晶体管T7的第二电极接入第一参考低电平信号VSSQ。
其中，下拉维持模块105包括第八晶体管T8、第九晶体管T9、第十晶体管T10、第十一晶体管T11、第十二晶体管T12、第十三晶体管T13、第十四晶体管T14以及第十五晶体管T15，第八晶体管T8的栅极电性连接于第三节点M，第八晶体管T8的第一电极电性连接于第一节点Q，第八晶体管T8的第二电极电性连接于第二节点P；第九晶体管T9的栅极电性连接于第三节点M，第九晶体管T9的第一电极电性连接于第二节点P，第九晶体管T9的第二电极接入第一参考低电平信号VSSQ；第十晶体管T10的栅极电性连接于第三节点M，第十晶体管T10的第一电极电性连接于本级扫描信号G(N)，第十晶体管T10的第二电极接入第一参考低电平信号VSSQ；第十一晶体管T11的栅极和第十一晶体管T11的第一电极均接入第二时钟信号CKN+1，第十一晶体管T11的第二电极电性连接于第四节点N；第十二晶体管T12的栅极电性连接于第四节点N，第十二晶体管T12的第一电极接入第二时钟信号CKN+1，第十二晶体管T12的第二电极电性连接于第三节点M；第十三晶体管T13的栅极电性连接于第五节点S，第十三晶体管T13的第一电极电性连接于第四节点N，第十三晶体管T13的第二电极接入第一参考低电平信号VSSQ；第十四晶体管T14的栅极电性连接于第五节点S，第十四晶体管T14的第一电极电性连接于第三节点M，第十四晶体管T14的第二电极接入第一参考低电平信号VSSQ；第十五晶体管T15的栅极接入复位信号RESET，第十五晶体管T15的第一电极电性连接于第五节点S，第十五晶体管T15的第二电极接入第一参考低电平信号VSSQ。
其中，上拉控制模块101包括第一晶体管T1，第一晶体管T1的栅极接入上一级级传信号ST(N-1)，第一晶体管T1的第一电极接入参考高电平信号VGH，第一晶体管T1的第二电极电性连接于第一节点Q。
其中，输出模块102包括第二晶体管T2，第二晶体管T2的栅极电性连接于第一节点Q，第二晶体管T2的第一电极接入第一时钟信号CK，第二晶体管T2的第二电极电性连接于本级扫描信号G(N)。
其中，级传模块103包括第三晶体管T3，第三晶体管T3的栅极电性连接于第一节点Q，第三晶体管T3的第一电极接入第一时钟信号CK，第三晶体管T3的第二电极电性连接于本级级传信号ST(N)。
其中，第一时钟信号CK的电位与第二时钟信号CKN+1的电位相反。进一步地，工作时启动信号STV输入第一级GOA单元的上拉控制模块101中以及最后一级GOA单元的下拉模块104中。
请参阅图6，图6为本申请实施例提供的GOA电路中一GOA单元的信号时序图。图6中示意的是一帧时间内一组时钟控制信号的GOA电路，采用的占空比为50/50的高频信号，在实际液晶显示器中可以根据需要设定不同占空比的时钟信号进行GOA电路的驱动，也可以根据液晶显示器面板的负载设计多组高频时钟信号。具体地，复位信号RESET接入使得第一节点Q放电。启动信号STV输入第一级GOA单元的上拉控制模块101中以及最后一级GOA单元的下拉模块104中，用于给第一节点Q充电。
具体地，GOA电路的启动信号STV负责启动第一级GOA电路，而第N+1级GOA电路的启动信号STV由第N级GOA电路的级传模块103中的本级级传信号ST(N)的信号负责产生，这样就可以逐级打开GOA驱动电路，实现行扫描驱动。
其中，第一时钟信号CK与第二时钟信号CKN+1的电位相反。其中，第二时钟信号CKN+1用于拉低第一节点Q和本级扫描信号G（N）的电位。具体地，第一时钟信号CK与第二时钟信号CKN+1为一组高低电位相同、相位相反的高频时钟信号，时钟信号的脉冲宽度、周期以及高低电位主要取决于液晶显示面板的扫描信号波形的设计需要，因此在实际液晶显示器应用中不一定是如图所示的占空比为50/50的信号，而且有时候根据面板设计的需要会采用不同数量的时钟信号来承受不同设计需要的负载。
其中，第一晶体管T1在上一级GOA电路的ST(N-1)信号以及第一晶体管T1的第一电极对应的上一级Gate的输出信号G(N-1)信号控制下开启第N级的GOA电路。
其中，第一节点Q的波形存在两次的电位抬升主要是为了确保所述本级扫描信号G(N)正常输出，而且第一节点Q还负责在Gate波形输出的作用期间关闭下拉维持模块105对第一节点Q和本级扫描信号G(N)的影响，而这一期间第一参考低电平信号VSSQ和第二参考低电平信号VSSG的电位直接决定了第一节点Q和本级扫描信号G(N)的输出波形。第一参考低电平信号VSSQ和第二参考低电平信号VSSG均为直流负压源，主要作用是保持第一节点Q和本级扫描信号G(N)非输出期间有一个稳定的关闭状态。
请参阅图7，图7为本申请实施例提供的显示面板的结构示意图。如图7所示，该显示面板包括显示区域100以及集成设置在显示区域100上的GOA电路10；其中，该GOA电路10与上述的GOA电路10的结构和原理类似，这里不再赘述。
以上对本申请实施例所提供的一种GOA电路及显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种GOA电路，其包括多级级联的GOA单元，每一级GOA单元均包括：上拉控制模块、输出模块、级传模块、下拉模块以及下拉维持模块；
    所述上拉控制模块，接入上一级级传信号以及参考高电平信号，并电性连接于第一节点，所述上拉控制模块用于在所述上一级级传信号的控制下将所述第一节点的电位拉高至所述参考高电平的电位；
    所述输出模块，接入第一时钟信号，并电性连接于所述第一节点以及所述本级扫描信号，所述输出模块用于在所述第一节点的电位控制下输出所述本级扫描信号；
    所述级传模块，接入所述第一时钟信号，并电性连接于所述第一节点以及本级级传信号，所述级传模块用于在所述第一节点的电位控制下输出所述本级级传信号；
    所述下拉模块，接入下一级扫描信号、所述本级级传信号、所述本级扫描信号、第一参考低电平信号以及第二参考低电平信号，并电性连接于第一节点、第二节点，所述下拉模块用于在所述下一级扫描信号的控制下拉低所述第一节点、所述第二节点以及所述本级级传信号的电位至所述第一参考低电平信号的电位，并拉低所述本级扫描信号的电位至所述第二参考低电平信号的电位；
    所述下拉维持模块，接入复位信号、第二时钟信号、所述本级扫描信号、所述第一参考低电平信号以及所述第二参考低电平信号，并电性连接于所述第一节点、所述第二节点，所述下拉维持模块用于在所述复位信号以及所述第二时钟信号的控制下使所述第一节点以及所述第二节点的电位保持在所述第一参考低电平信号的电位，并使所述本级扫描信号的电位保持在所述第二参考低电平信号的电位。
  2. 根据权利要求1所述的GOA电路，其中，所述GOA单元还包括自举电容，所述自举电容的两端分别电性连接于所述第一节点与所述本级扫描信号，所述自举电容用于二次抬升所述第一节点的电位，确保所述本级扫描信号正常输出。
  3. 根据权利要求2所述的GOA电路，其中，所述上拉控制模块包括第一晶体管，所述第一晶体管的栅极接入所述上一级级传信号，所述第一晶体管的第一电极接入所述参考高电平信号，所述第一晶体管的第二电极电性连接于所述第一节点。
  4. 根据权利要求3所述的GOA电路，其中，所述输出模块包括第二晶体管，所述第二晶体管的栅极电性连接于所述第一节点，所述第二晶体管的第一电极接入所述第一时钟信号，所述第二晶体管的第二电极电性连接于所述本级扫描信号。
  5. 根据权利要求4所述的GOA电路，其中，所述级传模块包括第三晶体管，所述第三晶体管的栅极电性连接于所述第一节点，所述第三晶体管的第一电极接入所述第一时钟信号，所述第三晶体管的第二电极电性连接于本级级传信号。
  6. 根据权利要求5所述的GOA电路，其中，所述下拉模块包括第四晶体管、第五晶体管、第六晶体管以及第七晶体管，所述第四晶体管的栅极接入所述本级级传信号，所述第四晶体管的第一电极电性连接于所述本级扫描信号，所述第四晶体管的第二电极电性连接于所述第二节点；
    所述第五晶体管的栅极接入所述下一级扫描信号，所述第五晶体管的第一电极电性连接于所述本级扫描信号，所述第五晶体管的第二电极接入所述第二参考低电平信号；
    所述第六晶体管的栅极接入所述下一级扫描信号，所述第六晶体管的第一电极电性连接于所述第一节点，所述第六晶体管的第二电极电性连接于所述第二节点；
    所述第七晶体管的栅极接入所述下一级扫描信号，所述第七晶体管的第一电极电性连接于所述第二节点，所述第七晶体管的第二电极接入所述第一参考低电平信号。
  7. 根据权利要求6所述的GOA电路，其中，所述下拉维持模块包括第八晶体管、第九晶体管、第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管以及第十五晶体管，所述第八晶体管的栅极电性连接于第三节点，所述第八晶体管的第一电极电性连接于所述第一节点，所述第八晶体管的第二电极电性连接于所述第二节点；
    所述第九晶体管的栅极电性连接于所述第三节点，所述第九晶体管的第一电极电性连接于所述第二节点，所述第九晶体管的第二电极接入所述第一参考低电平信号；
    所述第十晶体管的栅极电性连接于所述第三节点，所述第十晶体管的第一电极电性连接于所述本级扫描信号，所述第十晶体管的第二电极接入所述第二参考低电平信号；
    所述第十一晶体管的栅极和所述第十一晶体管的第一电极均接入所述第二时钟信号，所述第十一晶体管的第二电极电性连接于第四节点；
    所述第十二晶体管的栅极电性连接于所述第四节点，所述第十二晶体管的第一电极接入所述第二时钟信号，所述第十二晶体管的第二电极电性连接于所述第三节点；
    所述第十三晶体管的栅极电性连接于第五节点，所述第十三晶体管的第一电极电性连接于所述第四节点，所述第十三晶体管的第二电极接入所述第一参考低电平信号；
    所述第十四晶体管的栅极电性连接于所述第五节点，所述第十四晶体管的第一电极电性连接于所述第三节点，所述第十四晶体管的第二电极接入所述第一参考低电平信号；
    所述第十五晶体管的栅极接入所述复位信号，所述第十五晶体管的第一电极电性连接于所述第五节点，所述第十五晶体管的第二电极接入所述第一参考低电平信号。
  8. 根据权利要求1所述的GOA电路，其中，所述第一时钟信号的电位与所述第二时钟信号的电位相反。
  9. 根据权利要求1所述的GOA电路，其中，工作时，启动信号输入第一级GOA单元的所述上拉控制模块中以及最后一级GOA单元的所述下拉模块中。
  10. 根据权利要求7所述的GOA电路，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第八晶体管、所述第九晶体管、所述第十晶体管、所述第十一晶体管、所述第十二晶体管、所述第十三晶体管、所述第十四晶体管、所述第十五晶体管为同类型晶体管。
  11. 一种显示面板，其包括显示区域以及集成设置在所述显示区域上的GOA电路，所述GOA电路包括：多级级联的GOA单元，每一级GOA单元均包括：上拉控制模块、输出模块、级传模块、下拉模块以及下拉维持模块；
    所述上拉控制模块，接入上一级级传信号以及参考高电平信号，并电性连接于第一节点，所述上拉控制模块用于在所述上一级级传信号的控制下将所述第一节点的电位拉高至所述参考高电平的电位；
    所述输出模块，接入第一时钟信号，并电性连接于所述第一节点以及所述本级扫描信号，所述输出模块用于在所述第一节点的电位控制下输出所述本级扫描信号；
    所述级传模块，接入所述第一时钟信号，并电性连接于所述第一节点以及本级级传信号，所述级传模块用于在所述第一节点的电位控制下输出所述本级级传信号；
    所述下拉模块，接入下一级扫描信号、所述本级级传信号、所述本级扫描信号、第一参考低电平信号以及第二参考低电平信号，并电性连接于第一节点、第二节点，所述下拉模块用于在所述下一级扫描信号的控制下拉低所述第一节点、所述第二节点以及所述本级级传信号的电位至所述第一参考低电平信号的电位，并拉低所述本级扫描信号的电位至所述第二参考低电平信号的电位；
    所述下拉维持模块，接入复位信号、第二时钟信号、所述本级扫描信号、所述第一参考低电平信号以及所述第二参考低电平信号，并电性连接于所述第一节点、所述第二节点，所述下拉维持模块用于在所述复位信号以及所述第二时钟信号的控制下使所述第一节点以及所述第二节点的电位保持在所述第一参考低电平信号的电位，并使所述本级扫描信号的电位保持在所述第二参考低电平信号的电位。
  12. 根据权利要求11所述的显示面板，其中，所述GOA单元还包括自举电容，所述自举电容的两端分别电性连接于所述第一节点与所述本级扫描信号，所述自举电容用于二次抬升所述第一节点的电位，确保所述本级扫描信号正常输出。
  13. 根据权利要求12所述的显示面板，其中，所述上拉控制模块包括第一晶体管，所述第一晶体管的栅极接入所述上一级级传信号，所述第一晶体管的第一电极接入所述参考高电平信号，所述第一晶体管的第二电极电性连接于所述第一节点。
  14. 根据权利要求13所述的显示面板，其中，所述输出模块包括第二晶体管，所述第二晶体管的栅极电性连接于所述第一节点，所述第二晶体管的第一电极接入所述第一时钟信号，所述第二晶体管的第二电极电性连接于所述本级扫描信号。
  15. 根据权利要求14所述的显示面板，其中，所述级传模块包括第三晶体管，所述第三晶体管的栅极电性连接于所述第一节点，所述第三晶体管的第一电极接入所述第一时钟信号，所述第三晶体管的第二电极电性连接于本级级传信号。
  16. 根据权利要求15所述的显示面板，其中，所述下拉模块包括第四晶体管、第五晶体管、第六晶体管以及第七晶体管，所述第四晶体管的栅极接入所述本级级传信号，所述第四晶体管的第一电极电性连接于所述本级扫描信号，所述第四晶体管的第二电极电性连接于所述第二节点；
    所述第五晶体管的栅极接入所述下一级扫描信号，所述第五晶体管的第一电极电性连接于所述本级扫描信号，所述第五晶体管的第二电极接入所述第二参考低电平信号；
    所述第六晶体管的栅极接入所述下一级扫描信号，所述第六晶体管的第一电极电性连接于所述第一节点，所述第六晶体管的第二电极电性连接于所述第二节点；
    所述第七晶体管的栅极接入所述下一级扫描信号，所述第七晶体管的第一电极电性连接于所述第二节点，所述第七晶体管的第二电极接入所述第一参考低电平信号。
  17. 根据权利要求16所述的显示面板，其中，所述下拉维持模块包括第八晶体管、第九晶体管、第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管以及第十五晶体管，所述第八晶体管的栅极电性连接于第三节点，所述第八晶体管的第一电极电性连接于所述第一节点，所述第八晶体管的第二电极电性连接于所述第二节点；
    所述第九晶体管的栅极电性连接于所述第三节点，所述第九晶体管的第一电极电性连接于所述第二节点，所述第九晶体管的第二电极接入所述第一参考低电平信号；
    所述第十晶体管的栅极电性连接于所述第三节点，所述第十晶体管的第一电极电性连接于所述本级扫描信号，所述第十晶体管的第二电极接入所述第二参考低电平信号；
    所述第十一晶体管的栅极和所述第十一晶体管的第一电极均接入所述第二时钟信号，所述第十一晶体管的第二电极电性连接于第四节点；
    所述第十二晶体管的栅极电性连接于所述第四节点，所述第十二晶体管的第一电极接入所述第二时钟信号，所述第十二晶体管的第二电极电性连接于所述第三节点；
    所述第十三晶体管的栅极电性连接于第五节点，所述第十三晶体管的第一电极电性连接于所述第四节点，所述第十三晶体管的第二电极接入所述第一参考低电平信号；
    所述第十四晶体管的栅极电性连接于所述第五节点，所述第十四晶体管的第一电极电性连接于所述第三节点，所述第十四晶体管的第二电极接入所述第一参考低电平信号；
    所述第十五晶体管的栅极接入所述复位信号，所述第十五晶体管的第一电极电性连接于所述第五节点，所述第十五晶体管的第二电极接入所述第一参考低电平信号。
  18. 根据权利要求11所述的显示面板，其中，所述第一时钟信号的电位与所述第二时钟信号的电位相反。
  19. 根据权利要求11所述的显示面板，其中，工作时，启动信号输入第一级GOA单元的所述上拉控制模块中以及最后一级GOA单元的所述下拉模块中。
  20. 根据权利要求17所述的显示面板，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第八晶体管、所述第九晶体管、所述第十晶体管、所述第十一晶体管、所述第十二晶体管、所述第十三晶体管、所述第十四晶体管、所述第十五晶体管为同类型晶体管。
PCT/CN2022/092709 2022-04-27 2022-05-13 Goa电路及显示面板 WO2023206624A1 (zh)

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