WO2020206663A1 - 一种共模抑制的封装装置和印制电路板 - Google Patents

一种共模抑制的封装装置和印制电路板 Download PDF

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Publication number
WO2020206663A1
WO2020206663A1 PCT/CN2019/082335 CN2019082335W WO2020206663A1 WO 2020206663 A1 WO2020206663 A1 WO 2020206663A1 CN 2019082335 W CN2019082335 W CN 2019082335W WO 2020206663 A1 WO2020206663 A1 WO 2020206663A1
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WIPO (PCT)
Prior art keywords
signal
layer
plane
common mode
via hole
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Application number
PCT/CN2019/082335
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English (en)
French (fr)
Inventor
马超
范文锴
蔡树杰
Original Assignee
华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP19923992.2A priority Critical patent/EP3937596A4/en
Priority to CN201980094286.5A priority patent/CN113678574B/zh
Priority to PCT/CN2019/082335 priority patent/WO2020206663A1/zh
Publication of WO2020206663A1 publication Critical patent/WO2020206663A1/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0245—Lay-out of balanced signal pairs, e.g. differential lines or twisted lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P3/00—Waveguides; Transmission lines of the waveguide type
    • H01P3/02—Waveguides; Transmission lines of the waveguide type with two longitudinal conductors
    • H01P3/08—Microstrips; Strip lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array

Definitions

  • This application relates to the field of semiconductors, in particular to the field of common mode noise suppression.
  • differential interconnection lines For data with a rate of the order of Gbps, the industry usually adopts differential signal transmission technology to improve the signal's immunity to noise and suppress clock misalignment. Compared with a single interconnection line, a differential interconnection line has excellent noise immunity, robustness to discontinuous return paths, and electromagnetic interference cancellation characteristics. Based on the above characteristics, differential interconnection lines are widely used in basic standards for high-speed links.
  • the signal transmitted on the differential interconnection line includes not only the differential signal, but also the common mode signal (ie common mode noise).
  • the differential signal refers to the signal difference between the two signal lines of the differential interconnection line
  • the common mode signal refers to the above two signal lines.
  • the noise of a signal line to the ground is represented by the average voltage of two differential signals on the differential interconnection line.
  • the deviation of the driver of the differential interconnection line from the ideal state will cause the signal transmitted on the differential interconnection line to have a deviation in time.
  • factors such as line length differences, etch changes, proximity effects, and wire bending will cause the asymmetry of the differential interconnection line, resulting in common mode noise, which in turn causes signal integrity, power integrity and electromagnetic interference in high-speed circuit systems. problem.
  • FIG. 1 is a schematic diagram of a signal layer of a package device 100 for suppressing common mode noise in the prior art.
  • the packaging device 100 includes a pair of differential signal lines (differential interconnection lines) arranged in parallel in the signal layer of the packaging device 100, namely, a positive differential line 120 and a negative differential line 130.
  • the filter wiring 140 is arranged between the two differential signal lines, and its length is 1/2 of the wavelength corresponding to the noise to be filtered.
  • the midpoint of the filter trace 140 is also provided with a ground via 150 for connecting with the reference ground plane of the package device 100. In the area where the filter trace 140 is provided, the spacing between the positive differential line 120 and the negative differential line 130 is widened to provide a wiring space for the filter trace 140.
  • the packaging device 100 shown in FIG. 1 has good filtering characteristics in a certain frequency band, it has high requirements for the control of the processing technology, and the filter trace 140 and the ground via 150 occupy a large amount of physical space, which is not conducive to the packaging device 100 miniaturization.
  • the embodiment of the present application provides a packaging device with common mode suppression, which can be used to solve the problems of complex processing technology, waste of physical space, and high cost caused by suppressing common mode noise in the packaging device.
  • Plane layer In this application, it refers to the power layer or ground layer in the packaged device or printed circuit board (Printed Circuit Board, PCB), which can be provided on the surface layer or the middle layer.
  • PCB printed Circuit Board
  • Signal layers In this application, it refers to the layers used for arranging signal traces in the packaging device or PCB, and can also be used for arranging components.
  • Anti-pad In a certain signal layer or plane layer, the anti-pad is hollowed out around the via to form an empty area, so that the via is insulated from the surrounding conductive medium.
  • a packaging device with common mode suppression includes a substrate, and a first planar layer, a first signal via, a second signal via, and The first common mode suppression via, the first plane layer may be a ground layer or a power layer.
  • the above-mentioned first signal via hole and the second signal via hole are differential signal via holes for transmitting differential signals.
  • the first common mode suppression via is arranged between the first signal via and the second signal via.
  • the first end of the first common mode suppression via is electrically connected to the first planar layer, except for the first
  • the other part of the terminal is insulated from the surrounding medium, and at least a part of the first common mode suppression via is respectively located on the same horizontal plane as the two signal vias.
  • the first end of the above-mentioned first common mode suppression via can be understood as a part where the first common mode suppression via intersects the first plane layer.
  • the medium surrounding other parts of the first common-mode suppression via can be understood as a power layer, a ground layer, a signal layer or an insulating material through which other parts of the via pass except for the first end.
  • the above-mentioned medium may be wires or insulating materials arranged on these power supply layers, ground layers or signal layers, or may be insulating materials between wiring layers.
  • the first common mode suppression via satisfies the above positional relationship, it is located in the electric field formed by the common mode signal in the differential signal via, so the common mode signal can be suppressed.
  • the above-mentioned substrate may be an interposer implemented with passive silicon wafers. It should be noted that the first via in the claims may be the first common mode suppression via in the specification.
  • the common-mode signals transmitted in the first signal via and the second signal via form an electric field
  • the first common-mode suppression via forms a resonant circuit in the above-mentioned electric field, thereby exciting the resonance characteristics of the above-mentioned common-mode signal, while retaining the differential signal While suppressing the common mode signal.
  • the suppression of the common mode signal through the first common mode suppression via has relatively simple processing requirements for the packaging device, and no additional filtering wiring is required, which saves physical space and reduces costs.
  • the aforementioned packaging device further includes a second common mode suppression via. Similar to the first common mode suppression via, in order to make the second common mode suppression via located in the electric field formed by the common mode signal in the differential signal via, the second common mode suppression via is provided in the first signal via and the first signal via. Between the two signal vias, and the first end of the second common mode suppression via is electrically connected to the first planar layer, and the other part except the first end is insulated from the surrounding medium. At least a part of the second common mode suppression via holes are respectively located on the same horizontal plane as the two signal via holes. The first end of the second common mode suppression via can be understood as the part where the second common mode suppression via intersects the first plane layer.
  • the medium surrounding other parts of the second common-mode suppression via can be understood as a power layer, a ground layer, a signal layer, or an insulating material through which other portions of the via pass except the first end pass.
  • the above-mentioned medium may be wires or insulating materials arranged on these power supply layers, ground layers or signal layers, or may be insulating materials between wiring layers.
  • the first common mode suppression via hole and the second common mode suppression via hole are respectively disposed on both sides of the first virtual plane, and the first virtual plane is a plane formed by passing through the central axis of the two signal via holes.
  • the two common-mode suppression via holes arranged on both sides of the first virtual plane are both located in the electric field formed by the common-mode signal, a better suppression effect on the common-mode signal can be formed.
  • the second via in the claims may be the second common mode suppression via in the specification.
  • both the first common mode suppression via and the second common mode suppression via can be obtained by back-drilling the ground via or the power via in the package device.
  • Direct back-drilling the existing ground vias or power supply vias in the packaging device can obtain the above-mentioned common mode suppression vias, which simplifies the processing technology, and further reduces the cost of the packaging device.
  • the center axis of the first common mode suppression via and the center axis of the second common mode suppression via are both located on a second virtual plane, and the second virtual plane is the first signal path.
  • the above-mentioned second virtual plane is a zero potential plane, which can be regarded as a virtual ground plane.
  • the central axis of the common mode suppression via is set on the second virtual plane, so that the common mode suppression via does not affect the transmission of the differential signal, so that only the common mode signal is suppressed.
  • the first common mode suppression via and the second common mode suppression via are symmetric about the first virtual plane.
  • the common mode suppression vias are arranged symmetrically with respect to the first virtual plane to form a better suppression effect on common mode signals.
  • the packaging device further includes a second plane layer, and the first common mode suppression via and the second common mode suppression via respectively pass through the second plane layer.
  • the first common mode suppression via hole and the second common mode suppression via hole are respectively kept isolated from the second plane layer by a first anti-pad provided on the second plane layer, and the second plane layer is a ground layer or a power layer.
  • the common mode suppression via is kept isolated from other planar layers in the substrate through the anti-pad, so that the common mode suppression via has an effective length matching the frequency of the common mode signal to form an effective resonance circuit.
  • the first planar layer and the second planar layer are both ground layers
  • the packaging device further includes a ground via provided in the substrate, wherein: the ground via is connected to the first planar layer and the second The two plane layers are electrically connected.
  • the packaging device may further include a ground via, and the ground via and the common mode suppression via do not affect each other.
  • the packaging device further includes a signal layer, wherein one end of the first signal via and the second signal via are electrically connected to the signal layer, and the first common mode suppression via and the second signal via are electrically connected to the signal layer.
  • the common mode suppression via holes respectively pass through the signal layer, and are respectively kept isolated from the signal layer by third anti-pads arranged on the signal layer.
  • the common mode suppression via is kept isolated from other signal layers in the substrate through the anti-pad, so that the common mode suppression via has an effective length that matches the frequency of the common mode signal to form an effective resonance circuit.
  • the packaging device further includes a die and a first metal connector disposed on one side of the substrate.
  • the die is connected to the first signal via and the second signal via through the first metal connector. It is electrically connected to the first plane layer.
  • the above-mentioned packaging device is electrically connected to the die to transmit and process the signals in the packaging device to the die.
  • the above-mentioned packaging device further includes a second metal connector disposed on one side of the substrate, and the packaging device is electrically connected with the printed circuit board PCB through the second metal connector.
  • the above-mentioned packaging device is electrically connected to the PCB so as to transmit the signal in the packaging device to other circuits connected to the PCB through the PCB.
  • a printed circuit board PCB with common mode suppression includes a substrate, and a first plane layer, a first signal via, and a second signal via are provided in the substrate.
  • the hole and the first common mode suppression via hole, and the first plane layer may be a ground layer or a power layer.
  • the above-mentioned first signal via hole and the second signal via hole are differential signal via holes for transmitting differential signals.
  • the first common mode suppression via is arranged between the first signal via and the second signal via.
  • the first end of the first common mode suppression via is electrically connected to the first planar layer, except for the first
  • the other part of the terminal is insulated from the surrounding medium, and at least a part of the first common mode suppression via is respectively located on the same horizontal plane as the two signal vias.
  • the first end of the above-mentioned first common mode suppression via can be understood as a part where the first common mode suppression via intersects the first plane layer.
  • the medium surrounding other parts of the first common-mode suppression via can be understood as a power layer, a ground layer, a signal layer or an insulating material through which other parts of the via pass except for the first end.
  • the above-mentioned medium may be wires or insulating materials arranged on these power supply layers, ground layers or signal layers, or may be insulating materials between wiring layers.
  • the first common mode suppression via satisfies the above positional relationship, it is located in the electric field formed by the common mode signal in the differential signal via, so the common mode signal can be suppressed.
  • the above-mentioned substrate may be a PCB realized by using a copper clad laminate. It should be noted that the first via in the claims may be the first common mode suppression via in the specification.
  • the common-mode signals transmitted in the first signal via and the second signal via form an electric field
  • the first common-mode suppression via forms a resonant circuit in the above-mentioned electric field, thereby exciting the resonance characteristics of the above-mentioned common-mode signal, while retaining the differential signal While suppressing the common mode signal.
  • the PCB processing technology requirements are relatively simple, and no additional filtering wiring is required, which saves physical space and reduces costs.
  • the aforementioned PCB further includes a second common mode suppression via. Similar to the first common mode suppression via, in order to make the second common mode suppression via located in the electric field formed by the common mode signal in the differential signal via, the second common mode suppression via is provided in the first signal via and the first signal via. Between the two signal vias, and the first end of the second common mode suppression via is electrically connected to the first planar layer, and the other part except the first end is insulated from the surrounding medium. At least a part of the second common mode suppression via holes are respectively located on the same horizontal plane as the two signal via holes. The first end of the second common mode suppression via can be understood as the part where the second common mode suppression via intersects the first plane layer.
  • the medium surrounding other parts of the second common-mode suppression via can be understood as a power layer, a ground layer, a signal layer, or an insulating material through which other portions of the via pass except the first end pass.
  • the above-mentioned medium may be wires or insulating materials arranged on these power supply layers, ground layers or signal layers, or may be insulating materials between wiring layers.
  • the first common mode suppression via hole and the second common mode suppression via hole are respectively disposed on both sides of the first virtual plane, and the first virtual plane is a plane formed by passing through the central axis of the two signal via holes.
  • the two common-mode suppression via holes arranged on both sides of the first virtual plane are both located in the electric field formed by the common-mode signal, a better suppression effect on the common-mode signal can be formed.
  • the second via in the claims may be the second common mode suppression via in the specification.
  • both the first common mode suppression via and the second common mode suppression via can be obtained by back-drilling the ground via or the power via in the PCB.
  • the direct back-drilling of the existing ground vias or power vias in the PCB can obtain the above-mentioned common mode suppression vias, which simplifies the processing technology, and further reduces the cost of the PCB.
  • the center axis of the first common mode suppression via and the center axis of the second common mode suppression via are both located on a second virtual plane, and the second virtual plane is the first signal path.
  • the above-mentioned second virtual plane is a zero potential plane, which can be regarded as a virtual ground plane.
  • the central axis of the common mode suppression via is set on the second virtual plane, so that the common mode suppression via does not affect the transmission of the differential signal, so that only the common mode signal is suppressed.
  • the first common mode suppression via and the second common mode suppression via are symmetric about the first virtual plane.
  • the common mode suppression vias are arranged symmetrically with respect to the first virtual plane to form a better suppression effect on common mode signals.
  • the PCB further includes a second plane layer, and the first common mode suppression via and the second common mode suppression via respectively pass through the second plane layer.
  • the first common mode suppression via hole and the second common mode suppression via hole are respectively kept isolated from the second plane layer by a first anti-pad provided on the second plane layer, and the second plane layer is a ground layer or a power layer.
  • the common mode suppression via is kept isolated from other planar layers in the substrate through the anti-pad, so that the common mode suppression via has an effective length matching the frequency of the common mode signal to form an effective resonance circuit.
  • the above-mentioned first plane layer and the second plane layer are both ground layers
  • the PCB further includes a ground via provided in the substrate, wherein: the ground via is connected to the first plane layer and the second plane layer.
  • the plane layer is electrically connected.
  • the PCB may also include a ground via, and the ground via and the aforementioned common mode suppression via do not affect each other.
  • the PCB further includes a signal layer, wherein one end of the first signal via and the second signal via are electrically connected to the signal layer, and the first common mode suppression via and the second common
  • the mode suppression via holes respectively pass through the signal layer, and are respectively kept isolated from the signal layer by third anti-pads arranged on the signal layer.
  • the common mode suppression via is kept isolated from other signal layers in the substrate through the anti-pad, so that the common mode suppression via has an effective length that matches the frequency of the common mode signal to form an effective resonance circuit.
  • Figure 1 shows a packaging device for suppressing common mode noise in the prior art.
  • FIG. 2a is a schematic cross-sectional view of a packaging device in an embodiment of the application.
  • Figure 2b is a top view of a packaging device in an embodiment of the application.
  • 3a is a schematic cross-sectional view of a back drill of a packaging device in an embodiment of the application
  • FIG. 3b is a schematic cross-sectional view of back drilling of another packaging device in an embodiment of the application.
  • Fig. 4 is a top view of another packaging device in an embodiment of the present application.
  • FIG. 5a is an electric field diagram generated by a common mode signal of a packaging device in an embodiment of the application
  • FIG. 5b is a diagram of an electric field generated by a differential signal of a packaged device in an embodiment of the application.
  • FIG. 6 is a schematic cross-sectional view of a more specific packaging device in an embodiment of the application.
  • FIG. 7 is a schematic cross-sectional view of another more specific packaging device in an embodiment of the application.
  • FIG. 8 is a simulation diagram of common mode insertion loss of a packaging device in an embodiment of the application.
  • FIG. 9 is a schematic cross-sectional view of a printed circuit board in an embodiment of the application.
  • package device 200 substrate 210; first planar layer 220; first via 222; second planar layer 224; third planar layer 226; first signal via 230; second signal via 232; First signal layer 234; first common mode suppression via 240; second common mode suppression via 242; first anti-pad 246; second anti-pad 248; die 250; first metal connector 252; Two metal connectors 254; printed circuit board 256.
  • the packaging device 200 includes a substrate 210, and a first signal layer 234, a first planar layer 220, a first signal via 230, a second signal via 232, and a first common mode suppression via 240 disposed in the substrate 210.
  • the first signal via 230 and the second signal via 232 are differential signal vias for transmitting differential signals.
  • One end of the first signal via 230 and the second signal via 232 may be electrically connected to the first signal layer 234 provided in the substrate 210, and the other end may be electrically connected to other signal layers, or may be electrically connected to a circuit outside the package device 200.
  • the connection for example, is electrically connected to an external PCB (Printed Circuit Board, printed circuit board), or is electrically connected to a die.
  • the first common mode suppression via 240 is disposed between the first signal via 230 and the second signal via 232, and the first end of the first common mode suppression via 240 is electrically connected to the first planar layer 220, The other part except the first end is insulated from the surrounding dielectric.
  • the first end of the above-mentioned first common mode suppression via 240 can be understood as the part where the first common mode suppression via 240 and the first planar layer 220 intersect.
  • the medium surrounding other parts of the first common mode suppression via 240 can be understood as a power layer, a ground layer, a signal layer, or an insulating material through which other parts of the via hole pass except the first end.
  • the above-mentioned medium may be wires or insulating materials arranged on these power supply layers, ground layers or signal layers, or may be insulating materials between wiring layers.
  • the medium around the first common mode suppression via 240 except for the other part of the first end can be understood as the part of the substrate 210 through which the first common mode suppression via 240 passes. .
  • first common mode suppression via 240 in the vertical direction is located on the same horizontal plane as the first signal via 230 and the second signal via 232, that is, at least one is perpendicular to The virtual plane in the via direction simultaneously intercepts the two common mode suppression vias and the two signal vias.
  • the above-mentioned first plane layer 220 may be a ground layer that provides a reference ground, or a power layer that provides a working voltage.
  • common mode signals ie, common mode noise
  • the differential signals and common mode signals respectively generate different electric fields. Since the first common mode suppression via 240 is disposed between the first signal via 230 and the second signal via 232, and its first end is electrically connected to the planar layer and other parts are insulated from the surrounding dielectric, the first common The mode suppression via 240 forms a resonant circuit in the electric field generated by the common mode signal, thereby exciting the resonance characteristics of the common mode signal in the first signal via 230 and the second signal via 232, and suppresses the common mode signal while retaining the differential signal .
  • the present application uses the first common-mode suppression via 240 to suppress common-mode noise, which requires simpler processing technology, and No additional filtering wiring is required, so the physical space of the packaging device 200 is saved, which is conducive to its miniaturization and at the same time reduces its manufacturing cost.
  • first common mode suppression via 240 is electrically connected to the first planar layer, and other parts are isolated from the signal layer, the planar layer or other conductive media around the via.
  • the signal vias and the common mode suppression vias may be through holes, blind holes or buried holes, respectively.
  • the first planar layer 220 may be the first layer of the package device 200, that is, it is disposed on one of the surfaces of the package device 200, and the first common mode suppression via 240 may be a through hole, that is, the length Same as the packaging device 200, it can also be a blind hole, that is, the length is less than the thickness of the packaging device 200; the first planar layer 220 can also be an intermediate layer disposed inside the packaging device 200, and the first common mode suppression via 240 can It is a blind hole or a buried hole.
  • the above-mentioned substrate 210 may be an interposer implemented by a passive silicon wafer.
  • FIG. 2b a top view of the above-mentioned packaging device 200 is shown.
  • the first signal via 230 and the second signal via 232 are symmetrical about the second virtual plane 231.
  • the second virtual plane 231 is perpendicular to the substrate 210 (or perpendicular to the plane layer or signal layer) and passes through the first common mode suppression The plane of the central axis of the via 240.
  • the first common mode suppression via 240 is disposed between the third virtual plane 233 and the fourth virtual plane 235, for example, between the third virtual plane 233 and the second virtual plane 231, or between the second virtual plane 231 and
  • the fourth virtual plane 235 is a plane perpendicular to the substrate 210 and passing through the central axis of the first signal via 230
  • the fourth virtual plane 235 is a plane perpendicular to the substrate 210 and passing through the second signal via hole 230.
  • the plane of the central axis of the signal via 232, the third virtual plane 233 and the fourth virtual plane 235 are two symmetrical planes about the second virtual plane 231.
  • the position of the first common mode suppression via 240 is related to the effect of common mode suppression. The closer the first common mode suppression via 240 is to the symmetry plane 231, the better the common mode suppression effect.
  • the central axis of the first common mode suppression via 240 is located on the second virtual plane 231 described above.
  • the length of the first common mode suppression via 240 is smaller than the thickness of the package device 200 (in the direction of the via), and the first common mode suppression via 240 can be grounded through the package device 200. Holes or power supply vias are back drilled. Taking ground vias as an example, as shown in FIG. 3a is a schematic back-drilled cross-sectional view of the package device 200. The thickness of the package device 200 (along the direction of the via hole) is 1, and the length of the ground via is also 1. The ground via is back drilled from the lower surface of the package device 200, that is, the surface away from the first planar layer 220, toward the first planar layer 220, and the back drill length is l 1 .
  • the conductive material for example, copper layer
  • the ground via portion that is ground off the inner wall does not have a conductive effect.
  • Ll ground portion 1 the ground vias only shown in Figure 3a vias with a conductive material to retain the inner wall, a portion of the length ll of the first common-mode rejection is the through hole 240, and after back-drilling The part with the length l 1 does not belong to the first common mode suppression via 240.
  • the length of the first common mode suppression via 240 is equal to the thickness l of the packaging device 200, that is, the ground via is not back-drilled, and the entire ground via can be considered as the first common mode suppression. Via 240.
  • the length of the first common mode suppression via 240 can be controlled, that is, the length of the back drill can be controlled according to the frequency of common mode noise, so as to achieve better common mode suppression.
  • the portion of the via hole with a length of l 1 that is worn away does not belong to the first common mode suppression via 240, and the first common mode suppression via 240
  • the length should be understood as the length of the part with conductive material on the inner wall surface of the via, that is, ll 1 .
  • Only the first end of the first common mode suppression via 240 is electrically connected to the first planar layer 220, and the rest (including the other end) is isolated from the surrounding signal layer, planar layer or other conductive media, and does not form any form of electrical connection .
  • the ground via is back drilled, if one end of the ground via is electrically connected to another plane layer, the other end of the ground via is insulated from the surrounding dielectric, and the middle part of the ground via is insulated from the first A planar layer 220 is electrically connected, the portion of the ground via from the other end to the first planar layer 220 is the first common mode suppression via 240, and the ground from the first planar layer 220 to the other planar layer
  • the hole part does not belong to the first common mode suppression via 240.
  • the package device 200 further includes a second planar layer 224 disposed on the side of the first planar layer 220 away from the signal layer 234.
  • the two-plane layer can be the surface layer of the packaged device.
  • One end of the ground via with a length of 1 is connected to the second planar layer 224, and the back-drilling method and length of the ground via are the same as the ground via of the package device 200 in FIG. 3a.
  • a first common mode suppression apparatus 200 of the package 240 is a hole through the length of the ground over ll 1 -l 2
  • the hole part, that is, the first end should be the part where the ground via and the first plane layer 220 intersect.
  • the present application also provides a top view of another packaging device 200 as shown in FIG. 4, wherein the packaging device 200 further includes a second common mode suppression via 242, which is provided in the first signal via 230 and the second signal via 232.
  • the first end of the second common mode suppression via 242 is electrically connected to the first planar layer 220, and the other part except the first end is insulated from the surrounding dielectric.
  • the first end of the second common mode suppression via 242 can be understood as the part where the second common mode suppression via 242 intersects the first planar layer 220.
  • the medium surrounding other parts of the second common mode suppression via 242 can be understood as a power layer, a ground layer, a signal layer or an insulating material through which other portions of the via hole pass except for the first end.
  • the above-mentioned medium may be wires or insulating materials arranged on these power supply layers, ground layers or signal layers, or may be insulating materials between wiring layers.
  • the first common mode suppression via 240 and the second common mode suppression via 242 are respectively disposed on both sides of the first virtual plane 237, which simultaneously passes through the first signal via 230 and the second signal via.
  • the central axis of the hole 232 is perpendicular to the plane of the substrate 210.
  • the two common mode suppression via holes are respectively arranged on both sides of the first virtual plane 237, which is beneficial to the packaging device 200 to better suppress the common mode signal in the via holes.
  • the central axis of the first common mode suppression via 240 and the central axis of the second common mode suppression via 242 are both located on the second virtual plane 231, that is, located between the first signal via 230 and the The symmetry plane of the second signal via 232.
  • the first common mode suppression via 240 and the second common mode suppression via 242 are also symmetrical about the first virtual plane 237. Similar to the first common mode suppression via 240, the second common mode suppression via 242 can also be obtained by back-drilling ordinary ground vias or power vias, which will not be described here.
  • the electric field distribution formed by the common mode signal is as shown in FIG. 5a. Since the common mode signals are equal in magnitude and in the same direction, the direction of the electric field generated by the first signal via 230 and the second signal via 232 is from the signal via (for example, the first signal via 230 or the second signal via 232) To the second virtual plane 231. Since the first common mode suppression via 240 and the second common mode suppression via 242 form a resonant circuit, thereby exciting the resonance characteristics of the common mode signal, the common mode signal in the first signal via 230 and the second signal via 232 can be suppressed Transmission.
  • the first common mode suppression via 240 and the second common mode suppression via 242 are in the vertical direction (that is, along the above The position of the hole) needs to be matched with the first signal via 230 and the second signal via 232.
  • the packaging device 200 includes at least one metal layer, wherein the two common mode suppression vias and the two signal vias pass through the metal layer together.
  • the electric field distribution diagram formed by the differential signal is shown. Since the differential signals are equal in magnitude and opposite in direction, the electric field generated by the first signal via 230 and the second signal via 232 ranges from a via with a positive direction (for example, the first signal via 230) to a via with a negative direction ( For example, the second signal via 232), and a plane of zero potential is formed on the symmetry plane of the first signal via 230 and the second signal via 232 (ie, the second virtual plane 231), that is, a virtual ground plane.
  • first common-mode suppression via 240 and the second common-mode suppression via 242 are located on the second virtual plane 231, they are equivalent to being connected to the ground plane in terms of electrical performance. Therefore, while suppressing common-mode signals, they will not Affect the differential signal.
  • the packaging device 200 further includes a second planar layer 224, a third planar layer 226, and a signal layer 234 disposed in the substrate 210.
  • the second planar layer 224 is disposed on the side of the first planar layer 220
  • the third planar layer 226 is disposed on the side of the second planar layer 224 away from the first planar layer 220, the first planar layer 220, the second planar layer 226 and
  • the third plane layer 226 may be a ground layer or a power layer, respectively.
  • the above-mentioned first common mode suppression via 240 and second common mode suppression via 242 respectively pass through the second planar layer 224 and are respectively kept isolated from the second planar layer 224.
  • the first common mode suppression via 240 and the second common mode suppression via 242 are respectively held by the two first anti-pads 246 and the second plane layer 224 disposed on the second plane layer 224. isolation. Specifically, in order to prevent the common mode suppression via from forming an electrical connection with the planar layer, the conductive medium on the planar layer around the via is hollowed out to form the anti-pad.
  • the above-mentioned third plane layer 226 may be the last layer of the package device 200, that is, the surface of the package device 200 away from the first plane layer 220, or may be an intermediate layer provided inside the package device 200.
  • the first planar layer 220, the second planar layer 224, and the third planar layer 226 are all ground layers
  • the packaging device 200 described above further includes a first via 222, which is a ground via.
  • One end of the above-mentioned first via 222 is electrically connected to the first planar layer 220, passes through the second planar layer 224, and the other end is electrically connected to the third planar layer 226.
  • the aforementioned signal layer 234 may be disposed between the first planar layer 220 and the second planar layer 224, or between the second planar layer 224 and the third planar layer 226.
  • first signal via 230 and the second signal via 232 are respectively electrically connected to the signal layer, and the other end may be electrically connected to an external circuit through a metal piece, such as a solder ball.
  • first planar layer 220, the second planar layer 224, and the third planar layer 226 are all power layers, and in this case, the first via 222 is a power via.
  • the first common mode suppression via 240 and the second common mode suppression via 242 respectively pass through the signal layer 234, and respectively pass through two second anti-pads 248 disposed on the signal layer 234. Maintain isolation from the signal layer 234.
  • the packaging device 200 further includes a die 250 and a first metal connector 252 disposed on one side of the substrate.
  • the die 250 is disposed on the side of the first planar layer 220, and is electrically connected to the first signal via 230, the second signal via 232, and the first planar layer 220 through the first metal connector 252. connection.
  • the die 250 may also be electrically connected to the first via 222 through the first metal connection 252.
  • the above-mentioned die 250 is disposed on the side of the third plane layer 226, and is connected to the above-mentioned first signal via 230, the second signal via 232 and the first plane through the first metal connecting member 252.
  • Layer 220 is electrically connected.
  • the above-mentioned first metal piece may be a bump ball.
  • the packaging device 200 also includes a second metal connector 254 provided on one side of the substrate, and the second metal connector 254 is used to form an electrical connection between the packaging device 200 and an external circuit 256.
  • the external circuit may be a PCB or other packaging device.
  • the first metal connection member 252 and the second metal connection member 254 may both be solder balls, such as BGA (ball grid array, ball grid array) solder balls, or other metal connection materials. As shown in FIG.
  • the second metal connector 254 is disposed on the surface of the packaging device 200 close to the third plane layer 226, that is, the die 250 and the PCB 256 are respectively disposed on both sides of the packaging device 200; In another embodiment, the second metal connector 254 is disposed on the surface of the packaging device 200 close to the first plane layer 226, that is, the die 250 and the PCB 256 are respectively disposed on one side of the packaging device 200.
  • FIG. 8 is the simulation result of the common mode insertion loss of the packaging device 200, where the abscissa is the frequency of the common mode signal, and the ordinate is the insertion loss of the common mode signal.
  • the corresponding common-mode signals have different insertion losses.
  • the corresponding 3dB filtering frequency band is 22.55GHz-27.24GHz, which realizes the broadband common mode filtering of 4.69GHz; when the common mode suppression via length is 0.7mm, its corresponding The 3dB filtering frequency band is 28.8GHz-34.55GHz, which can achieve ultra-wideband common-mode filtering effects greater than 6GHz; when the common-mode rejection via length is 0.6mm, the corresponding 3dB filtering frequency band is greater than 34.09GHz.
  • an embodiment of the present application also provides a multilayer printed circuit board (PCB) 900.
  • PCB printed circuit board
  • at least one chip 902 may be provided on one side of the PCB 900, and the chip 902 is electrically connected to the PCB 900 through a solder ball 904.
  • the PCB 900 may further include at least one chip disposed on the other side.
  • the above-mentioned chip may use any packaging device provided in the embodiments of the present application, or may be a packaging device in the prior art.
  • the PCB 900 includes a substrate 910, and a first planar layer 220, a first signal via 230, a second signal via 232, and a first common mode suppression via 240 disposed in the substrate 910.
  • the substrate 210 may be a PCB realized by using a copper clad laminate.
  • the first signal via 230 and the second signal via 232 are differential signal vias for transmitting differential signals.
  • the differential signal is a signal input from the PCB 900 to the chip 902 or a signal input from the chip 902 to the PCB 900.
  • One end of the first signal via 230 and the second signal via 232 may be electrically connected to the first signal layer 234 provided in the substrate 902, and the other end may be electrically connected to the differential signal pin of the chip 902, or to other external Electrical connection of circuits or components.
  • the first planar layer 220, the first signal via 230, the second signal via 232, and the first common mode suppression via 240 may be the structure described in any embodiment of the application, and the foregoing satisfies any implementation of the application.
  • the PCB 900 may also include the first via 222, the second planar layer 224, the third planar layer 226, the first signal layer 234, the second common mode suppression via 242,
  • the structure and positional relationship of the first anti-pad 246 and the second anti-pad 248 are the same as those in the packaging device 200, and will not be repeated here.
  • common mode signals ie, common mode noise
  • the differential signals and common mode signals respectively generate different electric fields. Since the first common mode suppression via 240 is disposed between the first signal via 230 and the second signal via 232, and its first end is electrically connected to the planar layer and other parts are insulated from the surrounding dielectric, the first common The mode suppression via 240 forms a resonant circuit in the electric field generated by the common mode signal, thereby exciting the resonance characteristics of the common mode signal in the first signal via 230 and the second signal via 232, and suppresses the common mode signal while retaining the differential signal .
  • the present application uses the first common-mode suppression via 240 to suppress common-mode noise, which requires simpler processing technology, and No additional filter traces are needed, so the physical space of the PCB900 is saved, which is conducive to its miniaturization and at the same time reduces its manufacturing cost.

Abstract

一种共模抑制的封装装置，涉及封装装置中传输差分信号时共模噪声的抑制。该封装装置包括基板，以及设置于基板中的电源层或地层、一对传输差分信号的信号过孔和第一过孔，其中该第一过孔设置于上述一对信号过孔之间，且第一过孔的至少一部分与上述一对信号过孔位于同一水平面。第一过孔的一端与上述电源层或地层电连接，除这一段以外的其他部分与其周围的介质绝缘。上述第一过孔在共模信号产生的电场中形成谐振回路，从而抑制共模信号，其加工工艺简单，无需额外的滤波走线，有利于节省封装装置的物理空间，降低成本。

Description

一种共模抑制的封装装置和印制电路板 技术领域
本申请涉及半导体领域，尤其涉及共模噪声抑制领域。
背景技术
对于速率为Gbps数量级的数据，业界通常采用差分信号传输技术来提高信号对噪声的免疫力，同时抑制时钟错位。与单根互联线相比，差分互联线具有优良的抗噪性能、对返回路径不连续的鲁棒性以及电磁干扰对消特性。基于上述特性，差分互联线被广泛地应用于高速链路基础标准中。
差分互联线上所传输的信号不仅包含差分信号，还包含共模信号(即共模噪声)，其中差分信号指差分互联线这两根信号线之间的信号差值，共模信号指上述两根信号线对地的噪声，通过差分互联线上两个差分信号的平均电压来表示。在实际应用中，差分互联线的驱动器偏离理想状态会导致差分互联线上所传输的信号在时间上有偏差错位。此外，线长差异、刻蚀变化、临近效应、走线弯曲等因素会造成差分互联线的不对称，从而产生共模噪声，进而使高速电路系统出现信号完整性、电源完整性和电磁干扰的问题。
图1为现有技术中一种抑制共模噪声的封装装置100的信号层示意图。该封装装置100包括平行设置于封装装置100中信号层的一对差分信号线(差分互联线)，即正差分线120和负差分线130。滤波走线140设置于上述两条差分信号线之间，其长度为需要滤除的噪声对应的波长的1/2。该滤波走线140的中点还设置有接地过孔150，用于与封装装置100的参考地平面相连。在设置滤波走线140的区域，正差分线120和负差分线130之间的间距变宽，以提供滤波走线140的布线空间。图1所示的封装装置100虽然在一定频带内具有良好的滤波特性，但对加工工艺的控制要求较高，且滤波走线140和接地过孔150占用大量物理空间，不利于封装装置100的小型化。
发明内容
本申请的实施例提供了一种共模抑制的封装装置，可以用于解决抑制该封装装置中共模噪声而产生的加工工艺复杂、浪费物理空间、成本过高的问题。
为了清楚地描述本申请实施例，以下对部分术语进行解释：
平面层(planes)：在本申请中指封装装置或印制电路板(Printed Circuit Board，PCB)中的电源层或地层，可以设置于表面层或中间层。
信号层(signal layers)：在本申请中指封装装置或PCB中用于布置信号走线的层，也可以用于设置元件。
反焊盘(anti-pad)：反焊盘为在某一信号层或平面层中，将过孔周围挖空以形成一个空的区域，从而使得过孔与周围的导电介质绝缘。
第一方面，在本申请的实施例中提供一种共模抑制的封装装置，该封装装置包括基板，以及设置于基板中的第一平面层、第一信号过孔、第二信号过孔和第一共模抑制过孔，该第一平面层可以是地层或者电源层。其中，上述第一信号过孔和第二信号过孔为差分信号过孔，用于传输差分信号。第一共模抑制过孔设置于第一信号过孔和第二信号过孔之间，具体来说，第一共模抑制过孔的第一端与第一平面层电连接，除上述第一端的其他部分与其周围的介质绝缘，且第一共模抑制过孔的至少一部分分别与上述两个信号过孔位于同一水平面。上述第一共模抑制过孔的第一端可以理解为第一共模抑制过孔与第一平面层相交的部分。上述第一共模抑制过孔的其他部分周围的介质可以理解为，该过孔除了第一端以外其他部分所穿过的电源层、地层、信号层或者是绝缘材料。其中，上述介质可以是这些电源层、地层或信号层上设置的导线或者绝缘材料，也可以是各布线层之间的绝缘材料。在第一共模抑制过孔满足上述位置关系时，其位于差分信号过孔中的共模信号形成的电场中，因此可以对该共模信号进行抑制。上述基板可以为采用无源硅片实现的中介层(interposer)。需要注意的是，权利要求中的第一过孔可以是说明书中的第一共模抑制过孔。
第一信号过孔和第二信号过孔中传输的共模信号形成电场，而第一共模抑制过孔在上述电场中形成谐振回路，从而激发上述共模信号的谐振特性，在保留差分信号的同时抑制了共模信号。通过第一共模抑制过孔来抑制共模信号，对封装装置的加工工艺要求较为简单，且无需额外的滤波走线，节省了物理空间，且降低成本。
在一种可能的实施方式中，上述封装装置还包括第二共模抑制过孔。与第一共模抑制过孔类似，为了使得第二共模抑制过孔位于差分信号过孔中的共模信号形成的电场中，第二共模抑制过孔设置于第一信号过孔和第二信号过孔之间，且第二共模抑制过孔的第一端与第一平面层电连接，除第一端的其他部分与其周围的介质绝缘。第二共模抑制过孔的至少一部分分别与上述两个信号过孔位于同一水平面。上述第二共模抑制过孔的第一端可以理解为第二共模抑制过孔与第一平面层相交的部分。上述第二共模抑制过孔的其他部分周围的介质可以理解为，该过孔除了第一端以外其他部分所穿过的电源层、地层、信号层或者是绝缘材料。其中，上述介质可以是这些电源层、地层或信号层上设置的导线或者绝缘材料，也可以是各布线层之间的绝缘材料。此外，第一共模抑制过孔和第二共模抑制过孔分别设置于第一虚拟平面的两侧，该第一虚拟平面为穿过上述两个信号过孔的中轴线形成的平面。由于设置于第一虚拟平面两侧的两个共模抑制过孔均位于共模信号形成的电场中，因此可以对共模信号形成更好的抑制作用。需要注意的是，权利要求中的第二过孔可以是说明书中的第二共模抑制过孔。
在一种可能的实施方式中，上述第一共模抑制过孔和第二共模抑制过孔均可以通过对封装装置中接地过孔或电源过孔进行背钻得到。对封装装置中现有的接地过孔或电源过孔直接进行背钻可以得到上述共模抑制过孔，简化了加工工艺，使得封装装置的成本可以进一步降低。
在一种可能的实施方式中，上述第一共模抑制过孔的中轴线和上述第二共模抑制过孔的中轴线均位于第二虚拟平面上，该第二虚拟平面为第一信号过孔和第二信号过 孔的对称虚拟平面。对于差分信号形成的电场，上述第二虚拟平面为零电位平面，即可以看作虚拟地平面。将上述共模抑制过孔的中轴线设置于第二虚拟平面上，使得共模抑制过孔不会对差分信号的传输造成影响，从而只对共模信号进行抑制。
在一种可能的实施方式中，上述第一共模抑制过孔和第二共模抑制过孔关于上述第一虚拟平面对称。将上述共模抑制过孔关于第一虚拟平面对称设置，可以对共模信号形成更好的抑制作用。
在一种可能的实施方式中，封装装置还包括第二平面层，且第一共模抑制过孔和第二共模抑制过孔分别穿过该第二平面层。其中，第一共模抑制过孔和第二共模抑制过孔分别通过设置于第二平面层上的第一反焊盘与第二平面层保持隔离，第二平面层为地层或电源层。上述共模抑制过孔通过反焊盘与基板中的其他平面层保持隔离，使得共模抑制过孔具有与共模信号的频率匹配的有效长度，以形成有效的谐振回路。
在一种可能的实施方式中，上述第一平面层和第二平面层均为地层，且封装装置还包括设置于基板中的接地过孔，其中：该接地过孔与第一平面层和第二平面层电连接。封装装置还可以包括接地过孔，且该接地过孔和上述共模抑制过孔互不影响。
在一种可能的实施方式中，所述封装装置还包括信号层，其中第一信号过孔和第二信号过孔的一端分别与该信号层电连接，第一共模抑制过孔和第二共模抑制过孔分别穿过该信号层，且分别通过设置于该信号层上的第三反焊盘与信号层保持隔离。上述共模抑制过孔通过反焊盘与基板中的其他信号层保持隔离，使得共模抑制过孔具有与共模信号的频率匹配的有效长度，以形成有效的谐振回路。
在一种可能的实施方式中，封装装置还包括设置于基板一侧的裸片die和第一金属连接件，上述裸片通过第一金属连接件与第一信号过孔、第二信号过孔和第一平面层电连接。上述封装装置与裸片电连接，以将封装装置中的信号传输至裸片并进行处理。
在一种可能的实施方式中，上述封装装置还包括设置于基板一侧的第二金属连接件，封装装置通过该第二金属连接件与印制电路板PCB形成电连接。上述封装装置与PCB电连接，以将封装装置中的信号通过该PCB传输至与PCB连接的其他电路中。
第二方面，在本申请的实施例中提供一种共模抑制的印制电路板PCB，该PCB包括基板，以及设置于基板中的第一平面层、第一信号过孔、第二信号过孔和第一共模抑制过孔，该第一平面层可以是地层或者电源层。其中，上述第一信号过孔和第二信号过孔为差分信号过孔，用于传输差分信号。第一共模抑制过孔设置于第一信号过孔和第二信号过孔之间，具体来说，第一共模抑制过孔的第一端与第一平面层电连接，除上述第一端的其他部分与其周围的介质绝缘，且第一共模抑制过孔的至少一部分分别与上述两个信号过孔位于同一水平面。上述第一共模抑制过孔的第一端可以理解为第一共模抑制过孔与第一平面层相交的部分。上述第一共模抑制过孔的其他部分周围的介质可以理解为，该过孔除了第一端以外其他部分所穿过的电源层、地层、信号层或者是绝缘材料。其中，上述介质可以是这些电源层、地层或信号层上设置的导线或者绝缘材料，也可以是各布线层之间的绝缘材料。在第一共模抑制过孔满足上述位置关系时，其位于差分信号过孔中的共模信号形成的电场中，因此可以对该共模信号进行抑制。上述基板可以为采用覆铜箔层压板实现的PCB。需要注意的是，权利要求中 的第一过孔可以是说明书中的第一共模抑制过孔。
第一信号过孔和第二信号过孔中传输的共模信号形成电场，而第一共模抑制过孔在上述电场中形成谐振回路，从而激发上述共模信号的谐振特性，在保留差分信号的同时抑制了共模信号。通过第一共模抑制过孔来抑制共模信号，对PCB的加工工艺要求较为简单，且无需额外的滤波走线，节省了物理空间，且降低成本。
在一种可能的实施方式中，上述PCB还包括第二共模抑制过孔。与第一共模抑制过孔类似，为了使得第二共模抑制过孔位于差分信号过孔中的共模信号形成的电场中，第二共模抑制过孔设置于第一信号过孔和第二信号过孔之间，且第二共模抑制过孔的第一端与第一平面层电连接，除第一端的其他部分与其周围的介质绝缘。第二共模抑制过孔的至少一部分分别与上述两个信号过孔位于同一水平面。上述第二共模抑制过孔的第一端可以理解为第二共模抑制过孔与第一平面层相交的部分。上述第二共模抑制过孔的其他部分周围的介质可以理解为，该过孔除了第一端以外其他部分所穿过的电源层、地层、信号层或者是绝缘材料。其中，上述介质可以是这些电源层、地层或信号层上设置的导线或者绝缘材料，也可以是各布线层之间的绝缘材料。此外，第一共模抑制过孔和第二共模抑制过孔分别设置于第一虚拟平面的两侧，该第一虚拟平面为穿过上述两个信号过孔的中轴线形成的平面。由于设置于第一虚拟平面两侧的两个共模抑制过孔均位于共模信号形成的电场中，因此可以对共模信号形成更好的抑制作用。需要注意的是，权利要求中的第二过孔可以是说明书中的第二共模抑制过孔。
在一种可能的实施方式中，上述第一共模抑制过孔和第二共模抑制过孔均可以通过对PCB中接地过孔或电源过孔进行背钻得到。对PCB中现有的接地过孔或电源过孔直接进行背钻可以得到上述共模抑制过孔，简化了加工工艺，使得PCB的成本可以进一步降低。
在一种可能的实施方式中，上述第一共模抑制过孔的中轴线和上述第二共模抑制过孔的中轴线均位于第二虚拟平面上，该第二虚拟平面为第一信号过孔和第二信号过孔的对称虚拟平面。对于差分信号形成的电场，上述第二虚拟平面为零电位平面，即可以看作虚拟地平面。将上述共模抑制过孔的中轴线设置于第二虚拟平面上，使得共模抑制过孔不会对差分信号的传输造成影响，从而只对共模信号进行抑制。
在一种可能的实施方式中，上述第一共模抑制过孔和第二共模抑制过孔关于上述第一虚拟平面对称。将上述共模抑制过孔关于第一虚拟平面对称设置，可以对共模信号形成更好的抑制作用。
在一种可能的实施方式中，PCB还包括第二平面层，且第一共模抑制过孔和第二共模抑制过孔分别穿过该第二平面层。其中，第一共模抑制过孔和第二共模抑制过孔分别通过设置于第二平面层上的第一反焊盘与第二平面层保持隔离，第二平面层为地层或电源层。上述共模抑制过孔通过反焊盘与基板中的其他平面层保持隔离，使得共模抑制过孔具有与共模信号的频率匹配的有效长度，以形成有效的谐振回路。
在一种可能的实施方式中，上述第一平面层和第二平面层均为地层，且PCB还包括设置于基板中的接地过孔，其中：该接地过孔与第一平面层和第二平面层电连接。PCB还可以包括接地过孔，且该接地过孔和上述共模抑制过孔互不影响。
在一种可能的实施方式中，所述PCB还包括信号层，其中第一信号过孔和第二信 号过孔的一端分别与该信号层电连接，第一共模抑制过孔和第二共模抑制过孔分别穿过该信号层，且分别通过设置于该信号层上的第三反焊盘与信号层保持隔离。上述共模抑制过孔通过反焊盘与基板中的其他信号层保持隔离，使得共模抑制过孔具有与共模信号的频率匹配的有效长度，以形成有效的谐振回路。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍。
图1为现有技术中一种抑制共模噪声的封装装置。
图2a为本申请实施例中一种封装装置的剖面示意图；
图2b为本申请实施例中一种封装装置的俯视图。
图3a为本申请实施例中一种封装装置的背钻剖面示意图；
图3b为本申请实施例中另一种封装装置的背钻剖面示意图。
图4为被本申请实施例中另一种封装装置的俯视图。
图5a为本申请实施例中一种封装装置的共模信号产生的电场图；
图5b为本申请实施例中一种封装装置的差分信号产生的电场图。
图6为本申请实施例中一种更为具体的封装装置的剖面示意图。
图7为本申请实施例中另一种更为具体的封装装置的剖面示意图。
图8为本申请实施例中一种封装装置的共模插损仿真图。
图9为本申请实施例中一种印制电路板的剖面示意图。
附图标记说明：封装装置200；基板210；第一平面层220；第一过孔222；第二平面层224；第三平面层226；第一信号过孔230；第二信号过孔232；第一信号层234；第一共模抑制过孔240；第二共模抑制过孔242；第一反焊盘246；第二反焊盘248；裸片250；第一金属连接件252；第二金属连接件254；印制电路板256。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。
如图2a所示的是本申请提供的一种共模抑制的封装装置200的剖面示意图。该封装装置200包括基板210，以及设置于基板210中的第一信号层234、第一平面层220、第一信号过孔230、第二信号过孔232和第一共模抑制过孔240。第一信号过孔230和第二信号过孔232为差分信号过孔，用于传输差分信号。第一信号过孔230和第二信号过孔232的一端可以分别与设置于基板210中的第一信号层234电连接，另一端与其他信号层电连接，或者与封装装置200外部的电路电连接，例如与外部的PCB(Printed Circuit Board，印制电路板)电连接，或者与裸片(die)电连接。第一共模抑制过孔240设置于上述第一信号过孔230和第二信号过孔232之间，且第一共模抑制过孔240的第一端与上述第一平面层220电连接，除上述第一端的其他部分与其周围的介质绝缘。上述第一共模抑制过孔240的第一端可以理解为第一共模抑制过 孔240与第一平面层220相交的部分。上述第一共模抑制过孔240的其他部分周围的介质可以理解为，该过孔除了第一端以外其他部分所穿过的电源层、地层、信号层或者是绝缘材料。其中，上述介质可以是这些电源层、地层或信号层上设置的导线或者绝缘材料，也可以是各布线层之间的绝缘材料。在如图2a所示的封装装置200中，第一共模抑制过孔240除第一端的其他部分周围的介质可以理解为，该第一共模抑制过孔240所穿过的部分基板210。此外，第一共模抑制过孔240在垂直方向(即沿着过孔方向)的至少一部分分别与第一信号过孔230和第二信号过孔232位于同一水平面，即，至少有一个垂直于上述过孔方向的虚拟平面同时截断上述两个共模抑制过孔和上述两个信号过孔。上述第一平面层220可以为提供参考地的地层，或为提供工作电压的电源层。
第一信号过孔230和第二信号过孔232中除了存在差分信号，还存在共模信号(即共模噪声)，且上述差分信号和共模信号分别产生不同的电场。由于第一共模抑制过孔240设置在第一信号过孔230和第二信号过孔232之间，且其第一端与平面层电连接而其他部分与周围的介质绝缘，因此第一共模抑制过孔240在上述共模信号产生的电场中形成谐振回路，从而激发第一信号过孔230和第二信号过孔232中共模信号的谐振特性，在保留差分信号的同时抑制共模信号。相比于现有技术中通过滤波走线且额外打接地过孔的方式实现共模抑制，本申请通过第一共模抑制过孔240来抑制共模噪声，对加工工艺的要求较为简单，且无需额外的滤波走线，因此节省了封装装置200的物理空间，有利于其小型化，同时降低了其制造成本。
需要注意的是，上述第一共模抑制过孔240仅有第一端与上述第一平面层电连接，其他部分均与过孔周围的信号层、平面层或其他导电介质隔离。上述信号过孔和共模抑制过孔可以分别为通孔、盲孔或埋孔。在一种实施方式中，上述第一平面层220可以为封装装置200的第一层，即设置于封装装置200的其中一个表面，上述第一共模抑制过孔240可以为通孔，即长度与封装装置200相同，也可以为盲孔，即长度小于封装装置200的厚度；上述第一平面层220还可以为设置于封装装置200内部的中间层，上述第一共模抑制过孔240可以为盲孔，也可以为埋孔。上述基板210可以为采用无源硅片实现的中介层(interposer)。
如图2b所示的是上述封装装置200的俯视图。第一信号过孔230和第二信号过孔232关于第二虚拟平面231对称，上述第二虚拟平面231为垂直于基板210(或垂直于平面层或信号层)且穿过第一共模抑制过孔240的中心轴的平面。第一共模抑制过孔240设置于第三虚拟平面233以及第四虚拟平面235之间，例如设置于第三虚拟平面233和第二虚拟平面231之间，或者设置于第二虚拟平面231和第四虚拟平面235之间，其中上述第三虚拟平面为垂直于基板210且穿过第一信号过孔230的中心轴的平面，第四虚拟平面235为为垂直于基板210且穿过第二信号过孔232的中心轴的平面，第三虚拟平面233和第四虚拟平面235为关于上述第二虚拟平面231对称的两个平面。第一共模抑制过孔240的位置与共模抑制的效果相关，当第一共模抑制过孔240越靠近对称面231，则共模抑制效果越好。在一种实施方式中，第一共模抑制过孔240的中心轴位于上述第二虚拟平面231上。
在一种实施方式中，上述第一共模抑制过孔240的长度小于封装装置200的厚度(沿过孔的方向)，该第一共模抑制过孔240可以通过对封装装置200中接地过孔或电源过孔进行背钻得到。以接地过孔为例，如图3a所示的是封装装置200的背钻剖面示意图，封装装置200的厚度(沿过孔的方向)为l，接地过孔的长度也为l。从封装装置200的下表面，即远离上述第一平面层220的表面，朝向第一平面层220的方向对上述接地过孔进行背钻，且背钻长度为l 1。经过背钻后的接地过孔，其长度为l 1的过孔部分的内壁表面的导电材料(例如铜层)被磨掉，使得被磨掉内壁的接地过孔部分不具有导电作用。此时，上述接地过孔中仅有如图3a所示的l-l 1部分的接地过孔内壁保留有导电材料，该长度为l-l 1部分即为上述第一共模抑制过孔240，而经过背钻的、长度为l 1的部分不属于第一共模抑制过孔240。
在另一种实施方式中，上述第一共模抑制过孔240的长度等于封装装置200的厚度l，即不对接地过孔进行背钻，此时整个接地过孔可以认为是第一共模抑制过孔240。对于不同频率的共模信号，可以通过控制上述第一共模抑制过孔240的长度，也就是根据共模噪声的频率控制背钻的长度，以实现更好效果的共模抑制。例如，当第一共模抑制过孔240的长度为l-l 1＝0.8mm时，其对应的3dB滤波频段为22.55GHz—27.24GHz，可以实现4.69GHz的宽带共模抑制；当第一共模抑制过孔240的长度为l-l 1＝0.7mm时，其对应的3dB滤波频段为28.80GHz—34.86GHz，可以实现6.06GHz的宽带共模抑制。
需要注意的是，在图3a所示的封装装置200剖面示意图中，被磨掉的长度为l 1的过孔部分不属于第一共模抑制过孔240，第一共模抑制过孔240的长度应理解为过孔内壁表面有导电材料的部分的长度，即l-l 1。第一共模抑制过孔240仅第一端与第一平面层220电连接，其余部分(包括另一端)均与周围的信号层、平面层或其他导电介质隔离，不形成任何形式的电连接。因此，当对上述接地过孔进行背钻后，若该接地过孔的一端与另一平面层电连接，该接地过孔的另一端与周围的介质绝缘，而接地过孔中间部分与上述第一平面层220电连接，则该接地过孔从上述另一端到第一平面层220的部分为第一共模抑制过孔240，而从第一平面层220到上述另一平面层的接地过孔部分不属于第一共模抑制过孔240。
例如，在图3b所示的一种封装装置200剖面示意图中，封装装置200还包括第二平面层224，该第二平面层224设置于第一平面层220远离信号层234的一侧，第二平面层可以为封装装置的表面层。长度为l的接地过孔一端连接第二平面层224，且对该接地过孔的背钻方式和长度与图3a中封装装置200的接地过孔相同。由于接地过孔分别与间距为l 2的第一平面层220和第二平面层224电连接，因此该封装装置200中第一共模抑制过孔240是长度为l-l 1-l 2的接地过孔部分，即第一端应该为该接地过孔与第一平面层220相交的部分。
本申请还提供如图4所示的另一种封装装置200的俯视图，其中封装装置200还包括第二共模抑制过孔242，设置于上述第一信号过孔230和第二信号过孔232之间，且第二共模抑制过孔242的第一端与第一平面层220电连接，除上述第一端的其他部分与其周围的介质绝缘。上述第二共模抑制过孔242的第一端可以理解为第二共模抑制过孔242与第一平面层220相交的部分。上述第二共模抑制过孔242的其他部分周围的介质可以理解为，该过孔除了第一端以外其他部分所穿过的电源层、地层、信号 层或者是绝缘材料。其中，上述介质可以是这些电源层、地层或信号层上设置的导线或者绝缘材料，也可以是各布线层之间的绝缘材料。第一共模抑制过孔240和第二共模抑制过孔242分别设置于第一虚拟平面237的两侧，该第一虚拟平面237为同时穿过第一信号过孔230和第二信号过孔232的中心轴，且垂直于基板210的平面。将上述两个共模抑制过孔分别设置于上述第一虚拟平面237的两侧，有利于封装装置200更好地抑制过孔中的共模信号。在一种实施方式中，上述第一共模抑制过孔240的中轴线和第二共模抑制过孔242的中轴线均位于上述第二虚拟平面231上，即位于第一信号过孔230和第二信号过孔232的对称面上。在一种实施方式中，上述第一共模抑制过孔240和第二共模抑制过孔242还关于上述第一虚拟平面237对称。与第一共模抑制过孔240类似，第二共模抑制过孔242同样可以通过对普通的接地过孔或电源过孔进行背钻得到，此处不再赘述。
当第一信号过孔230和第二信号过孔232传输共模信号时，该共模信号形成的电场分布如图5a所示。由于共模信号大小相等，方向相同，因此第一信号过孔230和第二信号过孔232产生的电场的方向为从信号过孔(例如第一信号过孔230或第二信号过孔232)到第二虚拟平面231。由于第一共模抑制过孔240和第二共模抑制过孔242形成谐振回路，从而激发共模信号的谐振特性，因此可以抑制第一信号过孔230和第二信号过孔232中共模信号的传输。为了使得第一共模抑制过孔240和第二共模抑制过孔242位于上述电场中，第一共模抑制过孔240和第二共模抑制过孔242在垂直方向(即沿着上述过孔的方向)的位置需要与第一信号过孔230和第二信号过孔232匹配，具体来说，至少有一个垂直于上述过孔方向的虚拟平面同时截断上述两个共模抑制过孔和上述两个信号过孔。也就是说封装装置200至少包括一个金属层，其中上述两个共模抑制过孔和两个信号过孔共同穿过该金属层。
如图5b所示的是第一信号过孔230和第二信号过孔232在传输差分信号时，该差分信号形成的电场分布图。由于差分信号大小相等，方向相反，因此第一信号过孔230和第二信号过孔232产生的电场从方向为正的过孔(例如第一信号过孔230)到方向为负的过孔(例如第二信号过孔232)，且在第一信号过孔230和第二信号过孔232的对称面上(即第二虚拟平面231)形成一个零电位的平面，即虚拟地平面。当第一共模抑制过孔240和第二共模抑制过孔242位于该第二虚拟平面231，则在电性能上等价于与地平面连接，因此在抑制共模信号的同时，不会对差分信号产生影响。
如图6所示的是封装装置200的一种具体的实施方式。封装装置200还包括设置于基板210中的第二平面层224、第三平面层226和信号层234。其中，第二平面层224设置于第一平面层220一侧，第三平面层226设置于第二平面层224背离第一平面层220一侧，第一平面层220、第二平面层226和第三平面层226分别可以为地层或电源层。上述第一共模抑制过孔240和第二共模抑制过孔242分别穿过第二平面层224，且分别与第二平面层224保持隔离。在一种实施方式中，第一共模抑制过孔240和第二共模抑制过孔242分别通过设置于第二平面层224上的两个第一反焊盘246与第二平面层224保持隔离。具体来说，为了防止上述共模抑制过孔与平面层形成电连接，将过孔四周的、平面层上的导电介质挖空，以形成上述反焊盘。上述第三平面层 226可以为封装装置200的最后一层，即设置于封装装置200远离第一平面层220的表面，也可以为设置于封装装置200内部的中间层。
在一种实施方式中，第一平面层220、第二平面层224和第三平面层226均为地层，上述封装装置200还包括第一过孔222，该第一过孔为地过孔。上述第一过孔222的一端与第一平面层220电连接，穿过第二平面层224，且另一端与第三平面层226电连接。上述信号层234可以设置于第一平面层220和第二平面层224之间，也可以设置于第二平面层224和第三平面层226之间。在一种实施方式中，上述第一信号过孔230和第二信号过孔232的一端分别与信号层电连接，另一端可以与外部电路通过金属件，例如通过锡球进行电连接。在另一种实施方式中，上述第一平面层220、第二平面层224和第三平面层226均为电源层，此时上述第一过孔222为电源过孔。
在一种实施方式中，上述第一共模抑制过孔240和第二共模抑制过孔242分别穿过上述信号层234，且分别通过设置于信号层234的两个第二反焊盘248与信号层234保持隔离。
如图7所示的是封装装置200的一种更为具体的实施方式。封装装置200还包括设置于基板一侧的裸片(die)250和第一金属连接件252。在一种实施方式中，裸片250设置于第一平面层220一侧，并通过第一金属连接件252与上述第一信号过孔230、第二信号过孔232和第一平面层220电连接。裸片250还可以通过第一金属连接件252与第一过孔222电连接。
在另一种实施方式中，上述裸片250设置于第三平面层226一侧，并通过第一金属连接件252与与上述第一信号过孔230、第二信号过孔232和第一平面层220电连接。上述第一金属件可以为bump球。
封装装置200还包括设置于基板一侧的第二金属连接件254，该第二金属连接件254用于形成封装装置200和外部电路256的电连接，上述外部电路可以为PCB，或者其他封装装置。上述第一金属连接件252和第二金属连接件254可以均可以为锡球，例如BGA(ball grid array,球栅阵列)锡球，或者其他金属连接材料。如图6所示，在一种实施方式中，上述第二金属连接件254设置于封装装置200靠近第三平面层226的表面，即裸片250和PCB256分别设置于封装装置200的两侧；在另一种实施方式中，上述第二金属连接件254设置于封装装置200靠近第一平面层226的表面，即裸片250和PCB256分别设置于封装装置200的一侧。
如图8所示的是封装装置200的共模插损仿真结果，其中横坐标为共模信号的频率，纵坐标为共模信号的插损。对于不同的共模抑制过孔长度，其对应的共模信号的插损不同。当共模抑制过孔长度为0.8mm时，其对应的3dB滤波频段为22.55GHz—27.24GHz，实现了4.69GHz的宽带共模滤波；当共模抑制过孔长度为0.7mm时，其对应的3dB滤波频段为28.8GHz—34.55GHz，可实现大于6GHz的超宽带共模滤波效果；当共模抑制过孔长度为0.6mm时，其对应的3dB滤波频段大于34.09GHz。
如图9所示，本申请实施例还提供一种多层印制电路板(PCB)900。在一种实施方式中，该PCB900的一侧可以设置至少一个芯片902，且该芯片902通过锡球904与PCB900形成电连接。在另一种实施方式中，该PCB900还可以包括设置于另一侧的至少一个芯片。上述芯片可以采用本申请实施例提供的任一种封装装置，也可以是现有 技术中的一种封装装置。PCB900包括基板910，以及设置于基板910中的第一平面层220、第一信号过孔230、第二信号过孔232和第一共模抑制过孔240。其中，基板210可以为采用覆铜箔层压板实现的PCB。上述第一信号过孔230和第二信号过孔232为差分信号过孔，用于传输差分信号，该差分信号为从PCB900输入至芯片902的信号，或者为从芯片902输入至PCB900的信号。第一信号过孔230和第二信号过孔232的一端可以分别与设置于基板902中的第一信号层234电连接，另一端与上述芯片902的差分信号引脚电连接，或者与其他外部电路或元器件电连接。上述第一平面层220、第一信号过孔230、第二信号过孔232和第一共模抑制过孔240可以为本申请任一实施例所述的结构，且上述满足本申请任一实施例所述的位置关系。
进一步地，该PCB900还可以包括本申请任一实施例所述的第一过孔222、第二平面层224、第三平面层226、第一信号层234、第二共模抑制过孔242、第一反焊盘246以及第二反焊盘248，上述结构以及位置关系与其在封装装置200中的相同，此处不再赘述。
第一信号过孔230和第二信号过孔232中除了存在差分信号，还存在共模信号(即共模噪声)，且上述差分信号和共模信号分别产生不同的电场。由于第一共模抑制过孔240设置在第一信号过孔230和第二信号过孔232之间，且其第一端与平面层电连接而其他部分与周围的介质绝缘，因此第一共模抑制过孔240在上述共模信号产生的电场中形成谐振回路，从而激发第一信号过孔230和第二信号过孔232中共模信号的谐振特性，在保留差分信号的同时抑制共模信号。相比于现有技术中通过滤波走线且额外打接地过孔的方式实现共模抑制，本申请通过第一共模抑制过孔240来抑制共模噪声，对加工工艺的要求较为简单，且无需额外的滤波走线，因此节省了PCB900的物理空间，有利于其小型化，同时降低了其制造成本。

Claims (16)

  1. 一种共模抑制的封装装置，其特征在于，所述封装装置包括基板，以及设置于所述基板中的第一平面层、第一信号过孔、第二信号过孔和第一过孔，其中：
    所述第一信号过孔和所述第二信号过孔用于传输差分信号；
    所述第一过孔设置于所述第一信号过孔和所述第二信号过孔之间，且所述第一过孔的第一端与所述第一平面层电连接，所述第一过孔除所述第一端的其他部分与其周围的介质绝缘，所述第一过孔的至少一部分分别与所述第一信号过孔和所述第二信号过孔位于同一水平面，所述第一平面层为地层或电源层。
  2. 如权利要求1所述的封装装置，其特征在于，所述封装装置还包括第二过孔，设置于所述第一信号过孔和所述第二信号过孔之间，所述第二过孔的第一端与所述第一平面层电连接，所述第一过孔除所述第一端的其他部分与其周围的介质绝缘，所述第二过孔的至少一部分分别与所述第一信号过孔和所述第二信号过孔位于同一水平面，且所述第一过孔和所述第二过孔分别设置于第一虚拟平面的两侧，所述第一虚拟平面为穿过所述第一信号过孔的中轴线和所述第二信号过孔的中轴线形成的平面。
  3. 如权利要求2所述的封装装置，其特征在于，所述第一过孔和所述第二过孔的中轴线均位于第二虚拟平面上，所述第二虚拟平面为所述第一信号过孔和所述第二信号过孔的对称平面。
  4. 如权利要求2或3所述的封装装置，其特征在于，所述第一过孔和所述第二过孔关于所述第一虚拟平面对称。
  5. 如权利要求2至4任意一项所述的封装装置，其特征在于，所述封装装置还包括第二平面层，所述第一过孔和所述第二过孔分别穿过所述第二平面层，且所述第一过孔和所述第二过孔分别通过设置于所述第二平面层上的第一反焊盘和第二反焊盘与所述第二平面层保持隔离，所述第二平面层为地层或电源层。
  6. 如权利要求5所述的封装装置，其特征在于，所述第一平面层和所述第二平面层均为地层，所述封装装置还包括设置于所述基板中的接地过孔，其中：
    所述接地过孔与所述第一平面层和所述第二平面层电连接。
  7. 如权利要求2至6任意一项所述的封装装置，其特征在于，所述封装装置还包括信号层，所述第一信号过孔和所述第二信号过孔的一端分别与所述信号层电连接，所述第一过孔和所述第二过孔分别穿过所述信号层，且所述第一过孔和所述第二过孔分别通过设置于所述信号层上的第三反焊盘和第四反焊盘与所述信号层保持隔离。
  8. 如权利要求1至7任意一项所述的封装装置，其特征在于，所述封装装置还包 括设置于所述基板一侧的裸片和第一金属连接件，所述裸片通过所述第一金属连接件与所述第一信号过孔、所述第二信号过孔和所述第一平面层电连接。
  9. 如权利要求1至8任意一项所述的封装装置，其特征在于，所述封装装置还包括设置于所述基板一侧的第二金属连接件，所述封装装置通过所述第二金属连接件与印制电路板形成电连接。
  10. 一种共模抑制的印制电路板，其特征在于，所述印制电路板包括基板，以及设置于所述基板中的第一平面层、第一信号过孔、第二信号过孔和第一过孔，其中：
    所述第一信号过孔和所述第二信号过孔用于传输差分信号；
    所述第一过孔设置于所述第一信号过孔和所述第二信号过孔之间，且所述第一过孔的第一端与所述第一平面层电连接，所述第一过孔除所述第一端的其他部分与其周围的介质绝缘，所述第一过孔的至少一部分分别与所述第一信号过孔和所述第二信号过孔位于同一水平面，所述第一平面层为地层或电源层。
  11. 如权利要求10所述的印制电路板，其特征在于，所述印制电路板还包括第二过孔，设置于所述第一信号过孔和所述第二信号过孔之间，所述第二过孔的第一端与所述第一平面层电连接，所述第二过孔除所述第一端的其他部分与其周围的介质绝缘，所述第二过孔的至少一部分分别与所述第一信号过孔和所述第二信号过孔位于同一水平面，且所述第一过孔和所述第二过孔分别设置于第一虚拟平面的两侧，所述第一虚拟平面为穿过所述第一信号过孔的中轴线和所述第二信号过孔的中轴线形成的平面。
  12. 如权利要求11所述的印制电路板，其特征在于，所述第一过孔和所述第二过孔的中轴线均位于第二虚拟平面上，所述第二虚拟平面为所述第一信号过孔和所述第二信号过孔的对称平面。
  13. 如权利要求11或12所述的印制电路板，其特征在于，所述第一过孔和所述第二过孔关于所述第一虚拟平面对称。
  14. 如权利要求11至13任意一项所述的印制电路板，其特征在于，所述印制电路板还包括第二平面层，所述第一过孔和所述第二过孔分别穿过所述第二平面层，且所述第一过孔和所述第二过孔分别通过设置于所述第二平面层上的第一反焊盘和第二反焊盘与所述第二平面层保持隔离，所述第二平面层为地层或电源层。
  15. 如权利要求14所述的印制电路板，其特征在于，所述第一平面层和所述第二平面层均为地层，所述印制电路板还包括设置于所述基板中的接地过孔，其中：
    所述接地过孔与所述第一平面层和所述第二平面层电连接。
  16. 如权利要求11至15任意一项所述的印制电路板，其特征在于，所述印制电 路板还包括信号层，所述第一信号过孔和所述第二信号过孔的一端分别与所述信号层电连接，所述第一过孔和所述第二过孔分别穿过所述信号层，且所述第一过孔和所述第二过孔分别通过设置于所述信号层上的第三反焊盘和第四反焊盘与所述信号层保持隔离。
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