WO2020195808A1 - Semiconductor device production method and laminated body - Google Patents

Semiconductor device production method and laminated body Download PDF

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Publication number
WO2020195808A1
WO2020195808A1 PCT/JP2020/010413 JP2020010413W WO2020195808A1 WO 2020195808 A1 WO2020195808 A1 WO 2020195808A1 JP 2020010413 W JP2020010413 W JP 2020010413W WO 2020195808 A1 WO2020195808 A1 WO 2020195808A1
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WO
WIPO (PCT)
Prior art keywords
wafer
adhesive sheet
semiconductor device
attached
planned
Prior art date
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PCT/JP2020/010413
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French (fr)
Japanese (ja)
Inventor
祐介 文田
真也 田久
和人 愛澤
裕也 長谷川
Original Assignee
リンテック株式会社
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Application filed by リンテック株式会社 filed Critical リンテック株式会社
Priority to JP2021508991A priority Critical patent/JPWO2020195808A1/ja
Priority to KR1020217014295A priority patent/KR20210142584A/en
Priority to CN202080006808.4A priority patent/CN113165121B/en
Publication of WO2020195808A1 publication Critical patent/WO2020195808A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/50—Working by transmitting the laser beam through or within the workpiece
    • B23K26/53—Working by transmitting the laser beam through or within the workpiece for modifying or reforming the material inside the workpiece, e.g. for producing break initiation cracks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68336—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding involving stretching of the auxiliary support post dicing

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device and a laminate used in the method for manufacturing a semiconductor device.
  • DBG Depth Dicing Before Grinding
  • SDBG Stealth Dicing Before Grinding
  • SDBG is a modified layer that absorbs multiple photons inside the wafer by irradiating the wafer with a laser that has a wavelength that is transparent to the wafer and irradiates the wafer along the planned division line.
  • This is a processing method in which the back surface side of the wafer is ground to make the wafer thinner, and the wafer is divided into individual semiconductor chips using the modified layer as a division starting point. If a processing method such as SDBG in which the gap between chips in the divided wafer is very small is used, the fragmented semiconductor chip may be chipped or cracked. Therefore, for example, Patent Document 1 proposes to provide a chipping prevention layer made of a metal film or the like at each intersection of the planned division lines on the wafer surface.
  • the present invention relates to a method for manufacturing a semiconductor device in which chips are less likely to crack or chip during the manufacturing process even when the distance between adjacent chips after individualization is small, and a laminate suitable for the method.
  • the challenge is to provide.
  • the present inventors appropriately set the sticking direction of the adhesive sheet to be stuck on the circuit layer forming surface of the wafer based on the planned individualization area of the wafer. Then, they found that the above problems could be solved, and completed the present invention. That is, the present invention provides the following [1] to [6].
  • [1] A method for manufacturing a semiconductor device having a rectangular planar shape. An adhesive sheet is attached along the short side direction of the planned individualization region to the surface of the wafer including a plurality of rectangular individualized planned regions arranged in a matrix.
  • a method for manufacturing a semiconductor device in which the back surface of a wafer to which the adhesive sheet is attached is ground, and the wafer is divided along a planned division line defining the planned individualization region. [2] After the adhesive sheet is attached to the surface of the wafer, a modified portion serving as a starting point of division is formed inside the wafer at a plane position corresponding to the planned division line.
  • a method for manufacturing a semiconductor device in which cracks and chips are less likely to occur in the manufacturing process even when the distance between adjacent chips after individualization is small, and a laminate suitable for the method. be able to.
  • a schematic of a semiconductor chip as a semiconductor device which is obtained by processing a wafer on which a circuit layer is formed, a laminate in which an adhesive sheet is attached on the circuit layer of the wafer, and a wafer using the laminate.
  • the semiconductor device manufactured by the method for manufacturing a semiconductor device of the present embodiment includes a wafer portion and a circuit portion formed on the surface thereof, and has a rectangular planar shape.
  • semiconductor device refers to all devices used in processors, memories, sensors, etc. that can function by utilizing semiconductor characteristics. Specifically, a wafer having an integrated circuit, a thin wafer having an integrated circuit, a chip having an integrated circuit, a thin chip having an integrated circuit, an electronic component including these chips, and the electronic component concerned. Examples include electronic devices provided.
  • a semiconductor device is obtained by disassembling a wafer having a circuit layer on its surface. Further, in the step of processing a wafer provided with a circuit layer into a semiconductor device, a laminate in which an adhesive sheet is attached to the circuit layer forming surface of the wafer is used.
  • FIG. 1 shows a wafer on which a circuit layer is formed, a laminate in which an adhesive sheet is attached to a surface of the wafer on which a circuit layer is formed, and a semiconductor chip as a semiconductor device obtained by processing the wafer.
  • FIG. 1A first, a wafer W having a circuit layer C formed on its surface is prepared by a semiconductor forming process including a photolithography method.
  • FIG. 1B the adhesive sheet 1 is attached to the surface of the wafer W on which the circuit layer C is formed to obtain the laminated body 10.
  • the back surface of the wafer W is ground as necessary, and the wafer W is divided along the planned division line defining the planned individualization region to obtain individual pieces.
  • the wafer WI after conversion. In this way, the wafer W having the circuit layer C is fragmented into a plurality of pieces to obtain a semiconductor chip CP as a semiconductor device. The area to be separated will be described in detail later.
  • the wafer W is made by cutting out high-purity single crystal silicon into a disk shape.
  • the diameter of the wafer W is not limited to this, but is, for example, 12 inches.
  • the circuit layer C is a layer including a semiconductor circuit formed on the surface of the wafer W by the semiconductor manufacturing process.
  • the semiconductor process includes a step of forming a thin film of silicon oxide, aluminum, or the like as a circuit material on a silicon wafer by sputtering, electroplating, CVD, or the like, and then forming a semiconductor circuit by a photolithography method.
  • the photolithography method includes a step of coating the thin film formed on a silicon wafer with a resist film, a step of irradiating the resist film with UV light through a mask on which a circuit pattern is formed, and an uncured resist film.
  • the wafer W is divided into a plurality of semiconductor chips having a size when viewed in a plane and each having a size of about 12 mm ⁇ 6 mm. When divided into this size, about 1,000 semiconductor chips can be obtained from a wafer having a diameter of 12 inches.
  • the semiconductor chip which is a semiconductor device, includes a wafer portion derived from the wafer W and a circuit portion derived from the circuit layer C formed on the surface thereof.
  • the semiconductor chip obtained by the method for manufacturing the semiconductor device of the present embodiment has a rectangular planar shape. Therefore, various functions can be added to the semiconductor chip, and the top and bottom of the semiconductor chip can be easily grasped.
  • the adhesive sheet 1 is attached to the surface of the wafer W on which the circuit layer C is formed.
  • the pressure-sensitive adhesive sheet 1 is a laminate including a base material layer and a pressure-sensitive adhesive layer laminated on the base material layer, and is typically on the base material layer and at least one surface side of the base material layer. It is a laminate including a buffer layer provided and an adhesive layer provided on the other surface side of the base material layer.
  • the pressure-sensitive adhesive sheet 1 may contain other constituent layers other than these.
  • a primer layer may be formed on the surface of the base material on the pressure-sensitive adhesive layer side, and the surface of the pressure-sensitive adhesive layer may be formed during use.
  • a release sheet for protecting the pressure-sensitive adhesive layer may be laminated.
  • the base material may be a single layer or a multilayer.
  • the pressure-sensitive adhesive sheet 1 is attached to the wafer W so that the pressure-sensitive adhesive layer of the pressure-sensitive adhesive sheet 1 is in contact with the circuit layer C of the wafer W, so that the pressure-sensitive adhesive sheet 1 serves as a protective film that protects the circuit layer C of the wafer W. Play the role of.
  • the material of the base material is not particularly limited, but it may be a resin film from the viewpoint that it is suitable for processing members of electronic parts because it generates less dust than paper or non-woven fabric and is easily available. preferable.
  • the pressure-sensitive adhesive sheet has a base material layer, the shape stability of the pressure-sensitive adhesive sheet can be improved and the pressure-sensitive adhesive sheet can be given elasticity. Further, even when the circuit layer C of the wear W has large irregularities, the surface opposite to the surface on which the adhesive sheet is attached tends to be kept smooth.
  • the base material layer may be a base material layer made of a single layer film made of one resin film, or may be a base material layer made of a multi-layer film in which a plurality of resin films are laminated.
  • the thickness of the base material layer is preferably 5 to 250 ⁇ m, more preferably 10 to 200 ⁇ m, still more preferably 25, from the viewpoint of giving an appropriate elasticity to the pressure-sensitive adhesive sheet and from the viewpoint of handleability when the pressure-sensitive adhesive sheet is wound up. It is ⁇ 150 ⁇ m.
  • the resin film that can be used for the base material layer include polyolefin-based film, vinyl halide polymerization-based film, acrylic resin-based film, rubber-based film, cellulose-based film, polyester-based film, polycarbonate-based film, and polystyrene-based film.
  • polyester-based film used for the base material layer may be a film made of a copolymer of polyester, or may be a resin mixed film made of a mixture of the polyester and a relatively small amount of other resin.
  • polyester-based films polyethylene terephthalate film is preferable from the viewpoint of easy availability and high thickness accuracy.
  • the pressure-sensitive adhesive layer provided on the base material layer or the intermediate layer protects the circuit layer C by securely fixing the pressure-sensitive adhesive sheet to the circuit layer C of the wafer W.
  • the pressure-sensitive adhesive layer contains a pressure-sensitive adhesive. Examples of the adhesive include acrylic adhesives, rubber adhesives, urethane adhesives, silicone adhesives, polyvinyl ether adhesives, olefin adhesives and the like. These pressure-sensitive adhesives may be used alone or in combination of two or more.
  • the thickness of the pressure-sensitive adhesive layer can be appropriately adjusted according to the size of the unevenness of the circuit layer to be protected, but is preferably 5 to 200 ⁇ m, more preferably 7 to 150 ⁇ m, and further preferably 10 to 100 ⁇ m. is there.
  • the intermediate layer is not particularly limited, but is preferably formed from a resin composition containing a urethane (meth) acrylate and a thiol group-containing compound from the viewpoint of obtaining good unevenness absorption.
  • the thickness of the intermediate layer can be appropriately adjusted according to the size of the unevenness on the surface of the semiconductor to be protected, but is preferably 50 to 400 ⁇ m from the viewpoint of being able to absorb relatively large unevenness. It is more preferably 70 to 300 ⁇ m, still more preferably 80 to 250 ⁇ m.
  • FIG. 2 is an explanatory diagram showing the relationship between the sticking direction of the adhesive sheet 1 on the wafer W and the planned individualization region R on the wafer W.
  • a V notch Wv indicating the reference direction of processing or processing on the wafer W and the individual planned individualization regions R defined by the planned division line E are included.
  • the semiconductor circuit provided in the above is formed.
  • the semiconductor circuit is formed with reference to the direction indicated by the V notch Wv.
  • the bonding of the adhesive sheets which will be described later, is also performed with reference to the direction indicated by the V notch Wv.
  • the individualized area R has a rectangular shape in a plan view.
  • the planned division line E that defines the planned separation area R is a virtual one, and it is sufficient that individual circuits are formed so as not to straddle the planned division line E, and the planned separation area R is defined. It is not necessary to physically form the planned division line E on the surface of the wafer W or the circuit layer C. However, in order to make it easier to recognize the planned individualization region R and to facilitate the division of the wafer W, a processing groove or the like to be the planned division line E is formed in advance by the photolithography method. May be good. By making the area R to be separated into a rectangular shape, the shape of the finally obtained semiconductor chip is also rectangular. In the example shown in FIG.
  • each circuit of the circuit layer C is arranged so that the short side direction d2 of each planned individualization region R coincides with the direction d3 (hereinafter, also referred to as the vertical direction) indicated by the V notch Wv. It is formed.
  • the long side direction d1 of the planned individualization region coincides with the direction orthogonal to the direction d3 indicated by the V notch Wv (hereinafter, also referred to as the lateral direction).
  • the length of the planned individualization region R in the long side direction is preferably 5 to 5 from the viewpoint of easily suppressing chipping or cracking of the semiconductor chip during the manufacturing process and easily imparting various functions to the semiconductor chip. It is 50 mm, more preferably 7 to 40 mm, still more preferably 10 to 30 mm.
  • the length of the planned individualization region R in the short side direction is preferably 2 to 20 mm, more preferably 2 to 20 mm from the viewpoint of improving ease of handling and facilitating imparting the minimum necessary functions to the semiconductor chip. It is 3 to 18 mm, more preferably 4 to 15 mm.
  • the aspect ratio of the planned individualization region R which is expressed by the ratio of the length in the long side direction to the length in the short side direction (length in the long side direction / length in the short side direction), is a semiconductor in the manufacturing process. From the viewpoint of appropriately maintaining a balance between the ability to suppress chipping and cracking of the chip and the ability to impart functions to the semiconductor chip, the ratio is preferably 1.05 or more, more preferably 1.10 or more, still more preferably 1.15 or more. Yes, and is preferably 10 or less, more preferably 7.0 or less, and even more preferably 5.0 or less.
  • the wafer W is divided by SDBG, so that the distance between adjacent chips is substantially zero. Therefore, the vertical and horizontal lengths of the planned individualization region R match the vertical and horizontal lengths of the semiconductor chip. It should be noted that the semiconductor circuit may not be provided outside the planned individualization region R, or a semiconductor circuit that is not used outside the planned individualization region may be provided as a dummy circuit.
  • the pressure-sensitive adhesive sheet 1 has a length and width capable of covering the entire surface of the wafer W.
  • a wafer W having a diameter of 12 inches for example, a long adhesive sheet 1 having a width of 400 mm can be used.
  • the wafer W covered with the adhesive sheet 1 and the region R to be separated from the wafer W are shown by thin lines for easy understanding. If a light-transmitting adhesive sheet 1 is used, the shape and alignment direction of the individualized region R can be confirmed via the adhesive sheet 1.
  • the wafer W is set in the bonding device with reference to the direction d3 indicated by the V notch Wv.
  • the wafer W is set so that the sticking direction d4 of the adhesive sheet 1 by the sticking device is along the direction d3 indicated by the V notch Wv.
  • the short side direction d2 of the planned individualization region R is aligned with the direction d3 indicated by the V notch Wv.
  • the laminated body 10 is formed in a state where tension is applied in the direction along the short side direction d2 of the planned individualization region R.
  • the sticking direction d4 of the adhesive sheet is set so as to follow the direction d3 indicated by the V notch Wv (that is, the short side direction d2 of the planned individualization region R in this example), but FIG.
  • the sticking direction d4 of the adhesive sheet 1 may be set so as to be within a constant angle ⁇ with respect to the direction d3 indicated by the V notch Wv.
  • ⁇ is preferably in the range of ⁇ 45 °, more preferably ⁇ 40 °, and even more preferably ⁇ 35 ° with respect to the direction d3 indicated by the V notch Wv.
  • FIG. 3 is a schematic cross-sectional view showing a manufacturing process of the laminated body.
  • FIG. 3A is a diagram showing a state in which the wafer W on which the circuit layer C is formed is placed on the support 100
  • FIG. 3B is a view showing the adhesive sheet 1 on the circuit layer C of the wafer W
  • 3 (C) is a diagram showing a state in which the adhesive sheet 1 is attached on the circuit layer C of the wafer W.
  • FIG. 3 (A) after the wafer W is placed on the support 100 so that the back surface of the wafer W on which the circuit layer C is formed is in contact with the support 100, as shown in FIG. 3 (B).
  • the adhesive sheet 1 is attached onto the circuit layer C of the wafer W.
  • one end of the adhesive sheet 1 is wound by a winding member or gripped by a gripping member to hold the adhesive sheet 1 floating from the wafer W, and the adhesive sheet 1 is pressed from the other end by the pressing body 101.
  • the adhesive sheet 1 is attached to the forming surface of the circuit layer C of the wafer W.
  • a constant tension is applied in the longitudinal direction of the adhesive sheet 1 (that is, the sticking direction of the adhesive sheet 1) so as to minimize the slack of the adhesive sheet 1, and the pressing force by the pressing body is applied to the longitudinal direction of the adhesive sheet 1.
  • the adhesive sheet 1 is attached to the wafer W in a state where tension is applied in the attachment direction d4 by being added in the direction.
  • the adhesive sheet 1 is attached to the circuit layer C of the wafer W with almost no tension applied in the lateral direction of the adhesive sheet 1.
  • the adhesive sheet 1 protruding from the wafer W is cut and removed, if necessary. In this way, as shown in FIG. 3C, the laminated body 10 in which the adhesive sheet 1 is attached on the circuit layer C of the wafer W is produced.
  • the material constituting the support 100 is not particularly limited, and for example, a metal material such as stainless steel is used.
  • An example of the method for manufacturing a semiconductor device of the present embodiment is to process a laminate in which an adhesive sheet is attached on a circuit layer of a wafer, divide the wafer, grind the back surface of the wafer, and divide the wafer.
  • This includes a step of attaching a transfer sheet to a surface opposite to the circuit layer forming surface (that is, the back surface of the wafer), removing the adhesive sheet, and then dividing the wafer together with the transfer sheet into individual pieces.
  • the transfer sheet is a sheet for holding the wafer by being transferred to the front surface of the wafer after the wafer is separated from the adhesive sheet by being attached to the back surface of the wafer.
  • FIG. 4A is a diagram showing a state in which the laminated body 10 is placed on a support 200 different from the support 100. As shown in FIG. 4A, the laminated body 10 is placed on the support 200 so that the adhesive sheet 1 is in contact with the support 200.
  • the support 200 for example, one made of the same material as the support 100 or a ceramic porous table can be used.
  • FIG. 4B is a diagram showing how the wafer W is irradiated with a laser from the back surface side. As shown in FIG.
  • the condenser 102 is used to position the laser 103 so that the focusing point of the laser 103 having a wavelength that is transparent to the wafer W is inside the wafer W.
  • the laser 103 is irradiated to the wafer W from the back surface side while the laser 103 and the wafer W are relatively moved along the planned division line E defining the individualized planned region R.
  • the modified portion M is formed inside the wafer W at the plane position corresponding to the planned division line E.
  • the modified portion M is a portion where the wafer W is modified by irradiation with a laser, and serves as a starting point at which the wafer W is divided.
  • FIG. 4C is a diagram showing a state in which the back surface side of the wafer W is ground. As shown in FIG. 4C, the back surface of the wafer W is ground to a desired thickness using a grinder 104. By this process, the wafer W is made thinner and lighter. At the same time, the wafer W is cut along the planned division line E that defines the planned individualization region R with the reformed portion M as the starting point. Further, the modified portion M formed in the wafer W is removed by grinding.
  • the wafer W is cut into individual chips starting from the modified portion M, and at the same time, the stress in the laminate is released, and the chips are released in the direction in which the adhesive sheet is attached. It is presumed that the chips become easier to move, and as a result, the chips come into contact, press, rub, or collide with each other to induce cracks.
  • the reason why chipping or cracking of a chip is suppressed is not limited to this, but one of the following reasons can be considered. That is, by making the vertical length and the horizontal length of the chip different and attaching the adhesive sheet along the short side direction of the chip, compared with the case where the adhesive sheet is attached along the long side direction of the chip. Therefore, the number of cutting lines between the chips in the sticking direction of the adhesive sheet increases. As a result, it is presumed that the amount of movement of the chips in the sticking direction is dispersed by more chips, the contact, pressing, friction, collision, etc. between the chips are reduced, which leads to the suppression of cracking and chipping.
  • the modified portion is removed by grinding. However, for example, in applications where thinning of the wafer is not required or when the wafer is thick in the first place, at least one of the modified portions is removed even after grinding. The portion may remain on the wafer.
  • FIG. 5A shows a step of separating the laminated body 11 in which the wafer W is ground and divided from the support 200.
  • FIG. 5B shows a step of attaching the laminate 11 obtained by grinding and dividing the wafer W to the transfer sheet held on the ring frame 300.
  • FIG. 5C shows a step of separating the adhesive sheet 1 from the laminate 11 attached to the transfer sheet 303.
  • FIG. 5D shows an expanding step of separating individual chips together with the transfer sheet 303.
  • FIG. 5 (B) the periphery of the laminated body 11 in which the wafer W was ground and divided, which was separated from the support 200 as shown in FIG. 5 (A), was held by the ring frame 300.
  • the transfer sheet 303 including the film-like adhesive 301 and the support sheet 302 is attached to the film-like adhesive 301. Then, as shown in FIG. 5 (C), the adhesive sheet 1 is separated from the laminate 11 in which the wafer W is ground and divided, and further, as shown in FIG. 5 (D), the support sheet 302 is pulled. , The film-like adhesive 301 is also cut according to the chips (the film-like adhesive after cutting is indicated by reference numeral 301a), a gap G is provided between the chips, and the chips are separated into individual chips.
  • the transfer sheet 303 has curability on, for example, a support sheet 302 containing a base material made of the same material as the base material layer of the pressure-sensitive adhesive sheet 1 described above, via an adhesive layer as necessary. Those provided with the film-like adhesive 301 can be used.
  • the wafer is divided by SDBG, but the present invention is not limited to this, and for example, the wafer may be divided by using DBG.
  • DBG when DBG is used, when the distance between the chips formed by dicing is small, the effect of preventing chipping or cracking of the chips is likely to be exhibited.
  • the wafer When DBG is used, the wafer may be half-cut from the surface of the wafer on which the circuit layer is formed, an adhesive sheet may be attached to the circuit-forming surface of the wafer, and then the back surface of the wafer may be ground.
  • Examples and Comparative Examples The chips of Examples 1 to 3 and Comparative Examples 1 to 4 were produced by the following procedure. In Examples 1 to 3 and Comparative Examples 1 to 4, mirror wafers on which no circuit layer was formed were used from the viewpoint of making the experimental conditions as uniform as possible and facilitating the experiment.
  • Example 1 A single crystal silicon mirror wafer with a diameter of 12 inches is prepared, and the adhesive sheet is wafered along the direction indicated by the apex of the V notch (hereinafter referred to as the vertical direction) with reference to the V notch provided on the mirror wafer. It was affixed to one surface (hereinafter referred to as the first surface).
  • a back grind tape "E-3135KN” manufactured by Lintec Corporation was used as the adhesive sheet.
  • the adhesive sheet is attached using a pasting device (“RAD-3510F / 12” manufactured by Lintec Corporation), pushing amount 15 ⁇ m, protrusion amount 150 ⁇ m, sticking speed 5 mm / s, sticking stress 0.35 MPa, sticking temperature 23 ° C.
  • the other surface of the wafer (hereinafter referred to as the second surface) is ground until the thickness of the wafer reaches 30 ⁇ m, thereby causing the inside of the wafer to be ground.
  • the modified layer was removed and the wafer was split along the planned division line defining each planned fragmentation region.
  • a dicing tape (“D-175” manufactured by Lintec Corporation) installed on the tape mounter “RAD-2700” manufactured by Lintec Corporation is attached to the second surface of the individualized wafer, and an adhesive sheet is attached. Removed.
  • Example 2 In the same procedure as in Example 1, the length in the vertical direction is 4 mm and the length in the horizontal direction is 12 mm with respect to the wafer to which the adhesive sheet is attached to the first surface along the vertical direction.
  • the number of chips in which cracks were generated was 1 out of 1471, and the crack occurrence rate was 0.07%.
  • Example 3 In the same procedure as in Example 1, the length in the vertical direction is 8 mm and the length in the horizontal direction is 12 mm with respect to the wafer to which the adhesive sheet is attached to the first surface along the vertical direction.
  • the number of chips in which cracks were generated was 1 out of 735, and the crack occurrence rate was 0.13%.
  • FIG. 6 is a schematic plan view showing an embodiment of the present invention and a comparative example in comparison with each other.
  • the sticking direction d4 of the adhesive sheet 1 and the short side direction d2 of the planned individualization region R are set to the direction d3 indicated by the V notch Wv. Matching.
  • Example 3 Same as in Example 1 except that the length in the vertical direction is 12 mm and the length in the horizontal direction is 12 mm with respect to the wafer to which the adhesive sheet is attached to the first surface in the same manner as in Example 1. Under the conditions, the wafer was subjected to SDBG processing and fragmented into 490 chips. When the observation was carried out in the same manner as in Example 1, the number of chips in which cracks were generated was 6 out of 490, and the crack occurrence rate was 1.22%.
  • Example 4 Same as in Example 1 except that the length in the vertical direction is 12 mm and the length in the horizontal direction is 8 mm with respect to the wafer to which the adhesive sheet is attached to the first surface in the same manner as in Example 1. Under the conditions, the wafer was processed by SDBG and fragmented into 735 chips. When the observation was carried out in the same manner as in Example 1, the number of chips in which cracks were generated was 9 out of 735, and the crack occurrence rate was 1.22%.
  • Comparative Example 3 in which the shape of the chip is square and the length of one side is equal to the length of the long side of the chips of Examples 1 to 3, the number of cracked chips increases and the crack occurrence rate. It can be seen that the value of is increased 10 times or more as compared with Examples 1 and 2, and is increased nearly 10 times as compared with Example 3.
  • chips are less likely to be chipped or cracked even if a processing method such as SDBG for dividing a wafer is used so that the distance between chips becomes extremely small, and the processor, memory, sensor, etc. It can be suitably applied to the production of the semiconductor chip used.
  • the laminate of the present invention can be suitably used in the method for manufacturing the above-mentioned semiconductor device.
  • Adhesive sheet 10 Laminated body 11: Laminated body 100, 200 in which the wafer portion is ground and divided: Support 101: Pressing body 102: Condenser 103: Laser 104: Grinder 300: Ring frame 301: Film-like adhesion Agent 301a: Cut film-like adhesive 302: Support sheet 303: Transfer sheet C: Circuit layer CP: Semiconductor chip (semiconductor device) d1: Long side direction d2: Short side direction d3: Direction indicated by V notch d4: Attachment direction (tension direction) E: Scheduled division line G: Gap M: Modified part P: Crack R: Planned individualization area Wv: V notch W: Wafer WI: Individualized wafer

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Abstract

Provided is a semiconductor device production method with which it is unlikely to cause cracks or defects to a chip being manufactured even in the case when the distance between adjacent diced chips is small. This method is for producing a semiconductor device having a rectangular planar shape, and involves: pasting, on a surface of a wafer including a plurality of rectangular to-be-diced regions arranged in a matrix configuration, an adhesive sheet along a short-side direction of the to-be-diced regions; grinding the rear surface of the wafer having the adhesive sheet pasted thereon; and dividing chips along planned division lines that define the to-be-diced regions.

Description

半導体装置の製造方法及び積層体Manufacturing method and laminate of semiconductor devices
　本発明は、半導体装置の製造方法、及び、半導体装置の製造方法に用いられる積層体に関する。 The present invention relates to a method for manufacturing a semiconductor device and a laminate used in the method for manufacturing a semiconductor device.
　シリコン基板上に半導体回路が形成された半導体チップ等の半導体装置の製造プロセスとして、ＤＢＧ（Ｄｉｃｉｎｇ　Ｂｅｆｏｒｅ　Ｇｒｉｎｄｉｎｇ）と称される方法が知られている。ＤＢＧとは、仕上がり厚さに相当する深さの溝をウエハのストリートに形成しておき、ウエハの裏面を研削することによって、先に形成した溝をウエハの裏面から表出させてウエハを個々の半導体チップに分割する方法である。
　１枚のウエハからのチップの取り数を増やす等の目的で、ＳＤＢＧ（Ｓｔｅａｌｔｈ　Ｄｉｃｉｎｇ　Ｂｅｆｏｒｅ　Ｇｒｉｎｄｉｎｇ）と称される方法も提案されている。ＳＤＢＧとは、ウエハに対して透過性を有する波長のレーザーの集光点をウエハ内部に位置付けて、分割予定ラインに沿ってレーザーをウエハに照射して、ウエハ内部に多光子吸収による改質層を形成した後、ウエハの裏面側を研削してウエハを薄くするとともに、改質層を分割起点にしてウエハを個々の半導体チップに分割する加工方法である。
　ＳＤＢＧのように、分割されたウエハにおけるチップ間の隙間が非常に小さくなる加工方法を用いると、個片化された半導体チップに欠けや割れを生じることがある。このため、例えば、特許文献１では、ウエハ表面の分割予定ラインの各交差点に金属膜等からなる欠け防止層を設けることが提案されている。 As a manufacturing process of a semiconductor device such as a semiconductor chip in which a semiconductor circuit is formed on a silicon substrate, a method called DBG (Dicking Before Grinding) is known. In DBG, a groove having a depth corresponding to the finished thickness is formed on the street of the wafer, and the back surface of the wafer is ground so that the groove formed earlier is exposed from the back surface of the wafer and the wafer is individually formed. This is a method of dividing into semiconductor chips.
A method called SDBG (Stealth Dicing Before Grinding) has also been proposed for the purpose of increasing the number of chips taken from one wafer. SDBG is a modified layer that absorbs multiple photons inside the wafer by irradiating the wafer with a laser that has a wavelength that is transparent to the wafer and irradiates the wafer along the planned division line. This is a processing method in which the back surface side of the wafer is ground to make the wafer thinner, and the wafer is divided into individual semiconductor chips using the modified layer as a division starting point.
If a processing method such as SDBG in which the gap between chips in the divided wafer is very small is used, the fragmented semiconductor chip may be chipped or cracked. Therefore, for example, Patent Document 1 proposes to provide a chipping prevention layer made of a metal film or the like at each intersection of the planned division lines on the wafer surface.
特開２０１８－６６５３号公報JP-A-2018-6653
　しかしながら、チップサイズの小型化への要請はますます高まっており、半導体チップの小型化に伴って、半導体チップの割れや欠けの問題が顕著になっている。本発明者らの検討によれば、ＤＢＧでダイシングにより形成される隙間を極力小さくする方法や、ＳＤＢＧのようにウエハの分割時点では、隣り合うチップ間の間隔が実質的にゼロであるような方法を用いる場合、チップサイズが小型化すると、隣接するチップ同士の接触による割れや欠けの問題がより顕著になることが判明している。したがって、より効果的にチップの欠けや割れを防止できる新規かつ有用な半導体装置の製造方法が求められている。 However, the demand for miniaturization of chip size is increasing more and more, and with the miniaturization of semiconductor chips, the problem of cracking or chipping of semiconductor chips is becoming more prominent. According to the study by the present inventors, a method of minimizing the gap formed by dicing in DBG and a method such as SDBG in which the distance between adjacent chips is substantially zero at the time of wafer division. When the method is used, it has been found that as the chip size is reduced, the problem of cracking or chipping due to contact between adjacent chips becomes more prominent. Therefore, there is a demand for a new and useful semiconductor device manufacturing method capable of more effectively preventing chipping and cracking of chips.
　本発明は、上記問題を鑑み、隣接する個片化後のチップ間の距離が小さい場合でも、製造工程中にチップに割れや欠けが生じにくい半導体装置の製造方法、及び、それに適した積層体を提供することを課題とする。 In view of the above problems, the present invention relates to a method for manufacturing a semiconductor device in which chips are less likely to crack or chip during the manufacturing process even when the distance between adjacent chips after individualization is small, and a laminate suitable for the method. The challenge is to provide.
　本発明者らは、上記課題を解決すべく鋭意検討を重ねた結果、ウエハの回路層形成面に貼付する粘着シートの貼付方向を、ウエハの個片化予定領域に基づいて適切に設定することで、上記課題を解決し得ることを見出し、本発明を完成した。
　すなわち、本発明は、以下の［１］～［６］を提供するものである。
［１］平面形状が矩形状の半導体装置の製造方法であって、
　マトリクス状に並んでいる複数の矩形状の個片化予定領域を含むウエハの表面に、前記個片化予定領域の短辺方向に沿って粘着シートを貼付し、
　前記粘着シートが貼付されたウエハの裏面を研削するととともに、前記個片化予定領域を画定する分割予定線に沿って前記ウエハを分割する、半導体装置の製造方法。
［２］前記ウエハの表面に前記粘着シートを貼付した後、前記分割予定線に対応する平面位置における前記ウエハの内部に、分割の起点となる改質部を形成し、
　前記粘着シートが貼付された前記ウエハの裏面を研削し、前記分割予定線に沿って前記ウエハを分割する、上記［１］に記載の半導体装置の製造方法。
［３］前記個片化予定領域の、長辺方向の長さ／短辺方向の長さ、で表されるアスペクト比が、１．０５以上である、上記［１］又は［２］に記載の半導体装置の製造方法。
［４］前記個片化予定領域は、長辺方向の長さが５～５０ｍｍであり、短辺方向の長さが２～２０ｍｍである、上記［１］～［３］のいずれか一つに記載の半導体装置の製造方法。
［５］研削後の前記ウエハの裏面に転写シートを貼付し、
　前記転写シート貼付後に、前記粘着シートを前記ウエハから分離する、上記［１］～［４］のいずれか一つに記載の半導体装置の製造方法。
［６］マトリクス状に並んだ複数の矩形状の個片化予定領域を含むウエハと、
　前記個片化予定領域の短辺方向に沿ってテンションを付加した状態で、前記ウエハの表面に貼付された粘着シートと、を備える、積層体。 As a result of diligent studies to solve the above problems, the present inventors appropriately set the sticking direction of the adhesive sheet to be stuck on the circuit layer forming surface of the wafer based on the planned individualization area of the wafer. Then, they found that the above problems could be solved, and completed the present invention.
That is, the present invention provides the following [1] to [6].
[1] A method for manufacturing a semiconductor device having a rectangular planar shape.
An adhesive sheet is attached along the short side direction of the planned individualization region to the surface of the wafer including a plurality of rectangular individualized planned regions arranged in a matrix.
A method for manufacturing a semiconductor device, in which the back surface of a wafer to which the adhesive sheet is attached is ground, and the wafer is divided along a planned division line defining the planned individualization region.
[2] After the adhesive sheet is attached to the surface of the wafer, a modified portion serving as a starting point of division is formed inside the wafer at a plane position corresponding to the planned division line.
The method for manufacturing a semiconductor device according to the above [1], wherein the back surface of the wafer to which the adhesive sheet is attached is ground and the wafer is divided along the planned division line.
[3] The above-mentioned [1] or [2], wherein the aspect ratio represented by the length in the long side direction / the length in the short side direction of the planned individualization area is 1.05 or more. Manufacturing method of semiconductor devices.
[4] Any one of the above [1] to [3], wherein the individualized area has a length of 5 to 50 mm in the long side direction and a length of 2 to 20 mm in the short side direction. The method for manufacturing a semiconductor device according to.
[5] A transfer sheet is attached to the back surface of the wafer after grinding.
The method for manufacturing a semiconductor device according to any one of the above [1] to [4], wherein the adhesive sheet is separated from the wafer after the transfer sheet is attached.
[6] Wafers containing a plurality of rectangular individualized areas arranged in a matrix, and
A laminate comprising an adhesive sheet attached to the surface of the wafer in a state where tension is applied along the short side direction of the area to be individualized.
　本発明によれば、隣接する個片化後のチップ間の距離が小さい場合でも、製造工程において、チップに割れや欠けが生じにくい半導体装置の製造方法、及び、それに適した積層体を提供することができる。 According to the present invention, there is provided a method for manufacturing a semiconductor device in which cracks and chips are less likely to occur in the manufacturing process even when the distance between adjacent chips after individualization is small, and a laminate suitable for the method. be able to.
回路層が形成されたウエハ、このウエハの回路層上に粘着シートが貼付された積層体、及び、この積層体を用いてウエハを加工することにより得られる、半導体装置としての半導体チップの模式的な断面図である。A schematic of a semiconductor chip as a semiconductor device, which is obtained by processing a wafer on which a circuit layer is formed, a laminate in which an adhesive sheet is attached on the circuit layer of the wafer, and a wafer using the laminate. It is a cross-sectional view. ウエハへの粘着シートの貼付方向と、ウエハ上の個片化予定領域との関係を示す説明図である。It is explanatory drawing which shows the relationship between the sticking direction of an adhesive sheet to a wafer, and the region to be individualized on a wafer. 積層体の製造工程を示す模式的な断面図である。It is a schematic cross-sectional view which shows the manufacturing process of a laminated body. 半導体装置の製造工程を示す模式的な断面図である。It is a schematic cross-sectional view which shows the manufacturing process of a semiconductor device. 半導体装置の製造工程を示す模式的な断面図である。It is a schematic cross-sectional view which shows the manufacturing process of a semiconductor device. 本発明の実施例に係る半導体装置の製造方法で用いるウエハと、比較例に係る半導体装置の製造方法で用いるウエハとを、対比して示す模式的な平面図である。It is a schematic plan view which shows the wafer used in the manufacturing method of the semiconductor device which concerns on Example of this invention, and the wafer used by manufacturing method of a semiconductor device which concerns on a comparative example in comparison.
　以下、本発明の実施形態（以下、「本実施形態」と称することがある）について説明する。
［ウエハ、積層体、及び、半導体装置］
　本実施形態の半導体装置の製造方法によって製造される半導体装置は、ウエハ部分とその表面に形成された回路部とを備えており、平面形状が矩形状である。本明細書において、「半導体装置」とは、プロセッサ、メモリ、センサ等に用いられる、半導体特性を利用することで機能し得る装置全般を指す。具体的には、集積回路を備えるウエハ、集積回路を備える薄化されたウエハ、集積回路を備えるチップ、集積回路を備える薄化されたチップ、これらのチップを含む電子部品、及び当該電子部品を備える電子機器類等が挙げられる。パッケージングされる前のチップも含まれる。
　半導体装置は、回路層が表面に設けられたウエハを個片化することによって得られる。
　また、回路層が設けられたウエハを半導体装置へと加工する工程において、ウエハの回路層形成面に粘着シートを貼付した積層体が用いられる。 Hereinafter, embodiments of the present invention (hereinafter, may be referred to as “the present embodiment”) will be described.
[Wafers, laminates, and semiconductor devices]
The semiconductor device manufactured by the method for manufacturing a semiconductor device of the present embodiment includes a wafer portion and a circuit portion formed on the surface thereof, and has a rectangular planar shape. As used herein, the term "semiconductor device" refers to all devices used in processors, memories, sensors, etc. that can function by utilizing semiconductor characteristics. Specifically, a wafer having an integrated circuit, a thin wafer having an integrated circuit, a chip having an integrated circuit, a thin chip having an integrated circuit, an electronic component including these chips, and the electronic component concerned. Examples include electronic devices provided. It also includes chips before they are packaged.
A semiconductor device is obtained by disassembling a wafer having a circuit layer on its surface.
Further, in the step of processing a wafer provided with a circuit layer into a semiconductor device, a laminate in which an adhesive sheet is attached to the circuit layer forming surface of the wafer is used.
　以下、本発明の実施形態に係る、ウエハ、積層体、及び、半導体装置を、図面を用いて説明する。
　図１は、回路層が形成されたウエハ、このウエハの回路層が形成された面に粘着シートが貼付された積層体、及び、上記ウエハを加工することによって得られる、半導体装置としての半導体チップの模式的な断面図である。
　図１（Ａ）に示すように、まず、フォトリソ法を含む半導体形成プロセスによって、表面に回路層Ｃが形成されたウエハＷを準備する。
　次に、図１（Ｂ）に示すように、ウエハＷの回路層Ｃが形成された面に粘着シート１を貼付して、積層体１０を得る。
　さらに、図１（Ｃ）に示すように、ウエハＷの裏面を必要に応じて研削するとともに、ウエハＷを、個片化予定領域を画定する分割予定線に沿って分割することで、個片化後のウエハＷＩとする。こうして、回路層Ｃを有するウエハＷを複数に個片化し、半導体装置としての半導体チップＣＰを得る。個片化予定領域については後ほど詳しく説明する。 Hereinafter, the wafer, the laminate, and the semiconductor device according to the embodiment of the present invention will be described with reference to the drawings.
FIG. 1 shows a wafer on which a circuit layer is formed, a laminate in which an adhesive sheet is attached to a surface of the wafer on which a circuit layer is formed, and a semiconductor chip as a semiconductor device obtained by processing the wafer. It is a schematic cross-sectional view of.
As shown in FIG. 1A, first, a wafer W having a circuit layer C formed on its surface is prepared by a semiconductor forming process including a photolithography method.
Next, as shown in FIG. 1B, the adhesive sheet 1 is attached to the surface of the wafer W on which the circuit layer C is formed to obtain the laminated body 10.
Further, as shown in FIG. 1C, the back surface of the wafer W is ground as necessary, and the wafer W is divided along the planned division line defining the planned individualization region to obtain individual pieces. The wafer WI after conversion. In this way, the wafer W having the circuit layer C is fragmented into a plurality of pieces to obtain a semiconductor chip CP as a semiconductor device. The area to be separated will be described in detail later.
＜ウエハ＞
　ウエハＷは、高純度の単結晶シリコンを円盤状に切り出したものである。ウエハＷの直径は、これに限るものではないが、例えば１２インチである。
　回路層Ｃは、半導体製造プロセスによってウエハＷの表面に形成された半導体回路を含む層である。
　半導体プロセスは、シリコンウエハ上に回路の素材となる酸化シリコンやアルミニウム等を、スパッタリング、電気めっき、ＣＶＤ等によって薄膜形成した後、フォトリソ法によって半導体回路を形成する工程を含む。
　フォトリソ法は、シリコンウエハ上に形成された上記薄膜をレジスト膜で被覆する工程、回路パターンが形成されたマスクを介してＵＶ光を上記レジスト膜に照射する工程、上記レジスト膜のうち未硬化の部分を現像して選択的に除去する工程、現像によって露出した薄膜をエッチングして除去する工程、エッチングによって露出したシリコン基板にリンやホウ素等の不純物を注入して半導体特性を付与する工程、フラッシュランプやレーザー照射等を用いる熱処理によって不純物イオンを活性化する工程、及び、レジスト膜を剥離する工程、を有する。 <Wafer>
The wafer W is made by cutting out high-purity single crystal silicon into a disk shape. The diameter of the wafer W is not limited to this, but is, for example, 12 inches.
The circuit layer C is a layer including a semiconductor circuit formed on the surface of the wafer W by the semiconductor manufacturing process.
The semiconductor process includes a step of forming a thin film of silicon oxide, aluminum, or the like as a circuit material on a silicon wafer by sputtering, electroplating, CVD, or the like, and then forming a semiconductor circuit by a photolithography method.
The photolithography method includes a step of coating the thin film formed on a silicon wafer with a resist film, a step of irradiating the resist film with UV light through a mask on which a circuit pattern is formed, and an uncured resist film. A process of developing and selectively removing a part, a process of etching and removing a thin film exposed by development, a process of injecting impurities such as phosphorus and boron into a silicon substrate exposed by etching to impart semiconductor characteristics, and a flash. It includes a step of activating impurity ions by heat treatment using a lamp, laser irradiation, or the like, and a step of peeling the resist film.
＜半導体装置＞
　ウエハＷは、一例として、平面視したときのサイズで、それぞれが１２ｍｍ×６ｍｍ程度の大きさの複数の半導体チップとなるように分割される。このサイズに分割する場合、直径１２インチのウエハからは、約１，０００個の半導体チップが得られる。
　半導体装置である半導体チップは、上述したように、ウエハＷに由来するウエハ部分と、その表面に形成された回路層Ｃに由来する回路部とを備えている。
　本実施形態の半導体装置の製造方法によって得られる半導体チップは、矩形状の平面形状を有する。このため、半導体チップに様々な機能を付与したり、半導体チップの天地を容易に把握したりすることができる。 <Semiconductor device>
As an example, the wafer W is divided into a plurality of semiconductor chips having a size when viewed in a plane and each having a size of about 12 mm × 6 mm. When divided into this size, about 1,000 semiconductor chips can be obtained from a wafer having a diameter of 12 inches.
As described above, the semiconductor chip, which is a semiconductor device, includes a wafer portion derived from the wafer W and a circuit portion derived from the circuit layer C formed on the surface thereof.
The semiconductor chip obtained by the method for manufacturing the semiconductor device of the present embodiment has a rectangular planar shape. Therefore, various functions can be added to the semiconductor chip, and the top and bottom of the semiconductor chip can be easily grasped.
＜積層体＞
　積層体１０は、回路層Ｃが形成されたウエハＷの表面に粘着シート１が貼付されたものである。 <Laminated body>
In the laminated body 10, the adhesive sheet 1 is attached to the surface of the wafer W on which the circuit layer C is formed.
（粘着シート）
　粘着シート１は、基材層と、この基材層上に積層された粘着剤層とを含む積層体であり、典型的には、基材層と、基材層の少なくとも一方の面側に設けられた緩衝層と、基材層の他方の面側に設けられた粘着剤層とを含む積層体である。粘着シート１は、これら以外の他の構成層を含むことができ、例えば、粘着剤層側の基材表面にはプライマー層が形成されていてもよく、粘着剤層の表面には、使用時まで粘着剤層を保護するための剥離シートが積層されていてもよい。また、基材は単層であってもよく、多層であってもよい。緩衝層および粘着剤層も同様である。粘着シート１の粘着剤層がウエハＷの回路層Ｃに接するようにして、粘着シート１がウエハＷに貼付されることにより、粘着シート１は、ウエハＷの回路層Ｃを保護する保護フィルムとしての役割を果たす。 (Adhesive sheet)
The pressure-sensitive adhesive sheet 1 is a laminate including a base material layer and a pressure-sensitive adhesive layer laminated on the base material layer, and is typically on the base material layer and at least one surface side of the base material layer. It is a laminate including a buffer layer provided and an adhesive layer provided on the other surface side of the base material layer. The pressure-sensitive adhesive sheet 1 may contain other constituent layers other than these. For example, a primer layer may be formed on the surface of the base material on the pressure-sensitive adhesive layer side, and the surface of the pressure-sensitive adhesive layer may be formed during use. A release sheet for protecting the pressure-sensitive adhesive layer may be laminated. Further, the base material may be a single layer or a multilayer. The same applies to the buffer layer and the pressure-sensitive adhesive layer. The pressure-sensitive adhesive sheet 1 is attached to the wafer W so that the pressure-sensitive adhesive layer of the pressure-sensitive adhesive sheet 1 is in contact with the circuit layer C of the wafer W, so that the pressure-sensitive adhesive sheet 1 serves as a protective film that protects the circuit layer C of the wafer W. Play the role of.
（基材層）
　基材層の材質は、特に制限されないが、紙や不織布と比べて塵芥発生が少ないために電子部品の加工部材に好適であり、入手が容易であるとの観点から、樹脂フィルムであることが好ましい。粘着シートが基材層を有することで、粘着シートの形状安定性を向上させたり、粘着シートにコシを与えたりすることができる。また、ウエアＷの回路層Ｃの凹凸が大きい場合でも、粘着シートの貼付面と逆の面が平滑に保たれやすくなる。
　基材層は、１つの樹脂フィルムからなる単層フィルムからなる基材層でもよいし、複数の樹脂フィルムが積層した複層フィルムからなる基材層でもよい。
　基材層の厚さは、粘着シートに適度な弾力を与える観点、また、粘着シートの巻収時の取り扱い性の観点から、好ましくは５～２５０μｍ、より好ましくは１０～２００μｍ、さらに好ましくは２５～１５０μｍである。
　基材層に用いられ得る樹脂フィルムとしては、例えば、ポリオレフィン系フィルム、ハロゲン化ビニル重合体系フィルム、アクリル樹脂系フィルム、ゴム系フィルム、セルロース系フィルム、ポリエステル系フィルム、ポリカーボネート系フィルム、ポリスチレン系フィルム、ポリフェニレンサルファイド系フィルム、シクロオレフィンポリマー系フィルム、及び、ウレタン樹脂を含むエネルギー線硬化性組成物の硬化物からなるフィルムが挙げられる。
　基材層に用いられるポリエステル系フィルムは、ポリエステルの共重合体からなるフィルムであってもよく、上記ポリエステルと比較的少量の他樹脂との混合物からなる樹脂混合フィルムであってもよい。これらのポリエステル系フィルムの中でも、入手が容易で、厚み精度が高いとの観点から、ポリエチレンテレフタレートフィルムが好ましい。 (Base material layer)
The material of the base material is not particularly limited, but it may be a resin film from the viewpoint that it is suitable for processing members of electronic parts because it generates less dust than paper or non-woven fabric and is easily available. preferable. When the pressure-sensitive adhesive sheet has a base material layer, the shape stability of the pressure-sensitive adhesive sheet can be improved and the pressure-sensitive adhesive sheet can be given elasticity. Further, even when the circuit layer C of the wear W has large irregularities, the surface opposite to the surface on which the adhesive sheet is attached tends to be kept smooth.
The base material layer may be a base material layer made of a single layer film made of one resin film, or may be a base material layer made of a multi-layer film in which a plurality of resin films are laminated.
The thickness of the base material layer is preferably 5 to 250 μm, more preferably 10 to 200 μm, still more preferably 25, from the viewpoint of giving an appropriate elasticity to the pressure-sensitive adhesive sheet and from the viewpoint of handleability when the pressure-sensitive adhesive sheet is wound up. It is ~ 150 μm.
Examples of the resin film that can be used for the base material layer include polyolefin-based film, vinyl halide polymerization-based film, acrylic resin-based film, rubber-based film, cellulose-based film, polyester-based film, polycarbonate-based film, and polystyrene-based film. Examples thereof include a polyphenylene sulfide-based film, a cycloolefin polymer-based film, and a film composed of a cured product of an energy ray-curable composition containing a urethane resin.
The polyester-based film used for the base material layer may be a film made of a copolymer of polyester, or may be a resin mixed film made of a mixture of the polyester and a relatively small amount of other resin. Among these polyester-based films, polyethylene terephthalate film is preferable from the viewpoint of easy availability and high thickness accuracy.
（粘着剤層）
　基材層又は中間層上に設けられる粘着剤層は、ウエハＷの回路層Ｃに粘着シートを確実に固定することにより回路層Ｃを保護する。
　粘着剤層は粘着剤を含む。粘着剤としては、例えば、アクリル系粘着剤、ゴム系粘着剤、ウレタン系粘着剤、シリコーン系粘着剤、ポリビニルエーテル系粘着剤、オレフィン系粘着剤等が挙げられる。これらの粘着剤は、１種又は２種以上を組み合わせて用いてもよい。
　粘着剤層の厚さは、保護対象となる回路層の凹凸の大きさに応じて適宜調整することができるが、好ましくは５～２００μｍ、より好ましくは７～１５０μｍ、さらに好ましくは１０～１００μｍである。 (Adhesive layer)
The pressure-sensitive adhesive layer provided on the base material layer or the intermediate layer protects the circuit layer C by securely fixing the pressure-sensitive adhesive sheet to the circuit layer C of the wafer W.
The pressure-sensitive adhesive layer contains a pressure-sensitive adhesive. Examples of the adhesive include acrylic adhesives, rubber adhesives, urethane adhesives, silicone adhesives, polyvinyl ether adhesives, olefin adhesives and the like. These pressure-sensitive adhesives may be used alone or in combination of two or more.
The thickness of the pressure-sensitive adhesive layer can be appropriately adjusted according to the size of the unevenness of the circuit layer to be protected, but is preferably 5 to 200 μm, more preferably 7 to 150 μm, and further preferably 10 to 100 μm. is there.
（中間層）
　中間層は、特に制限されないが、良好な凹凸吸収性を得る観点から、ウレタン（メタ）アクリレート及びチオール基含有化合物を含む樹脂組成物から形成されることが好ましい。
　中間層の厚さは、保護対象となる半導体表面の凹凸の大きさに応じて適宜調整することができるが、比較的大きな凹凸を吸収することを可能とする観点から、好ましくは５０～４００μｍ、より好ましくは７０～３００μｍ、さらに好ましくは８０～２５０μｍである。 (Mesosphere)
The intermediate layer is not particularly limited, but is preferably formed from a resin composition containing a urethane (meth) acrylate and a thiol group-containing compound from the viewpoint of obtaining good unevenness absorption.
The thickness of the intermediate layer can be appropriately adjusted according to the size of the unevenness on the surface of the semiconductor to be protected, but is preferably 50 to 400 μm from the viewpoint of being able to absorb relatively large unevenness. It is more preferably 70 to 300 μm, still more preferably 80 to 250 μm.
（粘着シートの貼付方向）
　図２は、ウエハＷへの粘着シート１の貼付方向と、ウエハＷ上の個片化予定領域Ｒとの関係を示す説明図である。
　図２（Ａ）に示すように、ウエハＷの表面には、ウエハＷに対する処理や加工の基準方向を示すＶノッチＷｖと、分割予定線Ｅによって規定される個々の個片化予定領域Ｒ内に設けられた半導体回路とが形成されている。半導体回路はＶノッチＷｖが示す方向を基準にして形成されている。また、後述する粘着シートの貼り合わせもＶノッチＷｖが示す方向を基準にして行われる。
　ここで、個片化予定領域Ｒは平面視で矩形状である。個片化予定領域Ｒを画定する分割予定線Ｅは仮想的なものであり、分割予定線Ｅを跨がないように個々の回路が形成されていればよく、個片化予定領域Ｒを画定する分割予定線ＥをウエハＷの表面や回路層Ｃに物理的に形成しておく必要はない。しかし、個片化予定領域Ｒを認識しやすくしたり、ウエハＷの分割がスムーズに進むようにしたりするために、フォトリソ法によって予め、分割予定線Ｅとなる加工溝等を形成しておいてもよい。
　個片化予定領域Ｒを矩形状とすることにより、最終的に得られる半導体チップの形状も矩形となる。
　図２（Ａ）に示す例では、各個片化予定領域Ｒの短辺方向ｄ２が、ＶノッチＷｖが示す方向ｄ３（以下、縦方向ともいう）に一致するように回路層Ｃの各回路が形成されている。これにより、個片化予定領域の長辺方向ｄ１は、ＶノッチＷｖが示す方向ｄ３に直交する方向（以下、横方向ともいう）に一致している。 (Adhesive sheet sticking direction)
FIG. 2 is an explanatory diagram showing the relationship between the sticking direction of the adhesive sheet 1 on the wafer W and the planned individualization region R on the wafer W.
As shown in FIG. 2A, on the surface of the wafer W, a V notch Wv indicating the reference direction of processing or processing on the wafer W and the individual planned individualization regions R defined by the planned division line E are included. The semiconductor circuit provided in the above is formed. The semiconductor circuit is formed with reference to the direction indicated by the V notch Wv. Further, the bonding of the adhesive sheets, which will be described later, is also performed with reference to the direction indicated by the V notch Wv.
Here, the individualized area R has a rectangular shape in a plan view. The planned division line E that defines the planned separation area R is a virtual one, and it is sufficient that individual circuits are formed so as not to straddle the planned division line E, and the planned separation area R is defined. It is not necessary to physically form the planned division line E on the surface of the wafer W or the circuit layer C. However, in order to make it easier to recognize the planned individualization region R and to facilitate the division of the wafer W, a processing groove or the like to be the planned division line E is formed in advance by the photolithography method. May be good.
By making the area R to be separated into a rectangular shape, the shape of the finally obtained semiconductor chip is also rectangular.
In the example shown in FIG. 2A, each circuit of the circuit layer C is arranged so that the short side direction d2 of each planned individualization region R coincides with the direction d3 (hereinafter, also referred to as the vertical direction) indicated by the V notch Wv. It is formed. As a result, the long side direction d1 of the planned individualization region coincides with the direction orthogonal to the direction d3 indicated by the V notch Wv (hereinafter, also referred to as the lateral direction).
　個片化予定領域Ｒの長辺方向の長さは、製造工程中における半導体チップの欠けや割れを抑制しやすく、また、様々な機能を半導体チップに付与しやすくする観点から、好ましくは５～５０ｍｍ、より好ましくは７～４０ｍｍ、さらに好ましくは１０～３０ｍｍである。
　個片化予定領域Ｒの短辺方向の長さは、取り扱いの容易性を高めたり、半導体チップに必要最低限の機能を付与しやすくしたりする観点から、好ましくは２～２０ｍｍ、より好ましくは３～１８ｍｍ、さらに好ましくは４～１５ｍｍである。
　個片化予定領域Ｒの、長辺方向の長さと短辺方向の長さとの比率（長辺方向の長さ／短辺方向の長さ）で表されるアスペクト比は、製造工程中における半導体チップの欠けや割れの抑制性と、半導体チップへの機能の付与性のバランスを適切に保つ観点から、好ましくは１．０５以上、より好ましくは１．１０以上、さらに好ましくは１．１５以上であり、また、好ましくは１０以下、より好ましくは７．０以下、さらに好ましくは５．０以下である。 The length of the planned individualization region R in the long side direction is preferably 5 to 5 from the viewpoint of easily suppressing chipping or cracking of the semiconductor chip during the manufacturing process and easily imparting various functions to the semiconductor chip. It is 50 mm, more preferably 7 to 40 mm, still more preferably 10 to 30 mm.
The length of the planned individualization region R in the short side direction is preferably 2 to 20 mm, more preferably 2 to 20 mm from the viewpoint of improving ease of handling and facilitating imparting the minimum necessary functions to the semiconductor chip. It is 3 to 18 mm, more preferably 4 to 15 mm.
The aspect ratio of the planned individualization region R, which is expressed by the ratio of the length in the long side direction to the length in the short side direction (length in the long side direction / length in the short side direction), is a semiconductor in the manufacturing process. From the viewpoint of appropriately maintaining a balance between the ability to suppress chipping and cracking of the chip and the ability to impart functions to the semiconductor chip, the ratio is preferably 1.05 or more, more preferably 1.10 or more, still more preferably 1.15 or more. Yes, and is preferably 10 or less, more preferably 7.0 or less, and even more preferably 5.0 or less.
　なお、本実施形態においては、後述するように、半導体装置を製造する際、ＳＤＢＧによってウエハＷを分割するので、隣り合うチップ間の距離が実質的にゼロである。このため、個片化予定領域Ｒの縦方向及び横方向の長さが、半導体チップの縦方向及び横方向の長さに一致する。
　なお、個片化予定領域Ｒ以外に半導体回路を設けないようにしてもよいし、個片化予定領域外にも使用しない半導体回路をダミー回路として設けておいてもよい。 In the present embodiment, as will be described later, when the semiconductor device is manufactured, the wafer W is divided by SDBG, so that the distance between adjacent chips is substantially zero. Therefore, the vertical and horizontal lengths of the planned individualization region R match the vertical and horizontal lengths of the semiconductor chip.
It should be noted that the semiconductor circuit may not be provided outside the planned individualization region R, or a semiconductor circuit that is not used outside the planned individualization region may be provided as a dummy circuit.
　図２（Ｂ）に示すように、粘着シート１は、ウエハＷの表面全体を覆い得る長さと幅を有するものである。直径１２インチのウエハＷを用いる場合、粘着シート１としては、例えば、幅４００ｍｍの長尺のものを用いることができる。なお、図２（Ｂ）においては、理解を容易にするため、粘着シート１によって覆われたウエハＷとその個片化予定領域Ｒを薄線で示している。粘着シート１として光透過性を有するものを用いれば、粘着シート１を介して個片化予定領域Ｒの形状と並び方向を確認することができる。
　粘着シート１を貼付するにあたっては、ＶノッチＷｖが示す方向ｄ３を基準にして貼り合わせ装置にウエハＷをセットする。この際、貼付装置による粘着シート１の貼付方向ｄ４が、ＶノッチＷｖが示す方向ｄ３に沿うようにウエハＷをセットする。これによって、本実施形態においては、ＶノッチＷｖが示す方向ｄ３に、個片化予定領域Ｒの短辺方向ｄ２が沿うことになる。
　粘着シート１がウエハＷの回路層Ｃ上に貼付された後、必要に応じて、ウエハＷからはみ出した粘着シート１を切断して除去する。後述するように、粘着シート１の撓みをなくすようにテンションをかけながら貼付する方法等により粘着シート１を貼付すると、粘着シート１の貼付方向ｄ４に沿ってテンションが付加された状態で粘着シート１が回路層Ｃ上に貼付される。これにより、個片化予定領域Ｒの短辺方向ｄ２に沿う方向にテンションが付加された状態で積層体１０が形成される。
　ここで、粘着シートの貼付方向ｄ４は、ＶノッチＷｖが示す方向ｄ３（つまり、本例では個片化予定領域Ｒの短辺方向ｄ２）に沿うように設定されるが、図２（Ｂ）に示すように、粘着シート１の貼付方向ｄ４は、ＶノッチＷｖが示す方向ｄ３に対して一定の角度θ内となるように設定すればよい。ここで、θは、ＶノッチＷｖが示す方向ｄ３に対して、好ましくは±４５°、より好ましくは±４０°、さらに好ましくは±３５°の範囲内である。 As shown in FIG. 2B, the pressure-sensitive adhesive sheet 1 has a length and width capable of covering the entire surface of the wafer W. When a wafer W having a diameter of 12 inches is used, for example, a long adhesive sheet 1 having a width of 400 mm can be used. In FIG. 2B, the wafer W covered with the adhesive sheet 1 and the region R to be separated from the wafer W are shown by thin lines for easy understanding. If a light-transmitting adhesive sheet 1 is used, the shape and alignment direction of the individualized region R can be confirmed via the adhesive sheet 1.
When the adhesive sheet 1 is attached, the wafer W is set in the bonding device with reference to the direction d3 indicated by the V notch Wv. At this time, the wafer W is set so that the sticking direction d4 of the adhesive sheet 1 by the sticking device is along the direction d3 indicated by the V notch Wv. As a result, in the present embodiment, the short side direction d2 of the planned individualization region R is aligned with the direction d3 indicated by the V notch Wv.
After the pressure-sensitive adhesive sheet 1 is attached on the circuit layer C of the wafer W, the pressure-sensitive adhesive sheet 1 protruding from the wafer W is cut and removed, if necessary. As will be described later, when the adhesive sheet 1 is attached by a method of applying tension so as to eliminate the bending of the adhesive sheet 1, the adhesive sheet 1 is attached with tension along the application direction d4 of the adhesive sheet 1. Is affixed onto the circuit layer C. As a result, the laminated body 10 is formed in a state where tension is applied in the direction along the short side direction d2 of the planned individualization region R.
Here, the sticking direction d4 of the adhesive sheet is set so as to follow the direction d3 indicated by the V notch Wv (that is, the short side direction d2 of the planned individualization region R in this example), but FIG. As shown in the above, the sticking direction d4 of the adhesive sheet 1 may be set so as to be within a constant angle θ with respect to the direction d3 indicated by the V notch Wv. Here, θ is preferably in the range of ± 45 °, more preferably ± 40 °, and even more preferably ± 35 ° with respect to the direction d3 indicated by the V notch Wv.
［積層体の作製方法］
　図３は、積層体の作製工程を示す模式的な断面図である。図３（Ａ）は、回路層Ｃが形成されたウエハＷを支持体１００上に載置した様子を示す図であり、図３（Ｂ）は、ウエハＷの回路層Ｃ上に粘着シート１を貼付する様子を示す図であり、図３（Ｃ）は、ウエハＷの回路層Ｃ上に粘着シート１が貼付された様子を示す図である。
　図３（Ａ）に示すように、回路層Ｃが形成されたウエハＷの裏面が支持体１００に接するように、ウエハＷを支持体１００に載置した後、図３（Ｂ）に示すように、ウエハＷの回路層Ｃ上に粘着シート１を貼付する。本例では、粘着シート１の一端を、巻き取り部材で巻き取ったり、把持部材で把持したりして、ウエハＷから浮いた状態に保持しつつ、他端から押圧体１０１によって粘着シート１を順次押圧しながら、ウエハＷの回路層Ｃの形成面に粘着シート１を貼付する。
　このとき、粘着シート１の弛みをできるだけなくすように、一定のテンションが粘着シート１の長手方向（つまり、粘着シート１の貼付方向）に加えられたり、押圧体による押圧力が粘着シート１の長手方向に付加されたりすることによって、貼付方向ｄ４にテンションがかかった状態で粘着シート１がウエハＷに貼付される。粘着シート１の短手方向には殆どテンションがかからない状態で粘着シート１がウエハＷの回路層Ｃに貼付される。
　粘着シート１が回路層Ｃ上に貼付された後、必要に応じて、ウエハＷからはみ出した粘着シート１を切断して除去する。こうして、図３（Ｃ）に示すように、ウエハＷの回路層Ｃ上に粘着シート１が貼付された積層体１０が作製される。
　なお、支持体１００を構成する材料には、特に制限はなく、例えば、ステンレス等の金属材料が用いられる。 [Method for producing laminate]
FIG. 3 is a schematic cross-sectional view showing a manufacturing process of the laminated body. FIG. 3A is a diagram showing a state in which the wafer W on which the circuit layer C is formed is placed on the support 100, and FIG. 3B is a view showing the adhesive sheet 1 on the circuit layer C of the wafer W. 3 (C) is a diagram showing a state in which the adhesive sheet 1 is attached on the circuit layer C of the wafer W.
As shown in FIG. 3 (A), after the wafer W is placed on the support 100 so that the back surface of the wafer W on which the circuit layer C is formed is in contact with the support 100, as shown in FIG. 3 (B). The adhesive sheet 1 is attached onto the circuit layer C of the wafer W. In this example, one end of the adhesive sheet 1 is wound by a winding member or gripped by a gripping member to hold the adhesive sheet 1 floating from the wafer W, and the adhesive sheet 1 is pressed from the other end by the pressing body 101. While sequentially pressing, the adhesive sheet 1 is attached to the forming surface of the circuit layer C of the wafer W.
At this time, a constant tension is applied in the longitudinal direction of the adhesive sheet 1 (that is, the sticking direction of the adhesive sheet 1) so as to minimize the slack of the adhesive sheet 1, and the pressing force by the pressing body is applied to the longitudinal direction of the adhesive sheet 1. The adhesive sheet 1 is attached to the wafer W in a state where tension is applied in the attachment direction d4 by being added in the direction. The adhesive sheet 1 is attached to the circuit layer C of the wafer W with almost no tension applied in the lateral direction of the adhesive sheet 1.
After the adhesive sheet 1 is attached on the circuit layer C, the adhesive sheet 1 protruding from the wafer W is cut and removed, if necessary. In this way, as shown in FIG. 3C, the laminated body 10 in which the adhesive sheet 1 is attached on the circuit layer C of the wafer W is produced.
The material constituting the support 100 is not particularly limited, and for example, a metal material such as stainless steel is used.
［半導体装置の製造方法］
　本実施形態の半導体装置の製造方法の一例は、ウエハの回路層上に粘着シートが貼付された積層体に対して加工を行い、ウエハを分割するとともにウエハの裏面を研削し、分割されたウエハの、回路層形成面とは反対の面（つまり、ウエハの裏面）に転写シートを貼付し、粘着シートを除去した後、ウエハを転写シートとともに分断して個片化する工程を含む。以下、各工程について、順次説明する。なお、転写シートとは、ウエハの裏面に貼付されることにより、上記粘着シートからウエハが分離された後、当該ウエハがその表面に転写され、当該ウエハを保持するためのシートである。 [Manufacturing method of semiconductor devices]
An example of the method for manufacturing a semiconductor device of the present embodiment is to process a laminate in which an adhesive sheet is attached on a circuit layer of a wafer, divide the wafer, grind the back surface of the wafer, and divide the wafer. This includes a step of attaching a transfer sheet to a surface opposite to the circuit layer forming surface (that is, the back surface of the wafer), removing the adhesive sheet, and then dividing the wafer together with the transfer sheet into individual pieces. Hereinafter, each step will be described in sequence. The transfer sheet is a sheet for holding the wafer by being transferred to the front surface of the wafer after the wafer is separated from the adhesive sheet by being attached to the back surface of the wafer.
　図４、図５は、半導体装置の製造工程を示す模式的な断面図である。
　図４（Ａ）は、支持体１００とは別の支持体２００上に積層体１０を載置した状態を示す図である。図４（Ａ）に示すように、粘着シート１が支持体２００に接するように、積層体１０を支持体２００に載置する。なお、支持体２００としては、例えば、支持体１００と同様の材質のものや、セラミック製のポーラステーブルを用いることができる。
　図４（Ｂ）は、裏面側からウエハＷに対してレーザーを照射する様子を示す図である。図４（Ｂ）に示すように、集光器１０２を用いて、ウエハＷに対して透過性を有する波長のレーザー１０３の集光点がウエハＷの内部になるようにレーザー１０３の位置を定め、個片化予定領域Ｒを画定する分割予定線Ｅに沿ってレーザー１０３とウエハＷとを相対的に移動させながら、裏面側からウエハＷにレーザー１０３を照射する。これによって、分割予定線Ｅに対応する平面位置におけるウエハＷの内部に改質部Ｍが形成される。改質部Ｍはレーザーの照射によってウエハＷが改質された部分であり、ウエハＷが割断する起点となる。
　図４（Ｃ）は、ウエハＷの裏面側を研削する様子を示す図である。図４（Ｃ）に示すように、グラインダー１０４を用いて、所望の厚さになるまでウエハＷの裏面を研削する。この処理によって、ウエハＷは薄型化・軽量化される。同時に、改質部Ｍを起点にして、個片化予定領域Ｒを画定する分割予定線Ｅに沿ってウエハＷが割断される。また、ウエハＷ内に形成された改質部Ｍが研削によって除去される。 4 and 5 are schematic cross-sectional views showing a manufacturing process of a semiconductor device.
FIG. 4A is a diagram showing a state in which the laminated body 10 is placed on a support 200 different from the support 100. As shown in FIG. 4A, the laminated body 10 is placed on the support 200 so that the adhesive sheet 1 is in contact with the support 200. As the support 200, for example, one made of the same material as the support 100 or a ceramic porous table can be used.
FIG. 4B is a diagram showing how the wafer W is irradiated with a laser from the back surface side. As shown in FIG. 4B, the condenser 102 is used to position the laser 103 so that the focusing point of the laser 103 having a wavelength that is transparent to the wafer W is inside the wafer W. The laser 103 is irradiated to the wafer W from the back surface side while the laser 103 and the wafer W are relatively moved along the planned division line E defining the individualized planned region R. As a result, the modified portion M is formed inside the wafer W at the plane position corresponding to the planned division line E. The modified portion M is a portion where the wafer W is modified by irradiation with a laser, and serves as a starting point at which the wafer W is divided.
FIG. 4C is a diagram showing a state in which the back surface side of the wafer W is ground. As shown in FIG. 4C, the back surface of the wafer W is ground to a desired thickness using a grinder 104. By this process, the wafer W is made thinner and lighter. At the same time, the wafer W is cut along the planned division line E that defines the planned individualization region R with the reformed portion M as the starting point. Further, the modified portion M formed in the wafer W is removed by grinding.
　ＳＤＢＧでは、研削時にウエハが分割された時、隣り合うチップ間にはステルスダイシングによる亀裂（図４（Ｃ）の符号Ｐ）のみが存在し、チップ間の距離は実質的にゼロである。このため、わずかなストレスや衝撃でチップがシフトしてチップ同士が接触、押圧、摩擦又は衝突等を生じやすく、クラックが発生しやすい状況となっている。また、バックグラインド用保護シートなどの粘着シートを貼付する際、その貼付方向にテンションをかけて貼付されるため、粘着シート貼付後の積層体に応力が残りやすくなっている。このため、ウエハの裏面が研削されることによって、ウエハＷが改質部Ｍを起点にして個々のチップへと割断されると同時に積層体内の応力が解放され、粘着シートの貼付方向にチップが動きやすなり、結果的に、チップ同士が接触、押圧、摩擦又は衝突してクラックを誘発するものと推測される。 In SDBG, when the wafer is divided during grinding, only cracks due to stealth dicing (reference numeral P in FIG. 4C) exist between adjacent chips, and the distance between the chips is substantially zero. For this reason, the chips are likely to shift due to a slight stress or impact, and the chips are likely to come into contact, pressure, friction, collision, or the like, and cracks are likely to occur. Further, when an adhesive sheet such as a protective sheet for back grind is attached, tension is applied in the attaching direction, so that stress tends to remain in the laminated body after the adhesive sheet is attached. Therefore, by grinding the back surface of the wafer, the wafer W is cut into individual chips starting from the modified portion M, and at the same time, the stress in the laminate is released, and the chips are released in the direction in which the adhesive sheet is attached. It is presumed that the chips become easier to move, and as a result, the chips come into contact, press, rub, or collide with each other to induce cracks.
　本実施形態の半導体装置の製造方法において、チップの欠けや割れが抑制される理由は、これに限るものではないが、一つには、次の理由が考えられる。つまり、チップの縦方向の長さと横方向の長さとを異ならせ、チップの短辺方向に沿って粘着シートを貼付することにより、チップの長辺方向に沿って粘着シートを貼付する場合に比べて、粘着シートの貼付方向におけるチップ間の切断ラインの数が多くなる。これによって、貼付方向におけるチップの動き量がより多くのチップによって分散され、チップ同士の接触、押圧、摩擦、衝突等が少なくなり、割れや欠けの抑制につながるものと推測される。
　なお、本実施形態では、研削によって改質部を除去しているが、例えば、ウエハの薄型化が求められない用途や、ウエハがそもそも分厚い場合などにおいては、研削後も改質部の少なくとも一部がウエハに残るようにしてもよい。 In the method for manufacturing a semiconductor device of the present embodiment, the reason why chipping or cracking of a chip is suppressed is not limited to this, but one of the following reasons can be considered. That is, by making the vertical length and the horizontal length of the chip different and attaching the adhesive sheet along the short side direction of the chip, compared with the case where the adhesive sheet is attached along the long side direction of the chip. Therefore, the number of cutting lines between the chips in the sticking direction of the adhesive sheet increases. As a result, it is presumed that the amount of movement of the chips in the sticking direction is dispersed by more chips, the contact, pressing, friction, collision, etc. between the chips are reduced, which leads to the suppression of cracking and chipping.
In the present embodiment, the modified portion is removed by grinding. However, for example, in applications where thinning of the wafer is not required or when the wafer is thick in the first place, at least one of the modified portions is removed even after grinding. The portion may remain on the wafer.
　図５（Ａ）は、ウエハＷが研削・分割された積層体１１を支持体２００から分離する工程を示す。図５（Ｂ）は、ウエハＷが研削・分割された積層体１１をリングフレーム３００に保持された転写シートに貼着する工程を示す。図５（Ｃ）は、転写シート３０３に貼着された積層体１１から粘着シート１を分離する工程を示す。図５（Ｄ）は、転写シート３０３とともに個々のチップを分離するエキスパンド工程である。
　図５（Ａ）に示すように支持体２００から分離された、ウエハＷが研削・分割された積層体１１を、図５（Ｂ）に示すように、リングフレーム３００によって周囲が保持された、フィルム状接着剤３０１と支持シート３０２とを含む転写シート３０３の、フィルム状接着剤３０１に貼着する。そして、図５（Ｃ）に示すように、ウエハＷが研削・分割された積層体１１から粘着シート１を分離し、さらに、図５（Ｄ）に示すように、支持シート３０２を引っ張ることにより、フィルム状接着剤３０１もチップに合わせて切断し（切断後のフィルム状接着剤を符号３０１ａで示す）、チップ間に隙間Ｇを空け、個々のチップへと分離する。
　なお、転写シート３０３としては、例えば、上述した粘着シート１の基材層と同様の材質からなる基材を含む支持シート３０２上に、必要に応じて粘着剤層を介して、硬化性を有するフィルム状接着剤３０１が設けられたものを用いることができる。 FIG. 5A shows a step of separating the laminated body 11 in which the wafer W is ground and divided from the support 200. FIG. 5B shows a step of attaching the laminate 11 obtained by grinding and dividing the wafer W to the transfer sheet held on the ring frame 300. FIG. 5C shows a step of separating the adhesive sheet 1 from the laminate 11 attached to the transfer sheet 303. FIG. 5D shows an expanding step of separating individual chips together with the transfer sheet 303.
As shown in FIG. 5 (B), the periphery of the laminated body 11 in which the wafer W was ground and divided, which was separated from the support 200 as shown in FIG. 5 (A), was held by the ring frame 300. The transfer sheet 303 including the film-like adhesive 301 and the support sheet 302 is attached to the film-like adhesive 301. Then, as shown in FIG. 5 (C), the adhesive sheet 1 is separated from the laminate 11 in which the wafer W is ground and divided, and further, as shown in FIG. 5 (D), the support sheet 302 is pulled. , The film-like adhesive 301 is also cut according to the chips (the film-like adhesive after cutting is indicated by reference numeral 301a), a gap G is provided between the chips, and the chips are separated into individual chips.
The transfer sheet 303 has curability on, for example, a support sheet 302 containing a base material made of the same material as the base material layer of the pressure-sensitive adhesive sheet 1 described above, via an adhesive layer as necessary. Those provided with the film-like adhesive 301 can be used.
　以上の製造方法によれば、製造工程中にチップの欠けや割れの発生を抑制するとともに、高い良品率で半導体装置を製造することができる。 According to the above manufacturing method, it is possible to suppress the occurrence of chipping and cracking during the manufacturing process and to manufacture the semiconductor device with a high non-defective rate.
　なお、本実施形態においては、ＳＤＢＧによってウエハを分割しているが、これに限るものでなく、例えば、ＤＢＧを用いてウエハを分割してもよい。ＤＢＧを用いる場合、ダイシングにより形成されるチップ間の距離が小さい場合に、チップの欠けや割れを防止する効果が発揮されやすい。ＤＢＧを用いる場合は、回路層が形成されたウエハの表面からウエハをハーフカットした後、粘着シートをウエハの回路形成面に貼付し、その後にウエハの裏面を研削すればよい。 In the present embodiment, the wafer is divided by SDBG, but the present invention is not limited to this, and for example, the wafer may be divided by using DBG. When DBG is used, when the distance between the chips formed by dicing is small, the effect of preventing chipping or cracking of the chips is likely to be exhibited. When DBG is used, the wafer may be half-cut from the surface of the wafer on which the circuit layer is formed, an adhesive sheet may be attached to the circuit-forming surface of the wafer, and then the back surface of the wafer may be ground.
　次に、本発明の具体的な実施例を説明するが、本発明は、これらの例によってなんら限定されるものではない。
［実施例及び比較例］
　実施例１～３及び比較例１～４のチップを、以下の手順で作製した。なお、実施例１～３及び比較例１～４は、実験条件をできるだけ揃え、かつ、実験を容易にする観点から、全て回路層が形成されていないミラーウエハを使用した。 Next, specific examples of the present invention will be described, but the present invention is not limited to these examples.
[Examples and Comparative Examples]
The chips of Examples 1 to 3 and Comparative Examples 1 to 4 were produced by the following procedure. In Examples 1 to 3 and Comparative Examples 1 to 4, mirror wafers on which no circuit layer was formed were used from the viewpoint of making the experimental conditions as uniform as possible and facilitating the experiment.
＜実施例１＞
　直径１２インチの単結晶シリコンのミラーウエハを準備し、このミラーウエハに設けられたＶノッチを基準にして、Ｖノッチの頂点が示す方向（以下、縦方向という）に沿って、粘着シートをウエハの一方の面（以下、第１表面という）に貼付した。粘着シートとしては、リンテック株式会社製バックグラインドテープ「Ｅ－３１３５ＫＮ」を用いた。粘着シートの貼付は、貼付装置（リンテック株式会社製「ＲＡＤ－３５１０Ｆ／１２」）を用いて、押込量１５μｍ、突出量１５０μｍ、貼付速度５ｍｍ／ｓ、貼付応力０．３５ＭＰａ、貼付温度２３℃、の条件で行った。
　次に、縦方向の長さが６ｍｍ、縦方向に対して直交する方向（以下、横方向という）の長さが１２ｍｍとなるようにＳＤＢＧを施した。具体的には、株式会社ディスコ製ステルスダイシングレーザソー「ＤＦＬ７３６１」を用いて、ウエハの第１表面とは反対側の表面（以下、第２表面という）側からレーザー照射を行って、縦６ｍｍ×横１２ｍｍのサイズの個片化予定領域が９８０個、マトリクス状に並んで形成されるようにウエハ内部に改質層を形成した。
　さらに、裏面研削装置（株式会社ディスコ製「ＤＰＧ８７６０」）を用いて、ウエハの厚さが３０μｍとなるまで、ウエハの他方の面（以下、第２表面という）を研削することにより、ウエハ内部の改質層を除去するとともに各個片化予定領域を画定する分割予定線に沿ってウエハを割断させた。
　次に、リンテック株式会社製テープマウンター「ＲＡＤ－２７００」に設置されたダイシングテープ（リンテック株式会社製「Ｄ－１７５」）に、個片化されたウエハの第２表面に貼付し、粘着シートを除去した。そして、ステルスダイシングレーザソーに設置されているＩＲカメラを用いて、第１表面側からクラックの発生の有無を観察し、クラックが発生したチップの数をカウントした。
　クラックが発生したチップは９８０個のうち１個であり、クラックの発生率は０．１０％であった。 <Example 1>
A single crystal silicon mirror wafer with a diameter of 12 inches is prepared, and the adhesive sheet is wafered along the direction indicated by the apex of the V notch (hereinafter referred to as the vertical direction) with reference to the V notch provided on the mirror wafer. It was affixed to one surface (hereinafter referred to as the first surface). As the adhesive sheet, a back grind tape "E-3135KN" manufactured by Lintec Corporation was used. The adhesive sheet is attached using a pasting device (“RAD-3510F / 12” manufactured by Lintec Corporation), pushing amount 15 μm, protrusion amount 150 μm, sticking speed 5 mm / s, sticking stress 0.35 MPa, sticking temperature 23 ° C. I went under the conditions of.
Next, SDBG was applied so that the length in the vertical direction was 6 mm and the length in the direction orthogonal to the vertical direction (hereinafter referred to as the horizontal direction) was 12 mm. Specifically, using a stealth dicing laser saw "DFL7361" manufactured by DISCO Corporation, laser irradiation is performed from the surface (hereinafter referred to as the second surface) opposite to the first surface of the wafer, and the length is 6 mm ×. A modified layer was formed inside the wafer so that 980 areas to be separated into pieces having a size of 12 mm in width were formed side by side in a matrix.
Further, using a back surface grinding device (“DPG8760” manufactured by DISCO Co., Ltd.), the other surface of the wafer (hereinafter referred to as the second surface) is ground until the thickness of the wafer reaches 30 μm, thereby causing the inside of the wafer to be ground. The modified layer was removed and the wafer was split along the planned division line defining each planned fragmentation region.
Next, a dicing tape (“D-175” manufactured by Lintec Corporation) installed on the tape mounter “RAD-2700” manufactured by Lintec Corporation is attached to the second surface of the individualized wafer, and an adhesive sheet is attached. Removed. Then, using an IR camera installed in the stealth dicing laser saw, the presence or absence of cracks was observed from the first surface side, and the number of cracked chips was counted.
The number of cracked chips was 1 out of 980, and the crack occurrence rate was 0.10%.
＜実施例２＞
　実施例１と同様の手順で縦方向に沿って、第１表面に粘着シートが貼付されたウエハに対して、縦方向の長さが４ｍｍ、横方向の長さが１２ｍｍとなるようにした以外は、実施例１と同じ条件でウエハに対してＳＤＢＧによる加工を行い、１４７１個のチップとなるように個片化した。
　実施例１と同様にして観察を行ったところ、クラックが発生したチップは、１４７１個のうち１個であり、クラック発生率は０．０７％であった。 <Example 2>
In the same procedure as in Example 1, the length in the vertical direction is 4 mm and the length in the horizontal direction is 12 mm with respect to the wafer to which the adhesive sheet is attached to the first surface along the vertical direction. Was processed by SDBG on the wafer under the same conditions as in Example 1 and individualized into 1471 chips.
When the observation was carried out in the same manner as in Example 1, the number of chips in which cracks were generated was 1 out of 1471, and the crack occurrence rate was 0.07%.
＜実施例３＞
　実施例１と同様の手順で縦方向に沿って、第１表面に粘着シートが貼付されたウエハに対して、縦方向の長さが８ｍｍ、横方向の長さが１２ｍｍとなるようにした以外は、実施例１と同じ条件でウエハに対してＳＤＢＧによる加工を行い、７３５個のチップとなるように個片化した。
　実施例１と同様にして観察を行ったところ、クラックが発生したチップは、７３５個のうち１個であり、クラック発生率は０．１３％であった。 <Example 3>
In the same procedure as in Example 1, the length in the vertical direction is 8 mm and the length in the horizontal direction is 12 mm with respect to the wafer to which the adhesive sheet is attached to the first surface along the vertical direction. Was processed by SDBG on the wafer under the same conditions as in Example 1 and individualized so as to have 735 chips.
When the observation was carried out in the same manner as in Example 1, the number of chips in which cracks were generated was 1 out of 735, and the crack occurrence rate was 0.13%.
＜比較例１＞
　実施例１と同様の手順で縦方向に沿って、第１表面に粘着シートが貼付されたウエハに対して、縦方向の長さが１２ｍｍ、横方向の長さが６ｍｍとなるようにした以外は、実施例１と同じ条件でウエハに対してＳＤＢＧによる加工を行い、９８０個のチップとなるように個片化した。
　図６は、本発明の実施例と比較例とを対比して示す模式的な平面図である。図６（Ａ）に示すように、実施例１、２のウエハＷ１においては、粘着シート１の貼付方向ｄ４及び個片化予定領域Ｒの短辺方向ｄ２を、ＶノッチＷｖが示す方向ｄ３に一致させている。一方、図６（Ｂ）に示すように、比較例１のウエハＷ２においては、粘着シートの貼付方向ｄ４及び個片化予定領域Ｒの長辺方向ｄ１を、Ｖノッチが示す方向ｄ３に一致させている。
　実施例１と同様にして観察を行ったところ、クラックが発生したチップは、９８０個のうち１１個であり、クラック発生率は１．１２％であった。 <Comparative example 1>
In the same procedure as in Example 1, the length in the vertical direction is 12 mm and the length in the horizontal direction is 6 mm with respect to the wafer to which the adhesive sheet is attached to the first surface along the vertical direction. Was processed by SDBG on the wafer under the same conditions as in Example 1 and separated into 980 chips.
FIG. 6 is a schematic plan view showing an embodiment of the present invention and a comparative example in comparison with each other. As shown in FIG. 6A, in the wafers W1 of Examples 1 and 2, the sticking direction d4 of the adhesive sheet 1 and the short side direction d2 of the planned individualization region R are set to the direction d3 indicated by the V notch Wv. Matching. On the other hand, as shown in FIG. 6B, in the wafer W2 of Comparative Example 1, the sticking direction d4 of the adhesive sheet and the long side direction d1 of the planned individualization region R are made to coincide with the direction d3 indicated by the V notch. ing.
When the observation was carried out in the same manner as in Example 1, 11 out of 980 chips had cracks, and the crack occurrence rate was 1.12%.
＜比較例２＞
　実施例１と同様にして第１表面に粘着シートが貼付されたウエハに対して、縦方向の長さが１２ｍｍ、横方向の長さが４ｍｍとなるようにした以外は、実施例１と同じ条件でウエハに対してＳＤＢＧによる加工を行い、１４７１個のチップとなるように個片化した。
実施例１と同様にして観察を行ったところ、クラックが発生したチップは、１４７１個のうち１４個であり、クラック発生率は０．９５％であった。 <Comparative example 2>
Same as in Example 1 except that the length in the vertical direction is 12 mm and the length in the horizontal direction is 4 mm with respect to the wafer to which the adhesive sheet is attached to the first surface in the same manner as in Example 1. Under the conditions, the wafer was processed by SDBG and fragmented into 1471 chips.
When the observation was carried out in the same manner as in Example 1, 14 out of 1471 chips had cracks, and the crack occurrence rate was 0.95%.
＜比較例３＞
　実施例１と同様にして第１表面に粘着シートが貼付されたウエハに対して、縦方向の長さが１２ｍｍ、横方向の長さが１２ｍｍとなるようにした以外は、実施例１と同じ条件でウエハに対してＳＤＢＧ加工を行い、４９０個のチップとなるように個片化した。
実施例１と同様にして観察を行ったところ、クラックが発生したチップは、４９０個のうち６個であり、クラック発生率は１．２２％であった。 <Comparative example 3>
Same as in Example 1 except that the length in the vertical direction is 12 mm and the length in the horizontal direction is 12 mm with respect to the wafer to which the adhesive sheet is attached to the first surface in the same manner as in Example 1. Under the conditions, the wafer was subjected to SDBG processing and fragmented into 490 chips.
When the observation was carried out in the same manner as in Example 1, the number of chips in which cracks were generated was 6 out of 490, and the crack occurrence rate was 1.22%.
＜比較例４＞
　実施例１と同様にして第１表面に粘着シートが貼付されたウエハに対して、縦方向の長さが１２ｍｍ、横方向の長さが８ｍｍとなるようにした以外は、実施例１と同じ条件でウエハに対してＳＤＢＧによる加工を行い、７３５個のチップとなるように個片化した。
実施例１と同様にして観察を行ったところ、クラックが発生したチップは、７３５個のうち９個であり、クラック発生率は１．２２％であった。 <Comparative example 4>
Same as in Example 1 except that the length in the vertical direction is 12 mm and the length in the horizontal direction is 8 mm with respect to the wafer to which the adhesive sheet is attached to the first surface in the same manner as in Example 1. Under the conditions, the wafer was processed by SDBG and fragmented into 735 chips.
When the observation was carried out in the same manner as in Example 1, the number of chips in which cracks were generated was 9 out of 735, and the crack occurrence rate was 1.22%.
　実施例１～３及び比較例１～４の結果を表１に示す。
Figure JPOXMLDOC01-appb-T000001
 The results of Examples 1 to 3 and Comparative Examples 1 to 4 are shown in Table 1.
Figure JPOXMLDOC01-appb-T000001
　表１の結果から明らかなように、粘着シートの貼付方向と、チップの短辺方向とを揃えるようにした実施例１～３においては、クラックを発生したチップの数が少なく、クラック発生率も非常に小さい値を示すことが分かる。
　これに対して、粘着シートの貼付方向と、チップの長辺方向とを揃えるようにした比較例１、２、４においては、クラックが発生したチップの数が増えている。特に、比較例１、２は、クラック発生率の値が、実施例１、２に比べてそれぞれ１０倍以上に上昇しており、比較例４も実施例３の１０倍近くに上昇していることが分かる。
　また、チップの形状を正方形とし、１辺の長さを、実施例１～３のチップの長辺の長さと等しくした比較例３においても、クラックを発生したチップの数が増え、クラック発生率の値が、実施例１、２に比べてそれぞれ１０倍以上に上昇し、実施例３の１０倍近くに上昇していることが分かる。 As is clear from the results in Table 1, in Examples 1 to 3 in which the sticking direction of the adhesive sheet and the short side direction of the chips are aligned, the number of cracked chips is small and the crack occurrence rate is also high. It can be seen that it shows a very small value.
On the other hand, in Comparative Examples 1, 2 and 4 in which the sticking direction of the adhesive sheet and the long side direction of the chip are aligned, the number of cracked chips is increasing. In particular, in Comparative Examples 1 and 2, the value of the crack occurrence rate increased 10 times or more as compared with Examples 1 and 2, respectively, and Comparative Example 4 also increased nearly 10 times as compared with Example 3. You can see that.
Further, also in Comparative Example 3 in which the shape of the chip is square and the length of one side is equal to the length of the long side of the chips of Examples 1 to 3, the number of cracked chips increases and the crack occurrence rate. It can be seen that the value of is increased 10 times or more as compared with Examples 1 and 2, and is increased nearly 10 times as compared with Example 3.
　本発明の半導体装置の製造方法は、チップ間の距離が非常に小さくなるようにウエハを分割するＳＤＢＧ等の加工方法を用いてもチップの欠けや割れを生じにくく、プロセッサ、メモリ、センサ等に用いられる半導体チップの製造に好適に適用することができる。また、本発明の積層体は、上記半導体装置の製造方法に好適に使用することができる。 In the method for manufacturing a semiconductor device of the present invention, chips are less likely to be chipped or cracked even if a processing method such as SDBG for dividing a wafer is used so that the distance between chips becomes extremely small, and the processor, memory, sensor, etc. It can be suitably applied to the production of the semiconductor chip used. In addition, the laminate of the present invention can be suitably used in the method for manufacturing the above-mentioned semiconductor device.
１：粘着シート
１０：積層体
１１：ウエハ部分が研削・分割された積層体
１００、２００：支持体
１０１：押圧体
１０２：集光器
１０３：レーザー
１０４：グラインダー
３００：リングフレーム
３０１：フィルム状接着剤
３０１ａ：切断されたフィルム状接着剤
３０２：支持シート
３０３：転写シート
Ｃ：回路層
ＣＰ：半導体チップ（半導体装置）
ｄ１：長辺方向
ｄ２：短辺方向
ｄ３：Ｖノッチが示す方向
ｄ４：貼付方向（テンション方向）
Ｅ：分割予定線
Ｇ：隙間
Ｍ：改質部
Ｐ：亀裂
Ｒ：個片化予定領域
Ｗｖ：Ｖノッチ
Ｗ：ウエハ
ＷＩ：個片化されたウエハ

  1: Adhesive sheet 10: Laminated body 11: Laminated body 100, 200 in which the wafer portion is ground and divided: Support 101: Pressing body 102: Condenser 103: Laser 104: Grinder 300: Ring frame 301: Film-like adhesion Agent 301a: Cut film-like adhesive 302: Support sheet 303: Transfer sheet C: Circuit layer CP: Semiconductor chip (semiconductor device)
d1: Long side direction d2: Short side direction d3: Direction indicated by V notch d4: Attachment direction (tension direction)
E: Scheduled division line G: Gap M: Modified part P: Crack R: Planned individualization area Wv: V notch W: Wafer WI: Individualized wafer

Claims (6)

  1. 平面形状が矩形状の半導体装置の製造方法であって、
    マトリクス状に並んでいる複数の矩形状の個片化予定領域を含むウエハの表面に、前記個片化予定領域の短辺方向に沿って粘着シートを貼付し、
    前記粘着シートが貼付されたウエハの裏面を研削するととともに、前記個片化予定領域を画定する分割予定線に沿って前記ウエハを分割する、半導体装置の製造方法。     A method for manufacturing a semiconductor device having a rectangular planar shape.
    An adhesive sheet is attached along the short side direction of the planned individualization region to the surface of the wafer including a plurality of rectangular individualized planned regions arranged in a matrix.
    A method for manufacturing a semiconductor device, in which the back surface of a wafer to which the adhesive sheet is attached is ground, and the wafer is divided along a planned division line defining the planned individualization region.
  2. 前記ウエハの表面に前記粘着シートを貼付した後、前記分割予定線に対応する平面位置における前記ウエハの内部に、分割の起点となる改質部を形成し、
    前記粘着シートが貼付された前記ウエハの裏面を研削し、前記分割予定線に沿って前記ウエハを分割する、請求項１に記載の半導体装置の製造方法。     After the adhesive sheet is attached to the surface of the wafer, a modified portion serving as a starting point of division is formed inside the wafer at a plane position corresponding to the planned division line.
    The method for manufacturing a semiconductor device according to claim 1, wherein the back surface of the wafer to which the adhesive sheet is attached is ground and the wafer is divided along the planned division line.
  3. 前記個片化予定領域の、長辺方向の長さ／短辺方向の長さ、で表されるアスペクト比が、１．０５以上である、請求項１又は２に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the aspect ratio represented by the length in the long side direction / the length in the short side direction of the planned individualization region is 1.05 or more. ..
  4. 前記個片化予定領域は、長辺方向の長さが５～５０ｍｍであり、短辺方向の長さが２～２０ｍｍである、請求項１～３のいずれか１項に記載の半導体装置の製造方法。 The semiconductor device according to any one of claims 1 to 3, wherein the individualized region has a length of 5 to 50 mm in the long side direction and a length of 2 to 20 mm in the short side direction. Production method.
  5. 研削後の前記ウエハの裏面に転写シートを貼付し、
    前記転写シート貼付後に、前記粘着シートを前記ウエハから分離する、請求項１～４のいずれか１項に記載の半導体装置の製造方法。     A transfer sheet is attached to the back surface of the wafer after grinding, and the transfer sheet is attached.
    The method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the adhesive sheet is separated from the wafer after the transfer sheet is attached.
  6. マトリクス状に並んだ複数の矩形状の個片化予定領域を含むウエハと、
    前記個片化予定領域の短辺方向に沿ってテンションを付加した状態で、前記ウエハの表面に貼付された粘着シートと、を備える、積層体。

          A wafer containing a plurality of rectangular individualized areas arranged in a matrix, and
    A laminate comprising an adhesive sheet attached to the surface of the wafer in a state where tension is applied along the short side direction of the area to be individualized.
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